Silicon carbide semiconductor device and manufacturing method thereof

Abstract

To provide a SiC semiconductor device with a structure that can suppress wafer warpage and a method for manufacturing the same.SOLUTION: A structure consists of a barrier metal 10ba on the surface of an interlayer dielectric 9 and a barrier metal 10bb on the SiC surface on top of a metal silicide layer 10a. The barrier metal 10ba on the interlayer dielectric film 9 and the barrier metal 10bb on the SiC surface are not planar, and a step is provided between them. This allows the residual stress of the barrier metal 10ba to escape, so that the effect of residual stress can be suppressed and the SiC semiconductor device can be structured to suppress the warpage of the wafer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a semiconductor element with a trench gate structure made of SiC, and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 previously proposed a technology for reducing the cell pitch in a SiC semiconductor device with a trench gate structure without increasing the on-resistance. Specifically, the SiC semiconductor device has an interlayer insulating film and a barrier metal made of Ti or TiN embedded on a gate electrode inside a trench for forming the trench gate structure, with a source electrode formed on top of the interlayer insulating film. This configuration eliminates the need to expose the interlayer insulating film on the SiC surface, eliminating cell pitch restrictions when opening contacts and enabling the cell pitch to be reduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-3967 Summary of the Invention [Problem to be solved by the invention]

[0004] The SiC semiconductor device of Patent Document 1 has a structure in which a source electrode made of a Ni film or a Ti film is formed on a barrier metal, and a source electrode pad made of AlSi is further formed on top of that. The Ni film or Ti film is formed in a planar shape so as to straddle multiple trench gate structures.

[0005] Generally, metals such as Ti and TiN have large residual stresses, which can cause wafer warping and lead to transfer errors during the manufacturing process. Warping is particularly problematic for wafers with large diameters, such as 6-inch wafers.

[0006] In the SiC semiconductor device of Patent Document 1, a barrier metal made of Ti or TiN is embedded in a trench, and a Ti film is formed on top of the Ni film to form a source electrode, which is a metal film with a large residual stress. The Ni or Ti film provided in the source electrode is provided on one side of the wafer in a planar shape. This creates a manufacturing problem due to warpage.

[0007] In view of the above, an object of the present invention is to provide a SiC semiconductor device having a structure capable of suppressing wafer warpage, and a method for manufacturing the same. [Means for solving the problem]

[0008] In order to achieve the above object, the invention described in claim 1 is a SiC semiconductor device having a semiconductor element with a trench gate structure, including: a substrate (1) of a first or second conductivity type made of SiC; a drift layer (2) of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate; a channel layer (3) of the second conductivity type formed on the drift layer and having a contact region (3 a) formed in a surface layer portion thereof; a first conductivity type region (4) formed at a position different from the contact region on the channel layer and having a higher first conductivity type impurity concentration than the drift layer; a gate insulating film (7) covering an inner wall surface of a gate trench (6) penetrating the first conductivity type region and the channel layer; and a gate electrode (8) formed on the gate insulating film; an interlayer insulating film (9) covering the gate electrode in the gate trench; a first electrode (10) electrically connected to the contact region and the first conductivity type region; and a second electrode (11) formed on the back surface side of the substrate. In such a configuration, a step is formed between the upper surface of the interlayer insulating film and the upper surface of the first conductivity type region, thereby forming a recess (12), and the first electrode has a metal silicide layer (10a) formed on the surface of the contact region and the first conductivity type region, a barrier metal (10b) formed on the metal silicide layer and in the recess, and an electrode layer (10c) formed on the barrier metal, and a step is formed between a first barrier metal (10ba) formed in the recess and a second barrier metal (10bb) formed on the metal silicide layer, and the upper surface of the second barrier metal is located higher than the upper surface of the first barrier metal. The first barrier metal and the second barrier metal are separated from each other. .

[0009] In this way, a first barrier metal is formed in the recess, i.e., on the surface of the interlayer insulating film, and a second barrier metal is formed on the metal silicide layer on the SiC surface. The first barrier metal on the interlayer insulating film and the second barrier metal on the SiC surface are not flat, but rather a step is provided between them. This provides an escape route for residual stress in the barrier metal, thereby suppressing the effects of residual stress and enabling a SiC semiconductor device with a structure that can suppress wafer warpage.

[0010] The invention described in claim 7 is a method for manufacturing a SiC semiconductor device having a semiconductor element with a trench gate structure, which includes preparing a substrate (1) of a first or second conductivity type made of SiC, and forming a semiconductor element on the substrate. than the substrate The method includes forming a first conductivity type drift layer (2) with a low impurity concentration, forming a second conductivity type channel layer (3) on the drift layer, the second conductivity type channel layer (3) having a contact region (3 a) in a surface layer portion thereof, forming a first conductivity type region (4) on the channel layer at a position different from the contact region, the first conductivity type region (4) having a higher first conductivity type impurity concentration than the drift layer, forming a gate trench (6) penetrating the first conductivity type region and the channel layer, forming a gate insulating film (7) covering an inner wall surface of the gate trench, forming a gate electrode (8) on the gate insulating film, forming an interlayer insulating film (9) covering the gate electrode in the gate trench, forming a first electrode (10) electrically connected to the contact region and the first conductivity type region, and forming a second electrode (11) on the back surface side of the substrate.

[0011] Then, by forming the gate electrode, the upper surface of the gate electrode has a recessed shape recessed below the upper surface of the first conductivity type region, and by forming the interlayer insulating film, the recessed shape remains even after the interlayer insulating film has been formed, forming a concave portion (12) in the gate trench. Furthermore, by forming the first electrode, a metal film (20) is formed on the surface of the contact region and the first conductivity type region, including inside the concave portion, and then a heat treatment is performed to cause a silicidation reaction of the metal film to form a metal silicide layer (10a) on the surface of the contact region and the first conductivity type region, the metal film remaining on the concave portion is removed, and a barrier metal (10b) is formed on the concave portion and the metal silicide layer from which the metal film has been removed, thereby forming a first barrier metal (10ba) on the concave portion and a barrier metal (10b) on the metal silicide layer, the upper surface of which is positioned above the upper surface of the first barrier metal. and separated from the first barrier metal The method includes forming a second barrier metal (10bb) that covers the first barrier metal and forming an electrode layer (10c) on the barrier metal.

[0012] This manufacturing method allows for the fabrication of a structure in which a first barrier metal is formed in the recess, i.e., on the surface of the interlayer insulating film, and a second barrier metal is formed on the metal silicide layer on the SiC surface. The SiC semiconductor device fabricated in this manner has a structure in which the first barrier metal on the interlayer insulating film and the second barrier metal on the SiC surface are not planar, but have a step between them. This provides an escape route for the residual stress of the barrier metal, thereby suppressing the effects of the residual stress and enabling the fabrication of a SiC semiconductor device with a structure capable of suppressing wafer warpage.

[0013] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment. [Figure 2] FIG. 4 is a cross-sectional view showing a detailed structure of a source electrode. [Figure 3] FIG. 10 is a cross-sectional view showing a detailed structure of a source electrode when the barrier metal has a laminated structure. [Figure 4] 4 is a flowchart showing a process for forming a trench gate structure and a source electrode in the SiC semiconductor device according to the first embodiment. [Figure 5A] FIG. 5 is a cross-sectional view showing a state after the step of forming a gate trench in FIG. 4. [Figure 5B] FIG. 5 is a cross-sectional view showing a state after the etch-back step in FIG. 4. [Figure 5C] 5 is a cross-sectional view showing a state after the step of forming an interlayer insulating film in FIG. 4. FIG. [Figure 5D] 5 is a cross-sectional view showing a state after an etch-back process of the interlayer insulating film in FIG. 4. FIG. [Figure 5E] 5 is a cross-sectional view showing a state after the metal film forming step in FIG. 4. FIG. [Figure 5F]FIG. 5 is a cross-sectional view showing a state after a metal film removal step in FIG. 4. [Figure 5G] FIG. 5 is a cross-sectional view showing a state after the barrier metal forming step in FIG. 4. [Figure 5H] 5 is a cross-sectional view showing the state after the electrode layer forming step in FIG. 4. FIG. [Figure 6] FIG. 4 is a cross-sectional view showing a detailed structure of a source electrode of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 7] 10 is a flowchart showing a process for forming a trench gate structure and a source electrode in the SiC semiconductor device according to the second embodiment. [Figure 8A] 8 is a cross-sectional view showing a state after the step of forming an interlayer insulating film in FIG. 7. FIG. [Figure 8B] 8 is a cross-sectional view showing a state after an etch-back process of the interlayer insulating film in FIG. 7. FIG. [Figure 8C] 8 is a cross-sectional view showing a state after the metal film forming step in FIG. 7. FIG. [Figure 8D] FIG. 8 is a cross-sectional view showing a state after a metal film removal step in FIG. 7. [Figure 8E] 8 is a cross-sectional view showing a state after the step of forming a gate contact hole in FIG. 7. FIG. [Figure 8F] FIG. 8 is a cross-sectional view showing a state after the barrier metal forming step in FIG. 7. [Figure 8G] 8 is a cross-sectional view showing the state after the electrode layer forming step in FIG. 7. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) A first embodiment will be described. An SiC semiconductor device according to this embodiment will be described. Here, an SiC semiconductor device in which a MOSFET is formed as a semiconductor element with a trench gate structure will be described as an example.

[0017] The SiC semiconductor device according to this embodiment includes a vertical MOSFET with a trench gate structure as shown in Fig. 1. The vertical MOSFET is formed in a cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming a peripheral breakdown voltage structure surrounding the cell region, but only the vertical MOSFET of the SiC semiconductor device is shown here. In the following description, the left-right direction of Fig. 1 is defined as the width direction of the SiC semiconductor device, and the up-down direction is defined as the thickness direction or depth direction of the SiC semiconductor device.

[0018] The SiC semiconductor device includes n + A mold substrate 1 is used as a semiconductor substrate. + On the main surface of the mold substrate 1, a n-type SiC - The n-type drift layer 2 is epitaxially grown. - On the first conductivity type drift layer 2, a p-type base region 3 corresponding to a channel layer and an n-type region corresponding to a first conductivity type region are formed. + A source region 4 is formed in turn.

[0019] The p-type base region 3 is a region where a channel region is formed, and + A p-type contact region 3a having a locally increased p-type impurity concentration is formed in a surface layer portion at a position different from the position where the n-type source region 4 is disposed. + The n-type source region 4 - The impurity concentration is higher than that of the type drift layer 2.

[0020] Also, the p-type base region 3 and the n + through the n-type source region 4 - A gate trench 6 is formed so as to reach the n-type drift layer 2. The p-type base region 3 and the n-type base region 4 are formed so as to contact the side surfaces of the gate trench 6. +1, which corresponds to the width direction of the SiC semiconductor device, the longitudinal direction is the normal to the paper surface, and the depth direction is the vertical direction of the paper surface in FIG. 1, which corresponds to the thickness direction of the SiC semiconductor device. Although only one gate trench 6 is shown in FIG. 1, multiple gate trenches 6 are arranged at equal intervals in the horizontal direction of the paper surface to form a stripe pattern.

[0021] The portion of the p-type base region 3 located on the side of the gate trench 6 is an n-type + Type source region 4 and n - The gate trench 6 includes a channel region connecting the gate electrode 8 and the gate drift layer 2. A gate insulating film 7 is formed on the inner wall surface of the gate trench 6, including this channel region. A gate electrode 8 made of doped polysilicon is formed on the surface of the gate insulating film 7. The gate electrode 8 is doped with n-type or p-type doping. An interlayer insulating film 9 is formed on the gate insulating film 7 and gate electrode 8, thereby forming a trench gate structure. Furthermore, the gate trench 6 is not completely filled with the gate insulating film 7, gate electrode 8, and interlayer insulating film 9, but is filled with a barrier metal 10ba (described later and shown in FIG. 2) that is formed thereon.

[0022] More specifically, the n forming the entrance of the gate trench 6 + The upper surface of the gate electrode 8 is lower than the upper surface of the source region 4, and a step is formed between them, giving the gate electrode 8 a recessed shape. An interlayer insulating film 9 and a barrier metal 10ba are disposed in the recessed shape so as to fill this step, thereby filling the gate trench 6. Even when the interlayer insulating film 9 is formed on the gate electrode 8, the recessed shape remains, and a recess 12 having a depth of 10 to 150 nm, for example, about 70 nm, is formed. For this reason, the barrier metal 10ba is formed so as to be embedded in the recess 12 that constitutes the recessed shape. In other words, the lower surface of the barrier metal 10ba is n-type. +The recess 12 is located below the SiC surface formed by the p-type source region 4 and the p-type contact region 3a. A barrier metal 10ba is formed to fill the recess 12, and is preferably arranged to protrude above the SiC surface. The barrier metal 10ba is formed as part of the source electrode 10 (described later), but by being formed on the interlayer insulating film 9, it prevents other metals in the source electrode 10, specifically, the metal constituting the metal silicide layer 10a (described later), from diffusing into the interlayer insulating film 9.

[0023] Furthermore, a source electrode 10 corresponding to a first electrode, a gate wiring layer (not shown), and the like are formed on the interlayer insulating film 9. The source electrode 10 is connected to the n + The gate wiring portion is in contact with the contact regions of the p-type source region 4 and the p-type base region 3. In a cross section different from that of FIG.

[0024] As shown in FIG. 2, the source electrode 10 includes a metal silicide layer 10a, a barrier metal 10b, an electrode layer 10c, and the like.

[0025] The metal silicide layer 10a is an ohmic contact layer formed by a silicidation reaction with SiC. The metal silicide layer 10a provides an ohmic contact with low contact resistance between the source electrode 10 and SiC. The metal silicide layer 10a is made of a refractory metal or noble metal silicide, such as Ni (nickel) silicide, Ti (titanium) silicide, Ta (tantalum) silicide, W (tungsten) silicide, or Mo (molybdenum). The metal silicide layer 10a may be made of one type of metal or multiple types of metals. For example, the metal silicide layer 10a may be made of different types of metals for n-type SiC and p-type SiC. Here, the metal silicide layer 10a is made of Ni silicide, for example. The thickness of the metal silicide layer 10a is optional, but is preferably 10 to 100 nm, e.g., approximately 50 nm.

[0026] The barrier metal 10b includes a barrier metal 10ba corresponding to the first barrier metal formed on the interlayer insulating film 9 and a barrier metal 10bb corresponding to the second barrier metal formed on the metal silicide layer 10a. The barrier metal 10ba suppresses the diffusion of metal elements from the source electrode 10 to the interlayer insulating film 9 and gate electrode 8. The barrier metal 10bb suppresses the diffusion of metal elements from the metal silicide layer 10a constituting the source electrode 10 to the electrode layer 10c. If the metal silicide layer 10a is Ni silicide, the barrier metal 10ba suppresses the diffusion of Ni into the interlayer insulating film 9 and gate electrode 8, and the barrier metal 10bb suppresses the diffusion of Ni into the electrode layer 10c. The barrier metal 10b is composed of a metal that fulfills these roles, such as Ti or TiN (titanium nitride). While the barrier metal 10b is illustrated as a single-layer structure in FIG. 2, it may also have a multi-layer structure of multiple metals, such as Ti and TiN, as shown in FIG. 3.

[0027] Although the barrier metal 10ba and the barrier metal 10bb are formed simultaneously, they are not flat; instead, a step is formed between them, and the top surface of the barrier metal 10bb is located higher than the top surface of the barrier metal 10ba. Furthermore, in this embodiment, the barrier metal 10ba and the barrier metal 10bb are separated from each other. The thickness of the barrier metal 10b is arbitrary, but is set to be equal to or greater than the depth of the recess 12. When the barrier metal 10b has a layered structure of Ti and TiN, the Ti is set to 30 to 100 nm, for example, 50 nm, and the TiN is set to 50 to 100 nm, for example, 100 nm.

[0028] The electrode layer 10c is a portion that constitutes the pad portion of the source electrode 10. Here, the electrode layer 10c is made of a metal containing Al, such as AlSi. The electrode layer 10c is formed to be thicker than the metal silicide layer 10a and the barrier metal 10b. Although the electrode layer 10c is described here as having a single-layer structure, it may have a multilayer structure by plating the surface with Ni (nickel) or Au (gold), for example.

[0029] Furthermore, n + The back side of the mold substrate 1 is + A drain electrode 11 corresponding to a second electrode electrically connected to the substrate 1 is formed. With this structure, an n-channel type inversion trench gate structure vertical MOSFET is formed. A cell region is formed by arranging multiple vertical MOSFETs. A peripheral breakdown voltage structure such as a guard ring (not shown) is formed to surround the cell region in which the vertical MOSFET is formed, thereby forming a SiC semiconductor device.

[0030] Next, a method for manufacturing a SiC semiconductor device according to this embodiment will be described with reference to the flowchart shown in Fig. 4 and the cross-sectional views of the manufacturing steps shown in Fig. 5A to Fig. 5H. However, since the steps in the method for manufacturing a SiC semiconductor device according to this embodiment other than the step of forming gate electrode 8 may be performed by any publicly known steps, the step of forming gate electrode 8 will be mainly described here, and the other steps will be briefly described.

[0031] First, a wafer-shaped n-type semiconductor substrate made of SiC was used. + After preparing the mold substrate 1, + On the main surface of the substrate 1, - The n-type drift layer 2 is then epitaxially grown. - On the n-type drift layer 2, a p-type base region 3 and an n-type + The n-type source region 4 is formed by epitaxial growth or ion implantation. +A mask (not shown) is formed on the surface of the n-type source region 4, and p-type impurity ions are implanted to form the p-type contact region 3a. + A mask (not shown) is placed on the surface of the source region 4, and an opening is made in the mask in a region where a trench gate structure is to be formed.

[0032] Thereafter, the step of forming the gate trench 6 shown in Fig. 4 is carried out. For example, the above-mentioned mask is used to perform anisotropic etching such as RIE (Reactive Ion Etching), thereby forming the gate trench 6 as shown in Fig. 5A. Then, after removing the mask, the step of forming the gate insulating film 7 shown in Fig. 4 is carried out. For example, the gate insulating film 7 is formed by forming a silicon oxide film by CVD (chemical vapor deposition) or by forming a thermal oxide film by thermal oxidation.

[0033] 4 is formed in the gate trench 6, as shown in FIG. 5B. That is, a polysilicon film is formed on the surface of the gate insulating film 7 by CVD or the like so as to fill the gate trench 6, and then the polysilicon film is etched back by dry etching to remove the portion formed outside the gate trench 6. At this time, the polysilicon film is etched back until the inside of the gate trench 6 is recessed so that the inside of the gate trench 6 is not completely filled with the gate electrode 8.

[0034] Next, by performing the step of forming the interlayer insulating film 9 shown in FIG. 4, the interlayer insulating film 9 is formed on the gate electrode 8 so as to fill the gate trench 6, as shown in FIG. 5C. For example, the interlayer insulating film 9 can be formed by low-pressure CVD or the like. Then, the etch-back step of the interlayer insulating film 9 shown in FIG. 4 is performed. That is, as shown in FIG. 5D, the interlayer insulating film 9 is etched back by dry etching or the like so as to expose the SiC surface while leaving the interlayer insulating film 9 on the gate electrode 8, and to form a recess shape with the recess 12 remaining. The depth of the recess 12 at this time is arbitrary, but if the final depth of the recess 12 is to be approximately 70 nm, the depth of the recess 12 at this stage is set to approximately 100 nm.

[0035] Then, the metal film deposition process and the silicide formation process by heat treatment shown in FIG. 4 are performed. Specifically, as shown in FIG. 5E, a metal film 20 for forming a metal silicide layer 10a is deposited. Here, the Ni film is deposited by Ni sputtering. At this time, the recess 12 remains in the gate trench 6, so when the metal film 20 is deposited, a step is formed in the metal film 20 between above the gate trench 6 and outside the gate trench 6.

[0036] Then, a heat treatment is performed at 600 to 800° C., for example, 700° C., to cause a silicidation reaction between the metal constituting the metal film 20 and the Si in the SiC, thereby forming a metal silicide layer 10a. As a result, the metal silicide layer 10a is formed on the SiC surface, while the metal film 20 remains on the interlayer insulating film 9 without causing a silicidation reaction.

[0037] Thereafter, the metal film 20 remaining on the interlayer insulating film 9 is removed by performing the metal film 20 removal step shown in FIG. 4, as shown in FIG. 5F. For example, the metal film 20 is removed by wet etching. Even on the SiC surface, not all of the metal film 20 is necessarily silicided, and some of the metal film 20 may remain on the metal silicide layer 10a. In this case, the metal film 20 remaining on the metal silicide layer 10a is also removed at the same time. Although the metal silicide layer 10a is formed by the above-described heat treatment, if the heat treatment temperature is increased, the metal elements constituting the metal film 20 may diffuse into the interlayer insulating film 9. For this reason, the heat treatment may be performed at a relatively low temperature of 800°C or less. After the metal film 20 removal step, high-temperature annealing at a higher temperature of 900 to 1000°C, for example, 950°C, may be performed. This method further reduces the contact resistance between the metal silicide layer 10a and SiC.

[0038] Next, the barrier metal 10b formation process shown in FIG. 4 is performed. For example, the barrier metal 10b is formed by sequentially sputtering Ti and TiN. However, the barrier metal 10b may also be formed by sputtering a single layer film of Ti or TiN or other materials. As a result, as shown in FIG. 5G, the barrier metal 10b is formed on the metal silicide layer 10a and the interlayer insulating film 9. At this time, a step is formed between the interlayer insulating film 9 and the metal silicide layer 10a, and the barrier metal 10b formed thereon inherits this step. Thereafter, the electrode layer 10c formation process shown in FIG. 4 is performed. For example, AlSi or the like is sputtered. As a result, the electrode layer 10c is formed on the barrier metal 10b as shown in FIG. 5H. The electrode layer 10c and the barrier metal 10b are then patterned using a mask (not shown) to form the source electrode 10.

[0039] Finally, n + Then, processes such as forming a drain electrode 11 on the back surface of the mold substrate 1 are carried out. In this way, the SiC semiconductor device having the vertical MOSFET according to this embodiment shown in FIG.

[0040] As described above, in the SiC semiconductor device of this embodiment, the barrier metal 10ba is formed on the surface of the interlayer insulating film 9, and the barrier metal 10bb is formed on the metal silicide layer 10a on the SiC surface. The barrier metal 10ba on the interlayer insulating film 9 and the barrier metal 10bb on the SiC surface are not flat, but a step is provided between them. This provides an escape route for the residual stress of the barrier metal 10b, thereby suppressing the effects of the residual stress and achieving a SiC semiconductor device with a structure that can suppress wafer warpage.

[0041] In particular, in the SiC semiconductor device of Patent Document 1, Ni and Ti films are formed in sequence, but both are planar, which generates large residual stress and causes wafer warpage. In contrast, in this embodiment, although a barrier metal 10ba is formed on the interlayer insulating film 9, the metal film 20 used to form the metal silicide layer 10a is not formed, and the metal silicide layer 10a is simply formed on the SiC surface. Therefore, the metal silicide layer 10a is not planar, and no planar metal film 20 remains, so the effects of residual stress can be further suppressed.

[0042] Furthermore, the SiC semiconductor device of this embodiment can also provide the following effects.

[0043] (1) In the SiC semiconductor device of Patent Document 1, a barrier metal made of Ti or TiN, a Ni film for forming metal silicide, and a Ti film are formed in that order by sputtering, resulting in a large number of sputtering operations. In contrast, in the SiC semiconductor device of this embodiment, it is sufficient to form only a metal film 20 for forming a metal silicide layer 10a and a barrier metal 10b by sputtering. Because sputtering is typically performed on a single wafer, the number of sputtering operations increases the manufacturing cost of the SiC semiconductor device. Therefore, if the number of sputtering operations can be reduced, as in the SiC semiconductor device of this embodiment, the manufacturing process of the SiC semiconductor device can be simplified, thereby enabling a reduction in manufacturing costs.

[0044] (2) In this embodiment, the barrier metal 10ba and the barrier metal 10bb are separated. This separates the residual stress, further reducing the effect of the residual stress. When the barrier metal 10ba and the barrier metal 10bb are separated, the metal silicide layer 10a comes into contact with the electrode layer 10c from the step. However, this area is sufficiently small compared with the area of ​​the top surface of the metal silicide layer 10a. Therefore, if the top surface of the metal silicide layer 10a is covered with the barrier metal 10bb, it is possible to prevent the metal elements contained in the metal silicide layer 10a from diffusing toward the electrode layer 10c.

[0045] (Modification of the first embodiment) In the first embodiment, the barrier metal 10ba and the barrier metal 10bb are separated from each other, but they may be connected as shown in Fig. 6. Even if the barrier metal 10ba and the barrier metal 10bb are connected, a step formed between them can provide an escape route for residual stress. Therefore, the effects shown in the first embodiment can be obtained.

[0046] (Second embodiment) A second embodiment will be described. This embodiment shows the process of forming a gate wiring portion in comparison with the first embodiment, and other aspects are the same as those of the first embodiment, so only the differences from the first embodiment will be described.

[0047] In this embodiment, a formation process for forming a gate wiring portion connected to the gate electrode 8 at a location different from the vertical MOSFET, for example, at the longitudinal end of the trench gate structure, will be described with reference to FIG. 7 and FIGS. 8A to 8G. FIGS. 8A to 8G are cross-sectional views showing the state of each process, with the left-hand diagram showing a cross-sectional view of the vertical MOSFET and the right-hand diagram showing a cross-sectional view of the gate wiring portion formed at a location different from the vertical MOSFET, for example, in a connecting region located between the cell region and the peripheral breakdown withstanding structure. In the following description, steps with the same names as those in the first embodiment are performed using the same method as in the first embodiment.

[0048] First, the gate trench 6 formation process, gate insulating film 7 formation process, and polysilicon film formation process shown in FIG. 7 are performed using the same techniques as in the first embodiment. At this time, the gate insulating film 7 is formed on the SiC surface, even in the position where the gate wiring portion is to be formed, and a polysilicon film is also formed on the gate insulating film 7. Subsequently, an etch-back process is performed to pattern the polysilicon film, forming a gate electrode 8 in the gate trench 6 and a gate wiring layer 31 constituting part of the gate wiring portion in another position. Then, as shown in FIG. 8A , an interlayer insulating film 9 formation process is performed to form the interlayer insulating film 9 on the gate electrode 8 so as to fill the gate trench 6 and cover the gate wiring layer 31. Furthermore, the etch-back process of the interlayer insulating film 9 shown in FIG. 7 is performed. At this time, the cell region where a vertical MOSFET is to be formed is opened, and a mask (not shown) covering areas other than the cell region is formed on the interlayer insulating film 9 before the etch-back process. As a result, as shown in FIG. 8B , the gate wiring layer 31 remains covered with the interlayer insulating film 9, while the interlayer insulating film 9 remains only in the gate trench 6 in the cell region.

[0049] 7 are then performed. As a result, the metal film 20 on the interlayer insulating film 9 is removed, and a metal silicide layer 10a is formed on the SiC surface, as shown in FIGS. 8C and 8D. Furthermore, since the gate wiring layer 31 is covered with the interlayer insulating film 9, it remains covered with the interlayer insulating film 9 even after the metal film 20 thereon is removed.

[0050] Then, a photolithography process for the gate wiring portion shown in FIG. 7 is performed. Specifically, in the photolithography process, a mask (not shown) having an opening corresponding to the gate wiring layer 31 is formed, and then etching is performed to open a gate contact hole 9a connecting to the gate wiring layer 31 in the interlayer insulating film 9 as shown in FIG. 8E. Next, a process for forming a barrier metal 10b shown in FIG. 7 is performed. For example, the barrier metal 10b is formed by sputtering Ti and TiN in sequence. At this time, as shown in FIG. 8F, since the gate contact hole 9a has been formed, the barrier metal 10b is formed so as to also contact the gate wiring layer 31.

[0051] Furthermore, if the metal used for the barrier metal 10b is a material that undergoes a silicidation reaction, the heat treatment shown in FIG. 7 can form a metal silicide at the contact portion between the gate wiring layer 31 and the barrier metal 10b, forming an ohmic contact layer. For example, the heat treatment can be performed at 600 to 800°C, e.g., 700°C. This allows the metal constituting the barrier metal 10b and the polysilicon constituting the gate wiring layer 31 to undergo a silicidation reaction, forming a metal silicide layer. This allows, for example, Ti to be used both to form the barrier metal 10b and to form the ohmic contact layer with the gate wiring layer 31.

[0052] Furthermore, the barrier properties of TiN can be improved by oxidizing or annealing it. Therefore, when using TiN as the barrier metal 10b, it is preferable to expose the sample to the atmosphere after forming the TiN film to oxidize the TiN. If the sample is exposed to the atmosphere, oxidation can be achieved without increasing process costs. Furthermore, the above-mentioned heat treatment serves as an annealing treatment of the TiN. These processes can also improve the barrier properties of TiN.

[0053] Thereafter, the step of forming the electrode layer 10c shown in Fig. 7 is performed by sputtering, for example, AlSi. As a result, the electrode layer 10c is formed on the barrier metal 10b, as shown in Fig. 8G. Then, by patterning the electrode layer 10c and the barrier metal 10b using a mask (not shown), the source electrode 10 is formed, and a gate wiring portion including the gate wiring layer 31 and the barrier metal 10b and electrode layer 10c in contact therewith is also formed.

[0054] Finally, n + Steps such as forming a drain electrode 11 on the back surface of the mold substrate 1 are then performed, completing the SiC semiconductor device according to this embodiment, which has a vertical MOSFET and a gate wiring portion.

[0055] As described above, the gate wiring portion can be configured using the barrier metal 10b and electrode layer 10c used to form the source electrode 10 in a vertical MOSFET. If the barrier metal 10b is made of a metal that undergoes a silicidation reaction, an ohmic contact layer can be obtained by heat treatment. Furthermore, if TiN is used for the barrier metal 10b, the barrier properties can be improved by exposure to air or heat treatment.

[0056] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment and encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0057] (1) For example, in the above embodiment, an example of a vertical MOSFET having a trench gate structure has been described, but of course, other configurations may be provided using the above-described vertical MOSFET as a basic structure. For example, various structures may be provided, such as a structure in which a p-type deep layer is provided below the trench gate structure to suppress the rise of equipotential lines to the trench gate structure and thereby improve the breakdown voltage.

[0058] (2) In addition, in the above embodiments, an n-channel type vertical MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example, but a p-channel type vertical MOSFET in which the conductivity types of each component are reversed may also be used. In addition, in the above description, a vertical MOSFET has been described as an example of a semiconductor element having a trench gate structure, but the present invention can also be applied to an IGBT having a similar trench gate structure. In the case of an n-channel type IGBT, the n-channel type may be used in place of the n-channel type in the above embodiments. + The only difference is that the conductivity type of the substrate 1 is changed from n-type to p-type, and the other structures and manufacturing methods are the same as those of the above-described embodiments. [Explanation of symbols]

[0059] 1…n + Mold board, 2...n - p-type drift layer, 3...p-type base region 3a...p-type contact region, 4...n + type source region, 6...gate trench 7...gate insulating film, 8...gate electrode, 9...interlayer insulating film, 10...source electrode 10a...metal silicide layer, 10b, 10ba, 10bb...barrier metal 10c...electrode layer, 11...drain electrode, 12...recess, 20...polysilicon film 31...Gate wiring layer

Claims

1. A silicon carbide semiconductor device having a semiconductor element with a trench gate structure, A substrate (1) of a first or second conductivity type made of silicon carbide; A drift layer (2) of a first conductivity type formed on the substrate and having a lower impurity concentration than the substrate; A second conductivity type channel layer (3) formed on the drift layer and having a contact region (3 a) formed on a surface layer portion thereof; a first conductivity type region (4) formed at a position different from the contact region on the channel layer and having a first conductivity type impurity concentration higher than that of the drift layer; a trench gate structure including a gate insulating film (7) covering an inner wall surface of a gate trench (6) penetrating the first conductive type region and the channel layer, and a gate electrode (8) formed on the gate insulating film; an interlayer insulating film (9) covering the gate electrode in the gate trench; a first electrode (10) electrically connected to the contact region and the first conductivity type region; A second electrode (11) formed on the back side of the substrate, A recess (12) is formed by forming a step between an upper surface of the interlayer insulating film and an upper surface of the first conductivity type region, the first electrode has a metal silicide layer (10a) formed on the contact region and a surface of the first conductivity type region, a barrier metal (10b) formed on the metal silicide layer and in the recess, and an electrode layer (10c) formed on the barrier metal, a step is formed between a first barrier metal (10ba) formed in the recess and a second barrier metal (10bb) formed on the metal silicide layer, and an upper surface of the second barrier metal is located higher than an upper surface of the first barrier metal, the first barrier metal and the second barrier metal are separated from each other.

2. The silicon carbide semiconductor device according to claim 1 , wherein said barrier metal has a laminated structure of Ti and TiN.

3. a gate wiring portion connected to the gate electrode at a position different from a cell region in which the semiconductor element is formed; The gate wiring portion is a gate wiring layer (31) formed on the gate insulating film at a position different from the cell region; 2. The silicon carbide semiconductor device according to claim 1, further comprising: a barrier metal disposed on the interlayer insulating film in a position different from the cell region, the barrier metal having a gate contact hole (9a) formed therein that covers the gate wiring layer and is connected to the gate wiring layer through the gate contact hole.

4. The barrier metal has a laminated structure of Ti and TiN, The silicon carbide semiconductor device according to claim 3 , wherein in said gate wiring portion, a metal silicide of said Ti is formed at a portion of said barrier metal that contacts said gate wiring layer.

5. A method for manufacturing a silicon carbide semiconductor device having a semiconductor element with a trench gate structure, comprising: A method for manufacturing a semiconductor device comprising the steps of: preparing a first or second conductivity type substrate (1) made of silicon carbide; and forming a first conductivity type drift layer (2) on the substrate, the drift layer having a lower impurity concentration than the substrate; forming a second conductivity type channel layer (3) having a contact region (3 a) on a surface layer portion on the drift layer; forming a first conductivity type region (4) having a first conductivity type impurity concentration higher than that of the drift layer at a position different from the contact region on the channel layer; forming a gate trench (6) penetrating the first conductivity type region and the channel layer; forming a gate insulating film (7) covering an inner wall surface of the gate trench; forming a gate electrode (8) on the gate insulating film; forming an interlayer insulating film (9) covering the gate electrode in the gate trench; forming a first electrode (10) electrically connected to the contact region and the first conductivity type region; forming a second electrode (11) on the back side of the substrate; forming the gate electrode such that an upper surface of the gate electrode has a recessed shape recessed below an upper surface of the first conductivity type region; By forming the interlayer insulating film, the recess shape remains even after the interlayer insulating film is formed, so that a recess (12) is formed in the gate trench; In forming the first electrode, forming a metal film (20) on the surface of the contact region and the first conductivity type region including within the recess, and then performing a heat treatment to cause a silicidation reaction of the metal film, thereby forming a metal silicide layer (10a) on the surface of the contact region and the first conductivity type region; removing the metal film remaining on the recess; forming a barrier metal (10b) on the recess and on the metal silicide layer from which the metal film has been removed, thereby forming a first barrier metal (10ba) on the recess, and forming a second barrier metal (10bb) on the metal silicide layer, the upper surface of which is located higher than the upper surface of the first barrier metal and which is separated from the first barrier metal; forming an electrode layer (10c) on the barrier metal.

6. In the step of forming the gate insulating film, the gate insulating film is formed up to a position different from a cell region in which the semiconductor element is formed; In forming the gate electrode, a polysilicon film is formed to form the gate electrode in the cell region, and a gate wiring layer (31) is formed at a position different from the cell region; In the step of forming the interlayer insulating film, the interlayer insulating film is formed on the gate electrode and the interlayer insulating film is formed so as to cover the gate wiring layer; The metal silicide layer is formed while the gate wiring layer is covered with the interlayer insulating film, The metal film is removed by removing the metal film formed on the interlayer insulating film covering the gate wiring layer, After removing the metal film, the interlayer insulating film is left in the gate trench in the cell region, and a gate contact hole (9a) connected to the gate wiring layer is formed in the interlayer insulating film at a position different from the cell region; 6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein, in forming said barrier metal, said barrier metal is brought into contact with said gate wiring layer through said gate contact hole.

7. 7. The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein forming the barrier metal includes forming the barrier metal to have a laminated structure of Ti and TiN, and then performing a heat treatment to cause a silicidation reaction of the Ti with the gate wiring layer, thereby forming a metal silicide at a contact portion between the barrier metal and the gate wiring layer.

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