Fabrication of semiconductor structures with multiple quantum wells

Abstract

An example relates to a method of fabricating a semiconductor structure with multiple quantum wells, the method including providing a substrate comprising a binary semiconductor compound having a first lattice constant, depositing at least a first layer on the substrate, the first layer being of a first semiconductor alloy comprising InP, and a second layer in contact with the first layer, the second layer being of a second semiconductor alloy comprising InP, to form a substantially planar first stack of semiconductor layers on the substrate, depositing a third layer of the binary semiconductor compound having the first lattice constant in contact with the first stack, and depositing at least a fourth layer on the third layer, the fourth layer comprising the third semiconductor alloy comprising InP, and a fifth layer in contact with the fourth layer, the fourth layer comprising the fourth semiconductor alloy comprising InP, to form a substantially planar second stack of semiconductor layers on the third layer.

Description

[Background technology]

[0001] Quantum wells are commonly used in semiconductor structures to provide electronic confinement: for example, in optoelectronic devices, quantum wells are used to tune the electronic bandgap and thereby the energy (or frequency) of photons emitted (in the case of an emitter) or absorbed (in the case of an absorber).

[0002] In many applications, the effect of quantum wells can be enhanced by having multiple quantum wells in the stack: in an emitter such as a laser, this can increase the stimulated emission rate of the emitter, while in an absorber, this can increase the absorption rate.

[0003] A commonly commercially available material platform for optoelectronic devices is indium phosphide (InP), which allows the integration of optically active and passive functions into so-called photonic integrated circuits (PICs).

[0004] It would be desirable to provide a more reliable method for fabricating semiconductor structures with multiple quantum wells. [Brief description of the drawings]

[0005] [Figure 1] 1 is a flow diagram illustrating a method for fabricating a semiconductor structure with multiple quantum wells, according to an example. [Diagram 2] 1 is a scanning electron micrograph of a semiconductor structure comprising multiple InP-containing quantum wells, showing the resulting defects in the structure. [Diagram 3] 1 is a scanning electron micrograph of an InP-free multiple quantum well semiconductor structure; [Figure 4] 1 is a schematic diagram of a semiconductor structure, according to an example. [Diagram 5] 1 is a scanning electron micrograph of a semiconductor structure including multiple InP-containing quantum wells, according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] The examples described herein relate to methods of fabricating semiconductor structures, particularly, but not exclusively, as they relate to fabricating semiconductor structures with multiple quantum wells.

[0007] As will be described in more detail below, the examples described herein provide improved semiconductor structures, at least in the example semiconductor structures comprising quantum wells that include InP. Such structures can thus reduce scattering of light transmitted through the structure, increase the rate of stimulated emission in the light emitting portion, and increase the rate of absorption in the light absorbing portion. This allows for more efficient optoelectronic devices, and therefore more efficient PICs.

[0008] 1 is a flow chart illustrating a method 100 for fabricating, in a general manner, a semiconductor structure with multiple quantum wells, according to an example embodiment. A corresponding exemplary semiconductor structure is described below with reference to FIG.

[0009] A substrate is provided at block 102. The substrate includes a binary semiconductor compound having a first lattice constant.

[0010] For example, the substrate may be an InP substrate, i.e., the substrate is composed primarily of InP. The substrate 102 may be purely InP (within acceptable purity tolerances) or may include materials that include at least 99% InP along with other materials, such as dopants or impurities. For example, the substrate may be doped with a dopant material such that the substrate may be considered to be n-doped, or the substrate may be doped with a dopant material such that the substrate may be considered to be p-doped.

[0011] At block 104, the method 100 includes at least depositing a first layer on the substrate and a second layer in contact with the first layer to form a first stack of substantially planar semiconductor layers on the substrate, the first layer being a first semiconductor alloy including InP and the second layer being a second semiconductor alloy including InP.

[0012] The first stack includes a plurality of layers, the plurality of first stack layers being less than a threshold number of layers above which one or more layers of the stack exhibit defects. Fabricating the first stack includes depositing a plurality of layers of a first semiconductor alloy interspersed with a corresponding plurality of layers of a second semiconductor alloy. As described below with reference to FIG. 3, in at least some examples, particularly examples in which the first and second layers include InP, as the number of semiconductor layers increases, the tendency for defects to occur in the semiconductor layers of the first stack increases.

[0013] By the layers being substantially planar, it is envisaged that the layers are, for example, deposited on a substrate such that the top surface of each layer is parallel to the surface of the substrate on which the first layer is deposited.

[0014] In some examples, the first layer is on the substrate in the sense that it is deposited in contact with the substrate. In other examples, the first layer is on the substrate in that it is supported by the substrate but is not in direct contact with the substrate. For example, there are one or more intermediate layers, such as a non-InP-containing material, such as indium aluminum arsenide (InAlAs).

[0015] As a general comment regarding the term "on" as used herein, a layer specified as being in contact with a layer (e.g., a bottom layer) is in direct contact with that layer, while a layer specified as being on a layer (e.g., a bottom layer) may be in direct contact with that layer or may be supported by the layer with one or more intermediate layers (e.g., non-InP-containing materials) therebetween.

[0016] In some instances, each layer is deposited over substantially the entire surface area of ​​the substrate (eg, excluding the area of ​​the substrate that is clamped by a wafer clamp of the reactor in which the semiconductor is fabricated).

[0017] FIG. 2 is a scanning electron micrograph of a semiconductor structure containing multiple quantum wells (32 in total) containing InP. In this example, the quantum wells are formed from thin layers of indium gallium arsenide phosphide (InGaAsP) and are constructed to be strain-free by matching their lattice constant to that of the substrate. As can be seen in FIG. 2, growing many successive semiconductor quantum wells containing InP introduces morphological defects into the layers of the semiconductor structure, which can manifest as distinct non-planarity (e.g., undulations) in one or more layers of the semiconductor, as described below. These defects can lead to epitaxial growth failures or device failures in devices incorporating the semiconductor structure, and limit the number of quantum wells that can be grown within the structure.

[0018] As shown in Figure 2, undulations appear in the layers of the structure when viewed in cross section. These undulations may not be present on the surface of the processed structure, which may still exhibit a flat surface. This may be due, for example, to the planarizing effect of an InP layer deposited on the layers of the semiconductor structure (e.g., to form electrical contacts).

[0019] Thus, the inventors have realized that fabricating multiple quantum wells using InP creates problems that are not known to exist when fabricating multiple quantum wells using other semiconductor material platforms. The inventors have determined that, depending on the processing conditions (e.g., pressure and temperature), defects are observed when more than about 16 quantum wells are grown in a stack.

[0020] Thus, in some examples, the number of layers of each of the first and second semiconductor alloys is greater than eight and less than sixteen, such that the total number of layers in the first stack is less than thirty-two.

[0021] In contrast, Figure 3 is a scanning electron micrograph of a semiconductor structure containing 36 quantum wells that do not contain InP. In this example, the quantum wells are formed of indium aluminum gallium arsenide (InAlGaAs). As can be seen, the quantum wells shown in Figure 2 are substantially planar. This is so even though there are many more quantum wells that could be fabricated using quantum wells that contain InP without forming the defects seen in Figure 2.

[0022] 2, a third layer including a binary semiconductor material having a first lattice constant is deposited in contact with the first stack in block 106. For example, if the substrate is InP, the third layer can also be InP.

[0023] Next, in block 108, the method 100 includes depositing at least a fourth layer in contact with the third layer and a fifth layer in contact with the fourth layer to form a second stack of substantially planar semiconductor layers on the third layer, the fourth layer including a third semiconductor alloy including InP, and the fifth layer including a fourth semiconductor alloy including InP.

[0024] As one skilled in the art will appreciate, various techniques can be used to deposit layers of semiconductor material in accordance with the examples described herein, which may include chemical vapor deposition techniques such as metalorganic vapor phase epitaxy (MOVPE) and molecular beam epitaxy (MBE).

[0025] 4 is a diagram of a semiconductor structure 400, according to an example, which is fabricated according to the method described above with reference to FIG.

[0026] The semiconductor structure 400 includes a substrate 402 upon which the quantum wells are grown.

[0027] The semiconductor structure 400 includes a first stack of quantum wells 404. The first stack 404 includes multiple alternating layers of a first semiconductor alloy 406 and a second semiconductor alloy 408. A first layer of the first semiconductor alloy 406 is deposited on a substrate 402, and a second layer of the second semiconductor alloy 408 is deposited in contact with the first layer of the first semiconductor alloy 406, as described above with reference to block 104 of FIG. 1. The multiple quantum wells were fabricated by alternating a deposition process for depositing the first semiconductor alloy 406 and a deposition process for depositing the second semiconductor alloy 408.

[0028] For the reasons stated above, the first stack 404 includes fewer than 32 layers, that is, the first stack includes fewer than 16 layers of the first semiconductor alloy 406 and fewer than 16 layers of the second semiconductor alloy 408.

[0029] In some examples, each of the first and second semiconductor alloys 406, 408 includes a ternary semiconductor alloy or a quaternary semiconductor alloy. In examples, each of the first and second semiconductor alloys 406, 408 includes InGaAsP, with the relative amounts of indium phosphide (InP), gallium arsenide (GaAs), indium arsenide (InAs), and gallium phosphide (GaP) differing between the first and second semiconductor alloys 406, 408. Each of the first and second semiconductor alloys 406, 408 may be doped (e.g., p-doped or n-doped).

[0030] While in some examples it is assumed that each of the first and second semiconductor alloys 406, 408 is strain-free (e.g., the lattice constant of one layer matches the layer it is in contact with), it may be desirable to select a lattice constant that introduces strain, for example to modify the light absorption or emission characteristics of the semiconductor structure 400.

[0031] In some examples, each layer of the first and second semiconductor alloys 406, 408 is less than 15 nanometers (nm).

[0032] Deposited in contact with the first stack 404 is a third layer 410. The third layer 410 is a binary semiconductor having a lattice constant substantially equal to that of the substrate 402, as described above with reference to block 106 of Figure 1. By substantially equal, it is meant that the introduction of the third layer 410 is not intended to introduce any strain.

[0033] The thickness of the third layer 410 may range from 4 nm to 100 nm.

[0034] The inclusion of the third semiconductor layer 410 having a lattice constant substantially equal to that of the substrate 402 means that the manufacturing process (e.g., the method of FIG. 2) can be performed without modifying the manufacturing reactor or any of the reactor process conditions, e.g., temperature or pressure, prior to the manufacturing of the third layer 410. This may result in easy integration into existing manufacturing processes, for example.

[0035] Furthermore, the addition of only a single thin layer of binary semiconductor material has only a negligible effect on the overall electro-optical properties of semiconductor structure 400, and therefore the performance of devices incorporating semiconductor structure 400 is not adversely affected by the inclusion of third layer 410.

[0036] Deposited in contact with the third layer 410 is a second stack of quantum wells 412. The second stack 412 includes multiple alternating layers of a third semiconductor alloy 414 and a fourth semiconductor alloy 416. A layer of the third semiconductor alloy 414 is deposited on the third layer 410, and a layer of the fourth semiconductor alloy 416 is deposited on the layer of the third semiconductor alloy 414 that was deposited in contact with the third layer 410, as described above with reference to block 108. The multiple quantum wells are fabricated by alternating deposition processes for depositing the third semiconductor alloy 414 and the fourth semiconductor alloy 416.

[0037] For the reasons stated above, the second stack 412 also includes less than 32 layers, i.e., the first stack includes less than 16 layers of the first semiconductor alloy 406 and less than 16 layers of the second semiconductor alloy 408.

[0038] In some examples, each of the third and fourth semiconductor alloys 414, 416 includes a ternary semiconductor alloy or a quaternary semiconductor alloy. For example, each of the third and fourth semiconductor alloys 414, 416 includes InGaAsP, where indium phosphide (InP), gallium arsenide (GaAs), indium arsenide (InAs), and gallium phosphide (GaP) are different in the third and fourth semiconductor alloys (414, 416). Each of the third and fourth semiconductor alloys 414, 416 can be doped (e.g., p-doped or n-doped).

[0039] Although each of the third and fourth semiconductor alloys 414, 416 are assumed to be unstrained (e.g., the lattice constant of one layer matches the adjacent layer), in some instances it may be desirable to introduce strain, for example by selecting a lattice constant that alters the optical absorption or emission properties of the semiconductor structure 400.

[0040] In some examples, the process described with reference to blocks 106 and 108 of FIG. 1 may be repeated to further increase the number of quantum wells in semiconductor structure 400.

[0041] 4, the first stack 404 and the second stack 412 have the same number of layers, such that the third layer 410 is in the center of the entire stack; in other examples, the first stack 404 has a different number of quantum well layers than the second stack 412. That is, the third layer 410 may be elsewhere in the semiconductor structure 400 and not necessarily exactly in the middle of the layers of quantum wells. For example, in a semiconductor structure 400 including 25 quantum well layers, the third layer 410 may be deposited after 9 quantum wells have been fabricated, and 16 quantum wells may be fabricated above the third layer 410.

[0042] FIG. 5 is a scanning electron micrograph of a semiconductor structure containing 24 quantum wells containing InP. In this example, the quantum wells are formed of thin layers of indium gallium arsenide phosphide (InGaAsP) and are configured to be strain-free by matching their lattice constant to that of the substrate. The third layer 410, described above, can be identified as a bright band approximately in the middle of the stack of dark bands (corresponding to the quantum well structure). As can be seen in FIG. 2, the introduction of the third layer 410, which is a single thin layer of material, can significantly increase the number of InP-containing quantum well layers that can be fabricated in the semiconductor structure before defects such as those shown in FIG. 2 become present. Thus, the method described above with reference to FIG. 1 provides a simple and efficient method that allows for the growth of thicker stacks of quantum wells containing InP.

[0043] Increasing the total thickness of the stack of repeating epitaxial quantum well layers can be useful, for example, by increasing the confinement of light within the semiconductor, for example, making it possible to produce more efficient electroabsorption or electrorefractive modulators, since the efficiency of these modulators is related to the optical confinement.

[0044] The above examples should be understood as illustrative examples. It should be understood that any feature described in connection with any one example may be used alone or in combination with other features described, and may also be used in combination with one or more features of any other example, or any combination of any other example. Moreover, equivalents and modifications not described above may be used without departing from the scope of the appended claims.

Claims

1. 1. A method for fabricating a semiconductor structure having a plurality of quantum wells, comprising the steps of: providing a substrate comprising a binary semiconductor compound having a first lattice constant; depositing a first layer of a first semiconductor alloy comprising InP on the substrate and depositing a second layer of a second semiconductor alloy comprising InP in contact with the first layer to form a first stack of quantum wells comprising substantially planar semiconductor layers on the substrate, the first layer of the first semiconductor alloy comprising InP having more than 8 layers and less than 16 layers, and the second layer of the second semiconductor alloy comprising InP having more than 8 layers and less than 16 layers; depositing in contact with the first stack a third layer of a binary semiconductor compound having substantially the first lattice constant; a fourth layer on the third layer, the fourth layer comprising a third semiconductor alloy comprising InP; and a fifth layer in contact with the fourth layer, the fifth layer comprising a fourth semiconductor alloy comprising InP; forming a second stack of quantum wells comprising a substantially planar semiconductor layer on the third layer; A method comprising:

2. The method of claim 1, wherein the third layer is a single layer.

3. A method according to claim 1 or 2, wherein the third layer is a flat layer.

4. The method of claim 1 , wherein the first stack comprises less than 32 layers.

5. 5. The method of claim 1, comprising at least one of: the third semiconductor alloy being substantially the same as the first semiconductor alloy; or the fourth semiconductor alloy being substantially the same as the second semiconductor alloy.

6. 6. The method of claim 1, wherein each of the first semiconductor alloy, the second semiconductor alloy, the third semiconductor alloy, and the fourth semiconductor alloy is a ternary semiconductor alloy or a quaternary semiconductor alloy.

7. 7. The method of claim 1, wherein each of the first semiconductor alloy, the second semiconductor alloy, the third semiconductor alloy, and the fourth semiconductor alloy is InGaAsP, and the relative amounts of InP, GaAs, InAs, and GaP vary between the first semiconductor alloy and the second semiconductor alloy and between the third semiconductor alloy and the fourth semiconductor alloy.

8. The method of claim 1 , wherein the second stack comprises a plurality of layers, the number of layers of the second stack being equal to the number of layers of the first stack.

9. 9. The method according to claim 1, wherein the material of the third layer is InP.

10. The method according to any one of claims 1 to 9, wherein the material of the substrate is InP.

11. The method of claim 1 , wherein the third layer has a thickness greater than 4 nm.

12. 12. The method of claim 1, wherein the third layer has a thickness of less than 100 nm.

13. The method of claim 1 , wherein the first layer is in contact with the substrate.

14. 1. A semiconductor structure comprising a plurality of quantum wells, a substrate comprising a binary semiconductor compound having a first lattice constant; a first stack of quantum wells comprising substantially planar semiconductor layers including a first layer of a first semiconductor alloy comprising InP and a second layer of a second semiconductor alloy comprising InP in contact with the first layer, the first layer of the first semiconductor alloy comprising InP having more than 8 layers and less than 16 layers, and the second layer of the second semiconductor alloy comprising InP having more than 8 layers and less than 16 layers; a third layer in contact with the first stack, the third layer being of a binary semiconductor compound having substantially the first lattice constant; a second stack of substantially planar semiconductor layers on the third layer, the second stack comprising at least a fourth layer on the third layer, the fourth layer comprising a third semiconductor alloy comprising InP; and a fifth layer in contact with the fourth layer, the fifth layer comprising a fourth semiconductor alloy comprising InP; the second stack of quantum wells comprising: The semiconductor structure comprising:

15. The semiconductor structure of claim 14, wherein the third layer is a single layer.

16. The semiconductor structure of claim 14 or 15, wherein the third layer is a planar layer.

17. 17. The semiconductor structure of any one of claims 14 to 16, wherein said substrate material is InP.

18. 18. The semiconductor structure of any one of claims 14 to 17 wherein said third layer has a thickness greater than 4 nm.

19. 19. The semiconductor structure of any one of claims 14 to 18 wherein said third layer has a thickness of less than 100 nm.

20. 20. An electroabsorption modulator or electrorefractive element comprising a semiconductor structure according to any one of claims 14 to 19.

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