Semiconductor layout structure and semiconductor test structure

Abstract

The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor layout structure and a semiconductor test structure. The semiconductor layout structure includes an active layer and a gate layer. The active layer includes a first active region including a plurality of spaced apart first transistor regions and a second active region adjacent to the first active region including a plurality of spaced apart second transistor regions, and the active layers corresponding to adjacent first transistor regions are separated from each other. The gate layer includes the active layer, at least one first gate structure located above the active layer and extending in a first direction, and a plurality of second gate structures spaced apart along the first direction, the first gate structure and the second gate structure being adjacent to each other, the first gate structure corresponding to the first transistor region, and the second gate structure corresponding to the second transistor region.

Description

[Technical field]

[0001] The present invention claims priority to a Chinese patent application filed on April 12, 2022, bearing application number 202210382204.0 and titled "Semiconductor layout structure and semiconductor test structure", the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to the field of semiconductors, and more particularly to semiconductor layout structures and semiconductor test structures. [Background technology]

[0003] In a semiconductor manufacturing process, in order to effectively detect problems in the semiconductor manufacturing process and the performance of the completed transistors, and to facilitate adjustment and optimization of the manufacturing process, an electrical characteristic test structure is usually manufactured in the semiconductor structure. After the semiconductor structure is manufactured, an electrical characteristic test is performed on the electrical characteristic test structure in the semiconductor structure, and the reliability of the semiconductor manufacturing process and the stability of the transistors in the semiconductor structure are evaluated based on the resistance or compatibility of the electrical characteristic test structure, etc.

[0004] However, currently, after fabrication of semiconductor test structures, a problem exists in that the parasitic leakage of transistors is high. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor layout structure, the semiconductor layout structure including an active layer and a gate layer, the active layer including a first active region and a second active region adjacent to the first active region, the first active region including a plurality of spaced apart first transistor regions, the second active region including a plurality of spaced apart second transistor regions, the active layer corresponding to adjacent first transistor regions being separated from each other, a gate layer located above the active layer, the gate layer including at least one first gate structure extending in a first direction and a plurality of second gate structures spaced apart along the first direction, the first gate structure and the second gate structure being adjacent to each other, the first gate structure corresponding to the first transistor region, and the second gate structure corresponding to the second transistor region.

[0006] In some embodiments, the layout structure further includes a metal layer, the metal layer corresponding to the first transistor region and the second transistor region, and the metal layer located above the first transistor region and the metal layer located above the second transistor region are separated from each other.

[0007] In some embodiments, the first transistor region includes a first doped region and a second doped region, the first doped region being one of a source region and a drain region of the first transistor region and located on a side of the first transistor region away from the second transistor region, and the second doped region being the other of the source region and drain region of the first transistor region and located between the first transistor region and the second transistor region.

[0008] In some embodiments, the metal layer corresponding to the first doped region and the metal layer corresponding to the second doped region are separated from each other, and the metal layers corresponding to adjacent first doped regions are separated from each other.

[0009] In some embodiments, a metal layer corresponding to the second transistor region is located above the second gate structure.

[0010] In some embodiments, the metal layers overlying adjacent second gate structures are separated from each other.

[0011] In some embodiments, the second transistor region further includes a third doped region, the third doped region being located between adjacent second gate structures and being either a source region or a drain region of the second transistor region, the second doped region being further the other of the source region and the drain region of the second transistor region, the metal layer corresponding to the second transistor region also being located above the third doped region, and the metal layer corresponding to the second gate structures and the metal layer corresponding to the third doped region being separated from each other.

[0012] According to some embodiments of the present invention, another aspect of the embodiments of the present invention further provides a semiconductor test structure, the semiconductor test structure including a first active area and a second active area adjacent to the first active area, and a first gate structure and a second gate structure, the first active area is provided with a plurality of spaced apart first transistors, the second active area is provided with a plurality of spaced apart second transistors, the first active areas corresponding to adjacent first transistors are separated from each other, the first gate structure extends in a first direction, the second gate structure is spaced apart in the first direction, the first gate structure and the second gate structure are adjacent to each other, the first gate structure corresponds to the first transistor, and the second gate structure corresponds to the second transistor.

[0013] In some embodiments, the semiconductor device further includes a metal layer, the metal layer being electrically connected to the first transistor and the second transistor, respectively, and the metal layer electrically connected to the first transistor and the metal layer electrically connected to the second transistor being separated from each other.

[0014] In some embodiments, the first transistor includes a first doped region and a second doped region, the first doped region being located on a side of the first transistor away from the second transistor as one of a source and a drain of the first transistor, the second doped region being located between the first transistor and the second transistor as the other of the source and drain of the first transistor, and a metal layer corresponding to the first transistor being electrically connected to the first doped region and the second doped region, respectively.

[0015] In some embodiments, the metal layer corresponding to the first doped region and the metal layer corresponding to the second doped region are separated from each other, and the metal layers corresponding to adjacent first doped regions are separated from each other.

[0016] In some embodiments, the metal layer corresponding to the second transistor is electrically connected to the second gate structure.

[0017] In some embodiments, the metal layers corresponding to two adjacent second gate structures are separated from each other.

[0018] In some embodiments, the second transistor includes a third doping region, the third doping region being located between adjacent second gate structures as one of the source and drain of two adjacent second transistors, the second doping region further being the other of the source and drain of the second transistor, the metal layer corresponding to the second transistor is also electrically connected to the third doping region, and the metal layer corresponding to the second gate structure and the metal layer corresponding to the third doping region are separated from each other.

[0019] In some embodiments, two adjacent second transistors constitute one second transistor group, the second transistor group includes a third doping region, the third doping region is located between adjacent second gate structures in the second transistor group as a source or drain of two adjacent second transistors in the second transistor group, and metal layers corresponding to two opposing second gate structures in the adjacent second transistor groups are connected.

[0020] In the technical solution of the semiconductor layout structure according to the embodiment of the present invention, the first active areas corresponding to adjacent first transistor areas are arranged to be separated from each other, so that after the semiconductor test structure is manufactured using the semiconductor layout structure, the first transistors in the semiconductor test structure do not share the first active areas, and thus, when testing one of the first transistors, the first active areas do not cause a coupling effect on the adjacent first transistors, thereby preventing the occurrence of a leakage phenomenon caused by the active areas, and improving the parasitic leakage phenomenon of the semiconductor test structure. [Brief description of the drawings]

[0021] [Figure 1] 1 is a diagram illustrating an example of a configuration of a semiconductor layout structure according to an embodiment of the present invention; [Diagram 2] 1 is a diagram illustrating an example of a configuration of an active layer of a semiconductor layout structure according to an embodiment of the present invention. [Diagram 3] 1 is a diagram illustrating an example of a configuration of a semiconductor layout structure according to an embodiment of the present invention; [Figure 4] 1 is a diagram illustrating an example of a configuration of an active layer of a semiconductor layout structure according to an embodiment of the present invention. [Diagram 5] 10 is a diagram illustrating an example of a configuration of another semiconductor layout structure according to an embodiment of the present invention. [Figure 6] FIG. 13 is a diagram illustrating an example of a configuration of yet another semiconductor layout structure according to an embodiment of the present invention. [Figure 7]1 is an IV characteristic graph after an electrical characteristic test on a semiconductor structure. [Figure 8] 4 is an IV characteristic graph after electrical property testing of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] One or more embodiments are illustratively described by the images of the drawings corresponding thereto, but these illustrative descriptions do not constitute limitations on the embodiments, and the figures in the drawings do not constitute proportional limitations, unless otherwise specified. In order to more clearly explain the embodiments of the present invention or the technical solutions of the prior art, the drawings necessary for the embodiments are briefly described above, but the above drawings are only some embodiments of the present invention, and it is obvious to those skilled in the art that other drawings can also be obtained based on these drawings without exerting creative efforts.

[0023] As can be seen from the background art, conventional semiconductor test structures suffer from a problem of large parasitic leakage current from transistors.

[0024] FIG. 1 is a diagram showing an example of the configuration of a semiconductor layout structure, and FIG. 2 is a diagram showing an example of the configuration of an active layer of the semiconductor layout structure. Referring to FIG. 1 and FIG. 2, as a result of the study, one of the causes of the problem of large parasitic leakage of transistors in a semiconductor test structure manufactured by a conventional semiconductor layout structure is the use of the semiconductor test structure to test the electrical characteristics of the first transistor and the second transistor. In the conventional semiconductor layout structure, the gate layer corresponding to the multiple first transistor regions 1 is a continuous first gate structure 2, and the active regions 3 corresponding to adjacent first transistor regions 1 are connected to each other, that is, after being manufactured into the semiconductor test structure, the multiple first transistors are a shared gate structure, and the active regions corresponding to the sources or drains of the multiple first transistors are connected to each other. Furthermore, since the metal layer located above the first transistor region 1 and the metal layer located above the second transistor region 4 are connected to each other, when one of the first transistors is tested, a coupling effect occurs in the adjacent elements, causing the gate voltage of the adjacent elements to rise, resulting in an increase in leakage current.

[0025] An embodiment of the present invention provides a semiconductor layout structure and a semiconductor test structure, in which first active areas corresponding to adjacent first transistor areas are separated from each other in the semiconductor layout structure. Therefore, when a semiconductor test structure is manufactured based on the semiconductor layout structure and one of the first transistors is tested, no coupling effect is caused by the active areas to the adjacent first transistors, thereby preventing leakage caused by the active areas.

[0026] Hereinafter, the embodiments of the present invention will be described in detail in combination with the drawings. However, as can be understood by those skilled in the art, many technical details are proposed in the embodiments of the present invention to allow the reader to better understand the present invention. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present invention can be realized.

[0027] FIG. 3 is a diagram illustrating an example of a configuration of a semiconductor layout structure according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating an example of a configuration of an active layer of the semiconductor layout structure according to an embodiment of the present invention.

[0028] 3 and 4, the semiconductor layout structure includes an active layer and a gate layer, the active layer includes a first active region 101 and a second active region 102 adjacent to the first active region 101, the first active region 101 includes a plurality of first transistor regions 10 spaced apart, the second active region 102 includes a plurality of second transistor regions 11 spaced apart, the active layers corresponding to adjacent first transistor regions 10 are separated from each other, a gate layer is located above the active layer, the gate layer includes at least one first gate structure 103 extending in a first direction X and a plurality of second gate structures 104 spaced apart along the first direction X, the first gate structure 103 is adjacent to the second gate structure 104, the first gate structure 103 corresponds to the first transistor region 10, and the second gate structure 104 corresponds to the second transistor region 11.

[0029] By providing the first active regions 101 corresponding to adjacent first transistor regions 10 separately from each other, the adjacent first transistor regions 10 do not share the same first active region 101. After manufacturing a semiconductor test structure based on the semiconductor layout structure, when testing any one of the multiple first transistors, the first active region 101 does not cause a coupling effect on the adjacent first transistor, thereby improving the parasitic leakage phenomenon of the semiconductor test structure.

[0030] The first active area 101 and the second active area 102 are adjacent to each other, that is, the first transistor area 10 and the second transistor area 11 are adjacent to each other, forming two rows of transistor areas. The first transistor area 10 in one row corresponds to the same first gate structure 103, and each second transistor area 11 in one row of second transistor areas 11 corresponds to one second gate structure 104. Note that the embodiment of the present invention takes as an example the first active area 101 corresponding to the first transistor in one row and the second active area 102 corresponding to the second transistor in one row adjacent to the first transistor, but in reality, the substrate further includes a plurality of first active areas 101 and second active areas 102.

[0031] In some embodiments, the interval between the first active areas 101 corresponding to adjacent first transistor regions 10 can be designed to be within a suitable interval range, which is advantageous in increasing the process window for manufacturing the first active areas 101 that are provided separately from each other and reducing the difficulty of the manufacturing process. On the other hand, the interval between the first active areas 101 corresponding to adjacent first transistor regions 10 is not too large, so that a large space can be secured for the formation of the first active areas 101, and the size of the active area corresponding to the first transistor region 10 is not too small, so that the first transistor has better performance after the semiconductor test structure is manufactured based on the semiconductor layout structure.

[0032] In some embodiments, the layout structure further includes a metal layer 105, the metal layer 105 corresponds to the first transistor region 10 and the second transistor region 11, and the metal layer 105 located above the first transistor region 10 and the metal layer 105 located above the second transistor region 11 are separated from each other. The metal layer 105 is used, on one hand, to supply external electrical signals to the first transistor region 10 and the second transistor region 11, and, on the other hand, to derive electrical signals of the first transistor region 10 and the second transistor region 11 for performing electrical property testing. By providing the metal layer 105 located above the first transistor region 10 and the metal layer 105 located above the second transistor region 11 separately from each other, after manufacturing the semiconductor test structure based on the semiconductor layout structure, the metal layer 105 electrically connected to the first transistor and the metal layer 105 corresponding to the second transistor are separated from each other, so that when testing either the first transistor or the second transistor, the metal layer 105 does not cause a coupling effect on the other first transistor or second transistor that is not being tested, that is, the electrical characteristic tests on the first transistor and the second transistor do not affect each other, thereby improving the parasitic leakage phenomenon of the semiconductor test structure. Specifically, in some embodiments, the semiconductor test structure further includes a metal contact layer 12 corresponding to a metal contact structure between the metal layer and the first transistor region 10 and the second transistor region 11, and the metal contact structure is used to electrically connect the metal layer to the first transistor region 10 and the second transistor region 11.

[0033] 4, in some embodiments, the first transistor region 10 includes a first doping region 106 and a second doping region 107, the first doping region 106 is located on a side of the first transistor region 10 away from the second transistor region 11 as one of the source region and drain region of the first transistor region 10, and the second doping region 107 is located between the first transistor region 10 and the second transistor region 11 as the other of the source region and drain region of the first transistor region 10. In some embodiments, the first doping region 106 can be the source region of the first transistor region 10, the second doping region 107 can be the drain region of the first transistor region 10, and the second doping region 107 can also be the drain region of the second transistor region 11, that is, the first transistor region 10 and the second transistor region 11 share one second doping region 107 as the drain region, so that the semiconductor test structure formed based on the semiconductor layout structure has a small size. In some embodiments, the metal layer 105 located above the first transistor region 10 may be specifically located above the first doping region 106 and above the second doping region 107. Thus, in some embodiments, when the first doping region 106 is the source region of the first transistor region 10 and the second doping region 107 is the drain region of the first transistor, after forming the semiconductor test structure, the first doping region 106 is electrically connected to the metal layer 105, so that the metal layer 105 can, on the one hand, derive an electrical signal of the first transistor, and on the other hand, supply an external electrical signal to the source of the first transistor through the metal layer 105 to make the second transistor operate normally. The metal layer 105 electrically connected to the second doping region 107 is electrically connected to the corresponding sub-word line, so that the first transistor and the second transistor can drive the corresponding sub-word line.

[0034] In some embodiments, the metal layer 105 corresponding to the first doping region 106 is separated from the metal layer 105 corresponding to the second doping region 107, and the metal layers 105 corresponding to adjacent first doping regions 106 are separated from each other. In this way, an external electrical signal supplied from the metal layer 105 to the first doping region 106 does not interfere with the second doping region 107. The metal layers 105 corresponding to adjacent first doping regions 106 are separated from each other, so that when a test is performed on a first transistor corresponding to one of the first transistor regions 10 of a row of first transistor regions 10, there is no problem that electrons moving in the metal layer 105 above the first transistor to be tested are transmitted to the metal layer 105 above the adjacent first transistor, thereby preventing the occurrence of a coupling effect on the adjacent first transistor and further improving the parasitic leakage of the semiconductor test structure.

[0035] FIG. 5 is an exemplary diagram showing the configuration of another semiconductor layout structure according to one embodiment of the present invention. Referring to FIG. 5, in another embodiment, metal layers corresponding to adjacent first doping regions may not be separated.

[0036] In some embodiments, the metal layer 105 corresponding to the second transistor region 11 is located above the second gate structure 104. In this way, after manufacturing the semiconductor test structure based on the semiconductor layout structure, the metal layer 105 is electrically connected to the second gate, so that one side can transmit a driving signal for the second gate structure 104 to drive the second transistor through the metal layer 105, and the other side can perform an electrical characteristic test on the second transistor through the metal layer 105. In addition, the metal layer 105 located above the second gate structure 104 and the metal layer 105 located above the first transistor are isolated from each other, so that when the second transistor corresponding to the second transistor region 11 is tested, the metal layer 105 does not cause a coupling effect on the first transistor corresponding to the first transistor region 10. Specifically, because the metal layer 105 is electrically connected to the second gate structure 104, when the second transistor is turned on, electrons moving in the metal layer 105 electrically connected to the second gate structure 104 are not transmitted to the metal layer 105 electrically connected to the first transistor, thereby improving the coupling effect between the first transistor and the second transistor.

[0037] In some embodiments, the metal layers 105 located above adjacent second gate structures 104 are isolated from each other. That is, after the semiconductor test structure is manufactured based on the semiconductor layout structure, the metal layers 105 corresponding to adjacent second gate structures 104 are not connected to each other, so that when testing any of the second transistors in a row of second transistors, the metal layers 105 do not cause a coupling effect on the adjacent second transistors, for example, the gate voltage of the second gate structures 104 of the adjacent second transistors does not increase, thereby improving the parasitic leakage phenomenon of the semiconductor test structure.

[0038] 4, the second transistor region 11 further includes a third doping region 108, the third doping region 108 being located between adjacent second gate structures 104 as either a source region or a drain region of the second transistor region 11, the second doping region 107 being the other of the source region and the drain region of the second transistor region 11, the metal layer 105 corresponding to the second transistor region 11 being located above the third doping region 108, and the metal layer 105 corresponding to the second gate structure 104 and the metal layer 105 corresponding to the third doping region 108 being separated from each other. In some embodiments, when the second doping region 107 is the drain region of the second transistor region 11, the third doping region 108 can be the source region of the second transistor. In some embodiments, the third doped region 108 can be a common source region between the second transistor regions 11 corresponding to the adjacent second gate structures 104, i.e., by providing a few third doped regions 108 to configure a large number of second transistor regions 11, the size of the semiconductor layout structure can be reduced and the size of the manufactured semiconductor test structure can be reduced. Note that, in another embodiment, the second doped region 107 can be the source region of the second transistor region 11, and the third doped region 108 can be the drain region of the second transistor region 11.

[0039] When manufacturing the semiconductor test structure based on the semiconductor layout structure, the third doping region 108 is the common source of two adjacent second transistors. When an electrical characteristic test is performed on one of the second transistors, the second gate structure 104 of the second transistor turns on the second transistor based on the driving signal transmitted by the metal layer 105, and the metal layer 105 corresponding to the second gate structure 104 and the metal layer 105 corresponding to the third doping region 108 are separated from each other, so that the electrons or minority carriers moving in the second gate structure 104 are not transmitted to the third doping region 108 by the metal layer 105, and therefore no coupling effect occurs in the other second transistor sharing the third doping region 108, thereby improving the parasitic leakage of the semiconductor test structure.

[0040] 6 is a diagram illustrating the configuration of yet another semiconductor layout structure according to an embodiment of the present invention. Referring to FIG. 6 and FIG. 4, in some embodiments, the second gate structures 104 of the two second transistor regions 102 that do not share the third doping region 108 are provided opposite each other, and the metal layers 105 corresponding to the two opposite second gate structures 104 are connected, thereby reducing the difficulty of the manufacturing process of the actual metal layer 105. This is because, as the size of the semiconductor device becomes smaller, the size of the semiconductor layout structure also becomes smaller, so that the interval between the second gate structures 104 provided opposite each other in the two adjacent second transistors that do not share the third doping region 108 is small. By providing the metal layers 105 corresponding to the adjacent second gate structures 104 so that they are connected, the process window for manufacturing the metal layer 105 can be enlarged, which is advantageous for improving productivity.

[0041] In the semiconductor layout structure according to the above embodiment, the first active areas 101 corresponding to adjacent first transistor areas 10 are separated from each other, i.e., the adjacent first transistor areas 10 do not share the same first active area 101. As a result, in the manufactured semiconductor test structure, adjacent first transistors do not share the first active area 101. In other words, when an electrical characteristic test is performed on one first transistor, electrons moving in the first active area 101 corresponding to the first transistor are not moved to the first active area 101 corresponding to the adjacent first transistor. In other words, no coupling effect is caused by the first active area 101 to the adjacent first transistor, and the parasitic leakage phenomenon of the semiconductor test structure is improved.

[0042] Another embodiment of the present invention provides a semiconductor test structure, which can be manufactured by a semiconductor layout structure according to the above disclosed embodiment. The following provides a detailed description of the semiconductor test structure according to the another embodiment of the present invention.

[0043] The semiconductor test structure includes a first active area and a second active area adjacent to the first active area, and a first gate structure and a second gate structure, the first active area is provided with a plurality of spaced apart first transistors, the second active area is provided with a plurality of spaced apart second transistors, the first active areas corresponding to adjacent first transistors are separated from each other, the first gate structure extends in a first direction, the second gate structure is spaced apart in the first direction, the first gate structure and the second gate structure are adjacent to each other, the first gate structure corresponds to the first transistor, and the second gate structure corresponds to the second transistor.

[0044] By providing the first active regions between adjacent first transistors so as to be separated from each other, even if the first transistors have a shared gate structure, the first active regions between adjacent first transistors are not connected. Therefore, when testing one of the first transistors, no coupling effect is caused by the first active regions to the adjacent first transistor, thereby improving the parasitic leakage phenomenon of the semiconductor test structure.

[0045] FIG. 7 is an IV characteristic graph after an electrical characteristic test for a semiconductor structure, and FIG. 8 is an IV characteristic graph after an electrical characteristic test for a semiconductor structure according to an embodiment of the present invention. Referring to FIG. 7, curve 1 corresponds to a semiconductor structure in which a first active region is shared between adjacent first transistors, and referring to FIG. 8, curve 3 corresponds to a semiconductor structure in which the first active regions between adjacent first transistors are not connected. As can be seen by comparing curves 1 and 3, when the first active regions between adjacent first transistors are separated from each other, the leakage current of the semiconductor structure is significantly reduced.

[0046] In some embodiments, the substrate is a semiconductor substrate, and may be, for example, a silicon substrate, hi other embodiments, the semiconductor substrate material may be germanium, silicon germanium, silicon carbide, or the like.

[0047] The first and second active regions are located on a substrate, and in some embodiments, the first and second active regions are obtained by doping the substrate, and specifically, the first and second active regions may be doped with either P-type semiconductor ions or N-type semiconductor ions, and the P-type ions may be either boron ions, gallium ions, or indium ions, and the N-type ions may be either phosphorus ions, arsenic ions, or antimony ions. It should be noted that the embodiments of the present invention take as an example a first active region corresponding to a row of first transistors and a second active region corresponding to a row of second transistors adjacent to the first transistors, but in practice, the substrate may also include a plurality of first and second active regions.

[0048] In some embodiments, the first transistor and the second transistor may be a sub word-line driver (SWD) and may be used to provide a word-line voltage as a high voltage to drive the sub-word line, thus improving the delay of the word-line voltage. The first transistor and the second transistor may be configured to precharge the word line in response to a drive signal. Specifically, the first transistor and the second transistor have a source to which a drive voltage is provided and a drain connected to the sub-word line, and are turned on or off in response to the drive signal, thereby realizing the driving of the sub-word line.

[0049] The first active areas between the first transistors are separated from each other, i.e., each first transistor corresponds to one first active area, the first gate structure spans the first active areas of the first transistors to form a gate structure for the first transistors, i.e., the first transistors share one first gate structure, the second gate structures are arranged adjacent to the first gate structures, and each second gate structure is a gate structure for one second transistor.

[0050] The interval between the first active areas corresponding to the adjacent first transistors is controlled within a suitable range, and when one of the first transistors is tested, the active area corresponding to the first transistor does not cause a coupling effect to the first active area corresponding to the adjacent first transistor, thereby preventing the problem of high gate voltage of the adjacent first transistor caused by the coupling effect, and improving the parasitic leakage phenomenon. Furthermore, within this range, the interval between the first active areas corresponding to the adjacent first transistors is not too small, thereby reducing the difficulty of the actual manufacturing process and increasing the process window for manufacturing the first active areas separated from each other. On the other hand, within this range, the interval between the first active areas corresponding to the adjacent first transistors is not too large, ensuring a wide space for forming the first active areas, and the size of the first active area corresponding to the first transistor is not too small, thereby maintaining better performance of the first transistor.

[0051] In some embodiments, the semiconductor test structure further includes a metal layer, the metal layer being electrically connected to the first transistor and the second transistor, respectively, and the metal layer electrically connected to the first transistor and the metal layer electrically connected to the second transistor being separated from each other. The metal layer is used to derive electrical signals of the first transistor and the second transistor for testing, and in some embodiments, the metal layer can be electrically connected to the first transistor and the second transistor by an electrical contact structure. Specifically, the metal layer derives electrical signals of the first transistor and the second transistor to perform an electrical characteristic test, such as a resistance test, thereby determining whether an internal short circuit or an open circuit occurs in the semiconductor test structure. By providing the metal layer electrically connected to the first transistor and the metal layer electrically connected to the second transistor so as to be separated from each other, when testing either the first transistor or the second transistor, the two metal layers electrically connected to the first transistor and the second transistor are electrically connected to prevent a coupling effect from occurring in the adjacent first transistor and the second transistor, thereby improving the parasitic leakage phenomenon of the first transistor and the second transistor.

[0052] 7 and 8, curve 2 corresponds to a semiconductor structure connected to a metal layer electrically connected to a first transistor and a metal layer electrically connected to a second transistor, and referring to FIG. 8, curve 4 corresponds to a semiconductor structure in which the metal layer electrically connected to the first transistor and the metal layer electrically connected to the second transistor are separated from each other. By comparing curves 2 and 4, by isolating the metal layer corresponding to the first transistor and the metal layer corresponding to the second transistor from each other, the leakage current in the semiconductor structure is significantly reduced after the semiconductor structure is tested.

[0053] In some embodiments, the material of the metal layer may be either Cu, Al or W.

[0054] In some embodiments, the first transistor includes a first doped region and a second doped region, the first doped region being located on a side of the first transistor away from the second transistor as one of a source and a drain of the first transistor, the second doped region being located between the first transistor and the second transistor as the other of the source and drain of the first transistor, and a metal layer corresponding to the first transistor being electrically connected to the first doped region and the second doped region, respectively.

[0055] In some embodiments, the first doped region and the second doped region are located in the first active region, and in some embodiments, the ion doping type of the first doped region and the ion doping type of the second doped region are the same and the ion doping type of the first doped region is opposite to that of the substrate, and thus the first doped region and the second doped region and the substrate can respectively form a PN junction. Specifically, in some embodiments, the first doped region and the second doped region can be doped with N-type ions, and the substrate can be doped with P-type ions. In another embodiment, the first doped region and the second doped region can be doped with P-type ions, and the substrate can be doped with N-type ions. In some embodiments, the N-type ions can be at least one of arsenic ions, phosphorus ions, or antimony ions, and the P-type ions can be at least one of boron ions, indium ions, or gallium ions.

[0056] In some embodiments, the first doping region may be the source of the first transistor, the second doping region may be the drain of the first transistor, and the second doping region may further be the drain of the second transistor, i.e., the first transistor and the second transistor share one drain, thereby reducing the size of the semiconductor test structure. The metal layer is electrically connected to the first doping region, so that when the first doping region is used as the source of the first transistor, one can derive the electrical signal of the first transistor, and the other can supply an external electrical signal to the source of the first transistor through the metal layer to make the first transistor operate normally. The metal layer is further electrically connected to the second doping region, and when the second doping region is used as the drain of the first transistor and the second transistor, the metal layer can further be electrically connected to the corresponding sub-word line to realize driving of the first transistor and the second transistor to the sub-word line.

[0057] In some embodiments, the metal layer corresponding to the first doping region and the metal layer corresponding to the second doping region are separated from each other, and the metal layers corresponding to adjacent first doping regions are separated from each other. The metal layer corresponding to the first doping region and the metal layer corresponding to the second doping region are separated from each other, so that when the first doping region is the source of the first transistor and the second doping region is the drain of the first transistor, the metal layer electrically connected to the first doping region serves to provide a driving voltage to the source of the first transistor, and the metal layer electrically connected to the second doping region serves to drive the sub-word line, so that the electrical signals of the source and the drain do not interfere with each other.

[0058] In some embodiments, each first transistor corresponds to one first doping region, and the metal layers corresponding to adjacent first doping regions are separated from each other, so that when the first transistor is tested, the metal layers corresponding to adjacent first doping regions are electrically connected to each other, thereby preventing the problem of coupling effect in adjacent first transistors, thereby preventing an increase in the gate voltage of the adjacent first transistors and improving the parasitic leakage phenomenon.

[0059] In addition, in another embodiment, the metal layers corresponding to adjacent first doping regions may further be a continuous film layer structure, and the first doping regions of the multiple first transistors share the same metal layer. In this way, when the first doping regions are used as the sources of the first transistors, driving voltages can be input from any position node within the same metal layer, that is, driving voltages can be supplied simultaneously to the first doping regions corresponding to the multiple first transistors, so that the first transistors and the second transistors can have high operating efficiency.

[0060] In some embodiments, when the second doped region is the drain of the second transistor, considering that the drains of the first transistor and the second transistor are used for sub-word lines that are electrically connected to drive, in some embodiments, metal layers on the second doped region can be provided separately from each other, and in this way, the first transistor and the second transistor can each drive multiple sub-word lines.

[0061] In some embodiments, a metal layer corresponding to a second transistor is electrically connected to a second gate structure. One of them is that the metal layer can transmit a driving signal for the second gate structure to drive the second transistor, and the other is that the metal layer is used to perform an electrical property test on the second transistor. The metal layer electrically connected to the second gate structure and the metal layer electrically connected to the first transistor are isolated from each other, that is, when performing an electrical property test on the second transistor or the first transistor, no coupling effect is caused by the metal layer. For example, when performing an electrical property test on the first transistor, the first transistor needs to be turned on, and at this time, the channel between the first doping region and the second doping region of the first transistor is conducted, and the metal layer corresponding to the second gate structure and the metal layer corresponding to the first transistor are isolated from each other, so that the electrons moving in the metal layer electrically connected to the first transistor are not transmitted to the metal layer electrically connected to the second transistor, and thus no coupling effect is caused in the second transistor, that is, the gate voltage of the second gate structure in the second transistor is not increased by the metal layer electrically connected to the first transistor, thereby reducing the parasitic leakage.

[0062] Since each second gate structure is the gate structure of one second transistor, when the metal layer is electrically connected to the second gate structure, there may be a parasitic leakage between adjacent second transistors. In some embodiments, the metal layers corresponding to two adjacent second gate structures are separated from each other. In this way, when the electrical characteristics of one of the second transistors are tested, that is, when the second gate structure turns on the second transistor in response to the driving signal, the metal layers corresponding to the adjacent second gate structures are provided separated from each other, so that the coupling effect caused by the metal layer between the adjacent second gate structures is not generated, and the parasitic leakage phenomenon between the adjacent second transistors is improved.

[0063] In some embodiments, the second transistor includes a third doping region, the third doping region being located between adjacent second gate structures as one of the source and drain of the two adjacent second transistors, the second doping region further serving as the other of the source and drain of the second transistor, the metal layer corresponding to the second transistor being further electrically connected to the third doping region, and the metal layer corresponding to the second gate structure and the metal layer corresponding to the third doping region being separated from each other.

[0064] In some embodiments, a third doped region is located in the active region, and the ion doping type of the third doped region may be the same as the ion doping type of the first doped region and the second doped region.

[0065] In some embodiments, when the second doping region is the drain of the second transistor, the third doping region can be the source of the second transistor. Specifically, in some embodiments, the third doping region can be used as a common source between the second transistors corresponding to the adjacent second gate structures. That is, the second transistors corresponding to the second gate structures located on both sides of the third doping region share one source, and a plurality of second transistors are arranged at intervals in a row, and when the number of second transistors in one row is greater than two, the second gate structures of the two adjacent second transistors that do not share the third doping region are provided opposite each other. Furthermore, by using the second doping region as a common drain for the first transistor and the second transistor, many transistors can be formed by providing only a few doping regions, which is advantageous for space saving, and thus the semiconductor test structure can be made smaller. Note that, in another embodiment, the third doping region can be used as a common drain between the second transistors corresponding to the adjacent second gate structures, and the second doping region can be used as a common source for the first transistor and the second transistor.

[0066] In order to use the third doping region as a common source for two adjacent second transistors, the metal layer corresponding to the second gate structure and the metal layer corresponding to the third doping region are provided so as to be separated from each other, so that when an electrical characteristic test is performed on one of the second transistors, the metal layer corresponding to the second gate structure and the metal layer corresponding to the third doping region are electrically connected to each other, thereby preventing a problem of a coupling effect occurring in the adjacent second transistor. Specifically, when a test is performed on one of the second transistors, the second gate structure of the second transistor turns on the second transistor based on a drive signal transmitted from the metal layer, and since the metal layer corresponding to the second gate structure and the metal layer corresponding to the third doping region are separated from each other, electrons or minority carriers moving in the second gate structure are not transmitted to the third doping region by the metal layer, so that a coupling effect can be prevented from occurring in another second transistor sharing the third doping region with the second transistor.

[0067] In another embodiment, two adjacent second transistors constitute one second transistor group, and the second transistor group includes a third doping region, and the third doping region is located between adjacent second gate structures in the second transistor group as a source or drain of two adjacent second transistors in the second transistor group, and the metal layers corresponding to the two second gate structures provided opposite each other in the adjacent second transistor groups are connected. That is, two second transistors belonging to the same second transistor group share one third doping region. In two adjacent transistor groups, the second gate structures of two adjacent second transistors that do not share the third doping region are provided opposite each other, and the metal layers corresponding to the two opposing second gate structures are provided so as to be connected, which is advantageous in reducing the difficulty of the manufacturing process of the actual metal layer. This is because as the size of semiconductor devices becomes smaller, the feature size of semiconductor test structures also becomes smaller, thereby reducing the interval between the opposing second gate structures in two adjacent second transistors that do not share the third doping region. Therefore, in the manufacturing process of the metal layer corresponding to the actual second gate structure, by arranging the metal layers corresponding to adjacent second gate structures so as to be connected, the process window for manufacturing the metal layer can be enlarged, which contributes to improving productivity.

[0068] In another embodiment, when two second transistors in a second transistor group are provided to share one third doping region, the metal layers corresponding to two opposing second gate structures in adjacent second transistor groups can be provided to be separated. In this way, when one of two second transistors not sharing the third doping region is turned on for testing, the gate voltage of the other second transistor is not increased by the metal layer corresponding to the second gate structure, thereby reducing parasitic leakage.

[0069] Considering the actual manufacturing process, in some embodiments, the distance between the metal layers corresponding to the two opposing second gate structures is not too small, so that the difficulty of the actual manufacturing process can be reduced. This is because the two second gate structures are arranged opposite to each other and the size of the entire semiconductor test structure is small, so that the actual distance between the two second gate structures is small. When the metal layers corresponding to the opposing second gate structures are actually manufactured, if the distance between the corresponding metal layers is too small, the second gate structures may be damaged during the process, and the manufacturing process becomes more difficult. Therefore, if the distance between the metal layers corresponding to the opposing second gate structures is large, the difficulty of the process can be reduced. On the other hand, the distance between the metal layers corresponding to the second gate structures needs to be similar or equal to the distance between the two opposing second gate structures, so that the distance between the metal layers corresponding to the two opposing second gate structures needs to be not too large, so that the semiconductor test structure can be miniaturized.

[0070] In some embodiments, the active areas between adjacent second transistor groups are separated from each other. In the same second transistor group, two adjacent second transistors share the third doping region, so that it is necessary to connect the active areas between the two second transistors sharing the third doping region. For two second transistors that do not share the third doping region, two second gate structures are provided opposite to each other, i.e., no third doping region is provided between the two second gate structures, so that the active areas between the two opposite second gate structures are provided apart from each other, so that no coupling effect is caused by the active areas between the second transistors that do not share the third doping region, and the parasitic leakage between adjacent second transistors is further improved.

[0071] In the semiconductor test structure according to the above embodiment, the active regions between adjacent first transistors are separated from each other. In this way, even if the first transistors have a shared gate structure, the first active regions between adjacent first transistors are not connected. Therefore, when testing one of the first transistors, no coupling effect is caused by the first active regions to the adjacent first transistor, thereby improving the parasitic leakage phenomenon of the semiconductor test structure.

[0072] Those skilled in the art will understand that the above-mentioned embodiments are specific examples for realizing the present invention, but in actual application, various changes can be made to the form and details without departing from the spirit and scope of the present invention. Those skilled in the art can make all changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention shall comply with the scope limited by the claims.

Claims

1. A semiconductor layout structure, comprising: an active layer and a gate layer; the active layer includes a first active region and a second active region adjacent to the first active region, the first active region includes a plurality of spaced apart first transistor regions, the second active region includes a plurality of spaced apart second transistor regions, and the active layer corresponding to adjacent first transistor regions are separated from each other; the gate layer is located above the active layer, the gate layer including at least one first gate structure extending in a first direction and a plurality of second gate structures spaced apart along the first direction, the first gate structure being adjacent to the second gate structure, the first gate structure corresponding to the first transistor region, and the second gate structure corresponding to the second transistor region; the first transistor region includes a first doping region and a second doping region, and the second transistor region includes a third doping region; The semiconductor layout structure further includes a metal layer located above the first doped region, a metal layer located above the second doped region, a metal layer located above the second gate structure, and a metal layer located above the third doped region, wherein the metal layer located above the first doped region, the metal layer located above the second gate structure, and the metal layer located above the third doped region are separated from each other; the second transistor region includes a group of second transistors adjacent to each other, the second transistor group including two second transistors adjacent to each other; the third doping region is located between the second gate structures of adjacent second transistors in the second transistor group and serves as a source region or a drain region of the adjacent second transistors in the second transistor group; a metal layer located above the second gate structure and a metal layer located above the third doping region are separated from each other; a metal layer located above the second gate structure and a metal layer located above the third doping region are provided along the first direction, and metal layers located above the second gate structures of two of the second transistors that are provided opposite to each other in two adjacent second transistor groups are connected to each other. Semiconductor layout structure.

2. The first doping region is located on a side of the first transistor region away from the second transistor region as one of a source region and a drain region of the first transistor region, and the second doping region is located between the first transistor region and the second transistor region as the other of the source region and the drain region of the first transistor region. The semiconductor layout structure of claim 1 .

3. A metal layer located above the first doping region and a metal layer located above the second doping region are separated from each other, and metal layers located above adjacent first doping regions are separated from each other. The semiconductor layout structure of claim 2 .

4. metal layers located above the second gate structures of adjacent second transistors in the second transistor group are separated from each other; The semiconductor layout structure of claim 1 .

5. When the third doped region is a source region of an adjacent second transistor in the second transistor group, the second doped region is further a drain region of the second transistor region; When the third doped region is a drain region of an adjacent second transistor in the second transistor group, the second doped region is further a source region of the second transistor region. The semiconductor layout structure of claim 4.

6. A semiconductor test structure, comprising: a first active area; a second active area adjacent to the first active area; and a first gate structure and a second gate structure; A plurality of spaced apart first transistors are provided in the first active region, a plurality of spaced apart second transistors are provided in the second active region, and the first active regions corresponding to adjacent first transistors are separated from each other; the first gate structure extends in a first direction, the second gate structure is spaced apart in the first direction, the first gate structure is adjacent to the second gate structure, the first gate structure corresponds to the first transistor, and the second gate structure corresponds to the second transistor; the first transistor includes a first doping region and a second doping region, two adjacent second transistors constitute one second transistor group, the second transistor group includes a third doping region; The semiconductor test structure further includes a metal layer electrically connected to the first doped region, a metal layer electrically connected to the second doped region, a metal layer electrically connected to the second gate structure, and a metal layer electrically connected to the third doped region, wherein the metal layer electrically connected to the first doped region, the metal layer electrically connected to the second gate structure, and the metal layer electrically connected to the third doped region are separated from each other; the third doping region is located between the second gate structures adjacent to each other in the second transistor group, and serves as a source or a drain of two adjacent second transistors in the second transistor group; a metal layer electrically connected to the second gate structure and a metal layer electrically connected to the third doping region are separated from each other; a metal layer electrically connected to the second gate structure and a metal layer electrically connected to the third doping region are provided along the first direction, and a metal layer electrically connected to two second gate structures opposed to each other in adjacent second transistor groups is connected to each other; Semiconductor test structures.

7. The first doping region is located on a side of the first transistor away from the second transistor as one of a source and a drain of the first transistor, and the second doping region is located between the first transistor and the second transistor as the other of a source and a drain of the first transistor.

7. The semiconductor test structure of claim 6.

8. a metal layer electrically connected to the first doping region and a metal layer electrically connected to the second doping region are separated from each other, and adjacent metal layers electrically connected to the first doping region are separated from each other; 8. The semiconductor test structure of claim 7.

9. The metal layers electrically connected to the second gate structures of two adjacent second transistors in the second transistor group are separated from each other.

7. The semiconductor test structure of claim 6.

10. When the third doped region is configured as a source of two adjacent second transistors in the second transistor group, the second doped region is further configured as a drain of the second transistor, and when the third doped region is configured as a drain of two adjacent second transistors in the second transistor group, the second doped region is further configured as a source of the second transistor.

10. The semiconductor test structure of claim 9.

Images