Miller clamp circuit

Abstract

A mirror clamp circuit according to the present invention has: a comparator having a first input terminal that can be connected to a first control terminal of a transistor and a second input terminal to which a reference voltage is applied, said transistor having a first terminal to which a reference potential is applied and said first control terminal connected to one end of a resistor the other end of which receives an output voltage; a transistor switch that has a second control terminal to which a control terminal voltage based on a comparison signal output from the comparator is applied and that is inserted between the first control terminal and the reference potential; an OR circuit to which a signal based on the control terminal voltage and the output voltage are input; and a current supply unit for changing the current level of a current supplied to the comparator on the basis of an output from the OR circuit.

Description

[Technical field]

[0001] The present invention relates to a Miller clamp circuit that suppresses erroneous turn-on of a transistor. [Background technology]

[0002] Conventionally, there is a method called Miller clamp as a method for suppressing erroneous turning on of transistors such as MOSFETs (metal-oxide-semiconductor field-effect transistors) and IGBTs (insulated gate bipolar transistors). In Miller clamp, when the transistor is a MOSFET, a switch for Miller clamp is inserted between the gate of the transistor having a source to which a reference potential is applied and the reference potential. The switch is, for example, a MOSFET. By turning the switch on when the transistor is off, the Vgs (gate-source voltage) of the transistor is forced to be approximately 0V, thereby suppressing the rise in the gate voltage of the transistor. Note that when the transistor is an IGBT, a switch is inserted between the gate of the transistor having an emitter to which a reference potential is applied and the reference potential.

[0003] In addition, in the Miller clamp, the switch is turned on using a comparator that compares the gate voltage of the transistor with a predetermined reference voltage. Note that such a Miller clamp is disclosed in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-171720 A (Figure 9) Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional Miller clamp configuration, a relatively large current is constantly supplied to the comparator in order to increase the operating speed, which poses a problem of increased power consumption.

[0006] In view of the above circumstances, an object of the present invention is to provide a Miller clamp circuit that enables reduction in power consumption. [Means for solving the problem]

[0007] A Miller clamp circuit according to one aspect of the present invention includes: a transistor having a first control terminal connected to one end of a resistor to which the output voltage is applied and a first terminal to which a reference potential is applied, the transistor having a first input terminal connectable to the first control terminal and a second input terminal to which a reference voltage is applied; a transistor switch having a second control end to which a control end voltage based on a comparison signal output from the comparator is applied, the transistor switch being inserted between the first control end and the reference potential; an OR circuit to which a signal based on the control end voltage and the output voltage are input; a current supply unit that changes the amount of current supplied to the comparator based on an output of the OR circuit; The first configuration has the above structure.

[0008] Furthermore, in the above first configuration, a configuration may be made in which a latch section is provided that latches the control end voltage at a low level when the output voltage is at a high level (second configuration).

[0009] In addition, in the above first or second configuration, a configuration may be made which includes a delay circuit that delays the control end voltage and outputs a delayed signal, and the signal based on the control end voltage is the delayed signal (third configuration).

[0010] In any one of the first to third configurations, the current supply unit A first constant current source; a first current mirror that generates a first output current based on a first input current generated by the first constant current source; a second current mirror that generates a second output current based on the first input current; a changeover switch that is disposed in a path through which the second output current flows and that is switched on and off based on an output of the OR circuit; having When the changeover switch is in an on state, a current may be supplied to the comparator based on a current generated by combining the first output current and the second output current (fourth configuration).

[0011] In the fourth configuration, the first current mirror, the second current mirror, and the changeover switch may be configured using PMOS transistors (fifth configuration).

[0012] In any one of the first to fifth configurations, the transistor switch may be an NMOS transistor (sixth configuration).

[0013] Furthermore, an IC package according to one embodiment of the present invention is configured to have a Miller clamp circuit of any of the above configurations, an output terminal capable of outputting the output voltage to the outside, a Miller clamp terminal to which the first control terminal can be externally connected, and a reference potential terminal to which the reference potential can be applied (seventh configuration).

[0014] Furthermore, in the seventh configuration, the eighth configuration may further include a pulse generator that generates a pulse based on an input signal, a logic unit, an isolation transformer that transmits the pulse to the logic unit, and a switching arm that is configured with a switch element connected in series between a power supply voltage and the reference potential and that generates the output voltage when driven by the logic unit. Effect of the Invention

[0015] The Miller clamp circuit of the present invention makes it possible to reduce power consumption. [Brief description of the drawings]

[0016] [Figure 1] FIG. 2 is a diagram showing a configuration of a gate driver according to an exemplary embodiment of the present invention. [Diagram 2] 4 is a diagram illustrating a specific example of a circuit configuration of a comparator and a current supply unit; FIG. [Diagram 3] 1 is a timing chart illustrating an example of the operation of a Miller clamp circuit according to an exemplary embodiment of the present invention. [Figure 4] FIG. 13 is a diagram showing a configuration of a gate driver according to a modified example. [Diagram 5] 13 is a timing chart showing an example of the operation of a Miller clamp circuit according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings.

[0018] <Gate driver configuration> 1 is a diagram showing a configuration of a gate driver 10 according to an exemplary embodiment of the present invention. As shown in FIG 1, the gate driver 10 is a device that drives the gate of an NMOS transistor M1.

[0019] The gate driver 10 has a primary side circuit 1, a secondary side circuit 2, and an insulating transformer 3. The gate driver 10 is also an IC package having a GND1 terminal, a VCC1 terminal, an INA terminal, an INB terminal, a GND2 terminal (reference potential terminal), a VCC2 terminal, an OUT terminal (output terminal), and an MC terminal (Miller clamp terminal), which are external terminals (lead terminals) for establishing electrical connection with the outside.

[0020] The primary side circuit 1 has a first Schmitt trigger 11, a second Schmitt trigger 12, an AND circuit 13, a pulse generator 14, and a first UVLO (Under Voltage Lock Out) unit 15.

[0021] The secondary side circuit 2 has a logic section 21, a PMOS transistor 22, an NMOS transistor 23, a Miller clamp circuit 24, a second UVLO section 25, and an OVP (overvoltage protection) section .

[0022] The isolation transformer 3 is provided to connect the primary circuit 1 and the secondary circuit 2. The isolation transformer 3 transmits a signal from the primary circuit 1 to the secondary circuit 2 while insulating the primary circuit 1 from the secondary circuit 2.

[0023] The first UVLO unit 15 monitors the power supply voltage Vcc1 applied to the VCC1 terminal, and shuts down the primary side circuit 1 when the power supply voltage Vcc1 falls below a predetermined voltage.

[0024] The first Schmitt trigger 11 transmits a first input signal In1 externally input to an INA terminal to a first input terminal of the AND circuit 13. The second Schmitt trigger 12 transmits a second input signal In2 externally input to an INB terminal to a second input terminal of the AND circuit 13.

[0025] The AND circuit 13 performs a logical AND operation on the level of the signal input to the first input terminal and the inverted level of the signal input to the second input terminal. Therefore, when the first input signal In1 is low and the second input signal In2 is low, or when the first input signal In1 is low and the second input signal In2 is high, or when the first input signal In1 is high and the second input signal In2 is high, the output of the AND circuit 13 is low, and when the first input signal In1 is high and the second input signal In2 is low, the output of the AND circuit 13 is high.

[0026] The pulse generator 14 is triggered by the fall of the output of the AND circuit 13 from high level to low level, and generates a pulse narrower than the output of the AND circuit 13 and outputs it to the primary side of the isolation transformer 3. A change in current due to the pulse supplied to the primary side of the isolation transformer 3 generates a current on the secondary side of the isolation transformer 3, which is supplied to the logic unit 21. In this case, a high-level signal is output from the logic unit 21 and input to the gate of the PMOS transistor 22 and the gate of the NMOS transistor 23.

[0027] Here, a PMOS transistor 22 (switch element) and an NMOS transistor 23 (switch element) are connected in series between a power supply voltage Vcc2 applied to a VCC2 terminal and a second ground GND2 applied to a GND2 terminal to form a switching arm. Specifically, the source of the PMOS transistor 22 is connected to an application terminal of the power supply voltage Vcc2. The drain of the PMOS transistor 22 is connected to a drain of the NMOS transistor 23 at a node N2. The source of the NMOS transistor 23 is connected to an application terminal of the second ground GND2.

[0028] A node N 1 , to which the gate of the PMOS transistor 22 and the gate of the NMOS transistor 23 are connected, is connected to the output terminal of the logic section 21 .

[0029] The node N2 is connected to the OUT terminal. One end of a resistor R1 is externally connected to the OUT terminal. The other end of the resistor R1 is connected to the gate (first control end) of an NMOS transistor M1. The source (first end) of the NMOS transistor M1 is externally connected to the GND2 terminal. Note that the second ground GND2 serving as the reference potential of the secondary side circuit 2 is different from the first ground GND1 applied to the GND1 terminal and serving as the reference potential of the primary side circuit 1.

[0030] Here, as described above, when a high-level signal is applied to the node N1 from the logic unit 21, the PMOS transistor 22 is turned off, the NMOS transistor 23 is turned on, and the output voltage Out, which is the voltage of the OUT terminal, becomes the second ground GND2 (low level). As a result, the NMOS transistor M1 is turned off.

[0031] Meanwhile, the pulse generator 14, triggered by the rise of the output of the AND circuit 13 from low level to high level, generates a pulse narrower than the output of the AND circuit 13 and outputs it to the primary side of the isolation transformer 3. A change in current due to the pulse supplied to the primary side of the isolation transformer 3 generates a current on the secondary side of the isolation transformer 3, which is supplied to the logic unit 21. In this case, a low-level signal is output from the logic unit 21 and applied to the node N1.

[0032] In this case, the PMOS transistor 22 is turned on, the NMOS transistor 23 is turned off, and the output voltage Out becomes the power supply voltage Vcc2 (high level), which causes the NMOS transistor M1 to be turned on.

[0033] The transistor to be driven by the gate driver 10 may be an IGBT instead of the NMOS transistor M1. In this case, the other end of the resistor R1 is connected to the gate of the IGBT, and the GND2 terminal is connected to the emitter of the IGBT.

[0034] The second UVLO unit 25 monitors the power supply voltage Vcc2 applied to the VCC2 terminal, and when the power supply voltage Vcc2 falls below a predetermined voltage, shuts down the secondary side circuit 2. The OVP unit 26 is a circuit that detects an overvoltage of the power supply voltage Vcc2.

[0035] <Miller clamp circuit configuration> Next, we will describe the configuration of the Miller clamp circuit 24 in the secondary side circuit 2. The Miller clamp circuit 24 is a circuit that suppresses erroneous ON of the NMOS transistor M1 in the OFF state.

[0036] As shown in FIG. 1, the Miller clamp circuit 24 includes a comparator 241, a latch unit 242, an NMOS switch 243, an OR circuit 244, and a current supply unit 245.

[0037] The MC terminal is externally connected to a node N3 to which the other end of the resistor R1 and the gate of the NMOS transistor M1 are connected. The inverting input terminal (-) of the comparator 241 is connected to the MC terminal. As a result, the voltage of the MC terminal, i.e., the first gate voltage Gt of the NMOS transistor M1, is applied to the inverting input terminal (-) of the comparator 241. A predetermined reference voltage Vref is applied to the non-inverting input terminal (+) of the comparator 241.

[0038] The comparator 241 outputs a comparison signal Cmp as a comparison result between the first gate voltage Gt and the reference voltage Vref to the latch unit 242. Depending on the voltage level of the node N1, i.e., the level of the output voltage Out, the latch unit 242 switches between outputting the comparison signal Cmp at its original level as the second gate voltage Mcg, or latching and outputting the second gate voltage Mcg at a low level regardless of the comparison signal Cmp.

[0039] The NMOS switch 243, which is an NMOS transistor, is inserted between the MC terminal and the GND2 terminal. Specifically, the drain of the NMOS switch 243 is connected to the MC terminal. The source of the NMOS switch 243 is connected to the GND2 terminal. That is, the NMOS switch 243 is inserted between the gate of the NMOS transistor M1 and the second ground GND2 (reference potential).

[0040] A second gate voltage (control end voltage) Mcg is applied to the gate (second control end) of the NMOS switch 243. The second gate voltage Mcg is input to a first input end of the OR circuit 244, and the output voltage Out is input to a second input end of the OR circuit 244. The current supply unit 245 switches between supplying a current of a reference current amount to the comparator 241 and supplying a current of an amount increased from the reference current amount to the comparator 241, according to the output level of the OR circuit 244.

[0041] <Comparator and current supply configuration> FIG. 2 is a diagram showing a specific example of the circuit configuration of the comparator 241 and the current supply unit 245. As shown in FIG.

[0042] The comparator 241 includes PMOS transistors 241A and 241B, a current mirror CM241, a buffer BF, a clamper CLP, and voltage dividing resistors R21 to R24.

[0043] The source of the PMOS transistor 241A is connected to the current supply unit 245. A predetermined reference voltage REF obtained by dividing a voltage (hereinafter, referred to as an upper voltage) that is higher than the second ground GND2 by a predetermined voltage (for example, 5 V) using voltage dividing resistors R21 and R22 is applied to the gate of the PMOS transistor 241A.

[0044] The source of the PMOS transistor 241B is connected to the current supply unit 245. A divided voltage McD obtained by dividing the first gate voltage Gt (FIG. 1) by voltage dividing resistors R23 and R24 is applied to the gate of the PMOS transistor 241B.

[0045] The source and gate of the clamper CLP as a PMOS transistor are connected to the upper voltage application terminal, and the drain of the clamper CLP is connected to the gate of the PMOS transistor 241B.

[0046] The current mirror CM241 is composed of NMOS transistors N1 and N2. More specifically, the drain of the NMOS transistor N1 is shorted to the gate of the NMOS transistor N1. The gate of the NMOS transistor N1 is connected to the gate of the NMOS transistor N2. The sources of the NMOS transistors N1 and N2 are connected to the application terminal of the second ground GND2.

[0047] The drain of the PMOS transistor 241A is connected to the drain of the NMOS transistor N1. A signal generated at a node N241 where the drain of the PMOS transistor 241B and the drain of the NMOS transistor N2 are connected is output as a comparison signal Cmp (FIG. 1) via a buffer BF.

[0048] Moreover, the current supply unit 245 has a constant current source 245A, a PMOS transistor (changeover switch) 245C, a current mirror CM1 formed by a PMOS transistor, and a current mirror CM2 formed by a PMOS transistor.

[0049] The current mirror CM1 has a PMOS transistor PM1 as an input-side transistor, and multiplies the input current I1 generated by the constant current source 245A by 1 and outputs the multiplied current as an output current I2.

[0050] The current mirror CM2 has a PMOS transistor PM1 as an input transistor, and outputs the input current I1 multiplied by X (X>1) as an output current I3. However, the drain of the PMOS transistor 245C is connected to the source of the PMOS transistor PM2 on the output side of the current mirror CM2, and the source of the PMOS transistor 245C is connected to the application terminal of the upper voltage. The output signal of the OR circuit 244 is applied to the gate of the PMOS transistor 245C. Therefore, when the output of the OR circuit 244 is at a low level and the PMOS transistor 245C is in an on state, the output current I3 is generated. When the output of the OR circuit 244 is at a high level and the PMOS transistor 245C is in an off state, the output current I3 is not generated.

[0051] The output current I2 and the output current I3 are combined to generate the supply current I4. However, if the output current I3 is not generated, the output current I2 becomes the supply current I4 as it is. The supply current I4 is distributed and supplied to the PMOS transistors 241A and 241B.

[0052] Here, the distribution of the supply current I4 to the currents flowing through the PMOS transistors 241A and 241B changes according to the reference voltage REF and the divided voltage McD.

[0053] When the divided voltage McD is lower than the reference voltage REF, a larger current flows through the PMOS transistor 241B than through the PMOS transistor 241A, and the comparison signal Cmp becomes high level.

[0054] On the other hand, when the divided voltage McD is higher than the reference voltage REF, a larger current flows through the PMOS transistor 241A than through the PMOS transistor 241B, and the comparison signal Cmp becomes low level.

[0055] Therefore, in the configuration shown in FIG. 1 described above, the reference voltage Vref that the comparator 241 compares with the first gate voltage Gt is defined by the reference voltage REF and the resistor division ratio for generating the divided voltage McD.

[0056] When the PMOS transistor 245C is in the off state due to the output of the OR circuit 244, the output current I3 is not generated, and therefore the supply current I4 having a reference current amount generated based on the output current I2 is distributed and supplied to the PMOS transistors 241A and 241B.

[0057] On the other hand, when the PMOS transistor 245C is turned on by the output of the OR circuit 244, the output current I3 is generated, and the supply current I4, which is increased from the reference current generated by combining the output current I2 with I3, is distributed and supplied to the PMOS transistors 241A and 241B. This increases the operating speed of the comparator 241.

[0058] <Miller clamp circuit operation> Next, the operation of the Miller clamp circuit 24 will be described based on the configuration of Fig. 1 and the timing chart shown in Fig. 3. In Fig. 3, from the top, the output voltage Out, the first gate voltage Gt, the comparison signal Cmp, the second gate voltage Mcg, the OR output A which is the output of the OR circuit 244, and the supply current I from the current supply unit 245 are shown. In the configuration shown in Fig. 2, the supply current I corresponds to the supply current I4.

[0059] In FIG. 3, immediately before the timing t1 when the output voltage Out switches from high level to low level, the first gate voltage Gt is at high level, and therefore the comparison signal Cmp is at low level. Also, if the output voltage Out is at high level, and the NMOS switch 243 is on, an overcurrent flows from the OUT terminal to the NMOS switch 243 via the resistor R1 and the MC terminal, so it is desirable to turn the NMOS switch 243 off. Therefore, when the output voltage Out is at high level, the second gate voltage Mcg is latched to low level by the latch unit 242. Also, since the output voltage Out is at high level, the OR output A is at high level. As a result, the PMOS transistor 245C in FIG. 2 is off, and the supply current I is at the reference level.

[0060] Then, when the output voltage Out switches from high level to low level at timing t1, the first gate voltage Gt starts to drop more slowly than the output voltage Out due to the resistor R1. Also, when the output voltage Out becomes low level, the latch unit 242 outputs the level of the comparison signal Cmp as it is as the second gate voltage Mcg.

[0061] Therefore, the output voltage Out and the second gate voltage Mcg are both at low level, and the OR output A is at low level. As a result, the PMOS transistor 245C in Fig. 2 is turned on, and the supply current I is at a level increased from the reference level. Therefore, the operating speed of the comparator 241 can be increased in advance in preparation for the comparator 241 to detect that the first gate voltage Gt has reached the reference voltage Vref due to a drop in the first gate voltage Gt.

[0062] After that, when the first gate voltage Gt drops to the reference voltage Vref at timing t2, the comparator 241 sets the comparison signal Cmp to high level, and the second gate voltage Mcg is also switched to high level. This turns on the NMOS switch 243, forcing the Vgs of the NMOS transistor M1 to approximately 0V, and suppresses the gate voltage of the NMOS transistor M1 from rising. This makes it possible to suppress erroneous turning on of the NMOS transistor M1.

[0063] Furthermore, since the second gate voltage Mcg becomes high level, the OR output A becomes high level and the supply current I is reduced to the reference level.

[0064] After timing t2, the first gate voltage Gt drops to a low level.

[0065] After that, when the output voltage Out switches from low level to high level at timing t3, the first gate voltage Gt starts to rise gradually, and as described above, the second gate voltage Mcg is latched to low level by the latch unit 242. This turns off the NMOS switch 243. Also, since the output voltage Out is at high level, the OR output A is set to high level, and the supply current I is set to the reference level.

[0066] Thereafter, at time t4, when the first gate voltage Gt rises and reaches the reference voltage Vref, the comparison signal Cmp switches to a low level. After time t4, the first gate voltage Gt rises and reaches a high level.

[0067] In this way, the supply current I is increased only during the limited period (the period from timing t1 to t2) when the output voltage Out and the second gate voltage Mcg are both at a low level, making it possible to reduce power consumption while improving the operating speed of the comparator 241 only when necessary.

[0068] <Modification> FIG. 4 is a diagram showing a configuration of a gate driver 10 including a Miller clamp circuit 24X according to a modification of the above-described embodiment.

[0069] The difference between the configuration of the Miller clamp circuit 24X shown in FIG. 4 and the embodiment described above (FIG. 1) is that the Miller clamp circuit 24X includes a delay circuit 246.

[0070] More specifically, the delay circuit 246 is disposed after the latch unit 242 , delays the second gate voltage Mcg output from the latch unit 242 , and outputs the delayed signal Dly to the first input terminal of the OR circuit 244 .

[0071] FIG. 5 is a timing chart showing the operation of the Miller clamp circuit 24X according to this modified example.

[0072] 5, when the output voltage Out switches from high to low at timing t1, the OR output A of the OR circuit 244 switches from high to low, and the supply current I is increased from the reference level. After that, when the output voltage Out drops and reaches the reference voltage Vref at timing t2, the comparison signal Cmp switches to high, and the second gate voltage Mcg switches to high. This turns on the NMOS switch 243.

[0073] After that, at timing t21, which is delayed by the delay time Td from timing t2, the delay signal Dly switches to a high level, causing the OR output A to switch to a high level, and the supply current I drops to the reference level.

[0074] 5, the delay time Td is set to be longer than the time Tgt required for the first gate voltage Gt to fall from the reference voltage Vref to a low level, thereby making it possible to stabilize the supply current I without change until the first gate voltage Gt is completely switched to a low level.

[0075] <Other> It should be noted that the above-described embodiments are illustrative in all respects and should not be considered as limiting, and the technical scope of the present invention is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that are equivalent in meaning and scope to the claims. [Industrial Applicability]

[0076] The present invention can be used in, for example, a gate driver. [Explanation of symbols]

[0077] 10 Gate Driver 1 Primary side circuit 11 First Schmitt Trigger 12 Second Schmitt Trigger 13 AND Circuit 14 Pulse Generator 15 1st UVLO section 2 Secondary circuit 21 Logic Section 22 PMOS transistor 23 NMOS transistor 24 Miller clamp circuit 241 Comparator 242 Latch section 243 NMOS Switch 244 OR Circuit 245 Current supply section 246 Delay Circuit 25 2nd UVLO section 26 OVP section R1 Resistor M1 NMOS transistor

Claims

1. a transistor having a first control terminal connected to one end of a resistor to which an output voltage is applied and a first terminal to which a reference potential is applied, the transistor having a first input terminal connectable to the first control terminal and a second input terminal to which a reference voltage is applied; a transistor switch having a second control end to which a control end voltage based on a comparison signal output from the comparator is applied, the transistor switch being inserted between the first control end and the reference potential; an OR circuit to which a signal based on the control end voltage and the output voltage are input; a current supply unit that changes the amount of current supplied to the comparator based on an output of the OR circuit; having The current supply unit sets the supply current of the comparator to a level higher than a reference level when the output of the OR circuit is at a low level.

2. The Miller clamp circuit according to claim 1 , further comprising a latch section that latches the control end voltage at a low level when the output voltage is at a high level.

3. a delay circuit for delaying the control end voltage and outputting a delayed signal; The Miller clamp circuit according to claim 1 , wherein the signal based on the control end voltage is the delayed signal.

4. The current supply unit includes: A first constant current source; a first current mirror that generates a first output current based on a first input current generated by the first constant current source; a second current mirror that generates a second output current based on the first input current; a changeover switch that is disposed in a path through which the second output current flows and that is switched on and off based on an output of the OR circuit; having 4. The Miller clamp circuit according to claim 1, wherein when the changeover switch is in an on state, a current is supplied to the comparator based on a current generated by combining the first output current and the second output current.

5. 5. The Miller clamp circuit according to claim 4, wherein the first current mirror, the second current mirror, and the changeover switch are configured with PMOS transistors.

6. The Miller clamp circuit of claim 1 , wherein the transistor switch is an NMOS transistor.

7. A Miller clamp circuit according to any one of claims 1 to 6, an output terminal capable of outputting the output voltage to an outside; a Miller clamp terminal to which the first control end can be externally connected; a reference potential terminal to which the reference potential can be applied; The IC package has

8. A pulse generator that generates a pulse based on an input signal; The logic section and an isolation transformer that transmits the pulse to the logic unit; a switching arm including a switch element connected in series between a power supply voltage and the reference potential, the switching arm being driven by the logic unit to generate the output voltage; 8. The IC package of claim 7, comprising:

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