Semiconductor device and electronic device

Abstract

To provide a technology advantageous for miniaturizing a semiconductor device while providing ESD resistance. [Solution] A semiconductor device has a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and an electronic component, the interconnect structure including a pad region including a pad, and a circuit region, the pad region and the circuit region each including a plurality of interconnect layers, an interlayer insulating film disposed between the plurality of interconnect layers, and a via plug connecting the plurality of interconnect layers, the electronic component being an active element, the electronic component being electrically connected to the pad, and the electronic component being disposed in the circuit region and above an upper surface of the semiconductor substrate.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices include an ESD protection circuit for protecting electronic circuits disposed therein from noise such as ESD (Electro-Static Discharge).

[0003] Patent Document 1 describes an ESD protection circuit disposed between two bonding pads. In the ESD protection circuit ESD described in Patent Document 1, a resistor R1 and a capacitor C1 are connected in series between a power supply voltage VCC and a reference potential VSS, and an input part of an inverter Iv1 is connected to a connection part between the resistor R1 and the capacitor C1. The inverter Iv1 is configured by connecting a P-channel MOS transistor T1 and an N-channel MOS transistor T2 in series between a power supply voltage VCC and a reference potential VSS. The output part of the inverter Iv1 is connected to a gate of a clamping transistor T3 made of an N-channel MOS. One end of the source / drain of the transistor T3 is connected to the power supply voltage VCC, and the other end of the source / drain of the transistor T3 is connected to the reference potential VSS. The gate of the transistor T3 is connected to the reference potential VSS via a resistor R2, and a parasitic diode DP is formed at a junction part between the well region and the source of the transistor T3. In addition, a diode D1 is connected between the power supply voltage VCC and the reference potential VSS. In general, an ESD protection circuit built into a semiconductor device has a complex configuration and can occupy a large area in the semiconductor device, which leads to an increase in the size of the semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-88652 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a technique that is advantageous for miniaturizing a semiconductor device while providing ESD resistance. [Means for solving the problem]

[0006] A first aspect of the present invention relates to a semiconductor device having a semiconductor substrate, a wiring structure arranged on the semiconductor substrate, and an electronic component, wherein in the semiconductor device, the wiring structure includes a pad region including a pad, and a circuit region, each of the pad region and the circuit region includes a plurality of wiring layers, an interlayer insulating film arranged between the plurality of wiring layers, and a via plug connecting the plurality of wiring layers to each other, the electronic component is an active element, the electronic component is electrically connected to the pad, and the electronic component is arranged in the circuit region and above an upper surface of the semiconductor substrate.

[0007] A second aspect of the present invention relates to an electronic device, the electronic device including the semiconductor device according to the first aspect. Effect of the Invention

[0008] According to the present invention, a technique is provided that is advantageous for miniaturizing a semiconductor device while providing ESD resistance. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view illustrating a schematic configuration of a semiconductor device according to an embodiment; [Diagram 2] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to an embodiment; [Diagram 3] FIG. 2 is a diagram illustrating an equivalent circuit of a portion of a semiconductor device according to an embodiment; [Figure 4] 1A is a diagram showing a CAD layout of a conventional ESD protection circuit, and FIG. 1B is a diagram showing a schematic diagram of the CAD layout of an electronic component according to an embodiment of the present invention. [Diagram 5] 1 is a graph showing the results of an approximate calculation of the relationship between the area occupied by a protection element and HBM (Human Body Model) resistance. [Figure 6] 1 is a cross-sectional view of a semiconductor device incorporating a conventional ESD protection circuit ESDC. [Figure 7] FIG. 1 is a plan view of a semiconductor device incorporating a conventional ESD protection circuit ESDC. [Figure 8] 3 is a cross-sectional view of a semiconductor device of an electronic component EC according to the present embodiment. [Figure 9] FIG. 2 is a plan view of a semiconductor device of an electronic component EC according to the present embodiment. [Figure 10] 1A is a schematic plan view of the electronic component of the first embodiment, FIG. 1B is a schematic cross-sectional view of the electronic component of the first embodiment, and FIG. 1C is a schematic cross-sectional view of a modified example of the electronic component of the first embodiment. [Figure 11] 5A is a schematic plan view of an electronic component according to a second embodiment, FIG. 5B is a schematic cross-sectional view of the electronic component according to the second embodiment, and FIG. 5C is a schematic cross-sectional view of a modified example of the electronic component according to the second embodiment. [Figure 12] FIG. 13 is a schematic plan view of an electronic component according to a third embodiment. [Figure 13] FIG. 13A is a schematic cross-sectional view of an electronic component according to a third embodiment, and FIG. 13B is a schematic cross-sectional view of the electronic component according to the third embodiment. [Figure 14] FIG. 13 is a schematic plan view of an electronic component according to a fourth embodiment. [Figure 15] 10A is a schematic cross-sectional view of an electronic component according to a fourth embodiment, and FIG. 10B is a schematic cross-sectional view of the electronic component according to the fourth embodiment. [Figure 16] 13A is a schematic plan view of an electronic component according to a fifth embodiment, FIG. 13B is a schematic cross-sectional view of the electronic component according to the fifth embodiment, and FIG. 13C is a schematic cross-sectional view of a modified example of the electronic component according to the fifth embodiment. [Figure 17] FIG. 13 is a schematic plan view of an electronic component according to a sixth embodiment. [Figure 18] 13A is a schematic cross-sectional view of an electronic component according to a sixth embodiment, and FIG. 13B is a schematic cross-sectional view of the electronic component according to the sixth embodiment. [Figure 19]13A is a schematic plan view of an electronic component according to a seventh embodiment, and FIG. 13B is a schematic cross-sectional view of a modified example of the electronic component according to the seventh embodiment. [Figure 20] FIG. 13 is a schematic cross-sectional view of an electronic component according to an eighth embodiment. [Figure 21] FIG. 13 is a schematic cross-sectional view of an electronic component according to a ninth embodiment. [Figure 22] 10A is a schematic plan view of an electronic component according to a tenth embodiment, and FIG. 10B is a schematic cross-sectional view of a modified example of the electronic component according to the tenth embodiment. [Figure 23] 11(a) is a schematic plan view of the electronic component according to the 11th embodiment, and FIG. 11(b) is a schematic cross-sectional view of a modified example of the electronic component according to the 11th embodiment. [Figure 24] FIG. 23 is a schematic cross-sectional view of an electronic component according to a twelfth embodiment. [Diagram 25] FIG. 23 is a schematic cross-sectional view of an electronic component according to a thirteenth embodiment. [Figure 26] 11A to 11C are diagrams illustrating electronic devices according to application examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims, and not all combinations of features described in the embodiments are essential to the invention. Two or more features among the multiple features described in the embodiments may be arbitrarily combined. Also, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0011] 1 and 2 are a plan view and a cross-sectional view, respectively, that respectively show a schematic configuration of a semiconductor device 1 according to an embodiment. The semiconductor device 1 may include a semiconductor chip 12 having one or more electronic components EC and one or more pads 16. The semiconductor device 1 may also include one or more lead frames 14, and a package 10 that seals the semiconductor chip 12. Each pad 16 of the semiconductor chip 12 and the corresponding lead frame 14 may be electrically and physically connected by a bonding wire 18. When forming the bonding wire 18, a bonding ball 17 may be formed on the pad 16, and the pad 16 and the bonding wire 18 may be electrically and physically connected via the bonding ball 17. The semiconductor chip 12 may have a pad region including the pad 16, and a circuit region. In the circuit region, various circuit blocks, for example, a power supply circuit, an arithmetic circuit, an ADC (AD converter), a memory circuit, an audio processor, a DAC (DA converter), a video processor, a bus, a clock circuit, and the like, may be arranged.

[0012] 3 is a diagram illustrating an equivalent circuit of a part of the semiconductor device 1 of an embodiment. The semiconductor device 1 may include, for example, one or more power supply pads VDD, one or more ground pads GND, one or more input pads IN1, IN2, one or more output pads OUT1, OUT2, and one or more circuit blocks CB. Although not shown, the semiconductor device 1 may include one or more input / output pads. The power supply pads, ground pads, input pads, output pads, and input / output pads may be collectively referred to as pads. The power supply pad VDD may be electrically connected to the power supply line VDDL. The power supply line VDDL may be supplied with a voltage (a voltage converted by the power supply circuit) supplied from the power supply pad VDD via a power supply circuit.

[0013] Two or more pads may be electrically connected to each other by a path including the electronic component EC. Alternatively, two or more pads may be electrically connected to each other by a path including the electronic component EC and the resistive element R. In another aspect, the electronic component EC may be electrically connected to the pad by the wiring pattern WP. Alternatively, the electronic component EC may be electrically connected to the pad via the wiring pattern WP and the resistive element R. The electronic component EC may be, for example, a varistor having a molybdenum oxide film, or a varistor having another resistive film. Alternatively, the electronic component EC may be, for example, an active element having a molybdenum oxide film, or an active element having another semiconductor film. Such an active element may be an active element other than a varistor, for example, a transistor (for example, a bipolar transistor, a MOS transistor, a junction field effect transistor (JFET)), or a diode (for example, a general-purpose diode, a PN junction diode, a PIN diode, a Schottky diode).

[0014] Conventionally, semiconductor devices have protected their internal circuits from surge currents by an ESD protection circuit including a diode with a PN junction formed in a semiconductor substrate. The ESD protection circuit including a diode with a PN junction occupies a fairly large area, which causes the semiconductor device to become larger. In this embodiment, the semiconductor device 1 is made smaller by incorporating an electronic component EC as a protection element into the semiconductor device 1. The electronic component EC can have a structure selected from a variety of structures, as described below.

[0015] Fig. 4(a) shows a schematic CAD layout of a conventional ESD protection circuit ESDC incorporated in a semiconductor device. The ESD protection circuit ESDC can be electrically connected to a pad BP via a wiring pattern WP. Fig. 4(b) shows a schematic CAD layout of a varistor as an electronic component EC of this embodiment incorporated in a semiconductor device. The EC can be electrically connected to a pad BP via a wiring pattern WP.

[0016] 5 is a graph showing the results of estimating the relationship between the area occupied by the protection element and the HBM (Human Body Model) resistance, where the solid line shows the case where the electric component EC of this embodiment is used as the protection element, and the dotted line shows the case where the conventional ESD protection circuit ESDC shown in Fig. 4(a) is used as the protection element. According to this embodiment, it is possible to obtain excellent HBM resistance while reducing the area of ​​the protection element.

[0017] 6 and 7 respectively show a cross-sectional view and a plan view of a semiconductor device incorporating a conventional ESD protection circuit ESDC. In FIG. 6, a surge current path in the conventional semiconductor device is shown typically by a thick arrow. The semiconductor device has a wiring structure WS on a semiconductor substrate SS. The semiconductor device also has an ESD protection circuit ESDC arranged adjacent to a pad region PR including a pad BP to which a bonding wire BW is connected, and the pad BP and the ESD protection circuit ESDC are connected via a wiring pattern WP. The ESD protection circuit ESDC includes a PN junction formed in the semiconductor substrate SS.

[0018] 8 and 9 show a cross-sectional view and a plan view of the semiconductor device 1 of this embodiment in which the electronic component EC is incorporated, respectively. In FIG. 8, the path of the surge current in the semiconductor device 1 of this embodiment is shown typically by a thick arrow. The semiconductor device 1 has a wiring structure WS on a semiconductor substrate SS. The wiring structure WS includes a pad region PR including a pad BP and a circuit region CR, and each of the pad region PR and the circuit region CR may include a plurality of wiring layers WL, an interlayer insulating film ILIF disposed between the plurality of wiring layers WL, and a via plug VP connecting the plurality of wiring layers WL to each other. In this embodiment, the electronic component EC as a protective element is disposed in the circuit region CR and above the upper surface of the semiconductor substrate SS. On the other hand, a conventional protective element includes a PN junction formed on the semiconductor substrate SS. A bonding wire BW may be electrically and physically connected to the upper surface of the pad BP via a bonding ball BB.

[0019] The electronic component EC may be disposed in the circuit region CR at a position close to the pad region PR. The electronic component EC may be electrically connected to the pad BP by the wiring pattern WP. Alternatively, the electronic component EC may be electrically connected to the pad BP via a resistive element in addition to the wiring pattern WP. As shown in FIG. 1, the wiring structure WS of the semiconductor device 1 may have a plurality of pads 16 (including 16-1 and 16-2). The wiring structure WS may have, for example, a pad region PR-1 including a first pad 16-1 and a pad region PR-2 including a second pad 16-2, and the electronic component EC may be disposed between the first pad region PR-1 and the second pad region PR-2. The circuit region CR may include a transistor Tr disposed under the electronic component EC. This is advantageous for increasing the circuit size that can be incorporated in the semiconductor device 1.

[0020] 8, the electronic component EC may have an electrode including a conductive film arranged on a farthest wiring layer WLF among the multiple wiring layers WL that is farthest from the semiconductor substrate SS. In another aspect, the electronic component EC may include an electrode including a conductive film arranged on each of at least two wiring layers WL among the multiple wiring layers WL, as illustrated in FIG.

[0021] Below, a number of embodiments of the electronic component EC that can be incorporated into the semiconductor device 1 will be described. However, these are merely examples, and the electronic component EC may have other structures.

[0022] FIG. 10(a) is a schematic plan view of the electronic component EC of the first embodiment. FIG. 10(b) is a schematic cross-sectional view of the electronic component EC of the first embodiment. The electronic component EC of the first embodiment is configured as a varistor, and may have a resistive film 110, a first electrode 121 arranged in a first region R1 of a main surface 111 (here, the upper surface) of the resistive film 110, and a second electrode 122 arranged in a second region R2 of the main surface 111 of the resistive film 110. The second region R2 is separated from the first region R1. The first electrode 121 and the second electrode 122 may be configured of a conductive film arranged in one of the wiring layers WL, for example, the farthest wiring layer WLF farthest from the semiconductor substrate SS. The first electrode 121 and the second electrode 122 may be configured of, for example, a metal (for example, aluminum) or an alloy (for example, aluminum to which tungsten or copper is added). The resistive film 110 may be a molybdenum oxide film, but may be a film made of other materials. The first electrode 121 and the second electrode 122 may have a circular, elliptical, or round shape. Alternatively, the first electrode 121 and the second electrode 122 may have a rectangular shape with rounded corners. Alternatively, the first electrode 121 and the second electrode 122 may have a square or polygonal shape with rounded corners, or may have another shape.

[0023] 10(c) is a schematic cross-sectional view of a modified example of the electronic component EC of the first embodiment. The electronic component EC of the modified example of the first embodiment may have a resistive film 110, a first electrode 121 arranged in a first region R1 of a main surface 112 (here, the lower surface) of the resistive film 110, and a second electrode 122 arranged in a second region R2 of the main surface 112 of the resistive film 110. The second region R2 is separated from the first region R1. The first electrode 121 and the second electrode 122 may be formed of a conductive film arranged in one of the multiple wiring layers WL.

[0024] FIG. 11(a) is a schematic plan view of the electronic component EC of the second embodiment. FIG. 11(b) is a schematic cross-sectional view of the electronic component EC of the second embodiment. Matters not mentioned regarding the electronic component EC of the second embodiment (including modified examples) may follow the above description. The electronic component EC of the second embodiment may have an intermediate film 130 configured as a varistor and disposed between the main surface 111 of the resistive film 110 and the first electrode 121 and between the main surface 111 of the resistive film 110 and the second electrode 122. The intermediate film 130 may be, for example, a silicon film containing impurities (for example, a polysilicon film or an amorphous silicon film). The intermediate film 130 is advantageous for providing ohmic contact between the resistive film 110, which may be configured of a molybdenum oxide film or the like, and the first electrode 121 and the second electrode 122.

[0025] 11(c) is a schematic cross-sectional view of a modified example of the electronic component EC of the second embodiment. The electronic component EC of the modified example of the second embodiment may have intermediate films 130 disposed between the main surface 112 of the resistive film 110 and the first electrode 121, and between the main surface 112 of the resistive film 110 and the second electrode 122. The intermediate film 130 may be, for example, a silicon film containing impurities (for example, a polysilicon film or an amorphous silicon film). The intermediate film 130 is advantageous for providing ohmic contact between the resistive film 110, which may be composed of a molybdenum oxide film or the like, and the first electrode 121 and the second electrode 122.

[0026] FIG. 12 is a schematic plan view of the electronic component EC of the third embodiment. FIG. 13(a) is a schematic cross-sectional view of the electronic component EC of the third embodiment. Matters not mentioned regarding the electronic component EC of the third embodiment (including modified examples) may follow the above description. The electronic component EC of the third embodiment may be configured as a varistor and may have a resistive film 110, a first electrode 121 arranged in a first region of a main surface 111 (here, the upper surface) of the resistive film 110, and a second electrode 122 arranged in a second region of the main surface 111 of the resistive film 110. In the electronic component EC of the third embodiment, each of the first electrode 121 and the second electrode 122 includes at least two conductive films 201, 202 arranged on at least two wiring layers WL of the multiple wiring layers WL. The electronic component EC of the third embodiment may further include a plug VP that electrically connects the at least two conductive films 201, 202. The at least two conductive films 201, 202 may include a first conductive film 201 including a first pattern P1 and a second conductive film 202 including a plurality of second conductive patterns P2 smaller than the first pattern P1. Such a configuration is advantageous for adjusting the varistor voltage of the electronic component EC configured as a varistor. The varistor voltage may be adjusted, for example, by adjusting the area of ​​the second conductive pattern P2.

[0027] 13(b) is a schematic cross-sectional view of a modified example of the electronic component EC of the third embodiment. The electronic component EC of the modified example of the third embodiment may have a resistive film 110, a first electrode 121 arranged in a first region of a main surface 112 (here, the lower surface) of the resistive film 110, and a second electrode 122 arranged in a second region of the main surface 112 of the resistive film 110.

[0028] Fig. 14 is a schematic plan view of an electronic component EC of the fourth embodiment. Fig. 15(a) is a schematic cross-sectional view of the electronic component EC of the fourth embodiment. Matters not mentioned regarding the electronic component EC of the fourth embodiment (including modified examples) may follow the above description. The electronic component EC of the fourth embodiment may be configured as a varistor and may have intermediate films 130 arranged between the main surface 111 (here, the upper surface) of the resistive film 110 and the first electrode 121, and between the main surface 111 of the resistive film 110 and the second electrode 122.

[0029] 15(b) is a schematic cross-sectional view of a modification of the electronic component EC of the fourth embodiment. The electronic component EC of the modification of the second embodiment may have intermediate films 130 disposed between the main surface 112 (here, the lower surface) of the resistive film 110 and the first electrode 121, and between the resistive film 110 and the second electrode 122.

[0030] FIG. 16(a) is a schematic plan view of the electronic component EC of the fifth embodiment. FIG. 16(b) is a schematic cross-sectional view of the electronic component EC of the fifth embodiment. Matters not mentioned regarding the electronic component EC of the fifth embodiment (including modified examples) may follow the above description. The electronic component EC of the fifth embodiment may be configured as a varistor and may have a first electrode 121, a resistive film 110 disposed on the first electrode 121, and a second electrode 122 disposed on the resistive film 110. In other words, the electronic component EC of the fifth embodiment may have the first electrode 121 disposed on one main surface 112 side of the resistive film 110, and the second electrode 122 disposed on the other main surface 111 side of the resistive film 110. In the first to fourth embodiments, a current path is formed so that a current flows in a direction along the main surface of the resistive film 110, whereas in the fifth embodiment, a current path is formed so that a current flows in a thickness direction of the resistive film 110. The second electrode 122 may be formed of a conductive film disposed in one of the wiring layers WL, for example, the farthest wiring layer WLF from the semiconductor substrate SS. The first electrode 121 may be formed of a conductive film disposed in one of the wiring layers WL. The first electrode 121 and the second electrode 122 may be formed of a metal (for example, aluminum) or an alloy (for example, aluminum with added tungsten or copper).

[0031] 16(c) is a schematic cross-sectional view of a modification of the electronic component EC of the fifth embodiment. The electronic component EC of the modification of the fifth embodiment may have intermediate films 130 disposed between the resistive film 110 and the first electrode 121 and between the resistive film 110 and the second electrode 122.

[0032] FIG. 17 is a schematic plan view of the electronic component EC of the sixth embodiment. FIG. 18(a) is a schematic cross-sectional view of the electronic component EC of the sixth embodiment. Items not mentioned regarding the electronic component EC of the sixth embodiment (including modified examples) may follow the above description. The electronic component EC of the sixth embodiment may be configured as a varistor and may have a first electrode 121, a resistive film 110 disposed on the first electrode 121, and a second electrode 122 disposed on the resistive film 110. In the electronic component EC of the sixth embodiment, the first electrode 121 includes at least two conductive films 201a, 202a disposed on at least two wiring layers WL of the multiple wiring layers WL. In addition, in the electronic component EC of the sixth embodiment, the second electrode 122 includes at least two conductive films 201b, 202b disposed on at least two wiring layers WL of the multiple wiring layers WL. Moreover, the electronic component EC of the sixth embodiment can further include a plug VP that electrically connects at least two conductive films 201a, 202a, and a plug VP that electrically connects at least two conductive films 201b, 202b.

[0033] The at least two conductive films 201a, 202a may include a first conductive film 201a including a first pattern P1a and a second conductive film 202a including a plurality of second conductive patterns P2a smaller than the first pattern P1a. The at least two conductive films 201b, 202b may include a first conductive film 201b including a first pattern P1b and a second conductive film 202b including a plurality of second conductive patterns P2b smaller than the first pattern P1b. Such a configuration is advantageous for adjusting the varistor voltage of the electronic component EC configured as a varistor. The varistor voltage may be adjusted, for example, by adjusting the area of ​​the second conductive pattern P2.

[0034] 18(b) is a schematic cross-sectional view of a modified example of the electronic component EC of the sixth embodiment. The electronic component EC of the modified example of the second embodiment is configured as a varistor, and may have an intermediate film 130a arranged between one main surface 112 (here, the lower surface) of the resistive film 110 and the first electrode 121, and an intermediate film 130b arranged between the other main surface 111 (here, the upper surface) of the resistive film 110 and the second electrode 122, respectively.

[0035] FIG. 19(a) is a schematic cross-sectional view of an electronic component EC according to a seventh embodiment. The electronic component EC according to the seventh embodiment is configured as a transistor, more specifically, a bipolar transistor, and has an emitter 311, a base 312, and a collector 313. The electronic component EC according to the seventh embodiment includes a semiconductor layer 310, and more specifically, the emitter 311, the base 312, and the collector 313 may be disposed on the semiconductor layer 310. The semiconductor layer 310 may be a molybdenum oxide film, but may also be a film (e.g., a polysilicon film) configured of another semiconductor material. The electronic component EC according to the seventh embodiment may also have a first electrode 321 electrically connected to at least the emitter 311, and a second electrode 322 electrically connected to at least the collector 313. The second electrode 322 may be disposed so that the base 312 and the collector 322 are short-circuited, in which case the bipolar transistor may function as a diode. The first electrode 321 and the second electrode 322 may be formed of a conductive film disposed on one of the wiring layers WL, for example, the farthest wiring layer WLF from the semiconductor substrate SS. The first electrode 321 and the second electrode 322 may be formed of, for example, a metal (for example, aluminum) or an alloy (for example, aluminum with tungsten or copper added). The electronic component EC of the seventh embodiment may have an insulating film 331 that defines a region where the first electrode 321 and the second electrode 322 contact the semiconductor layer 310.

[0036] FIG. 19(b) is a schematic cross-sectional view of a modified electronic component EC of the seventh embodiment. The electronic component EC of the modified seventh embodiment is configured as a transistor, more specifically, a bipolar transistor, and has an emitter 311, a base 312, and a collector 313. The electronic component EC of the modified seventh embodiment includes a semiconductor layer 310, and more specifically, the emitter 311, the base 312, and the collector 313 may be disposed on the semiconductor layer 310. The semiconductor layer 310 may be a molybdenum oxide film, but may also be a film (e.g., a polysilicon film) configured of other semiconductor materials. The electronic component EC of the modified seventh embodiment may also have a first electrode 321 electrically connected to at least the emitter 311, and a second electrode 322 electrically connected to at least the collector 313. The first electrode 321 may be disposed so that the base 312 and the emitter 311 are short-circuited, in which case the bipolar transistor may function as a diode. The first electrode 321 and the second electrode 322 may be formed of a conductive film disposed on one of the wiring layers WL, for example, the farthest wiring layer WLF from the semiconductor substrate SS. The first electrode 321 and the second electrode 322 may be formed of, for example, a metal (for example, aluminum) or an alloy (for example, aluminum with tungsten or copper added). The electronic component EC of the seventh embodiment may have an insulating film 331 that defines a region where the first electrode 321 and the second electrode 322 contact the semiconductor layer 310.

[0037] FIG. 20 is a schematic cross-sectional view of an electronic component EC according to the eighth embodiment. Matters not mentioned regarding the electronic component EC according to the eighth embodiment (including modified examples) may follow those of the seventh embodiment. The electronic component EC according to the eighth embodiment is configured as a transistor, more specifically, a bipolar transistor, and has an emitter 311, a base 312, and a collector 313. The electronic component EC according to the eighth embodiment includes a semiconductor layer 310, and more specifically, the emitter 311, the base 312, and the collector 313 may be disposed on the semiconductor layer 310. The semiconductor layer 310 may be a molybdenum oxide film, but may also be a film (e.g., a polysilicon film) composed of another semiconductor material. The electronic component EC according to the eighth embodiment may also have a first electrode 321 electrically connected to the emitter 311 and a second electrode 322 electrically connected to the collector 313. In the electronic component EC according to the eighth embodiment, the base 312 is maintained in a floating state. The first electrode 321 may be formed of a conductive film arranged on one of the wiring layers WL, for example, the farthest wiring layer WLF, which is the furthest from the semiconductor substrate SS. The second electrode 322 may be formed of a conductive film arranged on one of the wiring layers WL, for example, the wiring layer WL below one of the farthest wiring layers WLF, which is the furthest from the semiconductor substrate SS. Alternatively, the second electrode 322 may be arranged between the wiring layers WL. The first electrode 321 and the second electrode 322 may be formed of, for example, a metal (for example, aluminum) or an alloy (for example, aluminum to which tungsten or copper is added). The electronic component EC of the eighth embodiment may have an insulating film 331 that defines a region where the first electrode 321 contacts the semiconductor layer 310.

[0038] FIG. 21 is a schematic cross-sectional view of an electronic component EC according to a ninth embodiment. The electronic component EC according to the ninth embodiment is configured as a transistor, more specifically, a MOS transistor, and has a source 411 and a drain 412 arranged on a semiconductor layer 410, and a gate 413 arranged on the semiconductor layer 410 via a gate insulating film 414. The semiconductor layer 410 may be, for example, a molybdenum oxide film, but may also be a film made of other semiconductor materials (for example, a polysilicon film). The source 411 and the drain 412 may have the same structure and may be interchangeable with each other. The electronic component EC according to the ninth embodiment may also have a first electrode 421 electrically connected to the source 411 and the gate 413, and a second electrode 422 electrically connected to the drain 412. Instead of such a configuration, the first electrode 421 may be electrically connected to the source 411, and the second electrode 422 may be electrically connected to the drain 412 and the gate 413. The first electrode 421 and the second electrode 422 may be formed of a conductive film disposed in one of the wiring layers WL, for example, the farthest wiring layer WLF farthest from the semiconductor substrate SS. The first electrode 421 and the second electrode 422 may be formed of, for example, a metal (for example, aluminum) or an alloy (for example, aluminum with tungsten or copper added).

[0039] FIG. 22(a) is a schematic cross-sectional view of an electronic component EC according to a tenth embodiment. The electronic component EC according to the tenth embodiment is configured as a transistor, more specifically, a junction field effect transistor (JFET), and has a first conductivity type region 511 and a second conductivity type region 512 arranged in a semiconductor layer 510. The first conductivity type region 511 and the second conductivity type region 512 are of opposite conductivity types. The semiconductor layer 510 may be, for example, a molybdenum oxide film, but may also be a film made of another semiconductor material (for example, a polysilicon film). The electronic component EC according to the tenth embodiment also has a first electrode 521 constituting a source electrode, a second electrode 522 constituting a drain electrode, and a third electrode 523 constituting a gate electrode. The first electrode 521 and the second electrode 522 are arranged to sandwich the second conductive type region 512 and to be electrically connected to the first conductive type region 511, and the third electrode 523 is arranged between the first electrode 521 and the second electrode 522 to be electrically connected to the second conductive type region 512. The first electrode 521, the second electrode 522, and the third electrode 523 may be arranged to be in contact with the upper surface of the semiconductor layer 510. The first electrode 521 and the second electrode 522 may be electrically connected, in which case the junction field effect transistor may function as a diode. The first electrode 521, the second electrode 522, and the third electrode 523 may be formed of a conductive film arranged in one of the wiring layers WL, for example, the farthest wiring layer WLF farthest from the semiconductor substrate SS. The first electrode 521, the second electrode 522 and the third electrode 523 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum doped with tungsten or copper). An insulating layer 530 may be disposed below the semiconductor layer 510.

[0040] FIG. 22(b) is a schematic cross-sectional view of an electronic component EC according to a modification of the tenth embodiment. The electronic component EC according to the modification of the tenth embodiment is configured as a transistor, more specifically, a junction field effect transistor (JFET), and has a first conductivity type region 511 and a second conductivity type region 512 arranged in a semiconductor layer 510. The first conductivity type region 511 and the second conductivity type region 512 are of opposite conductivity types. The semiconductor layer 510 may be, for example, a molybdenum oxide film, but may also be a film made of other semiconductor materials (for example, a polysilicon film). The electronic component EC according to the tenth embodiment also has a first electrode 521 constituting a source electrode, a second electrode 522 constituting a drain electrode, and a third electrode 523 constituting a gate electrode. The first electrode 521 and the second electrode 522 are arranged so as to be electrically connected to the first conductivity type region 511, and the third electrode 523 is arranged so as to be electrically connected to the second conductivity type region 512. The first electrode 521 and the second electrode 522 may be arranged so as to contact the lower surface of the semiconductor layer 510. The third electrode 523 may be arranged so as to contact the upper surface of the semiconductor layer 510. The first electrode 521 and the second electrode 522 may be electrically connected, in which case the junction field effect transistor may function as a diode. The third electrode 523 may be composed of a conductive film arranged in any one of the wiring layers WL, for example, the farthest wiring layer WLF, which is the furthest from the semiconductor substrate SS. The first electrode 521 and the second electrode 522 may be composed of a conductive film arranged in any one of the wiring layers WL, for example, the wiring layer WL below one of the farthest wiring layers WLF, which is the furthest from the semiconductor substrate SS. Alternatively, the first electrode 521 and the second electrode 522 may be arranged between the wiring layers WL and the wiring layers WL. The first electrode 521, the second electrode 522 and the third electrode 523 may be made of, for example, a metal (eg, aluminum) or an alloy (eg, aluminum doped with tungsten or copper).

[0041] FIG. 23(a) is a schematic cross-sectional view of an electronic component EC according to an eleventh embodiment. The electronic component EC according to the eleventh embodiment is configured as a diode, more specifically, a PN junction diode, and has a first-conductivity type region 611 and a second-conductivity type region 612. The first-conductivity type region 611 and the second-conductivity type region 612 are of opposite conductivity types, and their junction surface forms a PN junction. The first-conductivity type region 611 and the second-conductivity type region 612 may be, for example, a molybdenum oxide film, but may also be a film made of another semiconductor material (for example, a polysilicon film). The electronic component EC according to the eleventh embodiment also has one or more first electrodes 621 (two first electrodes 621a, 621b in the illustrated example) electrically connected to the first-conductivity type region 611, and one or more second electrodes 622 (two second electrodes 622a, 622b in the illustrated example) electrically connected to the second-conductivity type region 612. When a plurality of first electrodes 621 are provided, they may be electrically connected to each other. When a plurality of second electrodes 622 are provided, they may be electrically connected to each other. One or a plurality of first electrodes 621 and one or a plurality of second electrodes 622 may be made of, for example, a metal (for example, aluminum) or an alloy (for example, aluminum with added tungsten or copper). In the example shown in FIG. 23(a), the first electrode 621a and the second electrode 622a may be made of a conductive film arranged in any one of the wiring layers WL of the plurality of wiring layers WL, for example, the farthest wiring layer WLF farthest from the semiconductor substrate SS. The first electrode 621b and the second electrode 622b may be made of a conductive film arranged in any one of the wiring layers WL of the plurality of wiring layers WL, for example, the wiring layer WL below the farthest wiring layer WLF farthest from the semiconductor substrate SS. Alternatively, the first electrode 621b and the second electrode 622b may be arranged between the wiring layers WL and the wiring layers WL.

[0042] FIG. 23(b) is a schematic cross-sectional view of an electronic component EC according to a modification of the eleventh embodiment. The electronic component EC according to the eleventh embodiment is configured as a diode, more specifically, a PN junction diode, and has a first-conductivity type region 611 and a second-conductivity type region 612. The first-conductivity type region 611 and the second-conductivity type region 612 are of opposite conductivity types, and their junction surface forms a PN junction. The first-conductivity type region 611 and the second-conductivity type region 612 may be, for example, a molybdenum oxide film, but may also be a film made of another semiconductor material (for example, a polysilicon film). The electronic component EC according to the modification of the eleventh embodiment also has one or more first electrodes 621 electrically connected to the first-conductivity type region 611 and one or more second electrodes 622 electrically connected to the second-conductivity type region 612. When a plurality of first electrodes 621 are provided, they may be electrically connected to each other. Moreover, when a plurality of second electrodes 622 are provided, they may be electrically connected to each other. One or a plurality of first electrodes 621 and one or a plurality of second electrodes 622 may be made of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with added tungsten or copper). In the example shown in FIG. 23(b), the first electrode 621 may be made of a conductive film arranged in any one of the wiring layers WL, for example, the farthest wiring layer WLF, which is the furthest from the semiconductor substrate SS. The second electrode 622 may be made of a conductive film arranged in any one of the wiring layers WL, for example, the wiring layer WL below one of the farthest wiring layers WLF, which is the furthest from the semiconductor substrate SS. Alternatively, the second electrode 622 may be arranged between the wiring layers WL and the wiring layer WL.

[0043] FIG. 24 is a schematic cross-sectional view of an electronic component EC according to the twelfth embodiment. The electronic component EC according to the twelfth embodiment is configured as a diode, more specifically, a Schottky diode, and includes a semiconductor layer 710, a barrier metal 720 arranged so as to contact one surface of the semiconductor layer 710, a first electrode 731 arranged so as to contact the barrier metal 720, and a second electrode 732 arranged so as to contact the other surface of the semiconductor layer 710. The semiconductor layer 710 and the barrier metal 720 form a Schottky junction. The semiconductor layer 710 may be, for example, a molybdenum oxide film, but may also be a film made of another semiconductor material (for example, a polysilicon film). The first electrode 731 and the second electrode 732 may be, for example, a metal (for example, aluminum) or an alloy (for example, aluminum to which tungsten or copper is added). The first electrode 731 may be a conductive film arranged in any one of the wiring layers WL, for example, the farthest wiring layer WLF farthest from the semiconductor substrate SS. The second electrode 732 may be formed of a conductive film disposed in one of the wiring layers WL, for example, a wiring layer WL below the farthest wiring layer WLF furthest from the semiconductor substrate SS. Alternatively, the second electrode 732 may be disposed between the wiring layers WL.

[0044] FIG. 25 is a schematic cross-sectional view of an electronic component EC according to a thirteenth embodiment. The electronic component EC according to the thirteenth embodiment is configured as a diode, more specifically, a PIN diode, and has a first-conductivity-type region 811, a second-conductivity-type region 812, and an intrinsic semiconductor region 813 arranged in a semiconductor layer 810. The first-conductivity-type region 811 and the second-conductivity-type region 812 are of opposite conductivity types. The intrinsic semiconductor region 813 is arranged between the first-conductivity-type region 811 and the second-conductivity-type region 812. The semiconductor layer 810 may be, for example, a molybdenum oxide film, but may also be a film made of another semiconductor material (for example, a polysilicon film). The electronic component EC according to the thirteenth embodiment also has a first electrode 821 arranged to contact the first-conductivity-type semiconductor region 811, and a second electrode 822 arranged to contact the second-conductivity-type semiconductor region 812. The first electrode 821 and the second electrode 822 may be composed of, for example, a metal (e.g., aluminum) or an alloy (e.g., aluminum with added tungsten or copper). The first electrode 821 may be composed of a conductive film arranged in any one of the wiring layers WL, for example, the farthest wiring layer WLF, which is the furthest from the semiconductor substrate SS. The second electrode 822 may be composed of a conductive film arranged in any one of the wiring layers WL, for example, the wiring layer WL below one of the farthest wiring layers WLF, which is the furthest from the semiconductor substrate SS. Alternatively, the second electrode 822 may be arranged between the wiring layers WL and the wiring layer WL.

[0045] FIG. 26 shows a configuration example of an electronic device 1100 as an application example of the semiconductor device 1. The electronic device 1100 may be, for example, a computer, an information terminal, a communication terminal, a camera, a signal processing device, a vehicle control device, a flight control device, or the like, or a combination of at least two of these electronic devices. The electronic device 1100 includes a plurality of semiconductor devices 1101, 1102, and 1103, which may be arranged on one or more printed circuit boards (PCBs). At least one of the plurality of semiconductor devices 1101, 1102, and 1103 may incorporate an electronic component EC, as in the semiconductor device 1 described above. The electronic device 1100 may include one or more electronic components arranged outside the plurality of semiconductor devices 1101, 1102, and 1103. The electronic component EC may have the configuration described as any one of the first to sixth embodiments. The electronic component EC may be arranged between two or more signal lines 1112 in the electronic device 1100. Such two or more signal lines 1112 may be disposed adjacent to each other or may be disposed via other signal lines 1112. An electronic component EC may be disposed between a signal line 1112 and a power supply line. An electronic component EC may be disposed between a signal line 1112 and a ground line. An electronic component EC may be electrically connected to a pad or terminal 1111.

[0046] The invention is not limited to the above-described embodiment, and various modifications and variations are possible within the scope of the gist of the invention.

Claims

1. A semiconductor device having a semiconductor substrate, a wiring structure disposed on the semiconductor substrate, and an electronic component serving as a protective element, the wiring structure includes a pad region including a pad, and a circuit region, each of the pad region and the circuit region including a plurality of wiring layers, an interlayer insulating film disposed between the plurality of wiring layers, and a via plug connecting the plurality of wiring layers to each other; the electronic component is an active element, The electronic component is electrically connected to the pad, the electronic component is disposed in the circuit region and above the top surface of the semiconductor substrate; A semiconductor device comprising:

2. the electronic component is disposed in a position in the circuit region adjacent to the pad region; 2. The semiconductor device according to claim 1,

3. The electronic component is electrically connected to the pad by a wiring pattern.

2. The semiconductor device according to claim 1,

4. the electronic component is electrically connected to the pad via a wiring pattern and a resistive element; 2. The semiconductor device according to claim 1,

5. the wiring structure further comprises a second pad region including a second pad; the electronic component is disposed between the pad area and the second pad area; 2. The semiconductor device according to claim 1,

6. The electronic component has a molybdenum oxide film.

2. The semiconductor device according to claim 1,

7. the electronic component has an electrode including a conductive film disposed on a farthest wiring layer among the plurality of wiring layers that is farthest from the semiconductor substrate; 2. The semiconductor device according to claim 1,

8. The electronic component is a transistor.

2. The semiconductor device according to claim 1,

9. the transistor includes a molybdenum oxide film; 9. The semiconductor device according to claim 8.

10. The transistor is a bipolar transistor.

9. The semiconductor device according to claim 8.

11. The bipolar transistor has a base which is maintained floating.

11. The semiconductor device according to claim 10.

12. The bipolar transistor has a base and a collector shorted together, or a base and an emitter shorted together.

11. The semiconductor device according to claim 10.

13. The transistor is a MOS transistor.

10. The semiconductor device according to claim 9.

14. The MOS transistor has a gate and a source or a drain shorted together.

14. The semiconductor device according to claim 13.

15. The transistor is a junction field effect transistor.

10. The semiconductor device according to claim 9.

16. The junction field effect transistor has a source and a drain shorted together.

16. The semiconductor device according to claim 15,

17. The electronic component is a diode.

2. The semiconductor device according to claim 1,

18. the diode includes a molybdenum oxide film; 18. The semiconductor device according to claim 17 .

19. The diode is a PN junction diode.

20. The semiconductor device according to claim 18,

20. The diode is a Schottky diode.

18. The semiconductor device according to claim 17 .

21. The diode is a PIN junction diode.

18. The semiconductor device according to claim 17 .

22. the circuit region includes a transistor disposed under the electronic component; 22. The semiconductor device according to claim 1, wherein the first insulating layer is a conductive layer.

23. 22. An electronic device comprising the semiconductor device according to claim 1.

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