Voltage waveform generator for plasma-assisted processing equipment.

Abstract

The voltage waveform generator includes a common node, a voltage waveform generating circuit, and a current source. The voltage waveform generating circuit is operably connected to the common node and configured to apply a voltage signal to the common node. The current source is operably connected to the common node and configured to apply a DC current to the common node. The current source includes a first switch node connected to the common node through a first inductor and a first power supply connected to the first switch node. The power supply includes at least two first voltage nodes, and the current source is operable to switch the at least two first voltage nodes at the first switch node.

Description

[Technical field]

[0001] The present invention relates to a voltage waveform generator for a plasma assisted processing apparatus and to a method for generating a voltage waveform for use in plasma assisted processing, in particular for generating a voltage bias across a sheath of a plasma in contact with a substrate being processed. The voltage bias is advantageously used to control ion energy in plasma assisted etching, plasma assisted layer deposition, or reactive ion etching (REI). [Background technology]

[0002] In plasma-assisted etching and plasma-assisted layer deposition, radio frequency (RF) generators are used to generate bias voltages to control ion energy. Accurate control of the bias voltage and the resulting ion energy distribution (IED) is important for improved process control. This bias voltage is typically generated using linear amplifiers with limited efficiency (broadband) or switch-mode amplifiers with limited versatility (narrowband) or dedicated pulse-generating amplifiers. Typically, amplifiers only indirectly control the output voltage waveform (e.g., by controlling the output power or relying on calibration), which results in limited performance (the generated waveform does not approximate the desired output voltage waveform), less than desirable ion energy distribution, and limited repeatability (wafer-to-wafer and system-to-system variations).

[0003] US Patent Application Publication No. 2018 / 0032100 describes a waveform generator for a plasma-assisted processing apparatus in which multiple bridge legs, each with its own floating DC power supply, are cascaded to obtain a switched voltage waveform at an output node. The voltage waveform can include a voltage gradient obtained by driving a semiconductor switch according to a current control method such that the output voltage is proportional to a drive signal applied to the semiconductor switch.

[0004] No. 9,208,992 describes a plasma-assisted processing apparatus that includes a switch-mode power supply for forming a periodic voltage function at an irradiated surface of a substrate to be processed, the periodic voltage function producing a desired ion energy intensity distribution to perform etching of the substrate or plasma-assisted deposition on the substrate.

[0005] The above-mentioned switched-mode power supply can generate a waveform of a specific shape by the DC current to compensate the ion current (see FIG. 14 of US Pat. No. 9,208,992). To do so, the switched-mode power supply comprises two switch components, which are coupled in a half-bridge and controlled based on a drive signal generated by a controller as shown in FIG. 3 of US Pat. No. 9,208,992.

[0006] In current plasma-assisted processes, there is a trend towards higher commutation voltage levels, larger reactor sizes and higher capacities.

[0007] The inherent plasma reactor capacitance and the stray inductance of the interconnection between the reactor and the bias voltage generator form an LC circuit with inherent resonant characteristics. Due to the resonance in the system, a slow switching speed (limited dV / dt on the switch node) or damping resistors (or snubbers) are necessary to suppress the excitation of the resonance, which causes undesirable ringing of the sheath voltage. This voltage ringing has a negative effect on the desired IED. However, a slow switching speed leads to a longer discharge period, which effectively reduces the process / discharge ratio, thereby increasing the time to process the substrate. Too long a discharge time can also negatively affect the sheath formation or preservation. Furthermore, damping resistors (or snubbers) introduce additional undesirable losses. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] US Patent Application Publication No. 2018 / 0032100 [Patent Document 2] U.S. Patent No. 9,208,992 Summary of the Invention [Problem to be solved by the invention]

[0009] The object of the present invention is to overcome the above mentioned drawbacks. It is an object of the present invention to provide a voltage waveform generator and associated method of generating a voltage waveform for use in plasma assisted processing, which allows for improved control of the voltage waveform. An object is to provide such a generator and method that allows for the production of a more stable voltage signal with reduced vibrations. An object is to provide such a voltage waveform generator with a reduced footprint.

[0010] It is an object of the present invention to provide a plasma-assisted processing apparatus and associated methods that allow for improved process control. In particular, one object is to provide an apparatus and method that allows for more accurate arrival at an ideal or desired voltage waveform and / or allows for faster convergence to such an ideal voltage waveform. [Means for solving the problem]

[0011] According to a first aspect of the present invention, there is provided a voltage waveform generator as set out in the accompanying claims. The voltage waveform generator according to the aspect of the present invention comprises a common node, a voltage waveform generating circuit and a current source. The voltage waveform generating circuit is operably connected to the common node and configured to apply a voltage signal to the common node. The current source is operably connected to the common node and configured to apply a DC current to the common node, in particular the DC current is a negative current, i.e. the current source is configured to draw a DC current from the common node.

[0012] According to the invention, the current source comprises a first switch node connected to a common node through a first (physical) inductor and a first power supply connected to the first switch node. The power supply advantageously comprises at least two first voltage nodes, the first voltage nodes advantageously providing at least two voltage levels, the at least two voltage levels advantageously being adjustable. The current source is advantageously operable to switch the at least two first voltage nodes at the first switch node and thus to switch at least two voltage levels.

[0013] Such a current source advantageously allows for minimizing ripple on the DC current by appropriate switching between voltage nodes. Furthermore, the current source has a minimal footprint and allows for sharing of power supplies with the voltage waveform generating circuitry.

[0014] According to a second aspect of the present invention there is provided an apparatus for plasma assisted processing as set out in the accompanying claims.

[0015] According to a third aspect of the present invention there is provided a method of generating a voltage waveform as set out in the accompanying claims. The method as described herein is advantageously implemented in a voltage waveform generator or apparatus as described herein.

[0016] Aspects of the invention will now be described in more detail with reference to the accompanying drawings, in which like reference numerals denote like features, and in which: [Brief description of the drawings]

[0017] [Figure 1] FIG. 2 illustrates an example of a voltage waveform generator used in a bias generator for an ICP (inductively coupled plasma) reactor in accordance with an embodiment of the present invention. [Diagram 2] FIG. 1 illustrates a simplified plasma reactor model and a voltage waveform generator according to the present invention coupled thereto. [Diagram 3] FIG. 2 is a block diagram of components of a voltage waveform generator in accordance with the present invention. [Figure 4A] FIG. 1 shows the combination of plasma voltage and sheath voltage during the machining and discharge period, i.e. the voltage at the irradiated substrate surface. [Figure 4B] FIG. 4 shows the voltage at the substrate stage during the machining and discharge cycles, i.e. the voltage supplied by the bias generator according to the invention. [Figure 4C] FIG. 13 illustrates the voltage generated in the bias voltage generator and biased through a DC blocking capacitor during machining and discharge periods. [Figure 5A] FIG. 13 shows sheath current and ion current during machining and discharge cycles. [Figure 5B] FIG. 13 illustrates the substrate stage current during machining and discharge periods. [Figure 5C] FIG. 4 illustrates the current supplied by the bias generator according to the present invention during machining and discharge periods. [Figure 6] FIG. 2 is a circuit diagram of a bias voltage generator according to the present invention. [Figure 7] FIG. 7 is a circuit diagram of a neutral-point clamped (NPC) electrical converter used as a DC power supply in the pulse generation circuit of the bias voltage generator of FIG. 6. [Figure 8] FIG. 4D shows details of the voltage waveform of FIG. 4C during a discharge period. [Figure 9] FIG. 4 shows details of the current supplied by the pulse generating circuit during a discharge period. [Figure 10] FIG. 2 illustrates the current path in the bias voltage generator during the ramp-up period of a voltage discharge pulse that increases the current through the inductor coil of the pulse generation circuit. [Figure 11] FIG. 13 illustrates the current path in the bias voltage generator during a freewheeling period of a voltage discharge pulse following a ramp-up, reducing the current through the inductor coil of the pulse generation circuit. [Figure 12] FIG. 12 shows alternative current paths in the bias voltage generator during the same freewheeling period as FIG. 11. [Figure 13]FIG. 2 illustrates the current paths in the bias voltage generator during the voltage clamp period of a voltage discharge pulse, during which no current flows through the inductor coil of the pulse generation circuit. [Figure 14] FIG. 13 illustrates the current path in the bias voltage generator during the ramp-down period of a voltage discharge pulse that increases the reverse current through the inductor coil of the pulse generation circuit. [Figure 15] FIG. 13 illustrates the current paths in the bias voltage generator during a freewheel period following a ramp down that reduces the reverse current flowing through the inductor coil of the pulse generation circuit. [Figure 16] FIG. 2 is a circuit diagram of a power supply for a current source of the bias voltage generator described herein, implemented as a "rainstick" DC / DC converter. [Figure 17] FIG. 1 illustrates the voltage at the switch node of a current source versus the voltage at the common node of a bias voltage generator as described herein, where the current source is switched, resulting in a switched voltage at the switch node to minimize volt-seconds across the inductor of the current source. [Figure 18] FIG. 18 illustrates the current ripple on the current through the inductor of the current source associated with the voltage waveform of FIG. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] FIG. 1 shows one common use of a bias voltage waveform generator (BVG) 10 in an inductively coupled plasma (ICP) apparatus 100, where the BVG 10 controls the substrate 101 (typically a wafer) voltage by controlling the substrate stage voltage. In a plasma reactor 102, a plasma 103 is generated by introducing a plasma-forming gas 104 into a dielectric tube 108 surrounded by an induction coil 107. This configuration forms a plasma torch that directs the plasma 103 towards a platform 105 (substrate stage) on which the substrate 101 is placed. Optionally, a precursor 109 can be introduced into the plasma reactor 102. As known in the art, a radio frequency (RF) voltage is applied to the induction coil 107 through an RF power supply 120 and a matching network 121. The RF power supply 120 as well as the BVG 10 can be controlled through a system host controller 130. The plasma process suitable for the present invention is a so-called low pressure plasma or reduced pressure plasma, i.e. operates at pressures much lower than atmospheric pressure, for example between 1 mTorr and 10 Torr. To this end, the plasma reactor 102 is advantageously gas-tight and the desired pressure within the plasma reactor 102 is obtained by a vacuum pump 106 .

[0019] The BVG 10 can also be used in other configurations, such as a capacitively coupled plasma (CCP) reactor, or in a configuration where control signals are directly interconnected between the source generator (RF power supply) and the BVG (without going through a system host controller). Different sources can be used to generate the plasma (e.g., capacitively coupled plasma, electron cyclotron resonance, magnetron, DC voltage, etc.).

[0020] FIG. 2 depicts an electrical model of the plasma reactor 102, showing the loads imposed by the reactor, plasma, sheath, and substrate as seen by the BVG 10. The sheath is a boundary layer that has a higher density of positive ions and therefore an overall excess positive charge that forms on the irradiated surface of the substrate due to the plasma. The excess positive charge is generally counterbalanced by an opposite negative charge on the irradiated surface of the substrate that it contacts. Vpl represents the plasma potential in the sheath above the substrate, and I i represents the ion current in the sheath. v sh represents the voltage across the sheath, which is the sheath capacitance C sh and the sheath capacitance current i sh represents the limited ion mobility in the sheath during the process cycle, while the diode D p represents the high electron mobility in the sheath during the discharge period. sub represents the voltage across the substrate 101. The lumped capacitance C sub represents the capacitance of the dielectric substrate. L par is a lumped inductance representing the stray inductance of the BVG output power interconnect and return. C t is the capacitance of the substrate stage (e.g. due to an electrostatic (dielectric) chuck holder on / in the substrate stage), as well as the associated voltage v t and current i t is a lumped capacitance that represents the capacitance from the substrate stage power interconnect with ground 14 having a capacitance of 0.1 V. This capacitance is typically dominated by the capacitance from the substrate table to the dark shield, i.e., a metal shield adjacent to the platform 105 that prevents the plasma from propagating beyond the platform, e.g., to the pump 106.

[0021] The DC (bias) voltage across the sheath ideally results in a narrow IED, and the level of the DC voltage controls the level of the (average) ion energy. Positively charged ions collected on the plasma irradiated surface cause charge accumulation on the dielectric substrate and / or substrate stage of dielectric material (e.g., electrostatic chuck holder). Due to the charge accumulation, a decreasing (ever decreasing) voltage needs to be applied by the BVG to keep the sheath voltage constant. This is not feasible in practical implementations. To prevent damage to the substrate and / or substrate stage, the charge accumulation and thus the potential across the substrate and / or substrate stage needs to be limited. This compensation can be achieved by periodic discharge of the substrate and / or substrate stage during the discharge interval between successive (plasma) process cycles.

[0022] Referring to FIG. 4A, the process repeat period T C is the plasma processing period T process Including the plasma processing period T process The discharge period T D (or plasma processing period T process The discharge period T D (The plasma processing period T process During this time, the sheath voltage v sh and / or the process voltage on the illuminated surface of the substrate, V process =v sh +V pl is advantageously controlled (directly or indirectly) and kept constant. process Typical values ​​of range between 0V and -1000V. Successive plasma processing periods T process Discharge period T D During the discharge period T, a positive voltage pulse is applied to the substrate stage to remove any charge that may have built up on the substrate surface being illuminated. D is advantageously as small as possible, typically around 200-500 ns, and the voltage pulses occurring during this period are advantageously characterized by fast rise and fall times and, in some cases, minimal oscillations of the voltage peaks.

[0023] The voltage shapes described above can be obtained by generating a voltage waveform at the substrate stage by the BVG 10, as shown in Figure 4B. Considering the equivalent electrical scheme of Figure 2, T process A voltage gradient must be generated by the BVG during

[0024] 5A-5C, the process currents corresponding to the voltage waveforms of FIGS. 4A-4B are shown. D A voltage pulse of i sh while the plasma current I i is the total repeat period T C remains substantially constant during T process Between sh= 0. In the substrate, T D Very high current peaks during i sub On the other hand, ideally, T process Between sub =-I i It is. sub To generate T D During this period, the BVG generates a much higher current pulse i load must occur, whereas T process The current i that must be generated during load is generally between about 0A and 4A, as shown in Figure 2.

[0025]

number

[0026] ) one order of magnitude smaller.

[0027] Voltage waveform generator circuit To obtain the desired voltage waveforms described above, in accordance with the present invention, a BVG 10 is provided, as shown generally in Figure 3. The BVG 10 comprises a pulse generating circuit 11 and a current source 16 coupled to a common node 13. The common node 13 is coupled to an optional physical DC blocking capacitor C block 1 and is coupled to an output node 12 of the BVG 10 via

[0028] The pulse generating circuit 11 has a discharge period T D The voltage pulse is applied to the common node 13 and connected to a DC blocking capacitor C block A current source 16 is applied to the output node 12 via a current source 17. An optional voltage clamp circuit 15 may be coupled to the common node 13 to reduce voltage oscillations and / or overshoot at the upper plateau of the voltage pulse as described further below. process During this time, the current i CS while the pulse generating circuit 11 is advantageously configured to provide T process Therefore, Tprocess Between load =i CS holds true. i CS It is useful to note that V is generally negative (current source 16 sinks current).

[0029] According to one embodiment, the current source 16 is C It operates continuously for a period of time and is connected to the common node 13. CS In this case, the discharge period T D Between load =i CS +i pulse However, as is clear from the graphs 5A to 5C, i CS (between 0.5A and 4A, preferably between 1A and 2A) is T D Between pulse (peak amplitude is at least 30A, advantageously at least 40A) and therefore has a negligible effect on the generation of the voltage pulse.

[0030] Referring to FIG. 4C, a DC blocking capacitor C block DC bias voltage v Cblock is the voltage at the common node v CN Allows you to set the bias on

[0031] A circuit diagram of the various parts of the BVG 10 is represented in Fig. 6. In an exemplary embodiment, the pulse generator circuit 11 is a neutral-point clamped (NPC) bridge circuit with an active switch 112 connected to a (DC) power supply having at least two (DC) voltage nodes A-G, where G denotes electrical ground GND. The power supply is advantageously provided as a "rainstick" converter 110, possibly combined with a (separate) DC / DC converter as shown in Fig. 7, forming at least two voltage nodes A-G (seven voltage nodes in the example of Fig. 7, and therefore six DC bus voltages A-B, B-C, C-D, D-E, E-F and F-G). By way of example, each DC bus voltage A-B or F-G etc. can provide a DC voltage between 100V and 400V, advantageously between 200V and 400V. Advantageously, the DC bus voltages A-B, B-C etc. are controllable by adjusting the operation of the active switches of the converter 110.

[0032] The voltage nodes A-G are connected to a switch node 111 through an operable switch 112 of an NPC bridge, which is operably coupled to the control unit 17. The switch 112 is advantageously a semiconductor switch, for example implemented as a field effect transistor (FET), advantageously with an internal anti-parallel diode (not shown). The switch node 111 is connected to a physical inductor (e.g. a coil) L pulse is connected to the common node 13 via the inductor L pulse Advantageously, the current i drawn from the pulse generating circuit 11 pulse Precise control of i pulse When controlling the substrate stage, the parasitic inductance of the electrical coupling to the substrate stage (L in Figure 2) par In fact, the effect of L pulse In the absence of current i pulse is mainly the parasitic inductance L par and the parasitic inductance L par Since is unknown, i pulse is difficult to estimate accurately. Advantageously, L parL pulse It is relatively small compared to L pulse Providing a Vcc voltage at switch node 111 lowers the LC resonant frequency and increases the load impedance of the equivalent LC circuit seen by switch node 111. When a voltage is applied to switch node 111, the current increases more slowly, making it easier to calculate the timing of the voltage pulse applied to switch node 111 to generate a clean discharge pulse.

[0033] The voltage clamp circuit 15 forms a switchable connection between the common node 13 and a DC voltage node, in particular a voltage node of a DC power supply, such as the voltage node A of the power supply 110. For this purpose, the first branch 151 comprises one active switch or a series arrangement of active switches, for example active semiconductor switches 153, to form an actively switchable connection between the common node 13 and the voltage node A. The switches 153 can be operated through the control unit 17. The voltage clamp circuit comprises a second branch 152 in parallel with the first branch 151, which may comprise a passive switch, such as a diode or a series of diodes 155, such that the moment when the active switch 153 is turned on is not critical. The voltage clamp circuit 15 may comprise an electrical damping element, such as a resistor 154, which is advantageously connected to the first branch 151 in series with the switch 153, or alternatively to the second branch 152 or to both branches 151 and 152. The resistor 154 allows reducing / damping voltage oscillations caused by voltage mismatches when the voltage clamp circuit 15 is activated.

[0034] current source circuit According to one aspect of the invention, the current source 16 comprises a power supply having at least two voltage levels (nodes) X, Y switchably connected to a switch node 161 through a switch 162, which may be an active semiconductor switch such as a FET, and which may be operatively coupled to the control unit 17. The switch node 161 is advantageously connected to a physical inductor (e.g., coil) LCS 1. The current source 16 is advantageously arranged as a buck converter, making it possible to regulate the DC voltage at the switch node 161 of the current source by means of the duty ratio of the switch 162. Advantageously, a DC bus midpoint GND between the voltage nodes X and Y is connected to a common node 13 via CS is provided. GND CS The voltage level of the inductor L CS In one example, the (average) DC voltage at switch node 161 when the duty cycle of switch 162 is set to 0.5 (50%). In this case, the potentials of X and Y are advantageously set to GND. CS is symmetric with respect to

[0035] Referring to FIG. 16, the power supply of current source 16 is a multiple DC bus voltage X to GND. Cs , GND Cs Multiple voltage nodes X, Y, Z, and GND to realize ~Y, Y~Z, etc. CS The voltage of the DC bus can advantageously be adjusted by suitable switching of the switches of the DC / DC converter 160 and can be set to a suitable value by a voltage difference between successive nodes advantageously between 100V and 400V. CS serves as the DC bus midpoint in the buck converter of current source 16 and is inserted between nodes X and Y. Advantageously, "rainstick" DC / DC converter 160 and the "rainstick" converter of power supply 110 are connected to a shared power supply, in particular converter / power supplies 160 and 110 share a DC bus, e.g., DC buses E-F are shared between the two converters.

[0036] Voltage waveform (pulse) generation Next, the discharge period T D The operation of an exemplary embodiment of the pulse generation circuit 11 for generating a voltage pulse for a period of T DA voltage pulse v occurs at the common node 13 during CN The enlarged waveform of is shown by the solid line in FIG. pulse The corresponding current i flows through pulse is shown in FIG.

[0037] The voltage pulse begins at instant t1 and has a ramp-up period T 12 At instant t1, switch 112 is operated, for example by control unit 17, to connect a high voltage level, for example the voltage level at node A, to switch node 111. This corresponds to the voltage v SN In this case, all switches 112 between switch node 111 and node A are closed, and current flows through the pulse generation circuit, as shown by the grey arrows in FIG. 10. The high voltage causes L pulse The current i passing through pulse increases. i pulse The gradient of L pulse The inductance is determined by the inductance of L. Smaller inductance values ​​generally result in faster current and voltage ramp-up, but typically result in higher peak currents, making the switching timing discussed above more critical, and increasing sensitivity to signal oscillations if the switch timing is slightly off. pulse The larger the inductance value of L, the smaller the ramp slope. pulse The optimum inductance value is between 0.5 μH and 10 μH, preferably between 1 μH and 5 μH.

[0038] At time t2, switch 112 is opened to a non-conductive state and all switches 112 are maintained in a non-conductive state. This corresponds to a ramp-up period T 12 ends and the freewheeling period T 23The instant t2 can be selected as the instant at which the voltage at the common node 13 reaches approximately the voltage level at the switch node 111 (e.g., the voltage level of node A). pulse Current i flowing through pulse must be continuous, a current path is formed from electrical ground at node G through the internal anti-parallel diode of switch 112 located between node G and switch node 111, as shown by the grey arrow in FIG. SN falls to the voltage level of node G, while the voltage v at the common node 13 CN is the inductor L pulse It continues to rise somewhat due to the current in the inductor L pulse The current at v is still flowing, releasing its energy into the load capacitance, still charging this capacitance and ramping down. CN can finally reach the level of node A. Therefore, the inductor L pulse Current i flowing through pulse is reduced, and finally the freewheel period T 23 becomes zero at instant t3, indicating that

[0039] Alternatively, the freewheel period T 23 It is possible to connect the switch node 111 to the intermediate voltage levels B to F during i pulse The falling slope of changes, thus affecting the slope of the rising edge of the voltage, and therefore the appropriate voltage level can be selected based on the desired waveform. The current path for the exemplary case where switch node 111 is connected to voltage node F is shown in Figure 12. In this case, switch 112a is actively closed to provide a current path through node F.

[0040] At the instant t3, the voltage at the common node 13 advantageously changes to a value equal to the clamping period T 34During the instant t3, the voltage level at the common node 13 is clamped to the maximum level, for example the level of node A. A voltage clamp circuit 15 is advantageously used for this purpose. The switch 153 may be an active semiconductor switch, for example a FET, and is operated by the control unit 17 to be in a conducting state. The voltage level at the common node 13 is therefore clamped to the voltage of node A. Any voltage mismatch between the common node 13 and the voltage node A when the switch 153 is turned on is advantageously suppressed by the resistor 154. At the instant t3, the inductor L pulse Current i flowing through pulse is zero and T 34 Since all switches 112 are maintained in a non-conducting state for the entire clamp period T 34 Between pulse remains zero. The clamp period T 34 The length of the voltage pulse is preferably equal to the desired length T D are selected based on

[0041] The diode 155 in the clamp branch 152 is connected to the CN rises too fast, for example, too quickly, specifically, the inductor L pulse If the voltage v reaches the level of node A before the current through CN It is convenient to note that the clamping of the 1 / 100 Hz pulse width may be performed when a mismatch in switch timing occurs.

[0042] Clamp period T 34 The possible current paths through BVG in are represented by grey arrows in Figure 13. When the voltage level at common node 13 eventually reaches the level of node A on the other side of voltage clamp circuit 15, diode 155 may begin to conduct. At this point, switch 153 can be switched to a non-conducting state.

[0043] Alternatively, T 34 This means that the current source 16 can be kept in a conductive state for a discharge period T DThis is particularly relevant when switch 153 also operates during the clamp interval. Switch 153 then prevents the current drawn by current source 16 from discharging the load capacitance during the clamp interval and causing the voltage at common node 13 to drop below A. Thus, switch 153 directs the current drawn by current source 16, enabling the voltage at common node 13 to remain clamped to the voltage at voltage node A.

[0044] Alternatively, the clamp period T 34 In such a case, the voltage clamp circuit 15 does not need to be provided.

[0045] Advantageously, a clamping diode (not shown) is provided between the common node 13 and the voltage node G, making it possible to limit the magnitude of a voltage spike, as can be seen in Fig. 4C. Such a voltage spike is induced when the switch 153 of the clamping circuit 15 is turned off (opened), interrupting the current of the current source 16. The diode between 13 and G clamps this voltage spike.

[0046] At instant t4, the voltage pulse begins to ramp down. This corresponds to the clamp period T 34 ends, and the ramp-down period T 45 This indicates that the ramp-down has started. pulse The current i pulse is made negative. For this purpose, the switch node 111 is connected to a voltage node of the DC power supply 110 having a potential lower than the (instantaneous) potential of the common node 13. In the present exemplary embodiment, since the common node is fixed at voltage level A due to the voltage clamp circuit 15, it is sufficient to select one of the levels B to G. The selected level will of course affect the slope of the ramp down, and therefore a suitable level can be selected on the basis of the desired waveform.

[0047] As an example, the current path through BVG 10 during a ramp-down period is shown in FIG. 14 when switch node 111 is connected to voltage node C by operating switches 112b and 112c to a conductive state. 45 The voltage between CN and v SN is shown in Figure 8, and the inductor L pulse Current i flowing through pulse is shown in FIG.

[0048] Ramp-down period T 45 After the freewheel period T 56 Then the discharge period (and therefore the operation of the pulse generating circuit 11) ends and a new machining period T process Before the start of L pulse Current i flowing through pulse is returned to zero. For this purpose, at t5, the switches 112b and 112c are switched back to the non-conductive state, and all the switches 112 remain in the non-conductive state (or any other suitable voltage level can be selected). pulse must remain continuous, so the inductor L pulse conducts current between switch node 111 and voltage node A. Switch 112 may include an internal anti-parallel diode, which then conducts this current. Alternatively, an external diode may be provided anti-parallel to switch 112. Still alternatively, other solutions that mimic the operation of such anti-parallel diodes may be used, for example switch 112 may be a GaN normally-off junction-gate field-effect transistor (JFET) switch, which allows third quadrant operation, i.e., behavior similar to a diode in the reverse conduction state. T 56 The resulting current path during t6 is represented by the grey arrow in FIG. 15. The internal diode of the switch 112 passes the current i pulse After T becomes zero (see Fig. 9), the wire automatically becomes non-conductive. This means that the discharge cycle ends and a new machining cycle T process Indicates that a restart has started.

[0049] The instants t1 to t6 and the voltage levels A to G applied to the switch node 111 are advantageously pulse In other words, referring to FIG. 8, the curve v CN and the curve v SN The resulting area between D This means that the inductor L pulse Current i at pulse It is possible to maintain a steady state / operation where the average value of i does not fluctuate. CS T D When the current is continuously applied over a D (and T C ) over i pulse The average value of i CS and thus I i It is convenient to note that the period T 12 ~T 56 Additional voltage switching states (v SN period) to v CN It is convenient to note that one can obtain a desired voltage waveform for

[0050] Process period T process During this time, the pulse generating circuit 11 remains inoperative and the inductor L pulse current i pulse Therefore, L pulse The voltage across T is zero and the voltage level at the switch node 111 is process according to the voltage level of the common node 13 in the

[0051] current generation Next, the operation of the current source 16 will be described. i The load capacitance C due to sub To compensate for the charging of C sub (And therefore, C tFor this purpose, as shown in Figs. 4B-4C, a current needs to be taken in from the process period T process A voltage gradient must be obtained at the common node 13 (and therefore at the output node 12) during the period. A current source 16 supplies an appropriate DC current i CS The current source 16 is advantageously connected continuously to the common node 13 to provide a full repeat period T C That is, between T process and T D During both, the current i CS continuously because this eliminates distortions that occur when enabling / disabling or connecting / disconnecting the current source 16 and eliminates system complexity in terms of steps that need to be taken to implement connecting / disconnecting devices / circuits.

[0052] 17-18, one advantage of allowing switch node 161 of current source 16 to switch between different voltage levels (at nodes X-Y) is that the C or one process period T process Throughout i CS This is because the current ripple of the switch node 161 can be minimized. CS As can be seen in Figure 17, when the inductor L CS In FIG. 17, the shaded area indicates the voltage v at the common node 13. CN and v CS This shows that the difference between the voltages of i and i completely compensate each other over one period. CS This also means that the average value of i does not fluctuate and a steady state can be achieved. CS Measure the average value of i CSThis can be achieved by adapting the duty cycle of the switch 162 (which can be done by a current control loop implemented in the control unit 17) such that the average value of v at the switch node 161 is equal to a predefined value. Alternatively, or additionally, the potentials of the nodes X and Y can be appropriately adjusted. FIG. 17 shows the voltage v at the switch node 161. CS is switched between node X and node Y at instant t7.

[0053] The current ripple is v CS and v CN so that all the individual volt-second areas between the curves of v are minimized. CS v CN Alternatively or additionally, i CS The voltage levels of X and Y can be adapted to minimize the current ripple in v. This advantageously reduces the current ripple while maintaining the steady state, i.e., zero net volt-second region, or in other words, v CS The average of v CN It is executed for a time period equal to the average of i CS Reducing the current ripple above advantageously reduces the ripple in the sheath voltage.

[0054] In another aspect, the control unit 17 is configured to synchronize the switching of the switch 162 of the current source 16 and the switch 112 of the pulse generator circuit 11, advantageously in both frequency and phase. This can be achieved by implementing in the control unit 17 the same clock for operating the switches 162 and 112. This allows synchronizing the voltage switch of the switch node 161 of the current source and the voltage switch of the switch node 111 of the pulse generator circuit. Thus, over a given period, the inductor L CS The volt-seconds of the 1000V can be made zero very easily, eliminating any possible mismatch due to asynchronous clocks. Doing so allows for a smaller inductor coil L CS can be used, making the circuit more compact. CSAdvantageously, the current ripple occurring on the L CS The inductance of is between 500 μH and 1 mH. Advantageously, the switching frequency of the switch 162 is between 1 kHz and 10 MHz, in particular between 10 kHz and 1 MHz.

[0055] The current source 16 includes three or more switchable voltage levels, i CS In this way, the voltage at the switch node 161 of the current source can be reduced by a factor of 1. CN However, this can increase the footprint of the current source circuit, and a two-voltage level circuit (buck converter) can be considered as the best compromise between performance and footprint.

[0056] The current source 16 and possibly the pulse generating circuit 11 and / or the voltage clamp circuit 15 may be operated through an open loop by the control unit 17. Alternatively, it may be advantageous to implement a closed loop control in the control unit 17 for operating any one of the pulse generating circuit 11, the voltage clamp circuit 15 and the current source 16. To this end, the BVG 10 may comprise a measuring device configured to measure one or a combination of the following: a voltage waveform (voltage envelope), which may be measured at the common node 13 and / or at the output node 12; the voltage level of the common node 13 and / or the output node 12 at the beginning of the discharge period (instant t1), the voltage level of the common node 13 and / or the output node 12 at the end of the discharge period (instant t6), - Inductor L pulse Current i flowing through pulse , - (Inductor L Cs The current i generated by the current source 16 CS , - the current through the clamp circuit 15, - one or more voltage levels of the DC bus of the power sources 11 and / or 160; and - The process voltage in the plasma chamber 102 (e.g., v t ). Any one of the above measurements may be used in a feedback control loop implemented in the control unit 17 to control the operation of the pulse generation circuitry and / or the voltage clamp circuitry during the discharge period. Additionally or alternatively, these measurements may also be used to control the operation of the current source 16 during either or both of the process and discharge periods. [Explanation of symbols]

[0057] 10 Bias voltage waveform generator 11 Pulse generating circuit 12 Output Nodes 13 Common Node 14 Earth 15 Voltage clamp circuit 16 Current source 17 Control Unit 100 Inductively Coupled Plasma (ICP) Equipment 101 Substrate 102 Plasma Reactor 103 Plasma 104 Plasma forming gas 105 Platform 106 Vacuum Pump 107 Induction Coil 108 Dielectric tube 109 Precursors 110 Power supply 111 Switch Node 112 Switch 120 RF power supply 121 Matching Network 130 System Host Controller 151 First Branch 152 Second Branch 153 Active Switch 154 Resistor 155 Diode 160 DC / DC Converter 161 Switch Node 162 Switch A Voltage Node C block DC Blocking Capacitor C sub load capacity G voltage node i CS DC current i pulse current i sh Current Pulse i sub Current Peak L CS Inductors L pulse Inductors L par Parasitic Inductance T C Process Repeat Period T D discharge period T process Plasma Processing Cycle v sh Sheath Voltage v CN Voltage Pulse v SN Voltage

Claims

1. A voltage waveform generator (10) for a plasma assisted processing apparatus (100), comprising: A common node (13); Operatively connected to the common node (13), a voltage signal (v ＣＮ a voltage waveform generating circuit (11) configured to apply a A DC current (i ＣＳ and a current source (16) configured to apply a voltage waveform The current source (16) The first inductor (L ＣＳ a first switch node (161) connected to said common node (13) through a a first power supply (160) having at least two first voltage nodes (X, Y) connected to the first switch node (161); 13. A voltage waveform generator comprising: a first switch node (161) connected to said first voltage node (162) and a second switch node (163) connected to said first voltage node (164);

2. The at least two first voltage nodes (X, Y) are connected to the first switch node (161) through a first active switch (162), and the voltage waveform generator generates the voltage signal (v ＣＮ ) and the switching voltage (v ＣＳ 2. The voltage waveform generator of claim 1, further comprising a control unit configured to control the first active switch to minimize a difference between the first active switch and the second active switch over a predetermined period.

3. 3. The voltage waveform generator of claim 1 or 2, wherein the voltage waveform generating circuit (11) comprises at least two second voltage nodes (A, G), the voltage waveform generating circuit (11) is configured to switch the at least two second voltage nodes (A, G), and the voltage waveform generator comprises a control unit (17) configured to synchronize the switching of the current source between the at least two first voltage nodes (X, Y) and the switching of the voltage waveform generating circuit (11) between the at least two second voltage nodes (A, G).

4. 4. The voltage waveform generator of claim 3, wherein the control unit (17) is configured to control the switching of the current source (16) between the at least two first voltage nodes and the switching of the voltage waveform generating circuit (11) between the at least two second voltage nodes based on a same clock signal.

5. 5. The voltage waveform generator of claim 1, wherein the first power supply (160) is configured to provide at least two first adjustable voltage levels to the at least two first voltage nodes (X, Y).

6. The first power supply (160) connects a DC bus midpoint (GND) between the at least two first voltage nodes (X, Y). ＣＳ 6. The voltage waveform generator of claim 1 , comprising:

7. The at least two first voltage nodes (X, Y) are two first voltage nodes, and the first power source (160) is configured such that the two first voltage nodes (X, Y) are connected to the DC bus midpoint (GND ＣＳ 7. The voltage waveform generator of claim 6, configured to be operated to provide symmetrical voltage levels relative to the input of said input.

8. 8. The voltage waveform generator of claim 1, wherein the first power supply (160) comprises a "rainstick" DC / DC converter comprising the at least two first voltage nodes (X, Y).

9. The voltage waveform generator of claim 1 , wherein the first power supply (160) and the voltage waveform generating circuitry comprise a shared power supply.

10. The output terminal (12) is connected to the plasma-assisted processing device, and the common node (13) is connected to a DC current blocking capacitor (C ｂｌｏｃｋ 10. A voltage waveform generator as claimed in claim 1 , wherein said voltage waveform generator is connected to said output terminals through a first input terminal and a second input terminal.

11. 11. The voltage waveform generator of claim 1, wherein the current source (16) is configured to draw the DC current from the common node (13).

12. An apparatus (100) for plasma-assisted processing of a substrate (101), comprising: A means (102, 107) for generating a plasma (103); a processing platform (105) for supporting said substrate (101); 12. An apparatus comprising the voltage waveform generator (10) of any one of claims 1 to 11, wherein the common node (13) is electrically connected to the processing platform (105).

13. A method for generating a voltage waveform for a substrate (101) undergoing plasma assisted processing, comprising the steps of: A voltage signal (v CN ) is generated by a voltage waveform generating circuit (11), and the voltage signal (v CN ) is applied to a common node (13) electrically coupled to the substrate (101). ＣＮ ) and A step of generating a DC current (i CS ) by a current source circuit (16), applying a first switching voltage (v ＣＳ ), wherein the first switch node (161) is connected to a first inductor (L ＣＳ ) to the common node (13), and the first inductor (L ＣＳ ) to the DC current (i ＣＳ generating a DC current (i CS ) through which a DC current (i CS ) flows.

14. The first switching voltage (v ＣＳ 14. The method of claim 13, wherein the voltage signal is obtained by switching between at least two first voltage levels at a first instant in time, and the step of applying the voltage signal comprises switching between at least two second voltage levels at a second instant in time, the first and second instants being synchronized.

15. The method of claim 14 , wherein the first and second instants are timed based on the same clock signal.

16. The at least two first voltage levels are determined by the voltage signal (v ＣＮ ) and the first switching voltage (v ＣＳ 16. The method of claim 14 or 15, wherein the difference between the

17. The first and second instants correspond to the voltage signal (v ＣＮ ) and the first switching voltage (v ＣＳ 17. The method of claim 14, wherein the difference between the first and second inputs is selected to minimize the difference between the first and second inputs.

18. The first switching voltage (v ＣＳ ) is obtained by switching at least two first voltage levels at a first instant, the first instant being a first inductor (L ＣＳ 18. The method of claim 13, wherein volt-seconds of the first volt-seconds are selected to be zero over a predetermined period.

19. The DC current (i ＣＳ ) is the voltage signal (v ＣＮ 19. The method of claim 13, wherein the voltage Vcc is applied continuously during application of the voltage Vcc.

20. 20. A method according to any one of claims 13 to 19, implemented in the voltage waveform generator of any one of claims 1 to 11 or of the apparatus of claim 12.

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