Silicon carbide semiconductor device and method for inspecting silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device that can improve yield and a method for inspecting the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device has a working environmental temperature within a predetermined range of 100°C or higher, the total area of stacking faults in a semiconductor substrate is set larger as the breakdown voltage or the operating environment temperature, or both, are higher. Prior to shipment of the silicon carbide semiconductor device, a body diode is energized under the temperature environment of the inspection temperature equal to or lower than the operating environment temperature to grow stacking faults in the semiconductor substrate in advance. Then, silicon carbide semiconductor devices in which the ratio of the total area of stacking faults of the semiconductor substrate to the area of the active region is 0% or more and 15% or less are selected as non-defective products. When the silicon carbide semiconductor device is used at or above the operating environment temperature at which the value obtained by dividing the Von increase rate of the silicon carbide semiconductor device with a predetermined withstand voltage by the ratio of the stacking fault area of the semiconductor substrate to the area of the active region becomes zero, all silicon carbide semiconductor devices are non-defective products regardless of the presence or absence of stacking faults.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device and a method for inspecting a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, in a MOS-type silicon carbide (SiC) semiconductor device having a MOS gate (an insulated gate having a three-layer structure of metal-oxide-semiconductor), it is known that stacking faults (SF) grow when a current flows through a parasitic pn diode (body diode (BD)) formed at the pn junction between the base region and the drift region, and the drift resistance increases in the area where the stacking fault grows, resulting in an increase in the on-state voltage.

[0003] As a method for detecting stacking faults, a method has been proposed in which a semiconductor wafer, in which an epitaxial layer is grown on a starting substrate made of silicon carbide, is irradiated with laser light having energy greater than the band gap of silicon carbide before the formation of a surface electrode or before the formation of an element structure, to grow stacking faults in advance, and the location of the stacking faults is identified based on the intensity of light of a specific wavelength emitted from the semiconductor wafer during the irradiation of this laser light (see, for example, Patent Documents 1 and 2).

[0004] In the following Patent Documents 1 and 2, position information of stacking faults is acquired in the state of a semiconductor wafer, and semiconductor chips that are diced from the semiconductor wafer so as to contain stacking faults are excluded as defective chips based on the position information of the stacking faults. Another method of detecting stacking faults is known in which a current is passed through a body diode after a product (semiconductor chip) is completed to grow stacking faults, and all semiconductor chips whose characteristics vary greatly before and after the current is passed are excluded as defective chips.

[0005] In these methods for detecting stacking faults, the conditions for irradiating the semiconductor wafer with laser light and the conditions for energizing the body diode are appropriately set for each MOS type semiconductor device of various sizes (cell width of a unit cell (functional unit of an element)) so that the stacking faults can be grown by irradiation with laser light or energization of the body diode until they reach a size sufficient for detecting stacking faults.

[0006] In addition, the increase in on-state voltage of a MOS semiconductor device relative to the total area (total surface area) of stacking faults depends on the impurity concentration in the drift region, and the n + It has been disclosed that the adverse effects of stacking faults are small in n-type starting substrates and n-type contact epitaxial layers (see, for example, Non-Patent Document 1). In addition, Non-Patent Document 1 below discloses that the higher the operating temperature of a MOS semiconductor device, the smaller the adverse effects of stacking faults become. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2009-088547 A [Patent Document 2] JP 2014-022503 A [Non-patent literature]

[0008] [Non-Patent Document 1] S. Asada and 2 others, Effects of stacking faults on electron transport in 4H-SiC n-type epilayers under unipolar operation evaluated by TCAD simulation, Japanese Journal of Applied Physics, The Japan Society of Applied Physics, 2020, Vol. 59, p.54003-1~54003-6 Summary of the Invention [Problem to be solved by the invention]

[0009] However, in conventional stacking fault detection methods (e.g., Patent Documents 1 and 2), when a semiconductor wafer contains many basal plane dislocations (BPDs) that are converted into stacking faults by the recombination energy of electrons and holes, the number of stacking faults in the semiconductor wafer increases, which results in a problem that the number of semiconductor chips that are rejected as defective increases, resulting in a very poor yield.

[0010] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device and a method of inspecting a silicon carbide semiconductor device that can improve yield. [Means for solving the problem]

[0011] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. An active region is provided in a semiconductor substrate made of silicon carbide. A first semiconductor region of a first conductivity type is provided within the semiconductor substrate. A second semiconductor region of a second conductivity type is provided in the active region between a front surface of the semiconductor substrate and the first semiconductor region. An element structure is provided in which a current flows through a pn junction between the second semiconductor region and the first semiconductor region. The operating environment temperature is within a predetermined range of 100°C or more. a ratio of the total area of ​​stacking faults in the semiconductor substrate to the area of ​​the active region is 10% or less when the withstand voltage is 1.2 kV and the operating environment temperature is 150° C. or more; a ratio of the total area of ​​stacking faults in the semiconductor substrate to the area of ​​the active region is 5% or less when the withstand voltage is 1.2 kV and the operating environment temperature is less than 150° C.; a ratio of the total area of ​​stacking faults in the semiconductor substrate to the area of ​​the active region is 15% or less when the withstand voltage is 3.3 kV and the operating environment temperature is 150° C. or more; or a ratio of the total area of ​​stacking faults in the semiconductor substrate to the area of ​​the active region is 10% or less when the withstand voltage is 3.3 kV and the operating environment temperature is less than 150° C. Set it up.

[0015] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the rate of increase in on-voltage before and after energization of the body diode formed by the pn junction is a maximum of 3%.

[0016] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the first semiconductor region is 8×10 15 / cm 3 is as follows: The operating environment temperature is 275℃ less than It is characterized in that:

[0017] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the first semiconductor region is 4×10 15 / cm 3 is as follows: The operating environment temperature is 200℃ less than It is characterized in that:

[0018] In addition, the present invention provides a silicon carbide semiconductor device, comprising: The withstand voltage is 1.2kV. The impurity concentration of the first semiconductor region is 7×10 15 / cm 3 8×10 or more 15 / cm 3 The following is the result. The operating environment temperature is Over 150℃ Less than 275℃ The ratio of the total area of ​​stacking faults in the semiconductor substrate to the area of ​​the active region is set to 10% or less.

[0020] In addition, the present invention provides a silicon carbide semiconductor device, comprising: The withstand voltage is 3.3kV.The impurity concentration of the first semiconductor region is 2×10 15 / cm 3 More than 4×10 15 / cm 3 The following is the result. The operating environment temperature is Over 150℃ Less than 200℃ The ratio of the total area of ​​stacking faults in the semiconductor substrate to the area of ​​the active region is set to 15% or less.

[0022] In addition, in the silicon carbide semiconductor device according to the present invention, a breakdown voltage is set based on an impurity concentration of the first semiconductor region.

[0023] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the usage environment temperature is within a predetermined range of 300° C. or less.

[0024] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the element structure has the pn junction, a third semiconductor region of a first conductivity type, a gate insulating film, and a gate electrode. The third semiconductor region is selectively provided between a front surface of the semiconductor substrate and the second semiconductor region. The gate insulating film is provided in contact with a region of the second semiconductor region between the third semiconductor region and the first semiconductor region. The gate electrode is provided on the opposite side of the second semiconductor region with the gate insulating film interposed therebetween. A first electrode is electrically connected to the second semiconductor region and the third semiconductor region. A second electrode is provided on a rear surface of the semiconductor substrate.

[0025] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for inspecting a silicon carbide semiconductor device according to the present invention includes a semiconductor substrate made of silicon carbide, an active region provided in the semiconductor substrate made of silicon carbide, a first semiconductor region of a first conductivity type provided inside the semiconductor substrate, a second semiconductor region of a second conductivity type provided in the active region between a front surface of the semiconductor substrate and the first semiconductor region, and an element structure in which a current flows through a p-n junction between the second semiconductor region and the first semiconductor region, the method having an operating environment temperature in a predetermined range of 100° C. or higher, the method having the following features: A first step is performed in which a current is caused to flow in a forward direction through the p-n junction under an inspection temperature environment equal to or lower than the operating environment temperature. After the first step, a second step is performed in which stacking faults in the semiconductor substrate are detected. A third step is performed in which a total area of ​​stacking faults in the semiconductor substrate is calculated. A fourth step is performed in which the semiconductor substrate having a total area of ​​stacking faults within a predetermined range is selected as a non-defective product. In the fourth step, the higher the withstand voltage is set, the higher the upper limit of the predetermined range is set.

[0026] In the method of inspecting a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the fourth step, the upper limit of the predetermined range is set to a larger value as the inspection temperature is set higher.

[0027] In addition, the method for inspecting a silicon carbide semiconductor device according to the present invention is characterized in that, in the first step, the inspection temperature is lower than a predetermined reference temperature, and in the fourth step, the ratio of the predetermined range is greater than or equal to 0% and less than or equal to 15% with respect to an area of ​​the active region.

[0029] In the method for inspecting a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, an increase rate of the voltage applied to the pn junction before and after the first step is proportional to a ratio of a total area of ​​stacking faults in the semiconductor substrate to an area of ​​the active region. A proportionality coefficient of the proportional relationship having the increase rate as a numerator decreases in inverse proportion to the ambient temperature. The ambient temperature at which the proportionality coefficient becomes zero is obtained as the reference temperature before the fourth step.

[0030] Furthermore, the method of inspecting a silicon carbide semiconductor device according to the present invention is characterized in that, prior to the fourth step, the specified range is obtained within which a rate of increase in the voltage applied to the pn junction with respect to a total area of ​​stacking faults in the semiconductor substrate before and after the first step is 3% or less. Effect of the Invention

[0031] According to the silicon carbide semiconductor device and the method for inspecting the silicon carbide semiconductor device of the present invention, silicon carbide semiconductor devices that have conventionally been deemed defective can be made into non-defective products, thereby achieving an effect of improving the yield. [Brief description of the drawings]

[0032] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 2 is a cross-sectional view showing a state in which the active region of FIG. 1 is in operation. [Diagram 3] FIG. 1 is a characteristic diagram showing voltage-current characteristics in Experimental Example 1. [Figure 4] FIG. 1 is a characteristic diagram showing voltage-current characteristics in Experimental Example 1. [Diagram 5] 1 is a table showing the Von increase rate in Experimental Example 1. [Figure 6] FIG. 11 is a characteristic diagram showing the temperature dependence of the on-state voltage in Experimental Example 2. [Figure 7] 13 is a table showing an on-state voltage before a current is passed through a body diode in Experimental Example 2. [Figure 8] 13 is a table showing the increase in Von and the rate of increase in Von before and after current is passed through a body diode in Experimental Example 2. [Figure 9] FIG. 13 is a characteristic diagram showing the temperature dependency of an increase in Von in Experimental Example 2. [Figure 10] FIG. 13 is a characteristic diagram showing the temperature dependence of the Von increase rate in Experimental Example 2. [Figure 11] FIG. 13 is a characteristic diagram showing the relationship between on-state voltage and stacking fault area in Experimental Example 3. [Figure 12] FIG. 13 is a characteristic diagram showing the relationship between on-state voltage and stacking fault area in Experimental Example 3. [Figure 13] FIG. 13 is a characteristic diagram showing the temperature dependence of the ΔVon / SF area ratio in Experimental Example 4. [Figure 14] FIG. 13 is a characteristic diagram showing the relationship between drift resistance and stacking faults in the reference example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Preferred embodiments of the silicon carbide semiconductor device and the method for inspecting the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. In the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. Furthermore, it is preferable that the numerical values ​​of each temperature include up to ±5° C. in consideration of variations.

[0034] (Embodiment) A method for inspecting a silicon carbide semiconductor device according to an embodiment will be described by taking a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with a MOS gate) having a trench gate structure as an example. Fig. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. Fig. 2 is a cross-sectional view showing a state during operation of the active region of Fig. 1. Figs. 2(a) and 2(b) respectively show a MOSFET when it is on and a body diode (BD) of the MOSFET when it is conducting.

[0035] First, the structure of a silicon carbide semiconductor device according to an embodiment will be described. A silicon carbide semiconductor device 10 according to an embodiment shown in FIGS. 1 and 2 has a p-type base region (second semiconductor region) 4 and an n-type base region (second semiconductor region) 5 on the front surface side of a semiconductor substrate (semiconductor chip) 30 made of silicon carbide (SiC) in an active region 41. - The vertical MOSFET has a MOS gate (element structure) in which a current (drift current) flows in a direction (reverse direction of the pn junction) from the back surface to the front surface of the semiconductor substrate 30 through a pn junction with the first semiconductor region 2b. The operating temperature of the silicon carbide semiconductor device 10 is within a predetermined range of, for example, 100°C or higher and 300°C or lower.

[0036] The semiconductor substrate 30 is made of silicon carbide. + On the front surface of the starting substrate 31, n-type buffer regions 2a, - The epitaxial layers 32 to 34 that become the n-type drift region 2b and the p-type base region 4 are epitaxially grown in sequence. The main surface of the semiconductor substrate 30 facing the p-type epitaxial layer 34 is the front surface, and the n-type + The main surface on the mold starting substrate 31 side is referred to as the back surface. The active region 41 is a region through which a main current (drift current) flows when the MOSFET is in an on-state, and multiple unit cells of the MOSFET having the same structure are arranged adjacent to each other. The active region 41 has, for example, a substantially rectangular planar shape, and is a semiconductor substrate 30 It is located approximately in the center.

[0037] The edge termination region 42 is a region between the active region 41 and the end (chip end) of the semiconductor substrate 30, and surrounds the periphery of the active region 41 in a substantially rectangular shape. The edge termination region 42 has a function of maintaining a breakdown voltage by mitigating the electric field on the front surface side of the semiconductor substrate 30. A general breakdown voltage structure (not shown) is disposed in the edge termination region 42. The breakdown voltage is the limit voltage (withstand voltage) at which the silicon carbide semiconductor device 10 does not malfunction or break down. The overall breakdown voltage of the silicon carbide semiconductor device 10 is determined, for example, by the breakdown voltage of the active region 41, and is set to be higher in the active region 41 than in the edge termination region 42.

[0038] n +When basal plane dislocations are present in the starting substrate 31, the p-type base region 4 and the n - When a current flows in the forward direction from the front surface to the back surface of the semiconductor substrate 30 through the pn junction with the type drift region 2b (when a BD current is applied, which will be described later), + Stacking faults (SFs) 35 (hatched portion), which are factors that cause an increase in the on-voltage or on-resistance of the MOSFET (characteristic degradation), grow in the epitaxial layers 32 to 34 from the basal plane dislocations of the starting substrate 31. The on-voltage is the minimum drain-source voltage (the difference between the drain-source voltage of the p-type base region 4 and the n-type base region 5) required to turn on the silicon carbide semiconductor device 10. - 1. The voltage applied to the pn junction with the n-type drift region 2b.

[0039] The higher the breakdown voltage or the operating temperature of silicon carbide semiconductor device 10, or both, the smaller the adverse effects of stacking faults 35, so the ratio of the total area (total surface area: hereinafter referred to as stacking fault area) of stacking faults 35 in semiconductor substrate 30 to the area (surface area) of active region 41 can be set to a large value (see FIGS. 11 and 12). The upper limit of the operating temperature of silicon carbide semiconductor device 10 is determined by the heat resistance of peripheral members (not shown) such as wires, solder layers, and a resin case around semiconductor substrate 30. Since silicon carbide itself can withstand temperatures exceeding 300°C, the operating temperature of silicon carbide semiconductor device 10 may be higher than 300°C depending on the heat resistance of the peripheral members.

[0040] Furthermore, when the ambient temperature of silicon carbide semiconductor device 10 is equal to or higher than a predetermined temperature (hereinafter referred to as the reference temperature) described below (see FIG. 13), even if stacking faults 35 are present in semiconductor substrate 30, the on-voltage of silicon carbide semiconductor device 10 does not increase. Therefore, silicon carbide semiconductor device 10 is a good product regardless of the presence or absence of stacking faults 35. Therefore, when the ambient temperature of silicon carbide semiconductor device 10 is equal to or higher than the reference temperature, the stacking fault area of ​​semiconductor substrate 30 may be the same as the total area of ​​semiconductor substrate 30 or the total area of ​​active region 41 (i.e., the upper limit of the appropriate range of the ratio of the stacking fault area of ​​semiconductor substrate 30 to the area of ​​semiconductor substrate 30 or active region 41 may be 100%).

[0041] The criterion temperature is a temperature exceeding 100°C, and can be set lower as the withstand voltage is set higher. For example, when the withstand voltage is 1.2 kV or higher, the criterion temperature is about 275°C or lower. When the withstand voltage is 3.3 kV or higher, the criterion temperature is about 200°C. When the withstand voltage is more than 3.3 kV, n - Depending on the impurity concentration and thickness of the drift region 2b, the reference temperature may be less than 200° C. (for example, about 150° C.). - is set based on the impurity concentration (doping concentration) of the n-type drift region 2b. - The lower the impurity concentration in the type drift region 2b, the higher the impurity concentration becomes.

[0042] Specifically, n - The impurity concentration of the type drift region 2b is, for example, 8×10 15 / cm 3 When the withstand voltage is 3.3 kV or more, the 15 / cm 3 More specifically, when the withstand voltage is about 1.2 kV, n - The impurity concentration of the drift region 2b is, for example, 7×10 15 / cm 3 8×10 or more 15 / cm 3 For example, 7.4×10 15 / cm 3 When the withstand voltage is about 3.3 kV, n - The impurity concentration of the drift region 2b is, for example, 2×10 15 / cm 3 More than 4×10 15 / cm 3 For example, 2.9×10 15 / cm 3 That's about it.

[0043] On the other hand, when the ambient temperature of silicon carbide semiconductor device 10 is below the reference temperature, if the ratio of the stacking fault area of ​​semiconductor substrate 30 to the area of ​​active region 41 is, for example, about 0% to 15% (appropriate range), even silicon carbide semiconductor device 10 including stacking faults 35 can be determined to be a good product (see FIGS. 11 and 12). A good product is a silicon carbide semiconductor device 10 in which the rate of increase in on-voltage Von before and after energization of the body diode at the ambient temperature (hereinafter referred to as Von increase rate (relative value of on-voltage increase); Von increase rate [%] = increase in on-voltage before and after energization of body diode / on-voltage before energization of body diode × 100%) is, for example, about 3% or less.

[0044] The Von increase rate of the silicon carbide semiconductor device 10 can be set appropriately. The reference temperature differs depending on the element structure (e.g., breakdown voltage) of the silicon carbide semiconductor device 10. Therefore, the reference temperature is determined according to the element structure of the silicon carbide semiconductor device 10. When the ambient temperature of the silicon carbide semiconductor device 10 is lower than the reference temperature, the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 is determined according to the element structure of the silicon carbide semiconductor device 10 and the ambient temperature of the silicon carbide semiconductor device 10 so that the Von increase rate (or the Von increase amount described later) of the silicon carbide semiconductor device 10 is equal to or lower than a predetermined value.

[0045] Specifically, for example, when the withstand voltage is 1.2 kV, and the operating environment temperature of silicon carbide semiconductor device 10 is equal to or higher than 150° C. and lower than the judgment reference temperature, silicon carbide semiconductor device 10 can be judged as a good product if the ratio of the stacking fault area of ​​semiconductor substrate 30 is, for example, about 10% or less (appropriate range) to the area of ​​active region 41. Also, when the withstand voltage is 1.2 kV, and the operating environment temperature of silicon carbide semiconductor device 10 is, for example, lower than 150° C., silicon carbide semiconductor device 10 can be judged as a good product if the ratio of the stacking fault area of ​​semiconductor substrate 30 is, for example, about 5% or less (appropriate range) to the area of ​​active region 41.

[0046] When the withstand voltage is 3.3 kV, and the operating environment temperature of silicon carbide semiconductor device 10 is, for example, equal to or higher than 150° C. and lower than the judgment reference temperature, silicon carbide semiconductor device 10 can be judged as a good product if the ratio of the stacking fault area of ​​semiconductor substrate 30 is, for example, about 15% or less (appropriate range) to the area of ​​active region 41. Also, when the withstand voltage is 3.3 kV, and the operating environment temperature of silicon carbide semiconductor device 10 is, for example, lower than 150° C., silicon carbide semiconductor device 10 can be judged as a good product if the ratio of the stacking fault area of ​​semiconductor substrate 30 is, for example, about 10% or less (appropriate range) to the area of ​​active region 41.

[0047] The upper limit of the operating temperature of a MOSFET when the semiconductor material is silicon (Si) (the heat resistance temperature of silicon) is 150° C. For this reason, the silicon carbide semiconductor device 10 according to this embodiment is useful when the operating temperature is 150° C. or higher. Also, as described above, the higher the breakdown voltage, the smaller the adverse effect of stacking faults 35 (see FIGS. 11 and 12). For this reason, at a high breakdown voltage of 1.2 kV or higher, - It is estimated that by appropriately adjusting the impurity concentration in type drift region 2b, the effects of this embodiment can be obtained when silicon carbide semiconductor device 10 is used at an environmental temperature of 100° C. or higher, preferably 125° C. or higher.

[0048] n + The starting substrate 31 is n + The n-type drain region 1 is an n-type buffer region 2a. + Alternatively, the n-type buffer region 2a may have a two-layer structure in which a low-concentration n-type epitaxial layer and a high-concentration n-type epitaxial layer having a higher impurity concentration than the low-concentration n-type epitaxial layer are stacked in this order on the starting substrate 31. - Holes (positive holes) generated at the pn junction interface with the n-type drift region 2b recombine in the n-type buffer region 2a to form n + The n-type buffer region 2a has a function of preventing the n-type starting substrate 31 from being reached. + It has the function of suppressing the growth of stacking faults 35 in the epitaxial layers 32 to 34 from the starting substrate 31 .

[0049] The n-type buffer region 2a may not be provided. When the n-type buffer region 2a is not provided, + On the front surface of the starting substrate 31, - n-type drift region 2b - A type epitaxial layer 33 is epitaxially grown. - The n-type drift region 2b is - The n-type epitaxial layer 33 includes an n-type current diffusion region 3 and first and second p-type epitaxial layers 32, which will be described later. + Type regions 21, 22 and n + This is the part excluding the mold region 23. - The n-type drift region 2b is connected to the n-type current diffusion region 3 and the first and second p-type + Type regions 21, 22 and n + The dopant is provided between the n-type region 23 and the n-type buffer region 2a so as to be in contact with these regions.

[0050] The p-type base region 4 is a region of the p-type epitaxial layer 34, which will be described later. ++ A type source region (third semiconductor region) 5 and a p ++ The p-type base region 4 is a portion excluding the n-type contact region 6. - The n-type drift region 2b is provided between the n-type drift region 2b. - An n-type current diffusion region 3, which is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers, may be provided between the n-type drift region 2b and the p-type base region 4 in contact with these regions. The n-type current diffusion region 3 is located closer to the n-type drift region 2b than the bottom surface of a trench 7 described later. + The trench reaches a deep position on the drain region 1 side.

[0051] The MOS gate is a p-type base region 4, ++ Type source region 5, p ++ The trench gate structure is composed of a contact region 6, a trench 7, a gate insulating film 8 and a gate electrode 9, and is arranged for each unit cell of the MOSFET. ++ Type source region 5 and p ++The contact regions 6 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 4, in contact with the p-type base region 4, and exposed on the front surface of the semiconductor substrate 30. Exposure on the front surface of the semiconductor substrate 30 means that the contact regions 6 are in contact with a source electrode 13 (described later) through a contact hole in an interlayer insulating film 11 (described later).

[0052] p ++ The p-type contact region 6 may not be provided. ++ Instead of the p-type contact region 6, the p-type base region 4 is exposed on the front surface of the semiconductor substrate 30. + Type regions 21, 22 and n + The n-type region 23 is located closer to the bottom of the trench 7 than the n-type region 23. + The first and second p-type drain regions are disposed at a deep position on the side of the first and second p-type drain regions. + The mold regions 21 and 22 have the function of reducing the electric field applied to the bottom surface of the trench 7. + The first p-type region 21 is provided apart from the p-type base region 4 and faces the bottom surface of the trench 7 in the depth direction. + The mold region 21 may be electrically connected to the source electrode 13 at a portion not shown.

[0053] 1st p. + The mold region 21 may surround the bottom surface of the trench 7 and be exposed to the bottom surface of the trench 7. The exposure to the bottom surface of the trench 7 means that the bottom surface of the trench 7 is in contact with the gate insulating film 8. + The mold region 22 is formed between the adjacent trenches 7 and has a first p + The n-type region 21 and the trench 7 are spaced apart from each other, and are in contact with the p-type base region 4. + The mold region 23 is a second p + Type region 22 and n - The n-type drift region 2b is provided between the n-type drift region 2b and in contact with these regions. + The first p of the bottom surface of the trench 7 is formed by the mold region 23. + The breakdown voltage ensured by the mold region 21 is the second p between the adjacent trenches 7. + This is higher than the withstand voltage ensured by the mold region 22 .

[0054] Trench 7 is n ++ The n-type current diffusion region 3 (or the n-type current diffusion region 3 if the n-type current diffusion region 3 is not provided) penetrates the p-type source region 5 and the p-type base region 4. - The trench 7 extends from the source pad 14 to the gate electrode 9 (which is a first region of the trench 7 that extends from the source pad 14 to the gate electrode 9). A gate electrode 9 is provided inside the trench 7 with a gate insulating film 8 interposed therebetween. The gate electrodes 9 of all the unit cells are electrically connected to a gate pad (electrode pad: not shown). An interlayer insulating film 11 covers the gate electrode 9. A barrier metal 12 may be provided on the entire surface between the interlayer insulating film 11 and a source pad 14 (described later) to prevent diffusion of metal atoms from the source pad 14 side to the gate electrode 9 side, for example.

[0055] The source electrode (first electrode) 13 is an n-type GaN layer exposed through a contact hole in the interlayer insulating film 11. ++ Type source region 5 and p ++ Type contact region 6(p ++ When the n-type contact region 6 is not provided, the n-type contact region 6 is in contact with the p-type base region 4). ++ Type source region 5 and p ++ The source pad (electrode pad: first electrode) 14 is provided on substantially the entire front surface of the semiconductor substrate 30 so as to fill the contact hole of the interlayer insulating film 11. The drain electrode (second electrode) 15 is provided on the rear surface (n + The back surface of the starting substrate 31 is provided on the entire surface of the substrate. + The gate electrode 1 is electrically connected to the drain region 1 .

[0056] Since the silicon carbide semiconductor device 10 according to the embodiment described above is used at a high environmental temperature of 100° C. or more, the device has a configuration that suppresses heat dissipation from the semiconductor substrate 30 so that the temperature of the semiconductor substrate 30 does not drop. The configuration that suppresses heat dissipation from the semiconductor substrate 30 means, for example, not joining a heat dissipation means such as a heat dissipation fin to an insulating substrate such as a DCB (Direct Copper Bonding) substrate on which the semiconductor substrate 30 is mounted. Furthermore, the silicon carbide semiconductor device 10 according to the embodiment is screened for conformity or non-conformity by a screening test in which a body diode is energized under a predetermined inspection temperature environment described later before shipment or before mounting.

[0057] The operation of the silicon carbide semiconductor device 10 according to the embodiment will now be described. When a gate voltage equal to or greater than a gate threshold voltage is applied to the gate electrode 9 while a positive voltage (drain-source voltage Vds) with respect to the source pad 14 is applied to the drain electrode 15, a channel (n-type inversion layer) is formed in the portion of the p-type base region 4 along the trench 7. + From the n-type drain region 1 to the n-type buffer region 2a, - Through the drift region 2b and the channel ++ A drain-source current Ids flows toward the type-source region 5, and the MOSFET (silicon carbide semiconductor device 10) turns on (FIG. 2(a)).

[0058] On the other hand, when a gate voltage less than the gate threshold voltage is applied to the gate electrode 9 while a positive voltage with respect to the source pad 14 is applied to the drain electrode 15, the first and second p + The p-type regions 21 and 22 and the p-type base region 4, and the n-type current diffusion regions 3 and + type area 23, n - The pn junction between the n-type drift region 2b and the n-type buffer region 2a is reverse biased, so that the drain-source current Ids does not flow and the MOSFET remains in the off state. A depletion layer spreads from the pn junction, and the electric field applied to the gate insulating film 8 on the bottom surface of the trench 7 located on the source electrode 13 side of the pn junction is relaxed.

[0059] When the MOSFET is turned off, a negative voltage (forward voltage Vf of the body diode) is applied to the drain electrode 15 with respect to the source pad 14. + The p-type regions 21 and 22 and the p-type base region 4, and the n-type current diffusion regions 3 and + type area 23, n - A forward current If flows through a parasitic pn diode (body diode: BD) formed by the pn junction between the n-type drift region 2b and the n-type buffer region 2a (FIG. 2(b)). When a forward current If flows through the body diode of the MOSFET (when BD is energized), stacking faults 35 (see FIG. 1) grow inside the semiconductor substrate 30, and the on-voltage Von of the MOSFET increases.

[0060] Therefore, before the silicon carbide semiconductor device 10 (product) is shipped or mounted, a screening test is performed to select silicon carbide semiconductor devices 10 that are good products. Specifically, first, a current is passed through the body diode in advance in an inspection temperature environment that is equal to or lower than the usage environment temperature of the silicon carbide semiconductor device 10 (the lower limit if the usage environment temperature has a range), to grow stacking faults 35 in the semiconductor substrate 30 (first step). Next, the stacking faults 35 in the semiconductor substrate 30 are made to emit light by a general photoluminescence (PL) method and observed, to detect the positions and sizes of the stacking faults 35 in the semiconductor substrate 30 (second step).

[0061] Next, the stacking fault area of ​​the semiconductor substrate 30 is calculated based on the size (length and width) of the stacking faults 35 (see the hatched portion in FIG. 1) viewed from the front surface side of the semiconductor substrate 30 (third step). The stacking fault area of ​​the semiconductor substrate 30 is the total value of the surface area (≈length×width) of each stacking fault 35 viewed from the front surface side of the semiconductor substrate 30. Next, for example, based on the relationship between the Von increase rate at the operating temperature of the silicon carbide semiconductor device 10 and the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 (see FIGS. 11 and 12 described later), the above-mentioned appropriate range (predetermined range) of the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 at the operating temperature of the silicon carbide semiconductor device 10 is acquired.

[0062] This appropriate range may be obtained based on the increase in on-voltage before and after current is passed through the body diode of silicon carbide semiconductor device 10 (hereinafter referred to as the Von increase amount (absolute value of on-voltage increase)). The relationship between the Von increase rate (or Von increase amount) at the operating temperature of silicon carbide semiconductor device 10 and the ratio of the stacking fault area of ​​semiconductor substrate 30 to the area of ​​active region 41 is obtained in advance, for example, by simulation or experiment. At this time, for example, a judgment reference temperature may be obtained. Then, silicon carbide semiconductor device 10 having a ratio of the stacking fault area of ​​semiconductor substrate 30 to the area of ​​active region 41 within the above appropriate range is selected as a non-defective product (fourth step).

[0063] Also, as described above, if the operating environment temperature of silicon carbide semiconductor devices 10 is equal to or higher than the reference temperature, all silicon carbide semiconductor devices 10 may be determined to be non-defective. The reference temperature is obtained in advance by simulation, experiment, or the like based on the temperature dependency (see FIG. 13 described later) of a value obtained by dividing the Von increase rate of silicon carbide semiconductor devices 10 having a predetermined breakdown voltage by the ratio of the stacking fault area of ​​semiconductor substrate 30 to the area of ​​active region 41 (hereinafter referred to as ΔVon / SF area ratio: proportionality coefficient of the approximation line in FIGS. 11 and 12 described later). The operating environment temperature at which the ΔVon / SF area ratio becomes zero is obtained as the reference temperature.

[0064] (Experimental Example 1) The relationship between the on-voltage of the MOSFET and the stacking faults 35 was examined. FIGS. 3 and 4 are characteristic diagrams showing the voltage-current characteristics of Experimental Example 1. FIG. 5 is a chart showing the Von increase rate of Experimental Example 1. FIGS. 3 and 4 show the relationship between the drain-source voltage Vds and the drain-source current Ids when a MOSFET (hereinafter, referred to as Experimental Example 1) having a MOS gate of the silicon carbide semiconductor device 10 (see FIG. 1) according to the above-described embodiment is operated in a temperature environment of room temperature (25° C.) and 150° C. Both FIGS. 3 and 4 show a sample having stacking faults 35 (with stacking faults) and a sample having no stacking faults 35 (without stacking faults).

[0065] For both the samples with and without stacking faults in Experimental Example 1 in Figures 3 and 4, the breakdown voltage was 1.2 kV and the gate voltage was 15 V. Figure 5 shows the increase rate of the drain-source voltage Vds (part indicated by the horizontal double arrow) when the drain-source current Ids in Experimental Example 1 is 30 A. The increase rate of the drain-source voltage Vds is the ratio of the difference obtained by subtracting the drain-source voltage Vds of the sample without stacking faults from the drain-source voltage Vds of the sample with stacking faults to the drain-source voltage Vds of the sample with stacking faults, and is the increase rate of the on-voltage Von before and after current is passed through the body diode of the MOSFET (Von increase rate).

[0066] From the results shown in FIG. 5, the increase rate of the drain-source voltage Vds in a room temperature environment was 27% (≒(3.84V-3.03V) / 3.03V), whereas the increase rate of the drain-source voltage Vds in a 150°C temperature environment was 14% (≒(4.33V-3.80V) / 3.80V). It was confirmed that the increase rate of the drain-source voltage Vds in a 150°C temperature environment can be suppressed to about half that in a room temperature environment. Therefore, it was confirmed that even if stacking faults 35 exist in the semiconductor substrate 30, the adverse effects of the stacking faults 35 can be reduced by increasing the operating temperature of the MOSFET.

[0067] (Experimental Example 2) The relationship between the on-voltage of a MOSFET and the temperature of the environment in which it is used was examined. FIG. 6 is a characteristic diagram showing the temperature dependency of the on-voltage of Experimental Example 2. FIG. 7 is a chart showing the on-voltage before the body diode (BD) of Experimental Example 2 is energized. FIG. 8 is a chart showing the increase in Von and the increase rate of Von before and after the body diode is energized in Experimental Example 2. FIG. 6 shows the relationship between the on-voltage of a MOSFET (hereinafter, referred to as Experimental Example 2) having a MOS gate of silicon carbide semiconductor device 10 (see FIG. 1) according to the above-described embodiment (see FIG. 1) and the temperature of the environment in which it is used. FIG. 6 shows the on-voltage Von of two samples (hereinafter, referred to as samples 1 and 2) of Experimental Example 2.

[0068] For both Samples 1 and 2 of Experimental Example 2, the breakdown voltage was 1.2 kV, and the operating environment temperatures (ambient temperatures when measuring the on-state voltage and when the body diode was energized) were room temperature (25°C), 50°C, 100°C, and 150°C. Samples 1 and 2 of Experimental Example 2 were semiconductor chips (semiconductor substrate 30) cut from the same semiconductor wafer, in which stacking faults 35 had grown due to the body diode being energized. The horizontal and vertical axes of FIG. 6 respectively represent the operating environment temperature and on-state voltage of Experimental Example 2. The temperature dependence of the on-state voltage of Samples 1 and 2 of Experimental Example 2 before the body diode is energized is shown in FIG. 7, and the amount of Von increase and the Von increase rate are shown in FIG. 8.

[0069] 6 to 8, it was confirmed that when stacking faults 35 grow in semiconductor substrate 30 due to current flow through the body diode, the on-voltage increases. It was also confirmed that both the Von increase rate and the Von increase amount depend on the operating temperature of the MOSFET, and that the higher the operating temperature is, the less likely the on-voltage increases (the Von increase rate and Von increase amount become smaller). For example, it was confirmed that for both Samples 1 and 2 in Experimental Example 2, when the operating temperature is 150°C, the Von increase rate (or Von increase amount) is reduced to about half of that when the operating temperature is 25°C.

[0070] FIG. 9 is a characteristic diagram showing the temperature dependency of the Von increase amount in Experimental Example 2. FIG. 10 is a characteristic diagram showing the temperature dependency of the Von increase rate in Experimental Example 2. The horizontal axis of FIGS. 9 and 10 is the operating environment temperature of Experimental Example 2, and the vertical axis of FIGS. 9 and 10 is the Von increase amount and Von increase rate of Experimental Example 2 in FIG. 8, respectively. Based on the approximation line of each data point of Samples 1 and 2 of Experimental Example 2 shown in FIGS. 9 and 10, the operating environment temperatures at which the Von increase amount is 0V and the Von increase rate is 0% were extrapolated. As a result, it was confirmed that when the operating environment temperature of the MOSFET is about 300° C., the on-voltage does not increase (Von increase amount=0V, Von increase rate=0%).

[0071] Therefore, it has been confirmed that, if a MOSFET is used in a temperature environment with the highest possible temperature, even if stacking faults 35 occur in the semiconductor substrate 30, the on-voltage does not increase or increases only to a negligible extent. The operating temperature of a MOSFET is determined based on the heat resistance temperature of the peripheral components of the MOSFET (wires, solder layer, resin case), as described above. In addition, the operating temperature at which the on-voltage of a MOSFET does not increase (i.e., the increase in Von is 0 V and the increase rate of Von is 0%) is determined by the operating temperature of the element structure (specifically, n - Impurity concentration of the type drift region 2b: depends on the above-mentioned non-patent document 1).

[0072] (Experimental Example 3) The relationship between the on-voltage and the stacking fault area of ​​the MOSFET was examined. Figures 11 and 12 are characteristic diagrams showing the relationship between the on-voltage and the stacking fault area in Experimental Example 3. For a MOSFET (hereinafter referred to as Experimental Example 3) having a MOS gate of the silicon carbide semiconductor device 10 (see Figure 1) according to the above-mentioned embodiment, the relationship between the Von increase rate and the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 is shown in Figures 11 and 12. In Figures 11 and 12, the horizontal axis shows the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 (SF area [%]), and the vertical axis shows the Von increase rate (ΔVon [%]).

[0073] 11 and 12 show a number of samples with different operating environmental temperatures. In Experimental Example 3 of FIG. 11, the withstand voltage is 1.2 kV and the chip size (size of the semiconductor substrate 30) is 3.8 mm. 2 and the operating environment temperatures were room temperature (25° C.), 50° C., 100° C., and 150° C. In Experimental Example 3 of FIG. 12, the withstand voltage was 3.3 kV, the chip size was 7.6 mm×6.7 mm, and the operating environment temperatures were room temperature and 150° C. It was confirmed that for each sample of Experimental Example 3 of FIGS. 11 and 12, when the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 was 40% or less, the Von increase rate increased in proportion to the ratio of the stacking fault area.

[0074] Specifically, the proportionality coefficient (slope) of the approximation line of each sample in Experimental Example 3 in FIG. 11 was 0.84, 0.83, 0.70, and 0.45 at room temperature, 50° C., 100° C., and 150° C., respectively. The proportionality coefficient of the approximation line of each sample in Experimental Example 3 in FIG. 12 was 0.90 and 0.26 at room temperature and 150° C., respectively. The proportionality coefficient of the approximation line of each sample was calculated by dividing the Von increase rate ΔVon by the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 (SF area ratio). In both Experimental Example 3 in FIGS. 11 and 12, the proportionality coefficient (=ΔVon / SF area ratio) decreased as the operating environment temperature increased.

[0075] For example, in each of Experimental Examples 3 in FIGS. 11 and 12, it was confirmed that when the operating temperature is 150° C., the proportionality coefficient is about 0.5 times and about 0.3 times, respectively, compared to when the operating temperature is 25° C. The smaller the proportionality coefficient, the smaller the adverse effect caused by the stacking faults 35. That is, the higher the operating temperature of the MOSFET, the higher the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 can be. This proportionality relationship does not depend on the chip size. It was also confirmed that the higher the breakdown voltage, the higher the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 can be.

[0076] (Experimental Example 4) The temperature dependency of the Von increase rate with respect to the ratio of the stacking fault area of ​​the semiconductor substrate 30 to the area of ​​the active region 41 was examined. Fig. 13 is a characteristic diagram showing the temperature dependency of the ΔVon / SF area ratio in Experimental Example 4. Fig. 13 is a plot of the proportionality coefficient (ΔVon / SF area ratio: vertical axis) of the approximation line of each sample in Figs. 11 and 12 against the operating environment temperature (horizontal axis).

[0077] As shown in Fig. 13, the ΔVon / SF area ratio has a negative correlation with the use environment temperature. Based on the approximation line (solid line portion) of the data points of each sample in Experimental Example 3 in Fig. 13, the use environment temperature at which the ΔVon / SF area ratio becomes zero (= judgement The reference temperature is extrapolated (dashed line). judgementIn a temperature environment where the temperature is equal to or higher than the reference temperature, the on-state voltage of the MOSFET does not increase. For example, at a breakdown voltage of 1.2 kV, the ΔVon / SF area ratio becomes zero at 275°C (the part indicated by the arrow of reference symbol 51). judgement This is the reference temperature. At a breakdown voltage of 3.3 kV, the ΔVon / SF area ratio becomes zero at 200°C (the part indicated by the arrow of reference number 52). judgement This is the reference temperature.

[0078] (Reference example) The relationship between the drift resistance (resistance of the drift region) of a MOSFET and stacking faults 35 will be described. FIG. 14 is a characteristic diagram showing the relationship between the drift resistance and stacking faults of a reference example. FIG. 14 is FIG. 9 of the above-mentioned Non-Patent Document 1. The horizontal axis of FIG. 14 corresponds to the ambient temperature in which the MOSFET is used. The vertical axis of FIG. 14 is the ratio r of the drift resistance of a MOSFET having stacking faults 35 to the drift resistance of a MOSFET not having stacking faults 35 (hereinafter simply referred to as the drift resistance ratio). FIG. 14 shows a number of samples (MOSFETs) having different impurity concentrations in the drift region.

[0079] As shown in Fig. 14, Non-Patent Document 1 discloses that, for all samples, the higher the operating temperature of the MOSFET, the smaller the drift resistance ratio r becomes. The drift resistance ratio r becomes 1 when the operating temperature of the MOSFET is 574K (=300°C) (the point indicated by the vertical line of reference numeral 53). In other words, when the operating temperature of the MOSFET is 574K, the drift resistance of a MOSFET having stacking faults 35 becomes equal to the drift resistance of a MOSFET not having stacking faults 35. It is therefore possible to design a configuration that is not adversely affected by stacking faults 35, depending on the operating temperature of the MOSFET.

[0080] The method for inspecting silicon carbide semiconductor device 10 (semiconductor substrate 30) according to the present embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation, a database server, or a web server. The detection results of stacking faults 35 obtained by executing this program, and the calculation results of the stacking fault area and the Von increase rate (or Von increase amount) of semiconductor substrate 30, as well as information previously acquired for obtaining these detection results and calculation results, are stored in a computer-readable storage medium (not shown).

[0081] This program is recorded on a computer-readable recording medium and executed by being read from the recording medium by a computer or a server. The recording medium may be a solid state drive (SSD), a hard disk drive (HDD), a Blu-ray (registered trademark) Disc (BD), a flexible disk, a USB flash memory, a CD-ROM, an MO, a DVD, etc. This program may also be a transmission medium that can be distributed via a network such as the Internet.

[0082] As described above, according to the embodiment, the operating environment temperature is set within a predetermined range of 100° C. or more, and a current is passed through the body diode in a temperature environment at an inspection temperature equal to or lower than the operating environment temperature to grow stacking faults in advance in the semiconductor substrate (semiconductor chip). Then, silicon carbide semiconductor devices (semiconductor substrates on which element structures are formed: products) in which the total area of ​​stacking faults in the semiconductor substrate falls within the predetermined range are selected as non-defective products. The higher the breakdown voltage or the operating environment temperature, or both, the larger the total area of ​​stacking faults in the semiconductor substrate can be set, and silicon carbide semiconductor devices that were previously considered defective in the past (for example, in the above-mentioned Patent Documents 1 and 2) can be considered as non-defective products.

[0083] For example, assume that silicon carbide semiconductor devices with an increase rate of on-voltage (Von increase rate) of 3% or more before and after current is passed through the body diode are to be removed as defective products. In this case, a silicon carbide semiconductor device with a Von increase rate of less than 3% and an operating environment temperature of 150°C that is selected as a non-defective product will have a Von increase rate of 9% or more when used in a room temperature environment. In other words, by setting the operating environment temperature to 150°C, a silicon carbide semiconductor device that was removed as a defective product because its Von increase rate is 3% or more and less than 9% when used in a room temperature environment can be made a non-defective product when used in a temperature environment of 150°C.

[0084] Therefore, the higher the withstand voltage or the operating environment temperature, or both, the more relaxed the selection conditions for non-defective silicon carbide semiconductor devices are, and the more the yield can be improved. According to the embodiment, the present invention is useful for parts used in trains and automobiles where the operating environment temperature is 100°C or higher, and in spaces with a lot of radiation (outer space, inside nuclear power generators). Currently, by configuring the silicon carbide semiconductor device without providing a heat dissipation means, the silicon carbide semiconductor device reaches 100°C or higher in about 5 minutes from when it is turned on. Therefore, when the silicon carbide semiconductor device is used, the total area of ​​stacking faults in the semiconductor substrate can be maintained at approximately the same area as when the silicon carbide semiconductor device was inspected.

[0085] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, a MOS gate having a planar gate structure may be used instead of a trench gate structure. The present invention is also applicable to other silicon carbide semiconductor devices (such as pn junction diodes) having an element structure in which stacking faults grow when a forward current flows through a pn junction formed inside a semiconductor substrate. A plurality of element structures may be formed on a semiconductor substrate, such as when a circuit section for protecting and controlling a main semiconductor element is mounted on the same semiconductor substrate as the main semiconductor element. For example, in the above-mentioned embodiment, the dimensions and impurity concentrations of each part of the silicon carbide semiconductor device are set in various ways according to the required specifications. The present invention is also applicable when the conductivity type (n-type, p-type) is reversed. [Industrial Applicability]

[0086] As described above, the silicon carbide semiconductor device and the method for inspecting a silicon carbide semiconductor device according to the present invention are useful for silicon carbide semiconductor devices in which a parasitic pn diode (body diode) is formed at a pn junction inside a semiconductor substrate, and are particularly suitable for MOSFETs and pn diodes. [Explanation of symbols]

[0087] 1n + Type drain region 2a n-type buffer region 2b n - Type Drift Region 3 n-type current diffusion region 4 p-type base region 5n ++ Type Source Area 6 p ++ Mold Contact Area 7. Trench 8 Gate insulating film 9 Gate electrode 10 Silicon carbide semiconductor device 11 Interlayer insulating film 12 Barrier metal 13 Source electrode 14 Sauce Pad 15 Drain electrode 21,22 p + type area 23n + type area 30 Semiconductor substrate (semiconductor chip) 31 n + Starting substrate 32 n-type epitaxial layer 33n - Type epitaxial layer 34 p-type epitaxial layer 35 Stacking faults

Claims

1. an active region provided in a semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided within the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the front surface of the semiconductor substrate and the first semiconductor region in the active region; An element structure in which a current flows through a pn junction between the second semiconductor region and the first semiconductor region, The operating environment temperature is within a predetermined range of 100°C or higher, a breakdown voltage of 1.2 kV and an operating temperature of 150° C. or higher, and a ratio of a total area of ​​stacking faults in the semiconductor substrate to an area of ​​the active region is 10% or less; a breakdown voltage of 1.2 kV and an operating temperature of less than 150° C.; and a ratio of a total area of ​​stacking faults in the semiconductor substrate to an area of ​​the active region is 5% or less; a breakdown voltage of 3.3 kV and an operating temperature of 150° C. or higher, and a ratio of a total area of ​​stacking faults in the semiconductor substrate to an area of ​​the active region is 15% or less; 4. A silicon carbide semiconductor device, comprising: a breakdown voltage of 3.3 kV; an operating environment temperature of less than 150° C.; and a ratio of a total area of ​​stacking faults in the semiconductor substrate to an area of ​​the active region of 10% or less.

2. A silicon carbide semiconductor device as described in claim 1, characterized in that the increase rate of the on-voltage before and after the passage of current through the body diode formed by the pn junction is at most 3%.

3. The impurity concentration of the first semiconductor region is 8×10 15 / cm 3 or less, The silicon carbide semiconductor device according to claim 1 , wherein the ambient temperature during use is less than 275° C.

4. The impurity concentration of the first semiconductor region is 4×10 15 / cm 3 or less, The silicon carbide semiconductor device according to claim 3 , wherein the ambient temperature during use is less than 200° C.

5. The withstand voltage is 1.2 kV, the impurity concentration of the first semiconductor region is 7×10 15 / cm 3 or more and 8×10 15 / cm 3 or less; The operating environment temperature is 150° C. or higher and lower than 275° C., 2 . The silicon carbide semiconductor device according to claim 1 , wherein a ratio of a total area of ​​stacking faults in said semiconductor substrate to an area of ​​said active region is set to 10% or less.

6. The withstand voltage is 3.3 kV, the impurity concentration of the first semiconductor region is not less than 2×10 15 / cm 3 and not more than 4×10 15 / cm 3 , The operating environment temperature is 150° C. or higher and lower than 200° C., 2 . The silicon carbide semiconductor device according to claim 1 , wherein a ratio of a total area of ​​stacking faults in said semiconductor substrate to an area of ​​said active region is set to 15% or less.

7. A silicon carbide semiconductor device as described in any one of claims 1 to 6, characterized in that a breakdown voltage is set based on the impurity concentration of the first semiconductor region.

8. A silicon carbide semiconductor device as described in claim 1, characterized in that the operating environment temperature is within a predetermined range of 300°C or less.

9. The element structure comprises: The pn junction; a third semiconductor region of a first conductivity type selectively provided between the front surface of the semiconductor substrate and the second semiconductor region; a gate insulating film provided in contact with a region of the second semiconductor region between the third semiconductor region and the first semiconductor region; a gate electrode provided on the opposite side of the second semiconductor region with the gate insulating film interposed therebetween; a first electrode electrically connected to the second semiconductor region and the third semiconductor region; 9. The silicon carbide semiconductor device according to claim 1, further comprising: a second electrode provided on a back surface of the semiconductor substrate.

10. An active region provided in a semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided within the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the front surface of the semiconductor substrate and the first semiconductor region in the active region; An element structure in which a current flows through a pn junction between the second semiconductor region and the first semiconductor region, wherein the operating environment temperature is within a predetermined range of 100° C. or more, a first step of flowing a current through the pn junction in a forward direction in a temperature environment at a predetermined inspection temperature equal to or lower than the operating environment temperature; a second step of detecting stacking faults in the semiconductor substrate after the first step; A third step of calculating a total area of ​​stacking faults in the semiconductor substrate; a fourth step of selecting the semiconductor substrate having a total area of ​​stacking faults within a predetermined range as a non-defective product; Including, The method for inspecting a silicon carbide semiconductor device, wherein in the fourth step, the upper limit of the predetermined range is set to a larger value as the withstand voltage is set to a higher value.

11. The method for inspecting a silicon carbide semiconductor device as described in claim 10, characterized in that in the fourth step, the higher the inspection temperature is set, the higher the upper limit value of the specified range is set.

12. In the first step, the inspection temperature is less than a predetermined reference temperature, 12. The method of inspecting a silicon carbide semiconductor device according to claim 11, wherein in the fourth step, the ratio of the predetermined range is set to be equal to or greater than 0% and equal to or less than 15% with respect to an area of ​​the active region.

13. An increase rate of the voltage applied to the pn junction before and after the first step is proportional to a ratio of a total area of ​​stacking faults in the semiconductor substrate to an area of ​​the active region, a proportionality coefficient of the proportional relationship having the increase rate as a numerator becomes smaller in inverse proportion to the usage environmental temperature, 13 . The method of inspecting a silicon carbide semiconductor device according to claim 12 , further comprising the step of: acquiring, before the fourth step, the usage environment temperature at which the proportionality coefficient is zero as the reference temperature.

14. A method for inspecting a silicon carbide semiconductor device described in any one of claims 10 to 12, characterized in that before the fourth step, the specified range is obtained in which the increase rate of the voltage applied to the pn junction relative to the total area of ​​stacking faults in the semiconductor substrate before and after the first step is 3% or less.

Images