Semiconductor device manufacturing method

Abstract

This semiconductor device comprises a first wiring layer (101a), a first semiconductor chip (102a), a second wiring layer (101b), and a second semiconductor chip (102b). This semiconductor device also has formed therein a mold resin layer (104) for encapsulating the first semiconductor chip (102a) on the first wiring layer (101a), and a mold resin layer (104) for encapsulating the second semiconductor chip (102b) on the second wiring layer (101b). The mold resin layers (104) are integrally formed with a through hole (111) therebetween.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. Place It relates to a manufacturing method. [Background technology]

[0002] In recent years, mobile devices such as smartphones have rapidly developed, and the demand for higher density of electronic components is increasing. In response to this demand, active research has been conducted on the package-on-package (PoP) structure. The PoP structure is a structure in which multiple semiconductor chips are stacked vertically, which achieves high density mounting without changing the mounting area.

[0003] When considering mobile applications, the requirements for package thickness are severe, so technology to reduce the thickness of the completed electronic components is essential. a Against this background, attention is being paid to PoP structures that use wafer level packages (WLP). WLP is an integration technology that realizes simultaneous mounting by encapsulating multiple chips on a wafer scale using molding resin. With WLP, the thickness of the completed electronic components is reduced because a substrate is not required for the final package. In addition, due to the characteristics of the manufacturing process, WLP can reduce the manufacturing cost per package through mass production. Such a PoP structure that uses WLP is suitable for mobile applications.

[0004] A typical technique will be described with reference to FIG. 4 (Non-Patent Document 1). This semiconductor device includes a first wiring layer 301, and a first semiconductor chip 302 and a second semiconductor chip 303 mounted on the first wiring layer 301. The first semiconductor chip 302 and the second semiconductor chip 303 are electrically connected via wiring 301a formed on the first wiring layer 301. The wiring 301a is connected to a terminal 301b formed on the lower surface of the first wiring layer 301. The first semiconductor chip 302 and the second semiconductor chip 303 are molded with a first molding resin 304 on the first wiring layer 301.

[0005] Furthermore, second wiring layer 305 is formed in contact with first molding resin 304, and third semiconductor chip 306 and fourth semiconductor chip 307 are mounted on second wiring layer 305, and these are molded with second molding resin 308. Third semiconductor chip 306 and fourth semiconductor chip 307 are electrically connected via wiring 305a formed in second wiring layer 305.

[0006] The upper and lower semiconductor chips are connected by through electrodes 309, 310 that penetrate the first molding resin 304 and the second wiring layer 305, and bonding wires 311, 312. With this technology, as shown in Fig. 4, there is no substrate in the wiring layer, and the overall thickness of the semiconductor device is small.

[0007] Next, a method for manufacturing this semiconductor device will be described. First, by using a known WLP manufacturing process (RDL first method), a semiconductor chip and through electrodes 309, 310 are mounted on a support substrate on which a first wiring layer 301 is formed, and a molded resin layer is formed. Next, a semiconductor process device is used to form a second wiring layer 305 on the molded resin layer, and then a semiconductor chip is mounted on the second wiring layer 305 and is electrically connected to the through electrodes 309, 310 using bonding wires 311, 312. Next, the semiconductor chip on the second wiring layer 305 is molded with molded resin. Finally, the support substrate is peeled off, and a terminal is attached to the exposed first wiring layer 301. This manufacturing method is a batch mounting on a wafer scale, and is superior in manufacturing cost to manufacturing by package. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] SW Ho et al., "Development of FO-WLP Package-on-Package using RDL-first Integration Flow", 2018 IEEE 20th Electronics Packaging Technology Conference, DOI:10.1109 / EPTC.2018.8654431, pp. 621-617, 2018. Summary of the Invention [Problem to be solved by the invention]

[0009] However, the above-mentioned technology has a problem of warping of the wafer. Generally, in the WLP manufacturing process, wafer warping occurs during mold sealing due to differences in thermal expansion coefficients between components. A warped wafer can cause vacuum suction errors when fixing the wafer in a semiconductor process device, making it difficult to form wiring. In addition, Non-Patent Document 1 introduces a two-layer structure of a semiconductor package, but when three or more layers of semiconductor packages are stacked, the above-mentioned problem of wafer warping becomes more pronounced.

[0010] Another issue is manufacturing costs. Because the second wiring layer is fabricated directly on top of the first wiring layer, any defects in the formation of the second wiring layer result in a defective product, including the semiconductor package of the first layer wiring. This results in large losses when defects occur, leading to increased manufacturing costs. In addition, the above-mentioned technology requires a molding process for each layer on which a semiconductor package is mounted. The molding process requires time depending on the hardening of the resin used, and takes several hours with typical epoxy resin materials. This lengthy process must be performed multiple times, leading to an increase in manufacturing man-hours.

[0011] The present invention has been made to solve the above problems, and has an object to reduce the manufacturing cost of semiconductor devices. [Means for solving the problem]

[0012] half The conductor device includes a first wiring layer having a first wiring formed thereon, a first semiconductor chip mounted on the first wiring layer, a second wiring layer arranged on the first wiring layer and having a second wiring formed thereon, a second semiconductor chip mounted on the second wiring layer, a through hole formed in the second wiring layer, a molded resin layer for molding the first semiconductor chip on the first wiring layer and a molded resin layer for molding the second semiconductor chip on the second wiring layer, which are integrally formed via the through hole, and a through electrode formed through the molded resin layer that molds the first semiconductor chip and connects the first wiring and the second wiring.

[0013] Also, a method for manufacturing a semiconductor device according to the present invention includes a first step of forming a first wiring layer on a first support substrate, the first wiring layer having a first wiring formed thereon; a second step of forming an auxiliary substrate having an opening in a region where the first wiring is to be formed on the first wiring layer; a third step of mounting a first semiconductor chip on the first wiring layer in the opening of the auxiliary substrate; a fourth step of forming a second wiring layer on a second support substrate, the second wiring layer having a second wiring formed thereon and a through hole penetrating the second support substrate outside the region where the second wiring is to be formed; and a fifth step of mounting a second semiconductor chip on the second wiring layer. The method includes a sixth step of removing the second support substrate from the second wiring layer on which the second semiconductor chip is mounted, a seventh step of placing the second wiring layer from which the second support substrate has been removed on an auxiliary substrate, an eighth step of integrally forming a molded resin layer that molds the first semiconductor chip on the first wiring layer and a molded resin layer that molds the second semiconductor chip on the second wiring layer via through holes, and a ninth step of forming a through electrode that penetrates the molded resin layer that molds the first semiconductor chip and connects the first wiring and the second wiring.

[0014] In addition, a manufacturing method of a semiconductor device according to the present invention includes a first step of forming a first wiring layer having a first wiring formed on a first support substrate, a second step of mounting a first semiconductor chip on the first wiring layer, a third step of forming a first insulating layer covering the first semiconductor chip on the first wiring layer, a fourth step of forming a second wiring layer having a second wiring formed on a second support substrate, a fifth step of mounting a second semiconductor chip on the second wiring layer, a sixth step of forming a second insulating layer covering the second semiconductor chip on the second wiring layer, a seventh step of removing the second support substrate from the second wiring layer having the second semiconductor chip covered with the second insulating layer mounted thereon, an eighth step of arranging the second wiring layer from which the second support substrate has been removed on the first insulating layer, and a ninth step of forming a through electrode that penetrates the first insulating layer and connects the first wiring and the second wiring. Effect of the Invention

[0015] As described above, according to the present invention, the molding resin layers in the stacked wiring layers are integrally formed, so that the manufacturing costs of the semiconductor device can be reduced. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is a cross-sectional view showing a state of a semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. [Figure 2B] FIG. 2B is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2C] FIG. 2C is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2D] FIG. 2D is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2E] FIG. 2E is a cross-sectional view showing a state of the semiconductor device in the middle of a process, for illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2F] FIG. 2F is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2G] FIG. 2G is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2H] FIG. 2H is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2I] FIG. 2I is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a manufacturing method of the semiconductor device according to the first embodiment of the present invention. [Figure 2J] FIG. 2J is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 2K]FIG. 2K is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing the semiconductor device according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a cross-sectional view showing a state of a semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. [Figure 3B] FIG. 3B is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. [Figure 3C] FIG. 3C is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. [Figure 3D] FIG. 3D is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. [Figure 3E] FIG. 3E is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view showing the configuration of a conventional semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described below.

[0018] [Embodiment 1] First, a semiconductor device according to a first embodiment of the present invention will be described with reference to Fig. 1. This semiconductor device includes a first wiring layer 101a, a first semiconductor chip 102a, a second wiring layer 101b, and a second semiconductor chip 102b.

[0019] A first wiring 121a is formed on the first wiring layer 101a. A first semiconductor chip 102a is mounted on the first wiring layer 101a. A second wiring 121b is formed on the second wiring layer 101b. The second wiring layer 101b is formed on the first wiring layer 101a. A second semiconductor chip 102b is mounted on the second wiring layer 101b. A through hole 111 is formed in the second wiring layer 101b.

[0020] In addition, this semiconductor device has a molded resin layer 104 that molds the first semiconductor chip 102a on the first wiring layer 101a, and a molded resin layer 104 that molds the second semiconductor chip 102b on the second wiring layer 101b, and the molded resin layer 104 is formed integrally via a through hole 111.

[0021] The first wiring layer 101a, the first semiconductor chip 102a, and the molded resin layer 104 that molds the first semiconductor chip 102a can be made into one semiconductor package. Similarly, the second wiring layer 101b, the second semiconductor chip 102b, and the molded resin layer 104 that molds the second semiconductor chip 102b can be made into one semiconductor package.

[0022] This semiconductor device also includes a through electrode 110 that is formed penetrating the mold resin layer 104 that molds the first semiconductor chip 102a and connects the first wiring 121a and the second wiring 121b.

[0023] In the first embodiment, a third wiring layer 101c is further provided. The third wiring layer 101c has a third wiring 121c formed therein. The third wiring layer 101c is formed on the second wiring layer 101b. A third semiconductor chip 102c is mounted on the third wiring layer 101c. A through hole 112 is formed in the third wiring layer 101c.

[0024] In the first embodiment, a molded resin layer 104 for molding the third semiconductor chip 102c is also formed on the third wiring layer 101c, and the molded resin layer 104 is integrally formed via the through holes 111 and 112. The third wiring layer 101c, the third semiconductor chip 102c, and the molded resin layer 104 for molding the third semiconductor chip 102c can be made into one semiconductor package. In this example, three semiconductor packages are stacked.

[0025] In the first embodiment, the fourth semiconductor chip 103a is mounted on the first wiring layer 101a, the fifth semiconductor chip 103b is mounted on the second wiring layer 101b, and the sixth semiconductor chip 103c is mounted on the third wiring layer 101c. The fourth semiconductor chip 103a is molded in the mold resin layer 104 on the first wiring layer 101a. The fifth semiconductor chip 103b is molded in the mold resin layer 104 on the second wiring layer 101b. The sixth semiconductor chip 103c is molded in the mold resin layer 104 on the third wiring layer 101c. The through electrode 110 is also formed penetrating the mold resin layer 104 that molds the second semiconductor chip 102b, and connects the first wiring 121a, the second wiring 121b, and the third wiring 121c.

[0026] Moreover, this semiconductor device has terminals 122 connected to the first wiring 121a below (on the lower surface) of the first wiring layer 101a, and is electrically connected (mounted) to the printed circuit board 131 via the terminals 122. In this example, secondary mounting to the printed circuit board 131 is illustrated, but the effects of the present invention can also be obtained for designs that do not include secondary mounting.

[0027] According to the above-mentioned first embodiment, since the molded resin layer is integrally formed with the stacked wiring layers, it is not necessary to form the resin layer multiple times, and the manufacturing cost of the semiconductor device can be reduced. Furthermore, in the first embodiment, since the semiconductor package does not have a substrate, a semiconductor device with a package-on-package structure in which the overall thickness is reduced can be realized. The first semiconductor chip 102a and the second semiconductor chip 102b can be made of the same material, or can be made of different materials. Furthermore, each semiconductor chip can have the same thickness (height), or can have different thicknesses.

[0028] Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 2A to 2K.

[0029] First, as shown in FIG. 2A, a first wiring layer 101a having a first wiring 121a formed thereon is formed on a first support substrate 151a (first step). For example, the first wiring layer 101a is formed on the first support substrate 151a via an adhesive layer 152a. For example, the first wiring layer 101a can be formed by a known build-up method. The first support substrate 151a is, for example, a so-called wafer having a circular shape in a plan view, and a plurality of regions to be packaged are formed thereon. FIGS. 2A to 2C show a part of the above-mentioned regions. The first support substrate 151a can be made of, for example, a semiconductor such as silicon, glass, resin, metal, or the like.

[0030] Next, as shown in FIG. 2B, a first auxiliary substrate 153a having openings in the formation area of ​​the first wiring 121a is formed on the first wiring layer 101a (second step). The first auxiliary substrate 153a is, for example, a so-called wafer having a circular shape in a plan view, and has a plurality of openings formed corresponding to the area to be packaged. For example, the first auxiliary substrate 153a can be formed on the first wiring layer 101a by attaching the first auxiliary substrate 153a using silver paste.

[0031] Next, as shown in Fig. 2C, the first semiconductor chip 102a and the fourth semiconductor chip 103a are mounted on the first wiring layer 101a in the opening of the first auxiliary substrate 153a (third step). Each semiconductor chip has solder bumps mounted thereon, and after being mounted on the first wiring layer 101a by a chip mounter or the like, they are connected to the first wiring 121a by collective reflow. In addition, the first semiconductor chip 102a and the fourth semiconductor chip 103a are assumed to be thinner than the first auxiliary substrate 153a.

[0032] Next, as shown in FIG. 2D, the second wiring 121b is formed on the second support substrate 151b, and the second wiring layer 101b is formed with the through holes 111 and 111a penetrating the second support substrate 151b outside the formation region of the second wiring 121b (fourth step). The second wiring layer 101b is formed on the second support substrate 151b via an adhesive layer 152b. The second support substrate 151b is, for example, a so-called wafer that is circular in plan view, and a plurality of regions to be packaged are formed. FIGS. 2D to 2F show a part of the above-mentioned region. The second support substrate 151b can be made of, for example, a semiconductor such as silicon, glass, resin, metal, or the like.

[0033] In this example, as shown in FIG. 2E, a second auxiliary substrate 153b having openings in the formation area of ​​the second wiring 121b is formed on the second wiring layer 101b. The second auxiliary substrate 153b is, for example, a so-called wafer having a circular shape in a plan view, and has a plurality of openings formed corresponding to the area to be packaged. For example, the second auxiliary substrate 153b can be formed on the second wiring layer 101b by attaching the second auxiliary substrate 153b using silver paste.

[0034] Next, as shown in FIG. 2E, the second semiconductor chip 102b and the fifth semiconductor chip 103b are mounted on the second wiring layer 101b (5th step). Next, the second support substrate 151b is removed from the second wiring layer 101b on which the second semiconductor chip 102b is mounted, and the back surface of the second wiring layer 101b is exposed as shown in FIG. 2F (6th step). The adhesive layer 152b is peeled (removed) to remove the second support substrate 151b. For example, the second support substrate 151b can be removed (separated) by a separation technique such as laser peeling, thermal peeling, mechanical peeling, or solvent peeling.

[0035] 2G, the second wiring layer 101b from which the second support substrate 151b has been removed is placed (mounted) on the first auxiliary substrate 153a (seventh step). For example, the second wiring layer 101b can be mounted on the first auxiliary substrate 153a using Ag paste.

[0036] 2D, a third wiring 121c is formed on a third support substrate (not shown), and a third wiring layer 101c is formed in which through holes 112 and 112a are formed to penetrate the third support substrate outside the formation region of the third wiring 121c. The third wiring layer 101c is formed on the third support substrate via an adhesive layer.

[0037] Next, in the same manner as described with reference to Fig. 2E, a third auxiliary substrate 153c having an opening in a region where the third wiring 121c is to be formed is formed on the third wiring layer 101c. Next, in the same manner as described with reference to Fig. 2F, the third support substrate is removed from the third wiring layer 101c on which the third semiconductor chip 102c is mounted, exposing the back surface of the second wiring layer 101b.

[0038] 2H, the third wiring layer 101c from which the third support substrate has been removed is mounted on the second auxiliary substrate 153b. The third wiring layer 101c can be mounted on the second auxiliary substrate 153b using Ag paste.

[0039] Next, as shown in FIG. 2I, the molded resin layer 104 for molding the first semiconductor chip 102a and the fourth semiconductor chip 103a on the first wiring layer 101a, and the molded resin layer 104 for molding the second semiconductor chip 102b and the fifth semiconductor chip 103b on the second wiring layer 101b are integrally formed via the through holes 111 and 111a (8th step). In this example, the molded resin layer 104 for molding the third semiconductor chip 102c and the sixth semiconductor chip 103c on the third wiring layer 101c is also integrally formed via the through holes 112 and 112a. The molded resin can be formed by molding with the molded resin by a known trans-molding method, for example, and curing the molded resin.

[0040] 2J, through electrodes 110 are formed that penetrate the molded resin layer 104 that molds the first semiconductor chip 102a and the molded resin layer 104 that molds the second semiconductor chip 102b, and connect the first wiring 121a, the second wiring 121b, and the third wiring 121c (ninth step). For example, holes are formed in predetermined locations of the molded resin layer 104 by a laser or the like, and then the formed holes are filled with a metal such as copper by a plating method or the like, thereby forming the through electrodes 110.

[0041] Next, the first support substrate 151a is removed from the first wiring layer 101a to expose the back surface of the first wiring layer 101a as shown in FIG. 2K. The first support substrate 151a is removed by peeling (removing) the adhesive layer 152a. For example, the first support substrate 151a can be removed (separated) by a separation technique such as laser peeling, thermal peeling, mechanical peeling, or solvent peeling. In addition, a terminal 122 connected to the first wiring 121a is formed on the back surface (lower surface) of the exposed first wiring layer 101a. The terminal 122 can be, for example, a solder bump.

[0042] Next, each package area is cut out and separated using a dicing device. In this cutting process, each auxiliary substrate portion is simultaneously cut and removed, reducing the chip size in plan view. After this, each separated package is mounted on a printed circuit board via its terminal, thereby forming the semiconductor device shown in FIG. 1. For example, when solder bumps are used, mounting can be performed using a known reflow technique.

[0043] According to the manufacturing method of the semiconductor device according to the first embodiment described above, since the auxiliary substrate increases the mechanical strength of the wiring layer, even if the wiring layer is thin, the semiconductor device will not be broken due to insufficient mechanical strength during the manufacturing process. Furthermore, since the mechanical strength of the semiconductor device is increased by the mold resin after the mold resin layer is formed, even if the auxiliary substrate is removed by separating the first support substrate from the semiconductor device or by dicing, the semiconductor device will not be broken due to insufficient mechanical strength.

[0044] In addition, since the molded resin layer is formed after stacking each wiring layer, it is possible to form wiring without considering wafer warpage caused by the formation of the molded resin layer. For the same reason, it is possible to improve the yield of semiconductor packages in which multiple wiring layers are stacked. In addition, because each wiring layer is manufactured separately, it is possible to select and stack wiring layers that are free of defects, which reduces losses due to defects in the wiring layers after the stack is assembled. This makes it possible to reduce manufacturing costs. Furthermore, regardless of the number of layers in the semiconductor package, the molding process can be completed in one go, shortening the process time. For these reasons, the number of manufacturing steps can be reduced.

[0045] [Embodiment 2] Second Embodiment Next, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 3A to 3E.

[0046] First, as shown in FIG. 3A, a first wiring layer 201a having a first wiring 221a formed thereon is formed on a first support substrate 251a (first step). For example, the first wiring layer 201a can be formed by a known build-up method. The first support substrate 251a is, for example, a so-called wafer having a circular shape in a plan view, and a plurality of regions to be packaged are formed thereon. FIGS. 3A to 3D show some of the above-mentioned regions. The first support substrate 251a can be made of, for example, a semiconductor such as silicon, glass, resin, metal, or the like.

[0047] Also, a first semiconductor chip 202a and a fourth semiconductor chip 203a are mounted on the first wiring layer 201a (second process). Each semiconductor chip has solder bumps mounted thereon, and after being mounted on the first wiring layer 201a by a chip mounter or the like, they are connected to the first wiring 221a by collective reflow.

[0048] 3B, a first insulating layer 204a is formed on the first wiring layer 201a to cover the first semiconductor chip 202a and the fourth semiconductor chip 203a (third step). The first semiconductor chip 202a and the fourth semiconductor chip 203a are sealed with the first insulating layer 204a. For example, the first insulating layer 204a can be formed by applying and curing a low dielectric constant resin such as benzocyclobutene (BCB).

[0049] Next, a second wiring layer 201b having a second wiring 221b formed thereon is formed on a second support substrate (not shown) (fourth step), and a second semiconductor chip 202b and a fifth semiconductor chip 203b are mounted on the second wiring layer 201b (fifth step). For example, the second wiring layer 201b can be formed on the second support substrate via an adhesive layer (not shown). The second support substrate is, for example, a so-called wafer that is circular in plan view, and has a plurality of regions to be packaged formed therein. The second support substrate can be, for example, made of a semiconductor such as silicon, glass, resin, metal, or the like.

[0050] Next, a second insulating layer 204b that covers the second semiconductor chip 202b is formed on the second wiring layer 201b (sixth step). The second semiconductor chip 202b and the fifth semiconductor chip 203b are sealed with the second insulating layer 204b. For example, the second insulating layer 204b can be formed by applying and curing a low dielectric constant resin such as BCB.

[0051] Thereafter, the second support substrate is removed from the second wiring layer 201b on which the second semiconductor chip 202b and the fifth semiconductor chip 203b covered with the second insulating layer 204b are mounted, and the back surface of the second wiring layer 201b is exposed as shown in FIG. 3C (seventh step). The second support substrate can be removed by peeling (removing) the adhesive layer. For example, the second support substrate can be removed (separated) by a separation technique such as laser peeling, thermal peeling, mechanical peeling, or solvent peeling. Here, the second insulating layer 204b is formed to be sufficiently thick so that sufficient mechanical strength can be obtained by itself even after the second support substrate is removed.

[0052] Next, by carrying out the same process as described above, a third semiconductor chip 202c and a sixth semiconductor chip 203c are mounted to connect to the third wiring 221c, as shown in FIG. 3D, and a third wiring layer 201c is obtained in which these are sealed with a third insulating layer 204c.

[0053] Next, as shown in FIG. 3E, the second wiring layer 201b from which the second support substrate has been removed is disposed and fixed on the first insulating layer 204a (step 8). For example, an adhesive layer is formed by applying epoxy resin onto the first insulating layer 204a using an application device such as a spin coater. Next, the second wiring layer 201b is mounted on the adhesive layer, and the adhesive layer is thermally cured. As a result, the second wiring layer 201b can be fixed on the first insulating layer 204a. Similarly, the third wiring layer 201c is disposed and fixed on the second insulating layer 204b.

[0054] Next, the through electrodes 210 are formed (step 9) that penetrate the first insulating layer 204a and the second insulating layer 204b (and the third insulating layer 204c) and connect the first wiring 221a, the second wiring 221b, and the third wiring 221c. For example, holes are formed at predetermined locations using a laser or the like, and then the formed holes are filled with a metal such as copper using a plating method or the like, thereby forming the through electrodes 210.

[0055] Next, the first support substrate 251a is removed from the first wiring layer 201a to expose the back surface of the first wiring layer 201a. The first support substrate 251a is removed by peeling (removing) the adhesive layer 252a. For example, the first support substrate 251a can be removed (separated) by a separation technique such as laser peeling, thermal peeling, mechanical peeling, or solvent peeling. In addition, terminals 222 connected to the first wiring 221a are formed on the exposed back surface (lower surface) of the first wiring layer 201a. The terminals 222 can be, for example, solder bumps.

[0056] Next, each package area is cut out and divided into individual pieces by a dicing device. After this, each package is mounted on a printed circuit board via its terminals. For example, when solder bumps are used, mounting can be performed by a known reflow technique.

[0057] According to the manufacturing method of the semiconductor device according to the second embodiment described above, since the mechanical strength of the wiring layer is increased by the insulating layer that covers (seals) the semiconductor chip, even if the wiring layer is thin, no damage due to insufficient mechanical strength occurs during the manufacturing process. Moreover, since the mechanical strength of the semiconductor device is increased by the insulating layer after the insulating layer is formed, no damage due to insufficient mechanical strength occurs even if the support substrate is separated from the semiconductor device or the auxiliary substrate is removed by dicing.

[0058] As described above, according to the present invention, the molding resin layers in the stacked wiring layers are integrally formed, so that the manufacturing cost of the semiconductor device can be reduced.

[0059] It should be noted that the present invention is not limited to the above-described embodiments, and it is apparent that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention. [Explanation of symbols]

[0060] 101a...first wiring layer, 101b...second wiring layer, 101c...third wiring layer, 102a...first semiconductor chip, 102b...second semiconductor chip, 102c...third semiconductor chip, 103a...fourth semiconductor chip, 103b...fifth semiconductor chip, 103c...sixth semiconductor chip, 104...molded resin layer, 110...through electrode, 111...through hole, 112...through hole, 121a...first wiring, 121b...second wiring, 121c...third wiring, 122...terminal, 131...printed board.

Claims

1. a first step of forming a first wiring layer having a first wiring formed on a first support substrate; a second step of forming an auxiliary substrate on the first wiring layer, the auxiliary substrate having an opening in a region where the first wiring is to be formed; a third step of mounting a first semiconductor chip on the first wiring layer in the opening of the auxiliary substrate; a fourth step of forming a second wiring layer on a second support substrate, the second wiring being formed thereon and having a through hole penetrating the second support substrate outside a region where the second wiring is formed; a fifth step of mounting a second semiconductor chip on the second wiring layer; a sixth step of removing the second support substrate from the second wiring layer on which the second semiconductor chip is mounted; a seventh step of disposing the second wiring layer from which the second support substrate has been removed on the auxiliary substrate; an eighth step of integrally forming a molding resin layer that molds the first semiconductor chip on the first wiring layer and a molding resin layer that molds the second semiconductor chip on the second wiring layer through the through hole; a ninth step of forming a through electrode that penetrates a molding resin layer that molds the first semiconductor chip and connects the first wiring and the second wiring; A method for manufacturing a semiconductor device comprising the steps of:

2. a first step of forming a first wiring layer having a first wiring formed on a first support substrate; a second step of mounting a first semiconductor chip on the first wiring layer; a third step of forming a first insulating layer on the first wiring layer to cover the first semiconductor chip; a fourth step of forming a second wiring layer on the second support substrate, the second wiring being formed thereon; a fifth step of mounting a second semiconductor chip on the second wiring layer; a sixth step of forming a second insulating layer on the second wiring layer to cover the second semiconductor chip; a seventh step of removing the second support substrate from the second wiring layer on which the second semiconductor chip covered with the second insulating layer is mounted; an eighth step of disposing the second wiring layer from which the second support substrate has been removed on the first insulating layer; a ninth step of forming a through electrode that penetrates the first insulating layer and connects the first wiring and the second wiring; A method for manufacturing a semiconductor device comprising the steps of:

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