Wafer-scale direct-coupled array core blocks for active electronically steerable arrays (AESA)

Abstract

The array core block for the AESA includes a stack of 2×M alternating N-channel RFIC and MMIC power amplifier wafers bonded together by a wafer-scale direct-bonded hybrid (DBH) interconnect process that forms both metal-to-metal bonds and dielectric hydrogen bonds between the bonding surfaces to seal the wafer stack. Each array core block includes an array of through-substrate metal vias for distributing DC bias, LO signals, and information signals. Each array core block also includes a microchannel formed on the backside of at least one of the chips of each bonded pair and through-substrate via holes formed through the stack operatively coupling the microchannels to all of the bonded pairs, and includes a cooling system that receives and circulates fluid through the microchannels and through-substrate via holes to cool the RFIC and MMIC power amplifier chips and extract heated fluid.

Description

[Technical field]

[0001] Priority claims This application claims the benefit of priority to U.S. Patent Application No. 17 / 465,633, filed September 2, 2021, which is incorporated by reference in its entirety. [Background technology]

[0002] The present invention relates to Active Electronically Steerable Arrays (AESAs), and more particularly to array core blocks fabricated using a wafer-scale direct bond hybrid (DBH) interconnect process to facilitate integration of high power III-V Monolithic Millimeter-wave Integrated Circuit (MMIC) power amplifiers with silicon-based Radio Frequency Integrated Circuits (RFICs).

[0003] 2. Description of Related Art An AESA is a phased array system consisting of an M x N array of fixed antenna elements with active RF power amplifiers and active beamforming circuitry behind every antenna element. Each antenna element is excited with an RF signal. The relative phase of the excitation signals is controlled to form and steer the RF beam.

[0004] AESA architectures operating above 50 GHz are based on tile architectures. Examples of this architecture can be found in the literature Fully Integrated 384 element 16 Tile W-band Phase Array with Self-Alignment and Self-Test' by S.Shahramian et al., IEEE Journal of Solid State Circuits, Vol. 54, No. 9, pp 2419-2433, and U.S. Patent No. 10,5414,61, and references therein. These architectures utilize SiGe or CMOS RFIC chip tiles that contain arrays of fully integrated transceiver circuits providing signal up / down conversion, power amplification, and beamforming functions. These highly complex functions can be easily implemented in Si RFICs within a small chip area due to the tight design rules and high integration density provided by advanced Si chip fabrication techniques. These tiles typically contain between 4x4 and 8x8 elements. The tile dimensions are compatible with half-wave element spacing at the operating frequency. The RFIC array tiles are flip-chip attached to an antenna array plate which is typically mounted on a multi-layer printed circuit board or multi-layer ceramic or quartz. The antenna array plate also provides the RFIC bias, routing of IF and LO signals, and an interface for communication and control of the individual array elements. Heat is drawn off through the bottom of the tile through a heat sink.

[0005] These tile-based architectures can generate 100 times more RF power per chip area than Si RFICs, but are not compatible for integration with high-power Gallium Nitride (GaN) MMIC power amplifier chips, which do not offer the same level of integration as Si RFICs. GaN chips are composed of a different material system that cannot be easily integrated into Si-based RFIC chips. Tile architectures cannot handle the heat load generated by high-power GaN MMIC PAs and cannot provide the DC power distribution capacity to power the GaN MMIC PAs.

[0006] Timothy M. Hancock et.al., “Heterogeneous and 3D Integration at DARPA”, 2019 International 3D Systems Integration Conference (3DIC), describes a technique for integrating Si CMOS with InP, GaN, and GaAs for use in wideband RF and mixed-signal systems. As shown in Figure 2 by TMHancock, Northrop Grumman’s Diverse Accessible Heterogeneous Integration (DAHI) process stacks GaN HEMT chiplets on top of CMOS. The GaN chips are bonded face-up such that the SiC substrate of the GaN becomes a heat spreader under the device channel before transferring heat to the silicon CMOS substrate. Heat is drawn out the bottom of the stack through the Si CMOS substrate. Summary of the Invention

[0007] The following is a summary of the invention to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description and claims that are presented later.

[0008] The present invention provides a high-power array core block for AESA for operating frequencies above 50 GHz. The array core block includes a stack of 2*M alternating N-channel RFIC and MMIC power amplifier chips that are bonded together by a wafer-scale direct-bonding interconnect process to form M bonded pairs of M×N element array core blocks, where M and N are integers greater than 1. An array of through-substrate metal vias extends vertically through the stack to (a) distribute DC bias to the MMIC power amplifier chips as well as local oscillator (LO) and information signals to the RFIC chips, and (b) connect the N output channels of the RFIC chips to drive corresponding input channels of the MIMIC power amplifier chips, driving each antenna element integrated in the MIMIC power amplifier such that the M×N element array core block forms a steerable RF beam at the operating frequency. The cooling system includes microchannels formed on the backside of at least one of the chips in each bonded pair and through-substrate via holes formed through the stack operatively coupling the microchannels to all of the bonded pairs, and receives and circulates fluid through the microchannels and through-substrate via holes to cool the RFIC and MMIC power amplifier chips and extract heated fluid.

[0009] The wafer-scale Direct Bond Hybridization (DBH) (dielectric / metal) interconnect process forms both hydrogen bonds between dielectric layers and strong metal-to-metal thermal diffusion bonds between wafers. These bonds form strong mechanical connections and through-stack seals to contain circulating fluids. The Direct Bond Hybridization (DBH) process forms hydrogen bonds between opposing SiO2 bonded dielectric layers and mechanical bonds between opposing metal plugs.

[0010] In one embodiment, an M×N element array core block contains at least M=1 and N=4 elements. Typical block sizes may range between 1×8 and 16×16 elements.

[0011] In one embodiment, the LO signal and the information signal are distributed at frequencies less than 10% of the operating frequency. The RFIC chip is configured to upconvert the LO to the operating frequency.

[0012] In one embodiment, the cooling system is configured to receive and extract fluid at both the top and bottom of the stack. The fluid may be received and extracted as a liquid, a gas, or may be received as a liquid, undergo a state change, and extracted as a gas. Suitably, the microchannels are formed only on the backside of the RFIC chip.

[0013] In one embodiment, the RFIC chip is silicon material based and the MMIC power amplifier chip is III-V material based, typically GaN.

[0014] In one embodiment, the circuit sides of the RFIC chip and the MMIC power amplifier chip are bonded together.

[0015] In one embodiment, the MMIC power amplifier chip includes an in-plane transmission line that transfers power to an antenna element, preferably an end-fire antenna element.

[0016] In one embodiment, the AESA includes a frame, one or more PCBs attached to the frame for fanning out DC bias and LO and IF signals, an array core block disposed within the frame and electrically coupled to the one or more PCBs, and top and bottom manifolds configured to carry fluid to the array core block, circulate the fluid through microchannels and through-substrate via holes to cool the RFIC and MMIC power amplifier chips, and extract heated fluid from the array core block.

[0017] In one embodiment, multiple array core blocks are fabricated in a multi-wafer stack using a wafer-scale direct bond interconnect process, and the multi-wafer stack is diced to yield the individual array core blocks.

[0018] In one embodiment, RFIC and MMIC power amplifier wafers are formed in respective Si and III-V foundries from Si and III-V material systems and transferred to an integration foundry. At the integration foundry, the wafers are thinned to the thickness required for the operating frequency and fabricated to form through-substrate metal vias and cooling holes through the wafers and microchannels on the backside of the RFIC wafers. The wafers are aligned and interleaved to form a stack. The stacks are bonded using a DBH process to form both hydrogen bonds and metal-to-metal bonds between the wafers. The stacks are bumped to provide an interface for attaching a PCB and then diced to obtain multiple array core blocks.

[0019] These and other features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiments, taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is an exploded view of an embodiment of an AESA including a wafer level DBH coupled array core block. [Diagram 2] FIG. 1 is an assembled view of an embodiment of an AESA including a wafer level DBH coupled array core block. [Diagram 3] FIG. 2 is a perspective view of an array core block. [Figure 4] FIG. 13 is a side view of an array core block showing hydrogen bonds and mechanical bonds as well as an array of through-substrate metal vias. [Diagram 5] FIG. 13 is a top view of an array core block showing microchannels and through-substrate cooling holes. [Figure 6] FIG. 1 is a diagram of an MMIC power amplifier chip coupled between RFIC chips in an array core block. [Figure 7] 1 is a flow diagram of a portion of a manufacturing process for preparing RFIC and MMIC power amplifiers for direct coupling processing. [Figure 8A]FIG. 2 is a diagram of the circuit side of an RFIC wafer. [Figure 8B] FIG. 2 is a view of the backside of an RFIC wafer. [Figure 8C] FIG. 2 is a diagram of the circuit side of an MMIC power amplifier wafer. [Figure 9A] FIG. 13 is a diagram of the microchannels in the cover wafer for the stack. [Figure 9B] FIG. 13 is a view of the blank side of a cover wafer for a stack. [Figure 10] FIG. 1 illustrates a wafer-level DBH process for fabricating multiple array core blocks. [Figure 11] FIG. 1 is a schematic diagram of an RFIC chip or unit cell on an RFIC wafer. [Figure 12] FIG. 1 is a schematic diagram of a MMIC power amplifier chip or unit cell on a MMIC wafer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The present invention provides a design and fabrication method for array core blocks for AESAs that support larger M×N array sizes and higher power RF beams. To achieve higher RF power, MMIC power amplifiers formed from III-V material systems, typically GaN, must be integrated with Si RFICs. These high power III-IV MMIC power amplifiers generate more waste heat than their silicon counterparts. Conventional techniques that simply draw heat from one side of the array through a heat sink are insufficient.

[0022] The present invention provides an array core block for an AESA in which a stack of 2*M alternating N-channel RFIC and MMIC power amplifier wafers are bonded together by a wafer-scale direct bond interconnect process such as (Direct Bond Interconnect) DBI®, or DBH, which forms both mechanical and hydrogen bonds to seal the wafer stack. Each array core block includes an array of through-substrate metal vias extending vertically through the stack to distribute DC bias to the MMIC power amplifier chips, distribute LO and information signals to the RFIC chips, and connect the RFIC chips to the MMIC power amplifier chips. Each array core block also includes a microchannel formed on the backside of at least one of the chips of each bonded pair and through-substrate via holes formed through the stack operatively connecting the microchannels to all of the bonded pairs, and includes a cooling system that receives and circulates fluid through the microchannels and through-substrate via holes to cool the RFIC and MMIC power amplifier chips and extract heated fluid.

[0023] 1 and 2, one embodiment of an AESA 100 includes an array core block 102 disposed within an outer frame 104, such as machined from lightweight metal. Top and bottom liquid manifolds 106 and 108 are mounted on the frame 104 and operatively coupled to the top and bottom of the array core block 102 with leak-proof seals via seals 110 and 112, suitably elastomeric material, for recirculating a fluid 114 through the array core block 102 and cooling the RFIC and MMIC power amplifier chips. A pair of printed circuit boards 116 and 118 are suitably mounted on the frame 104 and electrically coupled to the array core block 102, for example via a flip chip ball grid array, to serve as an electronic interface between the array core block and an external bias power supply, external LO and information signal generators, and an external system controller.

[0024] Referring now to Figures 3, 4, 5 and 6, the array core block 102 includes M SiGe or CMOS (Si) RF integrated circuit (RFIC) chips 120 and M III-V (e.g., GaN) monolithic integrated millimeter wave circuit (MMIC) power amplifier chips 122 (and top and bottom cover wafers) that are bonded together in an alternating stack 124 using a wafer-scale direct bonding process such as DBI® or DBH. The wafer-scale direct bonding interconnect process forms both hydrogen bonds 126 and mechanical bonds 128 between the wafers. These bonds form a strong mechanical connection and a leak-proof seal through the stack to contain the circulating fluid. As used herein, the direct bonding hybridization (DBH) process forms hydrogen bonds between opposing SiO2 bonded dielectric layers 130 and diffused metal bonds between opposing metal plugs 132 in the interconnect dielectric layers 134.

[0025] Each coupled pair 136 of RFIC and MMIC power amplifier chips forms an N×1 element linear subarray that includes N antennas 138, suitably endfire antennas, spaced at half wavelength intervals at the operating frequency. In a preferred embodiment, the thickness of each coupled pair 136 is also equal to half a wavelength allowing for + / −60 degrees sidelobe free beam steering in both azimuth and elevation. The stack of M N×1 subarrays and top and bottom cover wafers forms an M×N element array core block.

[0026] An array of through-substrate metal-filled vias 140 runs vertically through the entire chip stack 124 and provides an interface for distributing DC bias to the MMIC power amplifier chip, LO and information signals to the RFIC chip, and digital communication control for both chips, and connecting the N output channels of the RFIC chip to drive corresponding input channels of the MMIC power amplifier chip. The LO and information signals are preferably distributed across the entire stack frequency at less than 10% of the operating frequency to eliminate insertion loss problems associated with distributing very high frequency signals. These signals are upconverted to the operating frequency by the RFIC on each N×1 subarray pair.

[0027] The cooling system 150 includes microchannels 152 formed on the backside of at least one of the chips of each bonded pair, and through-substrate via holes 154 formed through the stack operatively connecting the microchannels to all of the bonded pairs to receive and circulate the fluid 115 through the microchannels and through-substrate via holes to cool the RFIC and MMIC power amplifier chips and extract the heated fluid. In a preferred embodiment, the fluid is injected and extracted at both the top and bottom of the stack. The system may be a forced liquid or gas cooling system. For higher power consumption, a forced liquid biphasic method is preferred, where a liquid is injected into the array core block, heated to undergo a phase change to a gaseous state, and removed. The wafer-scale direct bonding process provides high quality seals due to the planarity of the direct bonding process and the high strength hydrogen and mechanical bonds.

[0028] In a preferred embodiment, the circuit side of the (Si / RFIC) is bonded to the circuit side of the (GaN MMIC) and the backside of the (Si / RFIC) is bonded to the backside of the (GaN MMIC) as shown in FIG. 6. This bonding configuration is preferred to minimize the transition loss between the two chips at operating frequencies above 50 GHz since it ensures that the interconnect distance between the two chips is the shortest. This configuration is also preferred because it provides more options for the design of compact matching and bias distribution networks on the GaN MMIC by utilizing more (7 or more) dense metal interconnect layers on the Si / RFIC wafer in addition to the metal interconnect layers (typically 2-3) available on the GaN / MMIC wafer.

[0029] As shown in FIG. 6, a highly efficient end-fire antenna 138 is realized in the top metallization layer of the GaN MMIC chip 122, and a microchannel 152 is etched on the backside of the Si / RFIC chip 120. The end-fire antenna is integrated on the GaN chip to minimize the insertion loss between the output of the GaN power amplifier and the antenna by removing the vertical transition between the chips. In-plane transmission lines transfer the power from the power amplifier channel to the respective end-fire antenna. The GaN chip is also thinner than the Si / RFIC chip to improve the radiation efficiency of the end-fire antenna. The microchannel is thicker and is etched into the Si / RFIC chip. The bonding interfaces on both sides of the chip include a SiO2 bonding layer 130 fabricated by a Cu damascene process, and a Cu plug array 132. The Cu plug array serves two purposes: to provide electrical connection between the chips and to provide a strong metal-to-metal mechanical bond between the chips after a post-bonding annealing process.

[0030] Referring now to Figures 7, 8A-8C, 9A-9B and 10, an exemplary process of array core block fabrication for a 12x12 element array for a 220 GHz operating frequency is shown. A Si / RFIC wafer 200, a GaN / MMIC wafer 202, and top and bottom cover wafers 204 are fabricated in respective foundry fabrication processes 206, 208, and 210. These foundry processes must support Cu damascene multi-layer metal interconnects to achieve wafer planarity and interface for the DBH bonding process. State-of-the-art Si / RFIC processes support more than seven metal interconnect layers, while GaN / MMIC processes typically support only two to three layers. In the preferred process flow, the same wafer diameter and the same reticle size are used for both sets of wafers, with the preferred wafer diameter being 200 mm or greater for compatibility with state-of-the-art line Si processing tools. The reticle size is selected to accommodate the entire 1xN element chip. The maximum reticle size is determined by the maximum field size of the photolithography stepper. As an example, 26mm x 33mm is the maximum field size of the current state of the art i193 EUV stepper.

[0031] After the front side processing at each foundry is completed, the wafers are sent to an integration foundry 212 where the Si / RFIC and GaN / MMIC wafers are thinned to the required thickness 214 with through-substrate metal vias 216, microchannels 218 for dual-phase cooling, and through-substrate via holes 220 for cooling medium distribution fabricated internally using standard back side of line semiconductor manufacturing technology. The integration foundry also fabricates the DBH bonding interfaces 222, SiO2 layers, and Cu plug arrays on both sides of the wafer using a Cu damascene process.

[0032] 8A-8C show details of four full reticles 300 and eight partial reticles 302 on a Si / RFIC wafer 304 and a corresponding GaN / MMIC wafer 306 as they are prepared for the wafer-scale DBH bonding step. An exemplary 1×12 element 220 GHz reticle has dimensions of 16.2 mm×24.4 mm. FIG. 8A shows the circuit side of the RFIC wafer with Si circuits 305, FIG. 8B shows the backside of the RFIC wafer, and FIG. 8C shows the circuit side of the MMIC power amplifier wafer with GaN circuits 307.

[0033] In an exemplary reticle layout, a 10 mm x 12 mm region 308 of the reticle is dedicated to circuitry on both wafers, and a 12 mm x 15 mm region 310 of the reticle is dedicated to a dual side pad / (through substrate metal via) array 311 used for bias routing, LO, IF and system clock distribution, and digital communication interface between the 12 x 1 element sub-array pair. The metal interconnect layers on both wafers of the 1 x 12 element sub-array pair are used to provide appropriate pads for the through substrate via array to the interface circuitry on each chip.

[0034] Other features of the Si / RFIC reticle shown in Figures 8A-8B are dry etched slot-through openings 312 for the endfire antenna elements, microchannel manifolds 314 for cooling fabricated by deep partial dry etching into the backside of the wafer, and dry etched through via holes 316 for coolant distribution.

[0035] Other features of the GaN / MMIC wafer shown in Figure 8C are endfire antenna elements 318, dry etched through via holes 320 for coolant distribution, and pad arrays for bias, LO and information signal distribution 321. These features on the GaN / MMIC wafer, along with the dual side pad / (through substrate) arrays, are designed to align with corresponding features on the Si / RFIC wafer and cover wafer during the DBH wafer bonding process.

[0036] 9A-9B show the top (blank side) and bottom (microchannel side) cover wafers 322 and 324, respectively. The cover wafer features dry etched slotted through openings 326 for endfire antenna elements, dry etched through via holes 328 for coolant distribution, and a dual side pad / (through substrate via) array 330. These features on the cover wafer are designed to align with corresponding features on the Si / RFIC and GaN MMIC wafers. The cover wafer does not contain any active circuitry. The bottom and top cover wafers differ in that the bottom cover wafer has microchannels for liquid cooling etched into its backside, while the top cover wafer does not have microchannels.

[0037] The wafers prepared for the wafer-level DBH bonding step are bonded to a multi-wafer stack in the sequence outlined in FIG. 10. The microchannel side of the bottom cover wafer 324, position 1, is bonded to the backside of the GaN / MMIC wafer 306 at position 2, which is bonded to the circuit side of the Si / RFIC wafer 304 at position 3. The GaN / MMIC and Si / RFIC wafer bonding sequence is then repeated 11 more times. The wafer stack is completed by bonding the top cover wafer 322 to the microchannel side of the Si / RFIC wafer 304 at position 25. Completion of the DBH bonding process results in a full multi-wafer stack 332. Details regarding the DBH interconnect process can be found in “Sub-10 μm Pitch Hybrid Direct Bond Interconnect Development for Die-to-Die Hybridization”, by John P. Mudrick et al., 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) and references therein, as well as U.S. Pat. No. 6,962,835 and references therein. Solder bumps are then deposited on corresponding pads on both sides of the multi-wafer stack 332, and the wafer stack is then diced along the cut lines using a saw 336 into individual array core blocks 334. Sixty 200 GHz 12×12 element array core blocks can be obtained from a single 200 mm diameter multi-wafer stack produced by the described process.

[0038] The lower frequency limit of the proposed array core block architecture is determined by the maximum wafer thickness. The standard thicknesses of 200 mm and 300 mm Si wafers are 725 μm and 775 μm, respectively. The total thickness of two stacked non-thinned Si wafers, including all metallization and bonding layers, is estimated to be in the range of 1.5 mm to 1.7 mm, which corresponds to a half-wavelength interval in the frequency range of 88 GHz to 100 GHz. The maximum wafer thickness can support frequencies of 50 GHz and above.

[0039] The upper frequency limit of the proposed architecture is determined by two factors. The first is the minimum thickness to which the wafer can be thinned and practically processed. Currently, a safe estimate for the minimum thickness of the thinned wafer, including all metallization and bonding layers, is in the range of 60 μm to 100 μm, which puts the upper frequency limit in the range of 750 GHz to 1250 GHz. The second factor is the reduced cross section of the microchannels for forced convection cooling when reducing the wafer thickness. The reduction in microchannel cross section impedes coolant flow rate and heat exchange. 500 μm is the estimated minimum thickness of two wafer stacks that can support forced two-phase cooling, which puts the upper frequency limit for most heat intensive applications at 300 GHz. For heat loads that can be handled by forced liquid cooling or gas flow microchannel cooling, the frequency range can be extended to the range of 750 GHz to 1250 GHz.

[0040] 11 and 12, there are shown schematic diagrams of a 12×1 unit cell circuit on a Si / RFIC wafer and a 12 channel unit cell circuit on a GaN / MMIC power amplifier wafer for a 12×12 element 220 GHz array core block.

[0041] 11, the Si / RFIC chip 400 includes an amplifier 401 and three amplified upconversion stages 402, each of which upconverts the signal by a factor of three, upconverting the 8.13 GHz LO signal 403 to 219.5 GHz. The 219.5 GHz LO signal is split into two paths via splitter 404 and amplified by amplifiers 406 and 408. One path feeds an upconversion mixer 410, which mixes the upconverted 219.5 GHz LO with a 0.5 GHz to 5.5 GHz information signal 412 to generate a 220 GHz to 225 GHz RF signal 414. The RF signal is high pass filtered at 416, amplified at 418, and split into 12 paths by a 12-way RF beamforming network 420, which includes a power splitter 422, a variable gain amplifier 424, and a phase shifter 426. The beam forming network also amplifies the RF signal to the power level required to drive the GaN MMIC high power amplifiers (HPAs) at 428. The output of each RF path on the Si / RFIC is connected to the input of a corresponding HPA on the GaN MMIC chip.

[0042] The second path of the 219.5 GHz LO signal feeds a built-in self-test (BIST) circuit 430 used for array self-calibration and testing. The BIST circuit monitors the amplitude and phase of the forward transmit and reflected RF signals at the output of each GaN MMIC power amplifier via an array of 24 RF ports connected to corresponding directional coupler ports on the GaN / MMIC chip. These ports can also be used to monitor the combined amplitude and phase of adjacent antenna elements by turning off the bias to the corresponding GaN MMIC HPA. The Si RFIC chip also contains a bias control circuit 432 that controls the bias of the individual active components on the 12×1 element subarray, and a microcontroller unit (MCU) 434 that is used to monitor and control the operation of the 12×1 element subarray to perform array self-calibration and interface with other subarrays and an external system controller.

[0043] Referring to FIG. 12, a Ga / MMIC chip 500 includes 12 identical HPAs 502 running in parallel. The HPAs are appropriately designed to be less than half-wavelength apart at the operating RF frequency, and include a sufficient number of RF amplification stages 504 to saturate the output stage when the maximum power that can be provided by the Si / RFIC is delivered to the HPA input. The advantage of the proposed array structure is that it eliminates the half-wavelength dimension requirement for the length of the HPA chip. Each HPA includes an endfire antenna 506 and a directional coupler 508 connected to the input port of the BIST circuit on the Si / RFIC.

[0044] In addition to the transmit-only array configurations outlined above, other array configurations, such as transmit / receive, can be implemented in the proposed architecture.

[0045] While several illustrative embodiments of the invention have been shown and described, numerous variations and alternative embodiments will occur to those skilled in the art. Such variations and alternative embodiments are contemplated and can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. 1. An array core block for an Active Electronically Steerable Array (AESA) for operating frequencies above 50 GHz, comprising: a stack of 2*M alternating N-channel RFIC and MMIC power amplifier chips bonded together by a wafer-scale direct bond interconnect process to form M bonded pairs of M×N element array core blocks; an array of through-substrate metal vias extending vertically through the stack (a) distributing DC bias to the MMIC power amplifier chips as well as local oscillator (LO) and information signals to the RFIC chips, and (b) connecting the N output channels of the RFIC chip to drive corresponding input channels of the MMIC power amplifier chip and driving respective antenna elements integrated in the MMIC power amplifier such that the M×N element array core block forms a steerable RF beam at the operating frequency; a cooling system including microchannels formed on the backside of at least one of the chips of each bonded pair and through-substrate via holes formed through the stack operatively coupling the microchannels to all of the bonded pairs, receiving and circulating a fluid through the microchannels and through-substrate via holes to cool the RFIC and MMIC power amplifier chips and extract the heated fluid; An array core block including:

2. The chip is provided with a SiO ２ 2. The array core block of claim 1 , bonded by hydrogen bonds between bonding dielectric layers and intermetallic bonds between opposing metal plugs, the hydrogen bonds and intermetallic bonds forming a seal throughout the stack to contain the circulating fluid.

3. 2. The array core block of claim 1, wherein the LO signal and information signal are at frequencies less than 10% of operating characteristics, and the RFIC chip is configured to upconvert the LO to the operating frequency.

4. The array core block of claim 1 , wherein the through-substrate via holes are configured to receive fluid and extract heated fluid at both the top and bottom of the stack.

5. The array core block of claim 1 , wherein the microchannels are formed only on the back surface of the RFIC chip.

6. The array core block of claim 1 , wherein the fluid is received as a liquid undergoes a phase change and is extracted as a gas.

7. 2. The array core block of claim 1, wherein said RFIC chip is in a silicon material system and said MMIC power amplifier chip is in a III-V material system.

8. 2. The array core block of claim 1, wherein the antenna elements are spaced apart at the operating frequency, with each coupled pair having a thickness of half a wavelength at the operating frequency.

9. 2. The array core block of claim 1, wherein each RFIC chip and each MMIC power amplifier chip has a circuit side and a back side, and in each bonded pair, the circuit sides face each other to minimize a length of the through-substrate metal vias connecting the RFIC chip to the MMIC power amplifier chip.

10. The array core block of claim 1 , wherein each MMIC chip further includes an in-plane transmission line that transfers power from a power amplifier channel to said antenna element.

11. 1. An M×N active electronically steerable array (AESA) for operating frequencies above 50 GHz, comprising: A frame, one or more printed circuit boards (PCBs) mounted to the frame for fanning out DC bias and local oscillator (LO) and information signals; an array core block disposed within the frame and electrically coupled to the one or more PCBs, a stack of 2*M alternating N-channel RFIC and MMIC power amplifier chips bonded together by a wafer-scale direct bond interconnect process to form M bonded pairs of M×N element array core blocks; an array of through-substrate metal vias extending vertically through the stack (a) distributing DC bias to the MMIC power amplifier chips as well as local oscillator (LO) and information signals to the RFIC chips, and (b) connecting the N output channels of the RFIC chip to drive corresponding input channels of the MMIC power amplifier chip and driving respective antenna elements integrated in the MMIC power amplifier such that the M×N element array core block forms a steerable RF beam at the operating frequency; a cooling system including microchannels formed on the backside of at least one of the chips of each bonded pair and through-substrate vias formed through the stack operatively coupling the microchannels to all of the bonded pairs; the array core block including: top and bottom manifolds configured to deliver fluid to the array core block, circulate the fluid through the microchannels and through-substrate via holes to cool the RFIC and MMIC power amplifier chips, and extract heated fluid from the array core block; An M×N active electronically steerable array (AESA) including:

12. The chip is provided with a SiO ２ 12. The AESA of claim 11, bonded by hydrogen bonds between bonding dielectric layers and intermetallic bonds between opposing metal plugs, the hydrogen bonds and intermetallic bonds forming a seal throughout the stack to contain the circulating fluid.

13. 12. The AESA of claim 11, wherein the through-substrate via holes are configured to receive a fluid at both the top and bottom of the stack, the fluid undergoing a phase change to a gas as it circulates through the microchannels and is extracted and heated at both the top and bottom of the stack.

14. 1. A multi-wafer stack for an active electronically steerable array (AESA) for operating frequencies above 50 GHz, the stack comprising: a stack of 2*M alternating N-channel RFIC and MMIC power amplifier wafers bonded together by a wafer-scale direct bond interconnect process, the N-channel RFIC and MMIC power amplifier wafers including a plurality of N-channel RFIC chips and N-channel MMIC power amplifier chips, respectively, aligned vertically through the stack to form M bonded pairs of the plurality of M×N element array core blocks; Each array core block is an array of through-metal vias extending through each array core block to (a) distribute DC bias to MMIC power amplifiers as well as local oscillator (LO) and information signals to the RF IC, and (b) connect IF modulated and upconverted LO from each of the N output channels of the RF IC to an input of a respective channel of the MMIC power amplifier that amplifies the signal to form a steerable RF beam at the operating frequency; a cooling system for each array core block, the cooling system including microchannels formed on the backside of the RF IC and vertical through-holes operatively coupling the microchannels to all of the bonded pairs, the cooling system receiving and circulating a fluid through the stack of microchannels and vertical through-holes to cool the chip and extract the heated fluid; Including, A multi-wafer stack, wherein the stack is separable into the plurality of M×N element array core blocks.

15. The chip is provided with a SiO ２ 15. The multi-wafer stack of claim 14, bonded by hydrogen bonds between bonding dielectric layers and intermetallic bonds between opposing metal plugs, the hydrogen bonds and intermetallic bonds forming a seal throughout the stack to contain the circulating fluid.

16. 15. The multi-wafer stack of claim 14, wherein through-substrate via holes are configured to receive a fluid at both the top and bottom of the stack, the fluid undergoing a phase change to a gas as it circulates through the microchannels and is extracted and heated at both the top and bottom of the stack.

17. The multi-wafer stack of claim 14, wherein the RFIC chips are in a silicon material system and the MMIC power amplifier chips are in a III-V material system.

18. 1. A method for manufacturing a plurality of array core blocks for an active electronically steerable array (AESA) for operating frequencies above 50 GHz, comprising: fabricating M RFIC wafers from a silicon based material system at a silicon foundry; fabricating M MMIC power amplifier wafers at a III-V foundry from a III-V material system at a III-V foundry; In integrated foundries, thinning said RFIC and MMIC wafers to a specified thickness; fabricating through-substrate metal vias in said RFIC and MMIC power amplifier wafers; Fabricating a microchannel on the backside of the RFIC wafer; fabricating through-substrate via holes in said RFIC and MMIC power amplifier wafers; fabricating direct bond dielectric interfaces on both sides of said RFIC and MMIC power amplifier wafers; performing a wafer-scale direct bonding process on alternating MMIC power amplifier and RFIC wafers to form mechanical and hydrogen bonds that seal the multi-wafer stack; Bumping the multi-wafer stack to provide an interface for attachment to a printed circuit board (PCB) that is electrically coupled to the through-substrate metal vias and distributes DC bias as well as local oscillator (LO) and information signals; dicing the multi-wafer stack to form a plurality of array core blocks in which fluid circulates through the microchannels and through through-substrate via holes to cool the RFIC and MMIC power amplifiers; A manufacturing method comprising:

19. 20. The method of claim 18, wherein the through-substrate via holes are fabricated to receive a fluid at both the top and bottom of the stack, the fluid undergoing a phase change to a gas as it circulates through the microchannels and is extracted and heated at both the top and bottom of the stack.

20. 20. The method of claim 18, wherein each RFIC chip and each MIMIC power amplifier chip has a circuit side and a back side, the circuit sides being bonded opposite one another to minimize a length of the through-substrate metal vias connecting the RFIC chips to the MIMIC power amplifier chips, and the microchannels are fabricated only on the back side of the RFIC chips.

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