Semiconductor device and method for controlling the semiconductor device

Abstract

To provide a semiconductor device capable of performing a highly accurate test about a D / A converter.SOLUTION: A semiconductor device comprises a digital-to-analog converter provided with a plurality of current cells, and a test circuit electrically connected to the digital-to-analog converter and testing the digital-to-analog converter. The test circuit includes an electric charge information holding circuit which holds a difference value between a first electric charge conforming to a first current by at least one or more current cells among the plurality of current cells and a second electric charge conforming to a second current as differential electric charge information, and a comparison circuit which compares a determination voltage conforming to the differential electric charge information with a reference voltage, and outputs the comparison results.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a digital-to-analog converter. [Background technology]

[0002] A digital camera captures a subject through a lens and forms an optical image on a solid-state imaging device. These solid-state imaging devices can be broadly divided into CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors. From the perspective of improving camera performance, CMOS image sensors are attracting increasing attention because they can easily incorporate CMOS circuits for image processing as peripheral circuits. CMOS image sensors are classified into analog image sensors and digital image sensors. Although both have their advantages and disadvantages, expectations are high for digital image sensors in terms of data processing speed.

[0003] In a digital image sensor, an analog-to-digital (A / D) converter is provided for each column of a pixel array (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-120310 A Summary of the Invention [Problem to be solved by the invention]

[0005] In this regard, in order to design a highly sensitive A / D converter, it is important to have a highly accurate D / A converter output voltage to compare with the voltage of the analog pixel signal. To do this, it is necessary to test the output voltage of the D / A converter, but even if a highly accurate external power supply is used as the reference voltage for testing, there is a possibility that the noise component will not be canceled due to the influence of fluctuations in the fixed voltage inside the chip (noise component), and the test cannot be performed correctly.

[0006] The present disclosure provides a semiconductor device capable of performing highly accurate testing of a D / A converter, and a control method thereof.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] According to one embodiment, a semiconductor device includes a digital-to-analog converter having a plurality of current cells, and a test circuit electrically connected to the digital-to-analog converter for testing the digital-to-analog converter. The test circuit includes a charge information storage circuit for storing a difference between a first charge according to a first current by at least one of the plurality of current cells and a second charge according to a second current as differential charge information, a reference voltage generation circuit for generating a reference voltage to be compared, and a comparison circuit for comparing a determination voltage according to the differential charge information with the reference voltage and outputting a comparison result.

[0009] According to one embodiment, a method for controlling a semiconductor device includes a digital-to-analog converter having a plurality of current cells and a test circuit electrically connected to the digital-to-analog converter for testing the digital-to-analog converter, the method including the steps of: storing a difference value between a first charge according to a first current by at least one of the plurality of current cells and a second charge according to a second current as differential charge information; generating a reference voltage to be compared; comparing a determination voltage according to the differential charge information with the reference voltage and outputting a comparison result. Effect of the Invention

[0010] According to one embodiment, it is possible to perform highly accurate testing of D / A converters. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating a configuration of an imaging device 1 based on an embodiment. [Diagram 2] 1 is a block diagram showing configurations of an A / D converter 11 and a reference voltage generating circuit 5 according to an embodiment. [Diagram 3] 10 is a diagram illustrating the characteristics of a reference voltage VOUT which is a ramp signal according to an embodiment. FIG. [Figure 4] 10 is a diagram illustrating a configuration of a current DAC8 according to an embodiment. FIG. [Diagram 5] 1A and 1B are diagrams illustrating a DNL test of a DA converter according to an embodiment. [Figure 6] 2 is a diagram illustrating a configuration of a test circuit 6 according to an embodiment. FIG. [Figure 7] FIG. 4 is a diagram for explaining a configuration of a non-inverting amplifier 402 according to an embodiment. [Figure 8] 11 is a diagram illustrating a case where reference charge information is stored in a reference voltage generating circuit 400 in a DNL test according to an embodiment. FIG. [Figure 9] FIG. 11 is a diagram (part 1) for explaining a case where differential charge information is stored in the charge information holding circuit 300 in a DNL test according to the embodiment. [Figure 10] FIG. 2 is a diagram (part 2) for explaining a case where differential charge information is stored in the charge information holding circuit 300 in a DNL test according to an embodiment. [Figure 11] FIG. 13 is a diagram for explaining a DNL spec lower limit test of differential charge information in a DNL test according to an embodiment. [Figure 12] FIG. 13 is another diagram for explaining the DNL spec upper limit test of the differential charge information in the DNL test according to the embodiment. [Figure 13] 1A and 1B are diagrams illustrating an INL test of a DA converter according to an embodiment. [Figure 14] 11 is a diagram illustrating a case where reference charge information is stored in a reference voltage generation circuit 400 in an INL test according to an embodiment. FIG. [Figure 15] FIG. 11 is a diagram (part 1) for explaining a case where differential charge information is stored in the charge information holding circuit 300 in an INL test according to an embodiment. [Figure 16] FIG. 2 is a diagram (part 2) illustrating a case where differential charge information is stored in the charge information holding circuit 300 in an INL test according to an embodiment. [Figure 17] 11A and 11B are diagrams illustrating determination of the polarity of differential charge information in an INL test according to an embodiment. [Figure 18] 11A and 11B are diagrams illustrating an INL spec lower limit test of differential charge information according to an embodiment. [Figure 19] 11A and 11B are diagrams for explaining an INL spec upper limit test of differential charge information according to an embodiment. [Figure 20] 11A and 11B are diagrams illustrating a gain error test of a DA converter according to an embodiment. [Figure 21] 11 is a diagram illustrating a case where reference charge information is stored in the reference voltage generating circuit 400 according to the embodiment. FIG. [Figure 22] 11 is a diagram illustrating a case (part 1) in which differential charge information is stored in the charge information holding circuit 300 in a gain error test according to an embodiment. FIG. [Figure 23] FIG. 2 is a diagram (part 2) illustrating a case where differential charge information is stored in the charge information holding circuit 300 in a gain error test according to an embodiment. [Figure 24] 11A and 11B are diagrams illustrating determination of the polarity of differential charge information in a gain error test according to an embodiment. [Diagram 25] FIG. 13 is a diagram illustrating a gain error spec lower limit test according to an embodiment. [Figure 26] FIG. 13 is a diagram illustrating a gain error spec upper limit test according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure will now be described in detail with reference to the accompanying drawings, in which the same or corresponding parts are designated by the same reference characters and will not be described repeatedly.

[0013] FIG. 1 is a diagram illustrating the configuration of an imaging device 1 based on an embodiment. 1, an imaging device 1 according to the embodiment is a semiconductor device formed on a semiconductor substrate, and includes a pixel array 2, a row selection circuit 3, and a control circuit 10 as shown in FIG.

[0014] The pixel array 2 includes a plurality of pixel circuits P arranged in a plurality of rows and a plurality of columns, a plurality of control lines each corresponding to the plurality of rows, and a plurality of signal lines each corresponding to the plurality of columns. Each pixel circuit P outputs a sampling pixel signal VA having a voltage corresponding to the amount of incident light. Each pixel circuit P is connected to the control line CL of the corresponding row and the signal line SL of the corresponding column. The plurality of control lines CL are connected to a row selection circuit 3.

[0015] The row selection circuit 3 is controlled by a control circuit 10, which sequentially selects the multiple rows one by one and sets the control line CL of the selected row to an activation level. Each pixel circuit P is activated in response to the corresponding control line CL being set to an activation level, and outputs a sampling pixel signal VA, the voltage of which corresponds to the amount of incident light, to the corresponding signal line SL. The control circuit 10 controls the entire imaging device.

[0016] The imaging device 1 also includes a reference voltage generating circuit 5, a plurality of A / D converters 11, a horizontal transfer circuit 13, and a signal processing circuit 12.

[0017] The reference voltage generating circuit 5 generates a reference voltage used by a plurality of A / D converters 11 . The reference voltage is applied to each of the plurality of A / D converters 11. The plurality of A / D converters 11 are respectively connected to the plurality of signal lines SL.

[0018] Each A / D converter 11 operates according to control instructions from the control circuit 10, and converts a sampled pixel signal VA output from a pixel circuit P activated by the row selection circuit 3 to a corresponding signal line SL into a multi-bit digital pixel signal DP.

[0019] Specifically, the A / D converter 11 performs A / D conversion on the sampled pixel signal VA to convert it into a multi-bit digital pixel signal DP based on a reference voltage VOUT, which is a ramp signal.

[0020] In this example, a case where a 10-bit data signal is generated will be described. The horizontal transfer circuit 13 temporarily holds the digital pixel signals DP for one row provided from the A / D converters 11, and then transfers the held digital pixel signals DP one by one in sequence to the signal processing circuit 12.

[0021] The signal processing circuit 12 generates a 10-bit digital pixel signal DO based on the 10-bit digital pixel signal DP, and outputs the generated digital pixel signal DO to the outside.

[0022] FIG. 2 is a block diagram showing configurations of the A / D converter 11 and the reference voltage generating circuit 5 according to the embodiment.

[0023] 2, the A / D converter 11 includes a comparison unit 108 and a latch 112. The comparison unit 108 includes a one-stage or multiple-stage pre-amplifier and a binarization circuit 110. The comparison unit 108 compares a sampled pixel signal output from the pixel circuit P to a control line CL with a reference voltage VOUT, which is a ramp signal. When the reference voltage VOUT, which is a ramp signal, is smaller, the output signal COMP operates to output an L level. The latch 112 includes a latch that captures the output signal COMP from the binarization circuit 110, and a counter latch in which the capture timing of a counter signal is controlled by the output of the comparison unit 108.

[0024] The 10-bit counter 7 is controlled by the control circuit 10 and is connected to the latch 112 of each AD converter 11. The bias circuit supplies a bias voltage to the preamplifier in the comparison unit .

[0025] In this example, a pre-amplifier having a three-stage configuration including a first amplifier 121, a second amplifier 122, and a third amplifier 123 is shown.

[0026] The input terminal and output terminal of the first amplifier 121 are connected via capacitors to the input terminal of the second amplifier 122. An auto-zero operation that closes the switches inserted between the input / output terminals of the first amplifier 121 and between the input / output terminals of the second amplifier 122 makes it possible to operate each amplifier at an optimal operating point, independent of the external signal DC level.

[0027] An input terminal of the first amplifier 121 is connected via a capacitor to the control line CL extending from the pixel circuit P. As a result, the voltage of the sampling pixel signal VA of the control line CL is input to the input terminal.

[0028] The other input terminal of the first amplifier 121 receives a reference voltage VOUT via a capacitor.

[0029] The comparison unit 108 may include a plurality of capacitors in addition to the second amplifier 122, the third amplifier 123, and the binarization circuit 110.

[0030] The output terminal of the first amplifier 121 is connected to the input terminal of the second amplifier 122 via a capacitor. The output terminal of the first amplifier 121 is connected to the input terminal of the second amplifier 122 via a capacitor. Therefore, a capacitor is disposed between the first amplifier 121 and the second amplifier 122. Thereby, the power supply voltage of the first amplifier 121 and the power supply voltage of the second amplifier 122 may be made different. For example, the power supply voltage of the second amplifier 122 may be made lower than the power supply voltage of the first amplifier 121. In this way, it is possible to reduce power consumption.

[0031] The output terminal of the second amplifier 122 is connected to the input terminal of the third amplifier 123. The output terminal of the third amplifier 123 is input to the binarization circuit 110. Therefore, the third amplifier 123 is connected between the second amplifier 122 and the binarization circuit 110. The output terminal of the second amplifier 122 is connected to the binarization circuit 110 via the third amplifier 123.

[0032] The reference voltage generating circuit 5 includes a 10-bit counter 7 , a current DAC 8 , and a test circuit 6 .

[0033] The reference voltage generating circuit 5 is controlled in accordance with a control instruction from a control circuit 10 . The 10-bit counter 7 is controlled by the control circuit 10 and is connected to the latch 112 of each AD conversion circuit. A bias circuit (not shown) is provided to supply a bias voltage to the preamplifier in each comparison unit .

[0034] The current DAC8 adjusts the amount of current flowing through the resistor R in accordance with a signal from the 10-bit counter 7. A reference voltage VOUT, which is a ramp signal generated by the resistor R, is generated from the current DAC8.

[0035] The comparison unit 108 compares the voltage of the sampled pixel signal VA with the voltage of the reference voltage VOUT, and outputs an output signal COMP indicative of the comparison result.

[0036] The reference voltage VOUT, which is a ramp signal, decreases over time as will be described later with reference to FIG.

[0037] Then, the time until the output inversion of the output signal COMP from the binarization circuit 110 is measured. The latch 112 holds the counter value of the 10-bit counter 7, triggered by the output determination of the output signal COMP. A 10-bit digital pixel signal DP corresponding to the sampled pixel signal VA is output in accordance with the counter value held in the latch 112. In this way, analog-to-digital conversion processing of the sampled pixel signal VA is performed.

[0038] FIG. 3 is a diagram illustrating the characteristics of the reference voltage VOUT which is a ramp signal according to the embodiment.

[0039] As shown in FIG. 3, a current DAC 8 adjusts the amount of current flowing through a resistor R in accordance with a signal from a 10-bit counter 7, and the amount of current decreases over time.

[0040] In this example, three waveforms are shown, with the solid line being the reference voltage VOUT, which is an ideal ramp signal, and the dashed line or double-dashed line being the actual reference voltage.

[0041] Due to sample variations, there may be deviations from the ideal ramp signal shown by the solid line. The test circuit 6 according to the embodiment tests whether the reference voltage VOUT, which is a ramp signal, is appropriate. Specifically, the variation in the reference voltage VOUT is verified according to the output TESTOUT of the test circuit 6, and it is determined whether the reference voltage VOUT is appropriate.

[0042] FIG. 4 is a diagram illustrating a configuration of the current DAC8 according to the embodiment. Referring to FIG. 4A, the current DAC8 includes a plurality of current cells arranged in a matrix. The current DAC8 also includes a row decoder and a column decoder, and sets the current cells to be driven (ON) according to the input of a digital code (10 bits). The current i of the current DAC8 is set according to the number of current cells to be turned ON. In this example, the current value i and the resistance R are set so that the current is 1V when all the current cells are turned ON.

[0043] 4B shows the characteristics of the current DAC8 according to the embodiment. The larger the code value of the input code (10 bits), the larger the DAC output. Basically, it is desirable for the DAC output to be linear with respect to the increase in the code value, but the actual DAC output characteristics have a nonlinear portion. It is important that the specification requirements are met even in the nonlinear portion.

[0044] FIG. 5 is a diagram for explaining a DNL test of a DA converter according to an embodiment. 5A shows a case where the reference voltage VOUT rises by a constant value as the code value of the digital code increases. On the other hand, FIG. 5B shows a case where the DNL is 1 LSB or more (LSB: least significant bit). Also, FIG. 5C shows a case where the DNL is negative, even though the reference voltage VOUT should increase as the digital code increases.

[0045] This situation must be judged as a defect since it affects the performance of the DA converter.

[0046] FIG. 6 is a diagram illustrating a configuration of a test circuit 6 according to an embodiment. 6, the test circuit 6 includes a comparison circuit 200, a charge information holding circuit 300, and a reference voltage generating circuit 400. The comparison circuit 200 includes a comparison circuit 200 and a charge information holding circuit 300. The comparison circuit 200 includes a reference voltage generating circuit 400.

[0047] The charge information holding circuit 300 holds, as differential charge information, a difference value between a first charge according to a first current by at least one or more current cells among the multiple current cells of the current DAC8 and a second charge according to a second current.

[0048] The reference voltage generating circuit 400 generates a reference voltage to be compared. The comparison circuit 200 compares a determination voltage according to the differential charge information with a reference voltage, and outputs a comparison result.

[0049] The charge information holding circuit 300 includes a capacitor 310 and switches 302, 304, 306, 308, 312, and 314. The switches may be PMOS / NMOS complementary switches. A dummy switch may be provided as a countermeasure against charge injection and clock feed-through during switch operation. An operating clock may be used during switch operation, and a non-overlapping clock may be used to prevent the switches from being turned on simultaneously.

[0050] The capacitor 310 is provided between the node N0 and the node N1. The switch 306 is provided between the node N2 and the node N0. The switch 308 is provided between the node N2 and the node N1. The switch 314 is provided between the node N1 and the fixed voltage VSS. The switch 312 is provided between the node N0 and the fixed voltage VSS. The switch 302 is provided between the node N0 and the node N3. The switch 304 is provided between the node N3 and the node N1.

[0051] The reference voltage generating circuit 400 includes a capacitor 406, a non-inverting amplifier 402, and a switch 408. The capacitor 406 is provided between an input node of the non-inverting amplifier 402 and a fixed voltage VSS. The switch 408 is provided between a node N2 and the non-inverting amplifier 402. The non-inverting amplifier 402 includes a variable resistance element 404. The amplification factor of the non-inverting amplifier 402 is adjusted by adjusting the resistance value of the variable resistance element 404.

[0052] The comparison circuit 200 includes a comparator 210 and switches 212, 214, 216, 218, and 220.

[0053] The switch 212 is provided between the input node N4 of the comparator 210 and a node N3. The switch 214 is provided between the input node N4 of the comparator 210 and a node N6. The switch 216 is provided between the input node N5 of the comparator 210 and a node N3. The switch 218 is provided between the input node N5 of the comparator 210 and a node N6. The switch 220 is provided between the input node N5 of the comparator 210 and a fixed voltage VSS. The node N6 is connected to the output node of the non-inverting amplifier 402.

[0054] The current DAC 8 includes a switch that controls the connection to the test circuit 6 . In this example, there are provided switches TS1, TS2, .... By operating the switches TS1 and TS2, it becomes possible to supply a current to the test circuit 6.

[0055] The control circuit 10 controls the reference voltage generating circuit 5 and executes various test operations by controlling the connections of the switches.

[0056] FIG. 7 is a diagram illustrating a configuration of the non-inverting amplifier 402 according to the embodiment. 7, the non-inverting amplifier 402 outputs an output voltage VO obtained by amplifying an input voltage VI. Specifically, the output voltage VO is output based on an amplification factor according to the resistance ratio of the variable resistance element 404. As an example, by setting the resistance ratio of resistors R1 and R2 of the variable resistance element 404 to 1:1, the non-inverting amplifier 402 outputs an output voltage VO that is twice the input voltage VI.

[0057] (DNL (differential non-linearity) test) A DNL test according to an embodiment will now be described.

[0058] 8 is a diagram for explaining a case where reference charge information is stored in the reference voltage generating circuit 400 in the DNL test according to the embodiment. Referring to FIG. 8, after the charge of the capacitor 406 is reset, the charge of all the current sources (1023i) is accumulated in the capacitor 406 as the reference charge information using a time t / 1023. Note that, as an example, a case where the digital code input to the current DAC8 is 10 bits will be explained. When the digital code input to the current DAC8 is 12 bits, the charge of all the current sources (4095i) may be accumulated in the capacitor 406 using a time t / 4095.

[0059] Specifically, the switches TS1, TS2, etc. are all turned on to connect all current cells of the current DAC 8 to the node N2. Also, the switch 408 is turned on to connect the node N2 to the capacitor 406. The other switches are turned off.

[0060] At this point, the amount of charge is adjusted by adjusting the on-time of the switch. Specifically, the time when the switch 408 is turned on is set to time t / 1023.

[0061] This sets the charge stored in capacitor 406 to Q=C×1023i×t / 1023.

[0062] 9 is a diagram (part 1) for explaining a case where differential charge information is stored in the charge information holding circuit 300 in a DNL test according to an embodiment. Referring to FIG. 9, after the charge of the capacitor 310 is reset, the charge of the current source (1i) is accumulated in the capacitor 310 as charge information using a time t.

[0063] Specifically, the switch TS1 is turned on to connect the 1LSB current cell to the node N2. Also, the switch 306 is turned on to connect the node N2 to the node N0 side of the capacitor 310. Also, the switch 314 is turned on to connect the node N1 side of the capacitor 310 to the fixed voltage VSS. The other switches are off.

[0064] Moreover, the amount of charge is adjusted by adjusting the on-time of the switch. Specifically, the time for turning on the switches 306 and 314 is set to time t.

[0065] This sets the charge stored in capacitor 310 to Q=C×i×t. 10 is a diagram (part 2) for explaining a case where differential charge information is stored in the charge information holding circuit 300 in the DNL test according to the embodiment. Referring to FIG.

[0066] Specifically, the switch TS2 is turned on to connect the 2LSB current cell to the node N2. Also, the switch 308 is turned on to connect the node N2 to the node N1 side of the capacitor 310. Also, the switch 312 is turned on to connect the node N0 side of the capacitor 310 to the fixed voltage VSS. The other switches are off.

[0067] Moreover, the amount of charge is adjusted by adjusting the on-time of the switch. Specifically, the time for turning on the switches 308 and 312 is set to time t.

[0068] As a result, the charge stored in the capacitor 310 from the node N1 side of the capacitor 310 is set to Q=C×2i×t.

[0069] Therefore, the differential charge information is stored as the charge information of the capacitor 310 . 11 is a diagram for explaining a DNL spec lower limit test of differential charge information in a DNL test according to an embodiment. The DNL spec lower limit test will be explained with reference to FIG. 11. The node N1 side of the capacitor 310 is set to +Qdiff, and the node N0 side is set to -Qidiff. The switch 304 is turned on to connect the node N1 and the node N3. The switch 312 is turned on to connect the node N0 and the fixed voltage VSS.

[0070] Also, the switch 212 of the comparison circuit 200 is turned on to connect the node N3 and the node N4, and the switch 220 of the comparison circuit 200 is turned on to connect the node N5 and the fixed voltage VSS, while the other switches are turned off.

[0071] As a result, the input node N4 of the comparator 210 receives an input of a voltage according to the charge stored in the capacitor 310. In addition, the input node N5 of the comparator 210 is connected to the fixed voltage VSS.

[0072] The comparator 210 outputs an "H" level if the voltage of the input node N4 of the comparator 210 is greater than a fixed voltage VSS (for example, 0 V). The comparator 210 outputs an "L" level if the voltage of the input node N4 of the comparator 210 is less than a fixed voltage VSS (for example, 0 V).

[0073] That is, if the differential charge information based on the current difference between the 2LSB and 1LSB current cells is positive, the comparator 210 outputs an "H" level. On the other hand, if the differential charge information based on the current difference between the 2LSB and 1LSB current cells is negative, the comparator 210 outputs an "L" level. In other words, as a test of the lower limit of the specification of the differential charge information, it is determined whether the differential charge information based on the current difference between the 2LSB and 1LSB current cells is positive or not.

[0074] If the comparator 210 is at "H" level, it is determined as OK, and if it is at "L" level, it is determined as NG.

[0075] 12 is another diagram for explaining the DNL spec upper limit test of the differential charge information in the DNL test according to the embodiment. The DNL spec upper limit test will be explained with reference to FIG. 12. The node N1 side of the capacitor 310 is set to +Qdiff, and the node N0 side is set to -Qidiff. The switch 304 is turned on to connect the node N1 and the node N3. The switch 312 is turned on to connect the node N0 and the fixed voltage VSS.

[0076] Also, the switch 216 of the comparison circuit 200 is turned on to connect the node N3 and the node N5, and the switch 214 of the comparison circuit 200 is turned on to connect the node N4 and the output node of the non-inverting amplifier 402. The other switches are off.

[0077] As a result, the input node N5 of the comparator 210 receives an input of a voltage according to the charge stored in the capacitor 310. In addition, the input node N4 of the comparator 210 is connected to the output node of the non-inverting amplifier 402.

[0078] The comparator 210 outputs an "H" level if the voltage of the input node N4 of the comparator 210 is greater than the voltage of the input node N5. The comparator 210 outputs an "L" level if the voltage of the input node N4 of the comparator 210 is less than the voltage of the input node N5. In this example, the voltage of the input node N4 of the comparator 210 is set to 2×Q / C.

[0079] That is, the comparator 210 compares the voltage of 2×Q / C with the voltage according to the differential charge information based on the current difference between the 2LSB and 1LSB current cells, and outputs an “H” level if the voltage of 2×Q / C is greater. On the other hand, if the voltage according to the differential charge information based on the current difference between the 2LSB and 1LSB current cells is greater, the comparator 210 outputs an “L” level. In other words, as a test of the upper limit of the specification of the differential charge information, it is determined whether the differential charge information based on the current difference between the 2LSB and 1LSB current cells exceeds 2DNL.

[0080] If the comparator 210 is at "H" level, it is determined as OK, and if it is at "L" level, it is determined as NG.

[0081] The DNL tests described above are performed in sequence, shifting one code at a time. Specifically, the node N0 side of the capacitor 310 is connected to the 2LSB current cell according to the procedure described above, and a charge according to the 2LSB current cell is stored. Next, the node N1 side of the capacitor 310 is connected to the 3LSB current cell, and a charge according to the 3LSB current cell is stored. This causes the capacitor 310 to store differential charge information between 3LSB and 2LSB. Then, the spec lower limit test and spec upper limit test are performed on the differential charge information as described in FIG. 11 and FIG. 12.

[0082] By executing all of this code, it is possible to detect defects in the DA converter in the DNL test described in Figure 5.

[0083] By the test method according to the embodiment, the capacitor 310 stores differential charge information. The capacitor 310 is connected to an internal fixed voltage VSS. Even if there is a fluctuation (noise component) in the fixed voltage, the noise component is cancelled in the differential charge information, so that it is possible to store highly accurate differential charge information excluding the noise component. In addition, since the same capacitor 310 is used for comparison, it is possible to suppress the influence of manufacturing variations in the capacitor. In addition, the reference voltage used in the test circuit 6 does not need to be input from the outside, but can be generated internally. Therefore, it is possible to generate the reference voltage in a simple manner without using an external power supply. Furthermore, it is possible to reduce the error of the comparator 210 by limiting the range in which the comparator 210 makes a comparison.

[0084] (INL (integral non-linearity) test) An INL test according to an embodiment will now be described.

[0085] FIG. 13 is a diagram illustrating an INL test of a DA converter according to an embodiment. 13, an ideal straight line following the DAC output characteristic is shown, and the actual DAC output is also shown.

[0086] INL indicates the deviation of the actual output characteristics from an ideal straight line over the entire relationship between the analog input voltage and digital output signal of a DA converter.

[0087] As an example, a comparison is shown of the charge Q300 in the code 300 and the charge Q300# for an ideal straight line. If the degree of deviation in the comparison is large, it will affect the performance of the DA converter and so it must be judged as defective.

[0088] 14 is a diagram for explaining a case where reference charge information is stored in the reference voltage generation circuit 400 in the INL test according to the embodiment. Referring to FIG. 14, after the charge of the capacitor 406 is reset, the charge of all the current sources (1023i) is accumulated in the capacitor 406 as the reference charge information using a time t / 1023.

[0089] Specifically, the switches TS1, TS32, etc. are all turned on to connect all current cells of the current DAC8 to the node N2. Also, the switch 408 is turned on to connect the node N2 to the capacitor 406. The other switches are turned off.

[0090] At this point, the amount of charge is adjusted by adjusting the on-time of the switch. Specifically, the time when the switch 408 is turned on is set to time t / 1023.

[0091] This sets the charge stored in capacitor 406 to Q=C×1023i×t / 1023.

[0092] 15 is a diagram (part 1) for explaining a case where differential charge information is stored in the charge information holding circuit 300 in an INL test according to an embodiment. Referring to FIG. 15, after the charge of the capacitor 310 is reset, the charge of the current source (1i) is accumulated in the capacitor 310 as charge information using a time t.

[0093] Specifically, the switch TS1 is turned on to connect the 1LSB current cell to node N2. Also, the switch 306 is turned on to connect node N2 to the node N0 side of the capacitor 310. Also, the switch 314 is turned on to connect the node N1 side of the capacitor 310 to the fixed voltage VSS. The other switches are off.

[0094] Moreover, the amount of charge is adjusted by adjusting the on-time of the switch. Specifically, the time for turning on the switches 306 and 314 is set to time t.

[0095] This sets the charge stored in capacitor 310 to Q=C×i×t. 16 is a diagram (part 2) for explaining a case where differential charge information is stored in the charge information holding circuit 300 in the INL test according to the embodiment. Referring to FIG.

[0096] Specifically, the switches TS1, TS32, etc. are all turned on to connect all current cells of the current DAC8 to the node N2. Also, the switch 308 is turned on to connect the node N2 to the node N1 side of the capacitor 310. Also, the switch 312 is turned on to connect the node N0 side of the capacitor 310 to the fixed voltage VSS. The other switches are off.

[0097] Moreover, the amount of charge is adjusted by adjusting the on-time of the switch. Specifically, the time when the switches 308 and 312 are turned on is set to time t / 1023.

[0098] As a result, the charge stored in the capacitor 310 from the node N1 side of the capacitor 310 is set to Q=C×1023i×t / 1023.

[0099] Therefore, the differential charge information is stored as the charge information of the capacitor 310 . That is, after accumulating the charge of a current cell of 1 LSB in the capacitor 310, a difference in charge equivalent to 1 LSB based on an ideal straight line for the DAC output characteristic is accumulated.

[0100] 17 is a diagram for explaining the determination of the polarity of the differential charge information in the INL test according to the embodiment. Referring to FIG. 17, as the differential charge information, the node N1 side of the capacitor 310 is set to +Qdiff, and the node N0 side is set to -Qidiff. The switch 304 is turned on to connect the node N1 and the node N3. The switch 312 is turned on to connect the node N0 and the fixed voltage VSS.

[0101] Also, the switch 212 of the comparison circuit 200 is turned on to connect the node N3 and the node N4, and the switch 220 of the comparison circuit 200 is turned on to connect the node N5 and the fixed voltage VSS, while the other switches are turned off.

[0102] As a result, the input node N4 of the comparator 210 receives an input of a voltage according to the charge stored in the capacitor 310. In addition, the input node N5 of the comparator 210 is connected to the fixed voltage VSS.

[0103] The comparator 210 outputs an "H" level if the voltage of the input node N4 of the comparator 210 is greater than a fixed voltage VSS (for example, 0 V). The comparator 210 outputs an "L" level if the voltage of the input node N4 of the comparator 210 is less than a fixed voltage VSS (for example, 0 V).

[0104] That is, the polarity of the capacitor 310 can be determined by the output of the comparator 210. When the output of the comparator 210 is at the "H" level, this indicates that the charge equivalent to 1LSB based on the ideal straight line is greater than the charge of the 1LSB current cell. In other words, this indicates that the charge amount of the 1LSB current cell is lower than the charge equivalent to 1LSB based on the ideal straight line. In this case, a test is performed to check the lower limit of the specification for the charge of the 1LSB current cell.

[0105] On the other hand, when the output of the comparator 210 is at the "L" level, it indicates that the charge equivalent to 1LSB based on the ideal straight line is less than the charge of the 1LSB current cell. In other words, it indicates that the charge amount of the 1LSB current cell is greater than the charge equivalent to 1LSB based on the ideal straight line. In this case, a test of the upper limit of the specification for the charge of the 1LSB current cell is performed.

[0106] 18 is a diagram for explaining an INL spec lower limit test of differential charge information according to an embodiment. The INL spec lower limit test will be explained with reference to FIG. 18. The node N1 side of the capacitor 310 is set to +Qdiff, and the node N0 side is set to -Qidiff. The switch 304 is turned on to connect the node N1 and the node N3. The switch 312 is turned on to connect the node N0 and the fixed voltage VSS.

[0107] Also, the switch 216 of the comparison circuit 200 is turned on to connect the node N3 to the node N5, and the switch 214 of the comparison circuit 200 is turned on to connect the node N4 to the node N6, while the other switches are turned off.

[0108] As a result, the input node N5 of the comparator 210 receives an input of a voltage according to the charge stored in the capacitor 310. In addition, the input node N4 of the comparator 210 is connected to the output node of the non-inverting amplifier 402.

[0109] The comparator 210 outputs an "H" level if the voltage of the input node N4 of the comparator 210 is higher than the voltage of the input node N5. The comparator 210 outputs an "L" level if the voltage of the input node N4 of the comparator 210 is lower than the voltage of the input node N5.

[0110] That is, when the charge amount of the current cell of 1 LSB is lower than the charge equivalent to 1 LSB based on the ideal straight line, the magnitude of the differential charge information is determined.

[0111] For example, the INL specification lower limit is set to 3 LSB. The reference voltage is set by adjusting the resistance value of the variable resistor element 404. Specifically, the resistors R1:R2 are set to 2:1. This setting outputs an output voltage VO that is three times the input voltage VI. This resistance ratio can be set to any value. Note that it is also possible to set the resistors R2>>R1 to output an output voltage VO that is one time the input voltage VI.

[0112] The comparator 210 outputs an "H" level if the magnitude of the differential charge information is less than 3 LSB. On the other hand, if the magnitude of the differential charge information is 3 LSB or more, it outputs an "L" level. In other words, it determines whether the degree of deviation is within 3 LSB as a test of the lower limit of the specification of the differential charge information.

[0113] If the comparator 210 is at "H" level, it is determined as OK, and if it is at "L" level, it is determined as NG.

[0114] 19 is a diagram for explaining an INL spec upper limit test of differential charge information according to an embodiment. The INL spec upper limit test will be explained with reference to FIG. 19. The node N0 side of the capacitor 310 is set to +Qdiff, and the node N1 side is set to -Qidiff. The switch 302 is turned on to connect the node N0 and the node N3. The switch 314 is turned on to connect the node N1 and the fixed voltage VSS.

[0115] Also, the switch 216 of the comparison circuit 200 is turned on to connect the node N3 to the node N5, and the switch 214 of the comparison circuit 200 is turned on to connect the node N4 to the node N6, while the other switches are turned off.

[0116] As a result, the input node N5 of the comparator 210 receives an input of a voltage according to the charge stored in the capacitor 310. In addition, the input node N4 of the comparator 210 is connected to the output node of the non-inverting amplifier 402.

[0117] The comparator 210 outputs an "H" level if the voltage of the input node N4 of the comparator 210 is higher than the voltage of the input node N5. The comparator 210 outputs an "L" level if the voltage of the input node N4 of the comparator 210 is lower than the voltage of the input node N5.

[0118] That is, when the charge amount of a current cell of 1 LSB is larger than the charge equivalent to 1 LSB based on an ideal straight line, the magnitude of the differential charge information is determined.

[0119] For example, the upper limit of the INL specification is set to 3 LSB. The reference voltage is set by adjusting the resistance value of the variable resistor element 404. Specifically, the resistors R1:R2 are set to 2:1. This setting outputs an output voltage VO that is three times the input voltage VI. This resistance ratio can be set to any value. Note that it is also possible to set the resistors R2>>R1 to output an output voltage VO that is one time the input voltage VI.

[0120] The comparator 210 outputs an "H" level if the magnitude of the differential charge information is less than 3 LSB. On the other hand, if the magnitude of the differential charge information is 3 LSB or more, it outputs an "L" level. In other words, it determines whether the degree of deviation is within 3 LSB as a test of the upper limit of the specification of the differential charge information.

[0121] If the comparator 210 is at "H" level, it is determined as OK, and if it is at "L" level, it is determined as NG.

[0122] The INL tests described above are executed in sequence, shifting one code at a time. Specifically, the node N0 side of the capacitor 310 is connected to the 2LSB current cell according to the procedure described above, and charge according to the 2LSB current cell is stored. Next, the node N1 side of the capacitor 310 is connected to all the current cells, and charge is stored in the capacitor 310 using a time period of 2t / 1023.

[0123] As a result, after accumulating a charge of 2LSB of the current cell in the capacitor 310, a charge difference equivalent to 2LSB based on an ideal straight line for the DAC output characteristics is accumulated. Then, for the differential charge information, an INL spec lower limit test and an INL spec upper limit test are performed based on the polarity of the differential charge information as described in Figs.

[0124] By executing all of this code, it becomes possible to detect defects in the DA converter in the INL test described with reference to FIG.

[0125] By the test method according to the embodiment, the capacitor 310 accumulates differential charge information. The capacitor 310 is connected to an internal fixed voltage VSS. Even if there is a fluctuation (noise component) in the fixed voltage, the noise component is cancelled in the differential charge information, so that it is possible to accumulate highly accurate differential charge information excluding the noise component. In addition, since the same capacitor 310 is used for comparison, it is possible to suppress the influence of manufacturing variations in the capacitor. In addition, the reference voltage used in the test circuit 6 does not need to be input from the outside, but can be generated internally. Therefore, it is possible to generate the reference voltage in a simple manner without using an external power supply. Furthermore, it is possible to reduce the error of the comparator 210 by limiting the range in which the comparator 210 makes a comparison.

[0126] (Gain Error Test) A gain error test according to an embodiment will now be described.

[0127] FIG. 20 is a diagram illustrating a gain error test of a DA converter according to an embodiment.

[0128] 20, an ideal straight line following the DAC output characteristic is shown, an actual DAC output is shown, and an ideal DAC output characteristic is shown.

[0129] Gain error indicates the deviation of gain between a straight line that follows an ideal DAC output characteristic and a straight line that follows an actual DAC output characteristic over the entire relationship between the analog input voltage and the digital output signal of a DA converter.

[0130] As an example, the maximum output at full code and the maximum output as a design result at full code are shown. If the degree of deviation is large in the comparison, it is necessary to judge it as defective because it will affect the performance of the DA converter.

[0131] 21 is a diagram for explaining a case where reference charge information is stored in the reference voltage generating circuit 400 according to the embodiment. Referring to FIG. 21, after the charge of the capacitor 406 is reset, the charge of the current source (1i) is accumulated in the capacitor 406 as the reference charge information using a time t / 2.

[0132] Specifically, the switch TS1 is turned on to connect the current cell of the current DAC8 to the node N2. Also, the switch 408 is turned on to connect the node N2 to the capacitor 406. The other switches are turned off. At this point, the amount of charge is adjusted by adjusting the on-time of the switches.

[0133] Specifically, the time when the switch 408 is turned on is set to time t / 2. This sets the charge stored in capacitor 406 to Q=C×i×t / 2.

[0134] 22 is a diagram for explaining a case (part 1) in which differential charge information is stored in the charge information holding circuit 300 in a gain error test according to an embodiment. Referring to FIG. 22, after the charge of the capacitor 310 is reset, the charge of the current source (1023i) is accumulated in the capacitor 310 as charge information using a time t.

[0135] Specifically, the switches TS1, T32, etc. are all turned on to connect all current cells (1023 LSB) of the current DAC8 to the node N2. Also, the switch 306 is turned on to connect the node N2 to the node N0 side of the capacitor 310. Also, the switch 314 is turned on to connect the node N1 side of the capacitor 310 to the fixed voltage VSS. The other switches are off.

[0136] Moreover, the amount of charge is adjusted by adjusting the on-time of the switch. Specifically, the time for turning on the switches 306 and 314 is set to time t.

[0137] This sets the charge stored in capacitor 310 to Q=C×1023i×t.

[0138] 23 is a diagram (part 2) illustrating a case where differential charge information is stored in the charge information holding circuit 300 in the gain error test according to the embodiment. Referring to FIG.

[0139] Specifically, the switch TS1 is turned on to connect the 1LSB current cell to the node N2. Also, the switch 308 is turned on to connect the node N2 to the node N1 side of the capacitor 310. Also, the switch 312 is turned on to connect the node N0 side of the capacitor 310 to the fixed voltage VSS. The other switches are off.

[0140] Moreover, the amount of charge is adjusted by adjusting the on-time of the switch. Specifically, the time when the switches 308 and 312 are turned on is set to time 1023t.

[0141] As a result, the charge stored in the capacitor 310 from the node N1 side of the capacitor 310 is set to Q=C×i×1023t.

[0142] Therefore, the differential charge information is stored as the charge information of the capacitor 310 . That is, as explained in FIG. 20, the difference between the charge accumulated according to the ideal straight line when a full code is input and the charge accumulated according to the actual DAC output characteristics is accumulated.

[0143] Fig. 24 is a diagram for explaining the determination of the polarity of the differential charge information in the gain error test according to the embodiment. Referring to Fig. 24, as the differential charge information, the node N1 side of the capacitor 310 is set to +Qdiff, and the node N0 side is set to -Qidiff. The switch 304 is turned on to connect the node N1 and the node N3. The switch 312 is turned on to connect the node N0 and the fixed voltage VSS.

[0144] Also, the switch 212 of the comparison circuit 200 is turned on to connect the node N3 and the node N4, and the switch 220 of the comparison circuit 200 is turned on to connect the node N5 and the fixed voltage VSS, while the other switches are turned off.

[0145] As a result, the input node N4 of the comparator 210 receives an input of a voltage according to the charge stored in the capacitor 310. In addition, the input node N5 of the comparator 210 is connected to the fixed voltage VSS.

[0146] The comparator 210 outputs an "H" level if the voltage of the input node N4 of the comparator 210 is greater than a fixed voltage VSS (for example, 0 V). The comparator 210 outputs an "L" level if the voltage of the input node N4 of the comparator 210 is less than a fixed voltage VSS (for example, 0 V).

[0147] That is, the polarity of the capacitor 310 can be determined by the output of the comparator 210. When the output of the comparator 210 is at the "H" level, this indicates that the charge accumulated based on the ideal straight line when a full code is input is greater than the charge accumulated based on the actual DAC output characteristics. In other words, this indicates that the gain characteristic of the actual DAC output characteristics is lower than the gain characteristic based on the ideal straight line. In this case, a test of the lower limit of the gain error specification is performed.

[0148] On the other hand, when the output of the comparator 210 is at the "L" level, it indicates that the charge based on the ideal straight line when a full code is input is less than the charge accumulated according to the actual DAC output characteristics. In other words, it indicates that the gain characteristic of the actual DAC output characteristics is higher than the gain characteristic based on the ideal straight line. In this case, a test of the upper limit of the gain error specification is performed.

[0149] Fig. 25 is a diagram for explaining a gain error spec lower limit test according to an embodiment. The gain error spec lower limit test will be explained with reference to Fig. 25. The switch 304 is turned on to connect the node N1 and the node N3. The switch 312 is turned on to connect the node N0 and the fixed voltage VSS.

[0150] Also, the switch 212 of the comparison circuit 200 is turned on to connect the node N3 and the node N4, and the switch 218 of the comparison circuit 200 is turned on to connect the node N5 and the node N6, while the other switches are turned off.

[0151] As a result, the input node N4 of the comparator 210 receives an input of a voltage according to the charge stored in the capacitor 310. In addition, the input node N5 of the comparator 210 is connected to the output node of the non-inverting amplifier 402.

[0152] The comparator 210 outputs an "H" level if the voltage of the input node N4 of the comparator 210 is higher than the voltage of the input node N5. The comparator 210 outputs an "L" level if the voltage of the input node N4 of the comparator 210 is lower than the voltage of the input node N5.

[0153] That is, the voltage according to the charge stored in the capacitor 310 is compared with the voltage of the gain error lower limit specification to determine whether it is greater than the gain error lower limit specification.

[0154] Comparator 210 outputs an "H" level when the voltage according to the charge accumulated in capacitor 310 is equal to or greater than the voltage of the gain error lower limit specification. On the other hand, comparator 210 outputs an "L" level when the voltage according to the charge accumulated in capacitor 310 is less than the voltage of the gain error lower limit specification.

[0155] If the comparator 210 is at "H" level, it is determined as OK, and if it is at "L" level, it is determined as NG.

[0156] The reference voltage is set by adjusting the resistance value of the variable resistance element 404 . As an example, the reference voltage is set to Q / 2C×(2−gain error spec lower limit / 100×2).

[0157] The lower limit of the gain error specification is set to within -10%. In this case, (2 - lower limit of gain error specification / 100 x 2) is set to 1.8 times.

[0158] Specifically, as an example, by setting the resistance ratio of resistors R1 and R2 of the variable resistor element 404 to 4:5, the non-inverting amplifier 402 outputs an output voltage VO that is 1.8 times the input voltage VI. This setting makes it possible to set the reference voltage of the lower limit of the gain error specification to -10%.

[0159] Fig. 26 is a diagram for explaining a gain error spec upper limit test according to an embodiment. The gain error spec upper limit test will be explained with reference to Fig. 26. The switch 302 is turned on to connect the node N0 and the node N3. The switch 314 is turned on to connect the node N1 and the fixed voltage VSS.

[0160] Also, the switch 216 of the comparison circuit 200 is turned on to connect the node N3 to the node N5, and the switch 214 of the comparison circuit 200 is turned on to connect the node N4 to the node N6, while the other switches are turned off.

[0161] As a result, the input node N5 of the comparator 210 receives an input of a voltage according to the charge stored in the capacitor 310. In addition, the input node N4 of the comparator 210 is connected to the output node of the non-inverting amplifier 402.

[0162] The comparator 210 outputs an "H" level if the voltage of the input node N4 of the comparator 210 is higher than the voltage of the input node N5. The comparator 210 outputs an "L" level if the voltage of the input node N4 of the comparator 210 is lower than the voltage of the input node N5.

[0163] That is, the voltage according to the charge stored in the capacitor 310 is compared with the voltage of the gain error upper limit specification to determine whether it is smaller than the gain error upper limit specification.

[0164] Comparator 210 outputs an "H" level when the voltage of the gain error upper limit specification is equal to or greater than the voltage according to the charge accumulated in capacitor 310. On the other hand, comparator 210 outputs an "L" level when the voltage according to the charge accumulated in capacitor 310 is greater than the voltage of the gain error upper limit specification.

[0165] If the comparator 210 is at "H" level, it is determined as OK, and if it is at "L" level, it is determined as NG.

[0166] The reference voltage is set by adjusting the resistance value of the variable resistance element 404 . As an example, the reference voltage is set to Q / 2C×(2+gain error specification upper limit / 100×2).

[0167] The upper limit of the gain error specification is set to +10%. In this case, set (2 + lower limit of the gain error specification / 100 x 2) to 2.2 times.

[0168] Specifically, as an example, by setting the resistance ratio of resistors R1 and R2 of the variable resistor element 404 to 6:5, the non-inverting amplifier 402 outputs an output voltage VO that is 2.2 times the input voltage VI. This setting makes it possible to set the reference voltage of the upper limit of the gain error specification to +10%.

[0169] The gain error spec upper limit test and lower limit test only require the above test, and there is no need to perform the tests shifted by one code.

[0170] In this example, the 10-bit counter 7 and the current DAC 8 are both 10 bits, but this is not limiting and they can be set to different bits. For example, a 12-bit counter 7 and a 10-bit current DAC 8 may be used.

[0171] While the present disclosure has been specifically described above based on the embodiments, it goes without saying that the present disclosure is not limited to the embodiments and can be modified in various ways without departing from the spirit of the present disclosure. [Explanation of symbols]

[0172] 1 imaging device, 2 pixel array, 3 row selection circuit, 5 reference voltage generation circuit, 6 test circuit, 10 control circuit, 11 A / D converter, 12 signal processing circuit, 13 horizontal transfer circuit, 108 comparison unit, 112 latch, 200 comparison circuit, 210 comparator.

Claims

1. a digital-to-analog converter having a plurality of current cells; a test circuit electrically connected to the digital-to-analog converter for testing the digital-to-analog converter; The test circuit includes: a charge information holding circuit that holds a difference between a first charge according to a first current by at least one current cell among the plurality of current cells and a second charge according to a second current as differential charge information; a reference voltage generating circuit for generating a reference voltage to be compared; a comparison circuit that compares a determination voltage according to the differential charge information with the reference voltage and outputs a comparison result; The charge information holding circuit includes: a first capacitor having a first electrode and an opposing second electrode; a switch connected to the first electrode of the first capacitor and capable of switching a current path following the first current to a current path connected to a second electrode of the first capacitor and following the second current.

2. The semiconductor device of claim 1, wherein the test circuit changes the differential charge information stored in the first capacitor by adjusting the time for forming the current path between at least one of the plurality of current cells and the first capacitor.

3. The reference voltage generating circuit, A second capacitor; 2. The semiconductor device according to claim 1, further comprising a non-inverting amplifier circuit for amplifying a held voltage according to the charge held in said second capacitor to generate said reference voltage.

4. the non-inverting amplifier circuit includes a variable resistance element connected to an input node, 4. The semiconductor device according to claim 3, wherein the amplification factor is changed by adjusting the resistance value of said variable resistance element.

5. 2. The semiconductor device according to claim 1, wherein said digital-to-analog converter and said test circuit are formed within a single semiconductor chip.

6. An imaging element; An analog-to-digital converter for converting an analog signal from the imaging element into a digital signal, 2. The semiconductor device according to claim 1, wherein said analog-to-digital converter receives an input of a comparison signal from said digital-to-analog converter.

7. A method for controlling a semiconductor device including a digital-to-analog converter having a plurality of current cells and a test circuit electrically connected to the digital-to-analog converter for testing the digital-to-analog converter, comprising: storing a difference value between a first charge according to a first current by at least one current cell among the plurality of current cells and a second charge according to a second current as differential charge information; generating a reference voltage to be compared; comparing a determination voltage according to the differential charge information with the reference voltage and outputting a comparison result; A method for controlling a semiconductor device, wherein the holding step includes a step of switching a current path connected to a first electrode of a first capacitor and following the first current to a current path connected to a second electrode of the first capacitor and following the second current.

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