Inverter device and inverter control method

Abstract

In a situation in which a drive pulse is imparted to each of a plurality of inverters that are interconnected in parallel and electrically connected to a terminal block via output cables having dissimilar lengths, the ON-time of the drive pulse imparted to each inverter is adjusted according to the length of each output cable.

Description

[Technical field]

[0001] The present invention relates to an inverter device and an inverter control method. [Background technology]

[0002] In a power conversion device, multiple inverters are sometimes connected in parallel to increase capacity. In such a case, when a current called a cross current flows between the inverters, a phenomenon occurs in which the currents flowing through each inverter become unbalanced (hereinafter referred to as "current imbalance"). The cause of the cross current is the difference in output voltage caused by a shift in switching timing between the inverters connected in parallel. The shift in switching timing occurs due to the variation in characteristics of the semiconductor switch elements (power transistors, etc.) that make up the inverter, and the delay time variation of components on the signal path for driving the inverter. In addition, the life of an inverter tends to become shorter as the amount of current flowing through the inverter increases. For this reason, current imbalance in an inverter leads to variation in the life of the inverter.

[0003] Patent document 1 describes a power conversion device equipped with a control device that determines the cross current flow between inverters by applying a predetermined coordinate transformation to the detected value of the cross current between inverters, and controls the output voltage or output current of each converter or each inverter based on the cross current flow. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-58045 Summary of the Invention [Problem to be solved by the invention]

[0005] As one of the conventional techniques for suppressing cross current, a technique of lengthening the output wiring of an inverter to increase the wiring resistance is known. However, in this conventional technique, when the output wiring of each inverter is connected together to a terminal block, the length of the output wiring of the inverter closer to the terminal block must be matched to the length of the output wiring of the inverter farther from the terminal block. Therefore, when the number of inverters connected in parallel increases, the excess length of the output wiring of the inverter closer to the terminal block (the difference between the actual wiring length and the originally required wiring length) becomes significant, and the output wiring of the inverters does not fit well.

[0006] An object of the present invention is to provide an inverter device and an inverter control method that can suppress inverter current imbalance caused by cross currents even when the output wiring lengths of the inverters connected in parallel are different. [Means for solving the problem]

[0007] In order to solve the above problems, for example, the configurations described in the claims are adopted. The present application includes a number of means for solving the above problems, one of which is an inverter device including a number of inverters electrically connected to a terminal block via output wires of different lengths and connected in parallel with each other, and an inverter control unit that provides drive pulses to the inverters individually. The inverter control unit adjusts the on-time of the drive pulses provided to the inverters in accordance with the lengths of the output wires.

[0008] The present application also provides an inverter control method for controlling multiple inverters that are electrically connected to a terminal block via output wiring of different lengths and connected in parallel with each other, in which drive pulses are individually applied to the multiple inverters and the on-time of the drive pulses is adjusted according to the length of the output wiring. Effect of the Invention

[0009] According to the present invention, even if the output wiring lengths of the inverters connected in parallel are different, it is possible to suppress current imbalance in the inverters caused by cross currents. Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a configuration of an elevator device including an elevator drive circuit according to an embodiment. [Diagram 2] FIG. 2 is an external view of an inverter unit included in the power conversion unit. [Diagram 3] FIG. 1 is a schematic diagram showing an example of mounting four parallel inverter units on a control panel. [Figure 4] 1 is a block diagram showing a configuration example of an inverter device according to an embodiment; [Diagram 5] 13A and 13B are diagrams illustrating an example in which the on-time of a drive pulse is adjusted. [Figure 6] FIG. 13 is a diagram for explaining a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In this specification and the drawings, elements having substantially the same functions or configurations are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0012] <Elevator equipment configuration> FIG. 1 is a diagram showing the configuration of an elevator device including an elevator drive circuit according to an embodiment. As shown in FIG. 1, elevator drive circuit 10 is a circuit for driving motor 11 for moving an elevator up and down. Motor 11 is composed of a three-phase motor. Motor 11 is a drive source for rotating sheave 12. Main rope 13 is wound around sheave 12. One end of main rope 13 is connected to car 14. The other end of main rope 13 is connected to counterweight 15.

[0013] When the sheave 12 is rotated clockwise in Fig. 1 by the drive of the motor 11, the car 14 rises in accordance with the movement of the main rope 13. When the sheave 12 is rotated counterclockwise in Fig. 1 by the drive of the motor 11, the car 14 descends in accordance with the movement of the main rope 13. At that time, the counterweight 15 rises and falls in the opposite direction to the car 14.

[0014] <Elevator drive circuit configuration> The elevator drive circuit 10 includes a three-phase AC power supply 20, a power supply filter unit 21, and a power conversion device 22. The three-phase AC power supply 20 outputs three-phase (R phase, S phase, T phase) AC power of a constant frequency. The power supply filter unit 21 reduces noise in the AC power output from the three-phase AC power supply 20. The power conversion device 22 converts the AC power input from the three-phase AC power supply 20 via the power supply filter unit 21 into three-phase (U phase, V phase, W phase) AC power of a variable frequency and outputs it. The motor 11 has three input terminals corresponding to the U phase, V phase, and W phase.

[0015] The power conversion device 22 is configured by connecting a plurality of power conversion units 30-1, 30-2, ..., 30-N in parallel. The number of power conversion units connected in parallel can be set according to the load capacity of a motor or the like. Taking the elevator device according to this embodiment as an example, the total number of power conversion units connected in parallel (the value of N) is set according to the load capacity required to drive the motor 11.

[0016] Each of the power conversion units 30-1, 30-2, ..., 30-N has a common configuration. In the following description, when there is no need to distinguish between each of the power conversion units 30-1, 30-2, ..., 30-N, they will simply be referred to as "power conversion units 30."

[0017] <Power conversion unit configuration> The power conversion unit 30 includes a converter circuit section 31 and an inverter circuit section 32. The converter circuit section 31 converts three-phase AC power input from the three-phase AC power supply 20 via the power supply filter section 21 into DC power. The inverter circuit section 32 converts the DC power converted by the converter circuit section 31 into three-phase AC power.

[0018] The converter circuit section 31 and the inverter circuit section 32 basically have a common configuration, except that the timings at which the switching elements of each circuit section are turned on and off are different. Therefore, in this embodiment, only the configuration of the inverter circuit section 32 will be described. Note that the converter circuit section 31 and the inverter circuit section 32 may have different circuit configurations.

[0019] The inverter circuit section 32 includes six switching elements SW1 to SW6, and a smoothing capacitor C and resistor R. The capacitor C and resistor R are connected in parallel between the output lines of the converter circuit section 31, respectively.

[0020] Each of the switching elements SW1 to SW6 is composed of a power transistor such as an IGBT (Insulated Gate Bipolar Transistor). The six switching elements SW1 to SW6 constitute a three-phase bridge inverter. Two switching elements SW1 and SW2 are connected in series to constitute one inverter (arm). That is, in this embodiment, a 2-in-1 type inverter is adopted. Similarly, two switching elements SW3 and SW4 are connected in series to constitute one inverter, and two switching elements SW5 and SW6 are connected in series to constitute one inverter. In this embodiment, as an example, the two switching elements SW1 and SW2 generate U-phase AC power, the two switching elements SW3 and SW4 generate V-phase AC power, and the two switching elements SW5 and SW6 generate W-phase AC power.

[0021] One end of an output line 33 is connected between the two switching elements SW1 and SW2. Furthermore, one end of an output line 34 is connected between the two switching elements SW3 and SW4, and one end of an output line 35 is connected between the two switching elements SW5 and SW6. The other end of the output line 33 is connected to an input terminal for a U phase of the motor 11 via a reactor 36. Furthermore, the other end of the output line 34 is connected to an input terminal for a V phase of the motor 11 via a reactor 37, and the other end of the output line 35 is connected to an input terminal for a W phase of the motor 11 via a reactor 38.

[0022] In the power conversion unit 30 configured as above, the DC power supplied from the converter circuit section 31 to the inverter circuit section 32 is converted into three-phase AC power according to the timing of turning on and off each of the switching elements SW1 to SW6. Also, by connecting power conversion units 30 configured in this way in parallel, the capacity of the power conversion device 22 can be increased.

[0023] <Inverter unit appearance> FIG. 2 is an external view of an inverter unit included in the power conversion unit 30. As shown in FIG. 2 is hardware constituting the above-mentioned inverter circuit section 32. The inverter unit 40 includes a DC side bus bar 41 serving as an input terminal for DC power, a smoothing capacitor 42, three inverter sections 43, 44, and 45, a gate drive board 46, three AC side bus bars 47, 48, and 49 serving as output terminals for AC power, a cooler 50, three cooling fans 51, 52, and 53, and two handles 54 and 55.

[0024] The DC side bus bar 41 is composed of a positive bus bar and a negative bus bar. The DC power converted by the converter circuit unit 31 is input to the DC side bus bar 41. The smoothing capacitor 42 smoothes the DC power input through the DC side bus bar 41.

[0025] The inverter unit 43 is composed of the two switching elements SW1 and SW2 described above. The inverter unit 43 generates U-phase AC power from DC power input through the DC side bus bar 41. The inverter unit 44 is composed of the two switching elements SW3 and SW4 described above. The inverter unit 44 generates V-phase AC power from DC power input through the DC side bus bar 41. The inverter unit 45 is composed of the two switching elements SW5 and SW6 described above. The inverter unit 45 generates W-phase AC power from DC power input through the DC side bus bar 41.

[0026] The gate drive substrate 46 generates drive pulses for driving the three inverter units 43, 44, 45 described above, and provides these drive pulses to the respective inverter units 43, 44, 45 according to predetermined conditions. When the respective inverter units 43, 44, 45 are configured using power transistors such as IGBTs, the drive pulses are provided to the respective inverter units 43, 44, 45 as gate drive command pulses for driving the gates of the power transistors. For this reason, the switching elements SW1 and SW2 constituting the inverter unit 43 are turned on when the drive pulse provided to the inverter unit 43 from the gate drive substrate 46 rises, and turned off when the drive pulse falls. This also applies to the switching elements SW3 and SW4 constituting the inverter unit 44 and the switching elements SW5 and SW6 constituting the inverter unit 45.

[0027] The AC-side busbar 47 is a terminal for outputting the U-phase AC power generated by the inverter unit 43. The AC-side busbar 48 is a terminal for outputting the V-phase AC power generated by the inverter unit 44, and the AC-side busbar 49 is a terminal for outputting the W-phase AC power generated by the inverter unit 45.

[0028] Cooler 50 is a device for cooling inverter units 43, 44, and 45. Cooler 50 is configured using, for example, a heat sink. Cooling fan 51 is a fan for cooling inverter unit 43. Cooling fan 52 is a fan for cooling inverter unit 44, and cooling fan 53 is a fan for cooling inverter unit 45. Handles 54 and 55 are parts for making it easier for an operator to hold inverter unit 40 when mounting inverter unit 40 on control panel 60 (see FIG. 3).

[0029] FIG. 3 is a schematic diagram showing an example in which four parallel inverter units are mounted on a control panel. As shown in FIG. 3, four inverter units 40-1, 40-2, 40-3, and 40-4 and a terminal block 70 are mounted on a control panel 60. The four inverter units 40-1, 40-2, 40-3, and 40-4 are electrically and mechanically connected in parallel. Each of the inverter units 40-1, 40-2, 40-3, and 40-4 has the same configuration as the inverter unit 40 shown in FIG. 2. That is, the four inverter units 40-1, 40-2, 40-3, and 40-4 have a common configuration. Therefore, when four inverter units 40 shown in FIG. 2 are prepared, each inverter unit 40 can be installed at any position among the first parallel, second parallel, third parallel, and fourth parallel.

[0030] 3, for ease of explanation, the AC bus bar 47 of the inverter unit 40 (40-1) installed in the first parallel arrangement is labeled with the reference symbol 47-1, and the AC bus bar 47 of the inverter unit 40 (40-2) installed in the second parallel arrangement is labeled with the reference symbol 47-2. Similarly, the AC bus bar 47 of the inverter unit 40 (40-3) installed in the third parallel arrangement is labeled with the reference symbol 47-3, and the AC bus bar 47 of the inverter unit 40 (40-4) installed in the fourth parallel arrangement is labeled with the reference symbol 47-4.

[0031] The terminal block 70 has a U-phase wiring connection portion 71, a V-phase wiring connection portion 72, and a W-phase wiring connection portion 73. The U-phase wiring connection portion 71 is provided with four connection terminals according to the number of parallel inverter units 40 (four parallel inverter units in the example shown in FIG. 3). This also applies to the V-phase wiring connection portion 72 and the W-phase wiring connection portion 73. The output wirings 61, 62, 63, and 64 are made of coated electric wires or the like in which a conductor is coated with an insulator. The output wirings 61, 62, 63, and 64 may be connected after the four inverter units 40 are mounted on the control panel 60 so that the four inverter units 40 can be installed at any positions as described above.

[0032] One end of output wiring 61 is connected to AC side bus bar 47-1 of inverter unit 40-1. Output wiring 61 is a wiring for outputting U-phase AC power generated by inverter section 43 (see FIG. 2) of inverter unit 40-1. The other end of output wiring 61 is connected to a connection terminal of wiring connection section 71 for U-phase.

[0033] One end of output wiring 62 is connected to AC side bus bar 47-2 of inverter unit 40-2. Output wiring 62 is wiring for outputting U-phase AC power generated by inverter section 43 of inverter unit 40-2. The other end of output wiring 62 is connected to a connection terminal of wiring connection section 71 for U-phase.

[0034] One end of output wiring 63 is connected to AC side bus bar 47-3 of inverter unit 40-3. Output wiring 63 is wiring for outputting U-phase AC power generated by inverter section 43 of inverter unit 40-3. The other end of output wiring 63 is connected to a connection terminal of wiring connection section 71 for U-phase.

[0035] One end of output wiring 64 is connected to AC side bus bar 47-4 of inverter unit 40-4. Output wiring 64 is wiring for outputting U-phase AC power generated by inverter section 43 of inverter unit 40-4. The other end of output wiring 64 is connected to a connection terminal of wiring connection section 71 for U-phase.

[0036] The inverter section 43 of the inverter unit 40-1, the inverter section 43 of the inverter unit 40-2, the inverter section 43 of the inverter unit 40-3, and the inverter section 43 of the inverter unit 40-4 are connected in parallel to each other via output wirings 61, 62, 63, and 64, respectively.

[0037] Here, comparing the installation positions of the inverter units 40-1, 40-2, 40-3, and 40-4 based on the position of the terminal block 70, the inverter unit 40-1 is installed at the farthest position from the terminal block 70, and the inverter unit 40-4 is installed at the closest position from the terminal block 70. For this reason, when the length of the output wiring 61 is L1 (mm), the length of the output wiring 62 is L2 (mm), the length of the output wiring 63 is L3 (mm), and the length of the output wiring 64 is L4 (mm), the relationship is L1>L2>L3>L4. In other words, the inverter parts 43 of the inverter units 40-1, 40-2, 40-3, and 40-4 are electrically connected to the terminal block 70 via the output wirings 61, 62, 63, and 64 of different lengths.

[0038] 3, the output wiring for outputting V-phase AC power and the output wiring for outputting W-phase AC power are omitted. The output wiring for outputting V-phase AC power is a wiring that electrically connects AC side bus bar 48, which is the output terminal of inverter section 44 of each inverter unit 40-1, 40-2, 40-3, 40-4, to the connection terminal of V-phase wiring connection section 72. The output wiring for outputting W-phase AC power is a wiring that electrically connects AC side bus bar 49, which is the output terminal of inverter section 45 of each inverter unit 40-1, 40-2, 40-3, 40-4, to the connection terminal of W-phase wiring connection section 73.

[0039] FIG. 4 is a block diagram illustrating a configuration example of an inverter device according to the embodiment. 4, the inverter device 75 includes the above-mentioned inverter units 40-1, 40-2, 40-3, and 40-4, and an inverter control unit 76. The inverter control unit 76 controls the driving of the inverter units 43, 44, and 45 in each of the inverter units 40-1, 40-2, 40-3, and 40-4 by individually providing drive pulses to the inverter units 43, 44, and 45 of the inverter units 40-1, 40-2, 40-3, and 40-4. For convenience of explanation, it is assumed here that a drive pulse φ1 is provided to the inverter unit 43 of the inverter unit 40-1, a drive pulse φ2 is provided to the inverter unit 43 of the inverter unit 40-2, a drive pulse φ3 is provided to the inverter unit 43 of the inverter unit 40-3, and a drive pulse φ4 is provided to the inverter unit 43 of the inverter unit 40-4.

[0040] The inverter control unit 76 includes a pulse generating unit 77 and a delay processing unit 78. The pulse generating unit 77 is a unit that generates a basic drive pulse. The delay processing unit 78 is a unit that performs processing to delay the rising timing and falling timing of the drive pulse generated by the pulse generating unit 77. Specifically, as shown in FIG. 5, the delay processing unit 78 performs processing to delay the rising timing of each of the drive pulses φ2, φ3, and φ4 by a predetermined time relative to the rising timing of the drive pulse φ1, and to delay the falling timing of each of the drive pulses φ3, φ2, and φ1 by a predetermined time relative to the falling timing of the drive pulse φ4.

[0041] In this way, the delay processing unit 78 delays the rising and falling timings of the drive pulses φ1, φ2, φ3, φ4, so that the on-times of the drive pulses φ1, φ2, φ3, φ4 provided to the inverter section 43 of each of the inverter units 40-1, 40-2, 40-3, 40-4 are changed. That is, the delay processing unit 78 adjusts the on-times of the drive pulses φ1, φ2, φ3, φ4 provided to the inverter section 43 of each of the inverter units 40-1, 40-2, 40-3, 40-4 in accordance with the lengths of the output wirings 61, 62, 63, 64. In this case, as a preferred embodiment, the delay processing unit 78 adjusts the on-times of the drive pulses φ1, φ2, φ3, φ4 provided to the inverter section 43 of each of the inverter units 40-1, 40-2, 40-3, 40-4 so that the on-times become shorter as the lengths of the output wirings 61, 62, 63, 64 become shorter.

[0042] The inverter control unit 76 may be realized by software or by hardware. When the inverter control unit 76 is realized by software, a program for inverter control may be stored in a ROM in a computer device such as a CPU, ROM, and RAM constituting the inverter control unit 76, and the CPU may read the program from the ROM to the RAM and execute it. When the inverter control unit 76 is realized by hardware, for example, a dial (not shown) having channels corresponding to the number of parallel connections of inverters may be added to the inverter unit 40, and the ON time of the drive pulses φ1, φ2, φ3, and φ4 may be adjusted by appropriately rotating the dial.

[0043] Here, a comparative example for comparison with this embodiment will be described with reference to FIG. In FIG. 6, elements corresponding to those shown in FIG. 3 are denoted by the same reference numerals. As can be seen by comparing FIG. 3 and FIG. 6, the difference between this embodiment and the comparative embodiment is the length of the output wirings 61, 62, 63, 64. Specifically, in this embodiment, the lengths of the output wirings 61, 62, 63, 64 are changed according to the difference in the distance from the terminal block 70 to the output terminals (47-1, 47-2, 47-3, 47-4) of the inverter units 40-1, 40-2, 40-3, 40-4. In contrast, in the comparative embodiment, the lengths of the output wirings 61, 62, 63, 64 are made uniform regardless of the difference in the distance from the terminal block 70 to the output terminals (47-1, 47-2, 47-3, 47-4) of the inverter units 40-1, 40-2, 40-3, 40-4. In other words, in the comparative embodiment, the length of the output wirings 61 connected to the output terminal of the inverter unit 40-1, which is the furthest from the terminal block 70, is made uniform to the length of the other output wirings 62, 63, 64.

[0044] When the lengths of the output wirings 61, 62, 63, and 64 are unified as in the comparative example, the wiring resistance of the output wirings 62, 63, and 64 can be increased to the same level as the wiring resistance of the output wiring 61, and the wiring resistance of each of the output wirings 61, 62, 63, and 64 can be unified. This makes it possible to suppress cross currents. However, in the comparative example, the output wirings 62, 63, and 64 have excess length portions 65, and the excess length portions 65 are bundled together in the control panel 60, resulting in a bundle of wiring. In addition, when the number of parallel connections of inverters increases, the output wirings become less compact, and in some cases, it becomes difficult to fit all the output wirings (including the excess length portions) in the control panel 60.

[0045] On the other hand, in this embodiment, the lengths of the output wirings 61, 62, 63, and 64 are changed according to the difference in the distance from the terminal block 70 to the output terminals of the inverter units 40-1, 40-2, 40-3, and 40-4. Therefore, it is not necessary to provide extra length portions in the output wirings 62, 63, and 64. Therefore, according to this embodiment, the output wirings 61, 62, 63, and 64 can be neatly stored in the control panel 60.

[0046] In this embodiment, the relationship between the length L1 of the output wiring 61, the length L2 of the output wiring 62, the length L3 of the output wiring 63, and the length L4 of the output wiring 64 is L1>L2>L3>L4. For this reason, the delay processing unit 78 adjusts the on-time T2 of the drive pulse φ2 to be shorter than the on-time T1 of the drive pulse φ1, as shown in FIG. 5. The delay processing unit 78 also adjusts the on-time T3 of the drive pulse φ3 to be shorter than the on-time T2 of the drive pulse φ2, and adjusts the on-time T4 of the drive pulse φ4 to be shorter than the on-time T3 of the drive pulse φ3. The on-times T1, T2, T3, and T4 of the drive pulses φ1, φ2, φ3, and φ4 and the delay times for adjusting them are set based on the lengths, conductor cross-sectional areas, and conductor resistivities of the output wirings 61, 62, 63, and 64.

[0047] In this way, by adjusting the on-times T1, T2, T3, and T4 of the drive pulses φ1, φ2, φ3, and φ4, it is possible to suppress the current imbalance of the inverters caused by cross currents even if the lengths of the output wirings 61, 62, 63, and 64 connected to the inverter parts 43 of the inverter units 40-1, 40-2, 40-3, and 40-4 are different. The reason for this will be explained below.

[0048] First, in the control panel 60 shown in FIG. 3, comparing the inverter unit 40-1 and the inverter unit 40-2, the inverter unit 40-1 is installed at a position farther from the terminal block 70 than the inverter unit 40-2. Therefore, the length of the output wiring 61 connected to the inverter unit 40-1 is longer than the length of the output wiring 62 connected to the inverter unit 40-2. Therefore, the wiring resistance of the inverter unit 40-1 having the long output wiring 61 is higher than the wiring resistance of the inverter unit 40-2. Therefore, the cross current is less likely to flow in the inverter section 43 of the inverter unit 40-1 that is far from the terminal block 70. Therefore, in the inverter section 43 of the inverter unit 40-1 that is far from the terminal block 70, the cross current can be suppressed even if the ON time T1 of the drive pulse φ1 is lengthened.

[0049] In contrast, the wiring resistance of inverter unit 40-2, which has a shorter output wiring 62, is lower than the wiring resistance of inverter unit 40-1. Therefore, cross currents are more likely to flow through inverter section 43 of inverter unit 40-2, which is closer to terminal block 70. However, the on-time T2 of drive pulse φ2 applied to inverter section 43 of inverter unit 40-2 is shorter than the on-time T1 of drive pulse φ1 applied to inverter section 43 of inverter unit 40-1. Therefore, the increase in current, including cross currents, flowing through inverter section 43 of inverter unit 40-2 can be canceled out by the difference (T1-T2) between on-times T1, T2 of drive pulses φ1, φ2.

[0050] As a result, current can be made to flow evenly through inverter section 43 of inverter unit 40-1 and inverter section 43 of inverter unit 40-2. This also applies to current flowing through inverter section 44 of inverter unit 40-1 and inverter section 44 of inverter unit 40-2, and current flowing through inverter section 45 of inverter unit 40-1 and inverter section 45 of inverter unit 40-2. The above-described relationship between inverter unit 40-1 and inverter unit 40-2 also holds true between inverter unit 40-2 and inverter unit 40-3, and between inverter unit 40-3 and inverter unit 40-4.

[0051] For the above reasons, in the four parallel inverter units 40-1, 40-2, 40-3, and 40-4, inverter current imbalance caused by cross currents can be suppressed. Therefore, according to this embodiment, it is possible to suppress variations in inverter life.

[0052] Furthermore, by adjusting the on-times T1, T2, T3, T4 of the drive pulses φ1, φ2, φ3, φ4 given to the inverter sections 43 of each inverter unit 40-1, 40-2, 40-3, 40-4 so that they become shorter as the lengths of the output wirings 61, 62, 63, 64 become shorter, the current imbalance of the inverter caused by cross currents can be more effectively suppressed.

[0053] The present invention is not limited to the above-described embodiment, but includes various modified examples. For example, the above-described embodiment has been described in detail to facilitate understanding of the contents of the present invention, but the present invention is not necessarily limited to having all the configurations described in the above-described embodiment. It is also possible to replace a part of the configuration of one embodiment with the configuration of another embodiment. It is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to delete a part of the configuration of each embodiment, add another configuration, or replace it with another configuration.

[0054] For example, the inverter controlled by inverter control unit 76 is not limited to the 2-in-1 type shown in FIG. 1, but may be of other types such as a 1-in-1 type or a 6-in-1 type.

[0055] In addition, the inverter that is controlled by the inverter control unit 76 may be unitized like the inverter units 43, 44, and 45 provided in the inverter unit 40 described above, or may be an independent configuration without being unitized.

[0056] Furthermore, the converter circuit section 31 is not limited to a configuration using semiconductor switching elements such as transistors as shown in FIG. 1, but may be a configuration using semiconductor elements such as diodes.

[0057] Furthermore, the inverter device according to this embodiment is not limited to being used as the power conversion device 22 for supplying AC power to the motor 11 for raising and lowering an elevator, but can also be widely used as a device for supplying AC power to loads such as motors used in various home appliances and industrial machines. [Explanation of symbols]

[0058] 43, 44, 45... inverter section (inverter), 61, 62, 63, 64... output wiring, 70... terminal block, 75... inverter device, 76... inverter control section, T1, T2, T3, T4... ON time, φ1, φ2, φ3, φ4... drive pulse

Claims

1. A terminal block for outputting AC power to a load; a plurality of inverter units each having a plurality of inverters electrically connected to the terminal block via output wires of different lengths and connected in parallel with each other; an inverter control unit that individually supplies drive pulses to the plurality of inverters; In an inverter device comprising: The inverter control unit adjusts an on-time of the drive pulse applied to the inverters so that the on-time becomes shorter as the length of the output wiring becomes shorter. Inverter device.

2. The inverter control unit sets an on-time of the drive pulse and a delay time for adjusting the on-time based on at least a length of the output wiring, a conductor cross-sectional area, and a conductor resistivity. The inverter device according to claim 1 .

3. An inverter control method for controlling a plurality of inverter units having a terminal block connected to a load side and a plurality of inverters electrically connected to the terminal block via output wiring of different lengths and connected in parallel with each other, comprising: A drive pulse is individually applied to the plurality of inverters, and the ON time of the drive pulse is adjusted so as to become shorter as the length of the output wiring is shorter. Inverter control method.

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