Semiconductor integrated circuit device

Abstract

Provided is a layout structure of a capacitive element that uses a forksheet FET. A capacitive structure constituting the capacitive element comprises: a transistor (N11) having a nanosheet (21a) that extends in the X direction, and gate wiring (31a) that extends in the Y direction and surrounds the outer perimeter of the nanosheet (21a); and a transistor (N12) having a nanosheet (21c) that extends in the X direction, and gate wiring (32a) that extends in the Y direction and surrounds the outer perimeter of the nanosheet (21c). The surface on the nanosheet (21c) side of the nanosheet (21a) is exposed from the gate wiring (31a), and the surface on the nanosheet (21a) side of the nanosheet (21c) is exposed from the gate wiring (32a).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor integrated circuit device including a nanosheet (nanowire) FET (Field Effect Transistor). [Background technology]

[0002] In semiconductor integrated circuit devices, the breakdown voltage of transistors tends to decrease with the miniaturization of processes. On the other hand, some interface sections that input and output signals to and from the outside of the device require a high voltage that exceeds the breakdown voltage of the transistors, depending on their specifications, etc.

[0003] Furthermore, one of the basic elements constituting a semiconductor integrated circuit is a capacitor, and in some semiconductor integrated circuit devices, the capacitor is formed using a transistor.

[0004] Furthermore, transistors, which are the basic building blocks of LSIs, have achieved increased integration density, reduced operating voltages, and increased operating speeds through the reduction of gate lengths (scaling). In recent years, however, excessive scaling has caused problems with off-current and the resulting dramatic increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional one. One such transistor that has attracted attention is the nanosheet (nanowire) FET.

[0005] Patent Document 1 discloses a high-voltage capacitance element configured by connecting transistors in series.

[0006] Non-Patent Documents 1 and 2 disclose layouts of SRAM memory cells and standard cells using nanosheet FETs with fork-shaped gate electrodes. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 8-306870 [Non-patent literature]

[0008] [Non-Patent Document 1] P. Weckx et al., “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm”, 2017 IEEE International Electron Devices Meeting (IEDM), December 2017, IEDM17-505~508 [Non-Patent Document 2] P. Weckx et al., "Novel forksheet device architecture as ultimate logic scaling device towards 2nm", 2019 IEEE International Electron Devices Meeting (IEDM), December 2019, IEDM19-871~874 Summary of the Invention [Problem to be solved by the invention]

[0009] In this specification, a nanosheet FET having a fork-shaped gate electrode is referred to as a fork sheet FET, following the description in Non-Patent Document 1.

[0010] However, up to now, no study has been done on the layout structure of a high-voltage capacitor using a fork sheet FET.

[0011] An object of the present disclosure is to provide a layout structure of a capacitive element having high withstand voltage using a fork sheet FET. [Means for solving the problem]

[0012] In a first aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a capacitive element, the capacitive element including at least one capacitive structure provided between a first node and a second node, the capacitive structure including a first transistor having a first nanosheet extending in a first direction, a first gate wiring extending in a second direction perpendicular to the first direction and formed to surround an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions, a second nanosheet extending in the first direction, and a first gate wiring extending in the second direction perpendicular to the first and second directions. and a second transistor having a second gate wiring formed to surround the outer periphery of the nanosheet in the second and third directions, wherein the first and second transistors are adjacent in the second direction, at least one of the nodes is connected to each other, the first nanosheet and the second nanosheet face each other in the second direction, the surface of the first nanosheet facing the second nanosheet is exposed from the first gate wiring, and the surface of the second nanosheet facing the first nanosheet is exposed from the second gate wiring.

[0013] According to this embodiment, the capacitive structure constituting the capacitive element includes a first transistor having a first nanosheet extending in a first direction and a first gate wiring extending in a second direction and surrounding the periphery of the first nanosheet, and a second transistor having a second nanosheet extending in the first direction and a second gate wiring extending in the second direction and surrounding the periphery of the second nanosheet. The first and second transistors are adjacent to each other in the second direction, and at least one of the nodes is connected to each other. The first nanosheet and the second nanosheet face each other in the second direction, and the surface of the first nanosheet facing the second nanosheet is exposed from the first gate wiring, and the surface of the second nanosheet facing the first nanosheet is exposed from the second gate wiring. This makes it possible to reduce the distance between the first nanosheet and the second nanosheet, which is necessary to separate the gate of the first transistor from the gate of the second transistor. Therefore, the size of the capacitive element in the second direction can be reduced, and the layout structure of a capacitive element having a high breakdown voltage using a fork sheet FET can be realized in a small area.

[0014] In a second aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a capacitive element, the capacitive element including at least one capacitive structure provided between a first node and a second node, the capacitive structure including: a first transistor having a first nanosheet extending in a first direction and a first gate wiring extending in a second direction perpendicular to the first direction and formed to surround an outer periphery of the first nanosheet in the second direction and a third direction perpendicular to the first and second directions; and a second transistor having a second nanosheet extending in the first direction and a second gate wiring extending in the second direction and formed to surround an outer periphery of the second nanosheet in the second and third directions, the first and second transistors being adjacent to each other in the first direction and one of the nodes being connected to each other, a first side surface of the first nanosheet in the second direction being exposed from the first gate wiring, and a first side surface of the second nanosheet in the second direction being exposed from the second gate wiring.

[0015] According to this embodiment, the capacitive structure constituting the capacitive element includes a first transistor having a first nanosheet extending in a first direction and a first gate wiring extending in a second direction and surrounding the periphery of the first nanosheet, and a second transistor having a second nanosheet extending in the first direction and a second gate wiring extending in the second direction and surrounding the periphery of the second nanosheet. The first and second transistors are adjacent to each other in the first direction, and one of the nodes is connected to each other. The first side surface of the first nanosheet in the second direction is exposed from the first gate wiring, and the same first side surface of the second nanosheet in the second direction is exposed from the second gate wiring. This makes it possible to reduce the distance between the capacitive structure and another capacitive structure adjacent to the first side in the second direction. Therefore, the size of the capacitive element in the second direction can be reduced, so that a layout structure of a capacitive element having a high breakdown voltage using a fork sheet FET can be realized in a small area.

[0016] A third aspect of the present disclosure provides a semiconductor integrated circuit device including a capacitive element, the capacitive element including at least one capacitive structure provided between a first node and a second node, the capacitive structure including a first transistor having a first nanosheet extending in a first direction and a second transistor having a second nanosheet extending in the first direction, the first and second transistors being adjacent to each other in a second direction perpendicular to the first direction, a first gate wiring extending in the second direction being formed so as to surround the periphery of the first and second nanosheets in the second direction and in a third direction perpendicular to the first and second directions, and a surface of the second nanosheet opposite the first nanosheet in the second direction is exposed from the first gate wiring.

[0017] According to this embodiment, the capacitive structure constituting the capacitive element includes a first transistor having a first nanosheet extending in a first direction and a second transistor having a second nanosheet extending in the first direction. The first and second transistors are adjacent to each other in the second direction, and a first gate wiring extending in the second direction is formed so as to surround the periphery of the first and second nanosheets. The surface of the second nanosheet opposite to the first nanosheet in the second direction is exposed from the first gate wiring. This makes it possible to reduce the distance between the capacitive structure and another capacitive structure adjacent to the second transistor side in the second direction. Therefore, the size of the capacitive element in the second direction can be reduced, and therefore a layout structure of a capacitive element having a high breakdown voltage using a fork sheet FET can be realized in a small area. Effect of the Invention

[0018] According to the present disclosure, a capacitive element having high breakdown voltage can be realized by using a fork sheet FET. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a plan view showing an example of a layout structure of a capacitive element according to a first embodiment; [Diagram 2] (a) and (b) are cross-sectional views in the vertical direction in plan view of FIG. [Diagram 3] Circuit diagram of the capacitance element shown in Figs. 1 and 2 [Figure 4] FIG. 11 is a plan view showing an example of a layout structure of a capacitive element according to a modification of the first embodiment; [Diagram 5] Circuit diagram of the capacitance element shown in Figure 4 [Figure 6] FIG. 11 is a plan view showing an example of a layout structure of a capacitive element according to a second embodiment; [Figure 7] 6 is a cross-sectional view in the vertical direction in plan view of FIG. [Figure 8] Circuit diagram of the capacitance element shown in Figures 6 and 7 [Figure 9] FIG. 13 is a plan view showing an example of a layout structure of a capacitive element according to a third embodiment; [Figure 10] Circuit diagram of the capacitance element shown in Figure 9 [Figure 11] FIG. 13 is a plan view showing an example of a layout structure of a capacitive element according to a modification of the third embodiment; [Figure 12] Circuit diagram of the capacitance element shown in Figure 11 [Figure 13] 1A and 1B are diagrams showing the basic structure of a fork-sheet FET, where (a) is a plan view and (b) is a cross-sectional view. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments will be described with reference to the drawings. In the following embodiments, the semiconductor integrated circuit device is assumed to include a nanosheet FET (Field Effect Transistor). A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows. The nanosheet is formed of, for example, silicon. In the semiconductor integrated circuit device, a part of the nanosheet FET is assumed to be a fork sheet FET having a fork-shaped gate electrode.

[0021] In addition, in the present disclosure, the semiconductor layer portions formed on both ends of the nanosheet and constituting the terminals that serve as the source or drain of the nanosheet FET are referred to as "pads".

[0022] First, the basic structure of the fork seat FET will be described.

[0023] 13 shows the basic structure of a fork-sheet FET, where (a) is a plan view and (b) is a cross-sectional view taken along line Y-Y' in (a). In the basic structure of FIG. 13, two transistors TR1 and TR2 are arranged side by side with a gap S therebetween in the Y direction. A gate wiring 531 serving as the gate of transistor TR1 and a gate wiring 532 serving as the gate of transistor TR2 both extend in the Y direction and are arranged at the same position in the X direction.

[0024] A channel portion 521 that becomes the channel region of the transistor TR1 and a channel portion 526 that becomes the channel region of the transistor TR2 are composed of nanosheets. In FIG. 13, the channel portions 521 and 526 are each composed of a nanosheet having a three-sheet structure that overlaps in a plan view. Pads 522a and 522b that become the source region or drain region of the transistor TR1 are formed on both sides of the channel portion 521 in the X direction. Pads 527a and 527b that become the source region or drain region of the transistor TR2 are formed on both sides of the channel portion 526 in the X direction. The pads 522a and 522b are formed by epitaxial growth from the nanosheet that constitutes the channel portion 521. The pads 527a and 527b are formed by epitaxial growth from the nanosheet that constitutes the channel portion 526.

[0025] The gate wiring 531 surrounds the outer periphery in the Y direction and Z direction of the channel section 521 made of the nanosheet via a gate insulating film (not shown). However, the surface of the nanosheet constituting the channel section 521 on the side of the transistor TR2 in the Y direction is not covered by the gate wiring 531 and is exposed from the gate wiring 531. That is, in the cross-sectional view of FIG. 13(b), the gate wiring 531 does not cover the right side of the nanosheet constituting the channel section 521 in the drawing, but covers the upper side, left side, and lower side in the drawing. The gate wiring 531 overlaps the nanosheet constituting the channel section 521 on the opposite side of the transistor TR2 in the Y direction by a length OL.

[0026] The gate wiring 532 surrounds the outer periphery in the Y direction and Z direction of the channel section 526 made of the nanosheet via a gate insulating film (not shown). However, the surface of the nanosheet constituting the channel section 526 on the side of the transistor TR1 in the Y direction is not covered by the gate wiring 532 and is exposed from the gate wiring 532. That is, in the cross-sectional view of FIG. 13(b), the gate wiring 532 does not cover the left side of the nanosheet constituting the channel section 526 in the drawing, but covers the upper side, right side, and lower side in the drawing. The gate wiring 532 overlaps the nanosheet constituting the channel section 526 on the opposite side of the transistor TR1 in the Y direction by a length OL.

[0027] If the width (size in the Y direction) of each nanosheet is W and its height (size in the Z direction) is H, then the effective gate width Weff is Weff=2×W+H Since the channel portions 521 and 526 of the transistors TR1 and TR2 are formed of three nanosheets, the effective gate widths of the transistors TR1 and TR2 are 3×(2×W+H) It becomes.

[0028] 13, the gate wiring 531 does not overlap the nanosheet constituting the channel portion 521 on the side of the transistor TR2 in the Y direction. Also, the gate wiring 532 does not overlap the nanosheet constituting the channel portion 526 on the side of the transistor TR1 in the Y direction. This allows the transistors TR1 and TR2 to be closer to each other, thereby realizing a smaller area.

[0029] The number of nanosheets constituting the channel portion of the transistor is not limited to three. That is, the nanosheet may be composed of a single sheet structure, or may be composed of a plurality of sheets overlapping in a plan view. In addition, in FIG. 13(b), the cross-sectional shape of the nanosheet is illustrated as a rectangle, but is not limited thereto, and the cross-sectional shape of the nanosheet may be, for example, a square, a circle, an ellipse, or the like.

[0030] Furthermore, a semiconductor integrated circuit device may contain a mixture of fork-sheet FETs and nanosheet FETs in which the gate wiring surrounds the entire periphery of the nanosheet.

[0031] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In addition, in this specification, expressions such as "same wiring width" that mean the width is the same, include the range of manufacturing variations.

[0032] In addition, in this specification, the source and drain of a transistor are appropriately referred to as a "node" of the transistor. In other words, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor.

[0033] (First embodiment) 1 and 2 are diagrams showing an example of a layout structure of a capacitive element according to the first embodiment, in which Fig. 1 is a plan view, and Figs. 2(a) and 2(b) are cross-sectional views in the vertical direction in a plan view. Fig. 2(a) is a cross-section along line Y1-Y1', and Fig. 2(b) is a cross-section along line Y2-Y2'.

[0034] In the following description, in plan views such as FIG. 1, the horizontal direction on the drawing is the X direction (corresponding to the first direction), the vertical direction on the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the third direction).

[0035] Fig. 3 is a circuit diagram showing the configuration of the capacitive element shown in Fig. 1 and Fig. 2. The semiconductor integrated circuit device according to this embodiment includes the capacitive element shown in Fig. 3. For example, a signal is applied to nodes IN1 and IN2. Alternatively, nodes IN1 and IN2 are connected to a power supply line. In this case, the capacitive element functions as an inter-power supply capacitance. The same applies to the capacitive elements shown hereinafter.

[0036] The capacitive element in FIG. 3 is connected to two nodes IN1. N-conductivity type transistors N11, N12, N13, and N14 are arranged between one node IN1 and node IN2. The gates of the transistors N11 and N13 are connected to the node IN1. The gates of the transistors N12 and N14 are connected to the node IN2. Both nodes of the transistors N11 and N12 are connected to each other. Both nodes of the transistors N13 and N14 are connected to each other. The transistors N11 and N13 share one node, and the transistors N12 and N14 share one node.

[0037] Between the other node IN1 and node IN2, N-conductivity type transistors N15, N16, N17, and N18 are arranged. The connection relationship of the transistors N15 to N18 is similar to the connection relationship of the transistors N11 to N14, and the details thereof are omitted here.

[0038] 3, the voltage applied to the transistors N11 to N14 and N15 to N18 is half the voltage between the nodes IN1 and IN2, so that a voltage higher than the withstand voltage of the transistors N11 to N14 and N15 to N18 can be applied to the capacitive element.

[0039] The capacitive element in Fig. 3 has four capacitive structures, each made up of two transistors whose sources and drains are connected to each other, provided between nodes IN1 and IN2. That is, the capacitive element in Fig. 3 includes a capacitive structure made up of transistors N11 and N12, a capacitive structure made up of transistors N13 and N14, a capacitive structure made up of transistors N15 and N16, and a capacitive structure made up of transistors N17 and N18.

[0040] As shown in Fig. 1, N-type transistors N11 to N18 are arranged in two rows in the X direction and four rows in the Y direction. That is, transistors N11 and N13 are arranged in the X direction, transistors N12 and N14 are arranged in the X direction, transistors N15 and N17 are arranged in the X direction, and transistors N16 and N18 are arranged in the X direction. Transistors N11, N12, N15, and N16 are arranged in a row in the Y direction. Transistors N13, N14, N17, and N18 are arranged in a row in the Y direction.

[0041] The transistors N11 to N14 each have a nanosheet 21a, 21c, 21b, or 21d, which is made up of three overlapping sheets in a planar view, as a channel portion. The transistors N15 to N18 each have a nanosheet 26a, 26c, 26b, or 26d, which is made up of three overlapping sheets in a planar view, as a channel portion. That is, the transistors N11 to N14 and N15 to N18 are nanosheet FETs.

[0042] As shown in FIG. 1, pads 22a, 22b, and 22c made of a semiconductor layer of an integral structure connected to the three sheet structures are formed on the left side of the nanosheet 21a, between the nanosheets 21a and 21b, and on the right side of the nanosheet 21b. The pads 22a and 22b become the source region and drain region of the transistor N11. The pads 22b and 22c become the source region and drain region of the transistor N13. Pads 22d, 22e, and 22f made of a semiconductor layer of an integral structure connected to the three sheet structures are formed on the left side of the nanosheet 21c, between the nanosheets 21c and 21d, and on the right side of the nanosheet 21d. The pads 22d and 22e become the source region and drain region of the transistor N12. The pads 22e and 22f become the source region and drain region of the transistor N14.

[0043] Pads 27a, 27b, and 27c made of a semiconductor layer of an integral structure connected to the three-sheet structure are formed on the left side of the nanosheet 26a, between the nanosheets 26a and 26b, and on the right side of the nanosheet 26b. The pads 27a and 27b become the source region and drain region of the transistor N15. The pads 27b and 27c become the source region and drain region of the transistor N17. Pads 27d, 27e, and 27f made of a semiconductor layer of an integral structure connected to the three-sheet structure are formed on the left side of the nanosheet 26c, between the nanosheets 26c and 26d, and on the right side of the nanosheet 26d. The pads 27d and 27e become the source region and drain region of the transistor N16. The pads 27e and 27f become the source region and drain region of the transistor N18.

[0044] Gate wirings 31a and 31b extending in parallel in the Y direction are formed in the region of the transistors N11 and N13. Gate wirings 32a and 32b extending in parallel in the Y direction are formed in the region of the transistors N12, N14, N15, and N17. Gate wirings 33a and 33b extending in parallel in the Y direction are formed in the region of the transistors N16 and N18. The gate wirings 31a, 32a, and 33a are aligned in a line in the Y direction. The gate wirings 31b, 32b, and 33b are aligned in a line in the Y direction. Dummy gate wirings 36a and 36b are formed on both sides of the gate wirings 31a and 31b in the X direction. Dummy gate wirings 36c and 36d are formed on both sides of the gate wirings 32a and 32b in the X direction. Dummy gate wirings 36e and 36f are formed on both sides of the gate wirings 33a and 33b in the X direction.

[0045] The gate wiring 31a surrounds the outer periphery in the Y direction and Z direction of the nanosheet 21a of the transistor N11 via a gate insulating film (not shown). The gate wiring 31a becomes the gate of the transistor N11. The gate wiring 31b surrounds the outer periphery in the Y direction and Z direction of the nanosheet 21b of the transistor N13 via a gate insulating film (not shown). The gate wiring 31b becomes the gate of the transistor N13.

[0046] The gate wiring 32a surrounds the outer peripheries in the Y and Z directions of the nanosheet 21c of the transistor N12 and the nanosheet 26a of the transistor N15 via a gate insulating film (not shown). The gate wiring 32a serves as the gates of the transistors N12 and N15. The gate wiring 32b surrounds the outer peripheries in the Y and Z directions of the nanosheet 21d of the transistor N14 and the nanosheet 26b of the transistor N17 via a gate insulating film (not shown). The gate wiring 32b serves as the gates of the transistors N14 and N17.

[0047] The gate wiring 33a surrounds the outer periphery in the Y direction and the Z direction of the nanosheet 26c of the transistor N16 via a gate insulating film (not shown). The gate wiring 33a becomes the gate of the transistor N16. The gate wiring 33b surrounds the outer periphery in the Y direction and the Z direction of the nanosheet 26d of the transistor N18 via a gate insulating film (not shown). The gate wiring 33b becomes the gate of the transistor N18.

[0048] In the local wiring layer, local wirings 41a, 41b, and 41c extending in parallel in the Y direction, and local wirings 46a, 46b, and 46c extending in parallel in the Y direction are formed. The local wiring 41a is connected to the pads 22a and 22d. The local wiring 41b is connected to the pads 22b and 22e. The local wiring 41c is connected to the pads 22c and 22f. The local wiring 46a is connected to the pads 27a and 27d. The local wiring 46b is connected to the pads 27b and 27e. The local wiring 46c is connected to the pads 27c and 27f.

[0049] In the M1 wiring layer, metal wirings 51, 52, and 53 extending in the X direction are formed. The metal wirings 51 and 53 correspond to node IN1 of the capacitance element, and the metal wiring 52 corresponds to node IN2 of the capacitance element. The metal wiring 51 is connected to the gate wirings 31a and 31b through vias. The metal wiring 52 is connected to the gate wirings 32a and 32b through vias. The metal wiring 53 is connected to the gate wirings 33a and 33b through vias.

[0050] Here, the nanosheet 21a and the nanosheet 21c face each other in the Y direction. The surface of the nanosheet 21a facing the nanosheet 21c in the Y direction is not covered by the gate wiring 31a and is exposed from the gate wiring 31a. The surface of the nanosheet 21c facing the nanosheet 21a in the Y direction is not covered by the gate wiring 32a and is exposed from the gate wiring 32a. Similarly, the nanosheet 21b and the nanosheet 21d face each other in the Y direction. The surface of the nanosheet 21b facing the nanosheet 21d in the Y direction is not covered by the gate wiring 31b and is exposed from the gate wiring 31b. The surface of the nanosheet 21d facing the nanosheet 21b in the Y direction is not covered by the gate wiring 32b and is exposed from the gate wiring 32b.

[0051] Further, the nanosheets 26a and 26c face each other in the Y direction. The surface of the nanosheet 26a facing the nanosheet 26c in the Y direction is not covered by the gate wiring 32a and is exposed from the gate wiring 32a. The surface of the nanosheet 26c facing the nanosheet 26a in the Y direction is not covered by the gate wiring 33a and is exposed from the gate wiring 33a. Similarly, the nanosheets 26b and 26d face each other in the Y direction. The surface of the nanosheet 26b facing the nanosheet 26d in the Y direction is not covered by the gate wiring 32b and is exposed from the gate wiring 32b. The surface of the nanosheet 26d facing the nanosheet 26b in the Y direction is not covered by the gate wiring 33b and is exposed from the gate wiring 33b.

[0052] Different signals are applied to the gates of transistors N11 and N13 and the gates of transistors N12 and N14. For this reason, gate wiring 31a and gate wiring 32a need to be separated, and gate wiring 31b and gate wiring 32b need to be separated. On the other hand, with the above configuration, the distance between nanosheets 21a and 21c and the distance between nanosheets 21b and 21d can be reduced (d1 < d2). Similarly, different signals are applied to the gates of transistors N15 and N17 and the gates of transistors N16 and N18. For this reason, gate wiring 32a and gate wiring 33a need to be separated, and gate wiring 32b and gate wiring 33b need to be separated. On the other hand, with the above configuration, the distance between nanosheets 26a and 26c and the distance between nanosheets 26b and 26d can be reduced.

[0053] Therefore, the gates of the transistors arranged between nodes IN1 and IN2 can be separated by a small distance between nanosheets, so that the size of the capacitive element in the Y direction can be reduced.

[0054] As described above, according to the present embodiment, the capacitance structure constituting the capacitance element includes, for example, a transistor N11 having a nanosheet 21a extending in the X direction and a gate wiring 31a extending in the Y direction and surrounding the outer periphery of the nanosheet 21a, and a transistor N12 having a nanosheet 21c extending in the X direction and a gate wiring 32a extending in the Y direction and surrounding the outer periphery of the nanosheet 21c. The transistors N11 and N12 are adjacent to each other in the Y direction, and both nodes are connected to each other. The nanosheets 21a and 21c face each other in the Y direction, and the surface of the nanosheet 21c of the nanosheet 21a is exposed from the gate wiring 31a, and the surface of the nanosheet 21c on the nanosheet 21a side is exposed from the gate wiring 32a. This makes it possible to reduce the distance between the nanosheets 21a and 21c, which is necessary to separate the gate of the transistor N11 from the gate of the transistor N12. Therefore, the size of the capacitance element in the Y direction can be reduced, so that a layout structure of a capacitance element having a high withstand voltage using a fork sheet FET can be realized in a small area.

[0055] In the above embodiment, both nodes, i.e., both the source and the drain, of the two transistors constituting the capacitance structure are connected, but only one of the nodes may be connected. In other words, it is sufficient that at least one of the nodes of the two transistors constituting the capacitance structure is connected.

[0056] Furthermore, in the above-described embodiment, the transistors aligned in the X direction share one node, but the node does not necessarily have to be shared.

[0057] In the above-described embodiment, each capacitance structure is configured with N-conductivity type transistors, but may be configured with P-conductivity type transistors. The capacitance element may have both a capacitance structure configured with N-conductivity type transistors and a capacitance structure configured with P-conductivity type transistors. For example, in the capacitance element of FIG. 3, the upper N-conductivity type transistors N11 to N14 may be replaced with P-conductivity type transistors.

[0058] In the above embodiment, two capacitive structures are arranged in the X direction, but three or more may be arranged in the X direction.

[0059] (Modification) Fig. 4 is a plan view showing an example of a layout structure of a capacitive element according to a modified example of the first embodiment. The layout structure of Fig. 4 corresponds to two capacitive elements of Fig. 1 arranged side by side in the Y direction. That is, both capacitive structures 1A and 1B have the same configuration as the capacitive element of Fig. 1.

[0060] Fig. 5 is a circuit diagram showing the configuration of the capacitive element shown in Fig. 4. The capacitive element in Fig. 5 is connected to two nodes IN1, with transistors N11 to N18 arranged between one node IN1 and node IN2, and transistors N21 to N28 arranged between node IN2 and the other node IN1.

[0061] The gates of transistors N11 and N13 are connected to node IN1. The gates of transistors N12, N14, N15, and N17 are connected to each other. The gates of transistors N16 and N18 are connected to node IN2. Both nodes of transistors N11 and N12 are connected to each other. Both nodes of transistors N13 and N14 are connected to each other. Both nodes of transistors N15 and N16 are connected to each other. Both nodes of transistors N17 and N18 are connected to each other. Transistors N11 and N13 share one node, and transistors N12 and N14 share one node. Transistors N15 and N17 share one node, and transistors N16 and N18 share one node.

[0062] The gates of transistors N21 and N23 are connected to node IN2. The gates of transistors N22, N24, N25, and N27 are connected to each other. The gates of transistors N26 and N28 are connected to node IN1. Both nodes of transistors N21 and N22 are connected to each other. Both nodes of transistors N23 and N24 are connected to each other. Both nodes of transistors N25 and N26 are connected to each other. Both nodes of transistors N27 and N28 are connected to each other. Transistors N21 and N23 share one node, and transistors N22 and N24 share one node. Transistors N25 and N27 share one node, and transistors N26 and N28 share one node.

[0063] 5, four stages of transistors are connected in series between nodes IN1 and IN2. That is, the voltage applied to the transistors N11 to N18 and N21 to N28 is 1 / 4 of the voltage between the nodes IN1 and IN2. Therefore, a voltage higher than the withstand voltage of the transistors N11 to N18 and N21 to N28 can be applied to the capacitive element.

[0064] 4, metal wires 51, 52, 53, 54, and 55 extending in the X direction are formed in the M1 wiring layer. The metal wires 51 and 55 correspond to the node IN1 of the capacitive element, and the metal wire 53 corresponds to the node IN2 of the capacitive element.

[0065] Both of the capacitance structures 1A and 1B have the same configuration as the capacitance element in Fig. 1. Therefore, as in the above-described embodiment, the gates of the transistors arranged between the nodes IN1 and IN2 can be separated by a small inter-nanosheet distance, so that the size of the capacitance element in the Y direction can be reduced.

[0066] The number of transistor stages connected in series between the nodes IN1 and IN2 is not limited to four stages, and may be more than four stages. Also, it is possible to configure an odd number of transistor stages, such as three stages, connected in series. In this case, one of the nodes IN1 and IN2 is connected to the node, not to the gate of the transistor.

[0067] Second embodiment 6 and 7 are diagrams showing an example of a layout structure of a capacitive element according to the second embodiment, where Fig. 6 is a plan view and Fig. 7 is a cross-sectional view in the vertical direction in a plan view. Fig. 7 is a cross-section taken along line Y3-Y3'.

[0068] FIG. 8 is a circuit diagram showing the configuration of the capacitance element shown in FIG. 6 and FIG. 7. N-conductivity type transistors N11, N12, N13, N14, N15, N16, N17, and N18 are arranged between nodes IN1 and IN2. The gates of the transistors N11, N13, N15, and N17 are connected to the node IN1. The gates of the transistors N12, N14, N16, and N18 are connected to the node IN2. The transistors N11 and N15 have both nodes connected to each other. The transistors N12 and N16 have both nodes connected to each other. The transistors N13 and N17 have both nodes connected to each other. The transistors N14 and N18 have both nodes connected to each other. The transistors N11 and N12 share one node, the transistors N12 and N13 share one node, and the transistors N13 and N14 share one node. The transistors N15 and N16 share one node, the transistors N16 and N17 share one node, and the transistors N17 and N18 share one node.

[0069] The capacitive element in Fig. 8 has four capacitive structures, each made up of two transistors with one node connected to each other, provided between nodes IN1 and IN2. That is, the capacitive element in Fig. 8 includes a capacitive structure made up of transistors N11 and N12, a capacitive structure made up of transistors N13 and N14, a capacitive structure made up of transistors N15 and N16, and a capacitive structure made up of transistors N17 and N18.

[0070] 6, N-type transistors N11 to N18 are arranged in four rows in the X direction and two rows in the Y direction. That is, transistors N11, N12, N13, and N14 are arranged in the X direction, and transistors N15, N16, N17, and N18 are arranged in the X direction. Transistors N11 and N15 are arranged in the Y direction, transistors N12 and N16 are arranged in the Y direction, transistors N13 and N17 are arranged in the Y direction, and transistors N14 and N18 are arranged in the Y direction.

[0071] The transistors N11 to N14 each have a nanosheet 121a, 121b, 121c, or 121d as a channel portion, each of which is made up of three overlapping sheets in a planar view. The transistors N15 to N18 each have a nanosheet 126a, 126b, 126c, or 126d as a channel portion, each of which is made up of three overlapping sheets in a planar view. In other words, the transistors N11 to N14 and N15 to N18 are nanosheet FETs.

[0072] As shown in FIG. 6, pads 122a, 122b, 122c, 122d, and 122e made of an integrally structured semiconductor layer connected to the three sheet structures are formed on the left side of the nanosheet 121a, between the nanosheets 121a and 121b, between the nanosheets 121b and 121c, between the nanosheets 121c and 121d, and on the right side of the nanosheet 121d. The pads 122a and 122b are the source and drain regions of the transistor N11. The pads 122b and 122c are the source and drain regions of the transistor N12. The pads 122c and 122d are the source and drain regions of the transistor N13. The pads 122d and 122e are the source and drain regions of the transistor N14.

[0073] Pads 127a, 127b, 127c, 127d, and 127e are formed on the left side of the nanosheet 126a in the drawing, between the nanosheets 126a and 126b, between the nanosheets 126b and 126c, between the nanosheets 126c and 126d, and on the right side of the nanosheet 126d in the drawing, and are made of a semiconductor layer of an integral structure connected to the three sheet structures. The pads 127a and 127b become the source region and drain region of the transistor N15. The pads 127b and 127c become the source region and drain region of the transistor N16. The pads 127c and 127d become the source region and drain region of the transistor N17. The pads 127d and 127e become the source region and drain region of the transistor N18.

[0074] Gate wirings 131a, 131b, 131c, and 131d extending in parallel in the Y direction are formed in the region of the transistors N11 to N14. Gate wirings 132a, 132b, 132c, and 132d extending in the Y direction are formed in the region of the transistors N15 to N18. The gate wirings 131a and 132a are aligned in a line in the Y direction. The gate wirings 131b and 132b are aligned in a line in the Y direction. The gate wirings 131c and 132c are aligned in a line in the Y direction. The gate wirings 131d and 132d are aligned in a line in the Y direction. Dummy gate wirings 136a and 136b are formed on both sides in the X direction of the gate wirings 131a to 131d and 132a to 132d.

[0075] The gate wiring 131a surrounds the outer periphery in the Y direction and Z direction of the nanosheet 121a of the transistor N11 via a gate insulating film (not shown). The gate wiring 131a becomes the gate of the transistor N11. Similarly, the gate wirings 131b, 131c, and 131d surround the outer periphery in the Y direction and Z direction of the nanosheets 121b, 121c, and 121d of the transistors N12, N13, and N14, respectively, via a gate insulating film (not shown). The gate wirings 131b, 131c, and 131d become the gates of the transistors N12, N13, and N14, respectively.

[0076] The gate wiring 132a surrounds the outer periphery in the Y direction and Z direction of the nanosheet 126a of the transistor N15 via a gate insulating film (not shown). The gate wiring 132a becomes the gate of the transistor N15. Similarly, the gate wirings 132b, 132c, and 132d surround the outer periphery in the Y direction and Z direction of the nanosheets 126b, 126c, and 126d of the transistors N16, N17, and N18, respectively, via a gate insulating film (not shown). The gate wirings 132b, 132c, and 132d become the gates of the transistors N16, N17, and N18, respectively.

[0077] The gate wirings 131a and 132a arranged in the Y direction are connected via a bridge portion 133a formed between the gate wiring 131a and the gate wiring 132a as a gate connection portion. The gate wirings 131b and 132b arranged in the Y direction are connected via a bridge portion 133b formed between the gate wiring 131b and the gate wiring 132b. The gate wirings 131c and 132c arranged in the Y direction are connected via a bridge portion 133c formed between the gate wiring 131c and the gate wiring 132c. The gate wirings 131d and 132d arranged in the Y direction are connected via a bridge portion 133d formed between the gate wiring 131d and the gate wiring 132d.

[0078] Local wirings 141a, 141b, 141c, 141d, and 141e extending in the Y direction are formed in the local wiring layer. The local wiring 141a is connected to the pads 122a and 127a. The local wiring 141b is connected to the pads 122b and 127b. The local wiring 141c is connected to the pads 122c and 127c. The local wiring 141d is connected to the pads 122d and 127d. The local wiring 141e is connected to the pads 122e and 127e.

[0079] In the M1 wiring layer, metal wirings 151 and 152 extending in the X direction are formed. The metal wiring 152 corresponds to the node IN1 of the capacitance element, and the metal wiring 151 corresponds to the node IN2 of the capacitance element. The metal wiring 151 is connected to the gate wirings 131b and 131d through vias. The metal wiring 152 is connected to the gate wirings 132a and 132c through vias.

[0080] Here, nanosheet 121a and nanosheet 126a face each other in the Y direction. The surface of nanosheet 121a facing nanosheet 126a in the Y direction is not covered by gate wiring 131a and is exposed from gate wiring 131a. The surface of nanosheet 126a facing nanosheet 121a in the Y direction is not covered by gate wiring 132a and is exposed from gate wiring 132a.

[0081] Similarly, the nanosheet 121b and the nanosheet 126b face each other in the Y direction. The nanosheet 121c and the nanosheet 126c face each other in the Y direction. The nanosheet 121d and the nanosheet 126d face each other in the Y direction. And the surfaces of the nanosheets 121b, 121c, 121d on the sides of the nanosheets 126b, 126c, 126d in the Y direction are not covered by the gate wirings 131b, 131c, 131d and are exposed from the gate wirings 131b, 131c, 131d. The surfaces of the nanosheets 126b, 126c, 126d on the sides of the nanosheets 121b, 121c, 121d in the Y direction are not covered by the gate wirings 132b, 132c, 132d and are exposed from the gate wirings 132b, 132c, 132d.

[0082] With the above configuration, the distance between the transistors N11 to N14 and the transistors N15 to N18 can be reduced (d1 < d2). Therefore, the size of the capacitive element in the Y direction can be reduced.

[0083] As described above, according to the present embodiment, the capacitive structure constituting the capacitive element includes, for example, a transistor N11 having a nanosheet 121a extending in the X direction and a gate wiring 131a extending in the Y direction and surrounding the outer periphery of the nanosheet 121a, and a transistor N12 having a nanosheet 121b extending in the X direction and a gate wiring 131b extending in the Y direction and surrounding the outer periphery of the nanosheet 121b. The transistors N11 and N12 are adjacent to each other in the X direction, and one of the nodes is connected to each other. And the surface of the nanosheet 121a on the first side (here, the lower side in the drawing) in the Y direction is exposed from the gate wiring 131a, and the surface of the nanosheet 121b on the same first side (here, the lower side in the drawing) in the Y direction is exposed from the gate wiring 131b. Thereby, the distance between the capacitive structure and the capacitive structure including the transistors N15 and N16 adjacent to the first side in the Y direction can be reduced. Therefore, the size of the capacitive element in the Y direction can be reduced.

[0084] In addition, in the capacitance structure consisting of the transistors N15 and N16, the surface of the nanosheet 126a on the first side in the Y direction (here, the upper side in the drawing) is exposed from the gate wiring 132a, and the surface of the nanosheet 126b on the same first side in the Y direction (here, the upper side in the drawing) is exposed from the gate wiring 132b. This makes it possible to reduce the distance between the capacitance structure and the capacitance structure consisting of the transistors N11 and N12 adjacent to the first side in the Y direction. Therefore, it is possible to reduce the size of the capacitance element in the Y direction.

[0085] In the above-described embodiment, each capacitance structure is configured with N-conductivity type transistors, but may be configured with P-conductivity type transistors. Also, the capacitance element may include both a capacitance structure configured with N-conductivity type transistors and a capacitance structure configured with P-conductivity type transistors.

[0086] In the above embodiment, two capacitive structures are arranged in the X direction, but three or more may be arranged in the X direction. Also, further capacitive structures may be arranged in the Y direction.

[0087] Third embodiment Fig. 9 is a diagram showing an example of a layout structure of a capacitive element according to a third embodiment. Fig. 10 is a circuit diagram showing a configuration of the capacitive element shown in Fig. 9. A semiconductor integrated circuit device according to this embodiment includes the capacitive element shown in Fig. 10. For example, a signal is applied to nodes IN1 and IN2. Alternatively, nodes IN1 and IN2 are connected to power supply lines. In this case, the capacitive element functions as an inter-power supply capacitance.

[0088] The capacitive element in Fig. 10 is connected to two nodes IN1. N-conductivity type transistors N11, N12, N13, and N14 are arranged between one node IN1 and node IN2. Both nodes of the transistors N11 and N13 are connected to the node IN1. Both nodes of the transistors N12 and N14 are connected to the node IN2. The gates of the transistors N11, N12, N13, and N14 are connected to each other.

[0089] N-type transistors N15, N16, N17, and N18 are arranged between node IN2 and the other node IN1. Both nodes of transistors N15 and N17 are connected to node IN2. Both nodes of transistors N16 and N18 are connected to node IN1. The gates of transistors N15, N16, N17, and N18 are connected to each other.

[0090] 10, the voltage applied to the transistors N11 to N18 is half the voltage between the nodes IN1 and IN2, so that a voltage higher than the withstand voltage of the transistors N11 to N18 can be applied to the capacitive element.

[0091] The capacitive element in Fig. 10 has four capacitive structures, each made up of two transistors whose gates are connected to each other, provided between nodes IN1 and IN2. That is, the capacitive element in Fig. 10 includes a capacitive structure made up of transistors N11 and N12, a capacitive structure made up of transistors N13 and N14, a capacitive structure made up of transistors N15 and N16, and a capacitive structure made up of transistors N17 and N18.

[0092] 9, N-type transistors N11 to N18 are arranged in two rows in the X direction and four rows in the Y direction. That is, transistors N11 and N13 are arranged in the X direction, transistors N12 and N14 are arranged in the X direction, transistors N15 and N17 are arranged in the X direction, and transistors N16 and N18 are arranged in the X direction. Transistors N11, N12, N15, and N16 are arranged in a row in the Y direction. Transistors N13, N14, N17, and N18 are arranged in a row in the Y direction.

[0093] The transistors N11 to N14 each have a nanosheet 221a, 221b, 221c, or 221d as a channel portion, each of which is made up of three overlapping sheets in a planar view. The transistors N15 to N18 each have a nanosheet 226a, 226b, 226c, or 226d as a channel portion, each of which is made up of three overlapping sheets in a planar view. In other words, the transistors N11 to N14 and N15 to N18 are nanosheet FETs.

[0094] As shown in FIG. 9, pads 222a, 222b, and 222c made of a semiconductor layer of an integral structure connected to the three sheet structures are formed on the left side of the nanosheet 221a, between the nanosheets 221a and 221b, and on the right side of the nanosheet 221b. The pads 222a and 222b become the source region and drain region of the transistor N11. The pads 222b and 222c become the source region and drain region of the transistor N13. Pads 222d, 222e, and 222f made of a semiconductor layer of an integral structure connected to the three sheet structures are formed on the left side of the nanosheet 221c, between the nanosheets 221c and 221d, and on the right side of the nanosheet 221d. The pads 222d and 222e become the source region and drain region of the transistor N12. The pads 222e and 222f become the source region and drain region of the transistor N14.

[0095] Pads 227a, 227b, and 227c are formed on the left side of the nanosheet 226a, between the nanosheets 226a and 226b, and on the right side of the nanosheet 226b. The pads 227a and 227b are the source and drain regions of the transistor N15. The pads 227b and 227c are the source and drain regions of the transistor N17. Pads 227d, 227e, and 227f are formed on the left side of the nanosheet 226c, between the nanosheets 226c and 226d, and on the right side of the nanosheet 226d. The pads 227d and 227e are the source and drain regions of the transistor N16. The pads 227e and 227f are the source and drain regions of the transistor N18.

[0096] Gate wirings 231a and 231b extending in parallel in the Y direction are formed in the region of the transistors N11 to N14. Gate wirings 232a and 232b extending in parallel in the Y direction are formed in the region of the transistors N15 to N18. The gate wirings 231a and 232a are aligned in a line in the Y direction. The gate wirings 231b and 232b are aligned in a line in the Y direction. Dummy gate wirings 236a and 236b are formed on both sides of the gate wirings 231a and 231b in the X direction. Dummy gate wirings 236c and 236d are formed on both sides of the gate wirings 232a and 232b in the X direction.

[0097] The gate wiring 231a surrounds the outer peripheries in the Y and Z directions of the nanosheet 221a of the transistor N11 and the nanosheet 221c of the transistor N12 via a gate insulating film (not shown). The gate wiring 231a serves as the gates of the transistors N11 and N12. The gate wiring 231b surrounds the outer peripheries in the Y and Z directions of the nanosheet 221b of the transistor N13 and the nanosheet 221d of the transistor N14 via a gate insulating film (not shown). The gate wiring 231b serves as the gates of the transistors N13 and N14.

[0098] The gate wiring 232a surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 226a of the transistor N15 and the nanosheet 226c of the transistor N16 via a gate insulating film (not shown). The gate wiring 232a serves as the gates of the transistors N15 and N16. The gate wiring 232b surrounds the outer peripheries in the Y direction and Z direction of the nanosheet 226b of the transistor N17 and the nanosheet 226d of the transistor N18 via a gate insulating film (not shown). The gate wiring 232b serves as the gates of the transistors N17 and N18.

[0099] In the local wiring layer, local wirings 241a, 241b, and 241c extending in parallel in the Y direction, local wirings 242a, 242b, and 242c extending in parallel in the Y direction, and local wirings 243a, 243b, and 243c extending in parallel in the Y direction are formed. The local wiring 241a is connected to the pad 222a. The local wiring 241b is connected to the pad 222b. The local wiring 241c is connected to the pad 222c. The local wiring 242a is connected to the pads 222d and 227a. The local wiring 242b is connected to the pads 222e and 227b. The local wiring 242c is connected to the pads 222f and 227c. The local wiring 243a is connected to the pad 227d. The local wiring 243b is connected to the pad 227e. The local wiring 243c is connected to the pad 227f.

[0100] In the M1 wiring layer, metal wirings 251, 252, 253, 254, and 255 extending in the X direction are formed. The metal wirings 251 and 255 correspond to the node IN1 of the capacitive element, and the metal wiring 253 corresponds to the node IN2 of the capacitive element. The metal wiring 251 is connected to the local wirings 241a, 241b, and 241c through vias. The metal wiring 252 is connected to the gate wirings 231a and 231b through vias. The metal wiring 253 is connected to the local wirings 242a, 242b, and 242c through vias. The metal wiring 254 is connected to the gate wirings 232a and 232b through vias. The metal wiring 255 is connected to the local wirings 243a, 243b, and 243c through vias.

[0101] Here, the nanosheet 221c and the nanosheet 226a face each other in the Y direction. The surface of the nanosheet 221c facing the nanosheet 226a in the Y direction is not covered by the gate wiring 231a and is exposed from the gate wiring 231a. The surface of the nanosheet 226a facing the nanosheet 221c in the Y direction is not covered by the gate wiring 232a and is exposed from the gate wiring 232a. Similarly, the nanosheet 221d and the nanosheet 226b face each other in the Y direction. The surface of the nanosheet 221d facing the nanosheet 226b in the Y direction is not covered by the gate wiring 231b and is exposed from the gate wiring 231b. The surface of the nanosheet 226b facing the nanosheet 221d in the Y direction is not covered by the gate wiring 232b and is exposed from the gate wiring 232b.

[0102] Furthermore, the surface of nanosheet 221a on the upper side in the Y direction in the drawing is not covered by gate wiring 231a and is exposed from gate wiring 231a. The surface of nanosheet 221b on the upper side in the Y direction in the drawing is not covered by gate wiring 231b and is exposed from gate wiring 231b. The surface of nanosheet 226c on the lower side in the Y direction in the drawing is not covered by gate wiring 232a and is exposed from gate wiring 232a. The surface of nanosheet 226d on the lower side in the Y direction in the drawing is not covered by gate wiring 232b and is exposed from gate wiring 232b.

[0103] 10, the gates of transistors N11 to N14 are separated from the gates of transistors N15 to N18. For this reason, gate wiring 231a and gate wiring 232a must be separated, and gate wiring 231b and gate wiring 232b must be separated. On the other hand, with the above configuration, the distance between nanosheets 221c and 226a and the distance between nanosheets 221d and 226b can be reduced (d1 <d2)。

[0104] Therefore, the gates of adjacent transistors included in the two capacitance structures connected to node IN2 can be separated by a small inter-nanosheet distance, thereby reducing the size of the capacitance element in the Y direction.

[0105] As described above, according to the present embodiment, the capacitance structure constituting the capacitance element includes, for example, a transistor N11 having a nanosheet 221a extending in the X direction and a transistor N12 having a nanosheet 221c extending in the X direction. The transistors N11 and N12 are adjacent to each other in the Y direction, and the gate wiring 231a is formed so as to surround the outer periphery of the nanosheets 221a and 221c. The surface of the nanosheet 221c opposite to the nanosheet 221a in the Y direction is exposed from the gate wiring 231a. This makes it possible to reduce the distance between the capacitance structure and the capacitance structure consisting of the transistors N15 and N16 adjacent to the transistor N12 side in the Y direction. Therefore, the size of the capacitance element in the Y direction can be reduced, and therefore the layout structure of a capacitance element having a high breakdown voltage using a fork sheet FET can be realized in a small area.

[0106] In addition, in the capacitance structure consisting of the transistors N15 and N16, the surface of the nanosheet 226a opposite to the nanosheet 226c in the Y direction is exposed from the gate wiring 232a. This makes it possible to reduce the distance between the capacitance structure and the capacitance structure consisting of the transistors N11 and N12 adjacent to the transistor N15 side in the Y direction. Therefore, the size of the capacitance element in the Y direction can be reduced.

[0107] In the above-described embodiment, each transistor constituting the capacitance structure has both nodes, that is, both the source and the drain, connected to the node IN1 or the node IN2, but only one of the nodes may be connected.

[0108] In the above embodiment, the gates of the transistors arranged in the X direction are connected to each other, but they do not have to be connected.

[0109] In the above-described embodiment, each capacitance structure is configured with N-conductivity type transistors, but may be configured with P-conductivity type transistors. The capacitance element may have both a capacitance structure configured with N-conductivity type transistors and a capacitance structure configured with P-conductivity type transistors. For example, in the capacitance element of FIG. 10, the upper N-conductivity type transistors N11 to N14 may be replaced with P-conductivity type transistors.

[0110] In the above embodiment, two capacitive structures are arranged in the X direction, but three or more may be arranged in the X direction.

[0111] (Modification) Fig. 11 is a diagram showing an example of a layout structure of a capacitive element according to a modified example of the third embodiment. Fig. 12 is a circuit diagram showing a configuration of the capacitive element shown in Fig. 11. The capacitive elements shown in Figs. 11 and 12 are similar in layout structure and circuit configuration to the capacitive elements shown in Figs. 9 and 10. However, the capacitive elements shown in Figs. 11 and 12 differ from the capacitive elements shown in Figs. 9 and 10 in the connection relationship with nodes IN1 and IN2. That is, in Fig. 11, a metal wiring 251 corresponds to node IN1 of the capacitive element, and a metal wiring 255 corresponds to node IN2 of the capacitive element.

[0112] In this modification, four stages of N-type transistors are connected in series between nodes IN1 and IN2. Transistors N11 and N13 are connected to node IN1, and transistors N16 and N18 are connected to node IN2.

[0113] In this modified example, as in the above-described embodiment, the gates of adjacent transistors included in the two capacitance structures connected between nodes IN1 and IN2 can be separated by a small inter-nanosheet distance, thereby reducing the size of the capacitance element in the Y direction. [Industrial Applicability]

[0114] The present disclosure makes it possible to realize a layout structure of a capacitive element having high withstand voltage using a fork sheet FET in a small area, which is useful for miniaturizing semiconductor chips and improving their integration, for example. [Explanation of symbols]

[0115] 21a, 21b, 21c, 21d, 26a, 26b, 26c, 26d Nanosheets 31a, 31b, 32a, 32b, 33a, 33b Gate wiring 121a, 121b, 121c, 121d, 126a, 126b, 126c, 126d Nanosheets 131a, 131b, 131c, 131d, 132a, 132b, 132c, 132d Gate wiring 133a, 133b, 133c, 133d Bridge section (gate connection section) 221a, 221b, 221c, 221d, 226a, 226b, 226c, 226d Nanosheets 231a, 231b, 232a, 232b Gate wiring IN1 1st node IN2 2nd node N11~N18, N21~N28 Transistors

Claims

1. A semiconductor integrated circuit device including a capacitive element, the capacitive element comprises at least one capacitive structure disposed between a first node and a second node; The capacitance structure comprises: a first transistor including a first nanosheet extending in a first direction and a first gate wiring extending in a second direction perpendicular to the first direction and formed so as to surround an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions; a second transistor including a second nanosheet extending in the first direction and a second gate wiring extending in the second direction and formed so as to surround the periphery of the second nanosheet in the second and third directions; the first and second transistors are adjacent to each other in the second direction, and at least one node of each of the first and second transistors is connected to each other; The first nanosheet and the second nanosheet face each other in the second direction, and a surface of the first nanosheet facing the second nanosheet is exposed from the first gate wiring, and a surface of the second nanosheet facing the first nanosheet is exposed from the second gate wiring. A semiconductor integrated circuit device characterized by:

2. 2. The semiconductor integrated circuit device according to claim 1, The first gate wiring is connected to the first node, and the second gate wiring is connected to the second node. A semiconductor integrated circuit device characterized by:

3. 2. The semiconductor integrated circuit device according to claim 1, the capacitive element includes a plurality of the capacitive structures, the plurality of capacitance structures include first and second capacitance structures arranged side by side in the first direction; The first transistor of the first capacitance structure and the first transistor of the second capacitance structure share one node, and the second transistor of the first capacitance structure and the second transistor of the second capacitance structure share one node. A semiconductor integrated circuit device characterized by:

4. 2. The semiconductor integrated circuit device according to claim 1, the capacitive element includes a plurality of the capacitive structures, the plurality of capacitance structures include first and second capacitance structures arranged side by side in the second direction; The second gate wiring of the first capacitance structure and the first gate wiring of the second capacitance structure are integrally formed. A semiconductor integrated circuit device characterized by:

5. 5. The semiconductor integrated circuit device according to claim 4, The first gate wiring of the first capacitance structure is connected to the first node, and the second gate wiring of the second capacitance structure is connected to the second node. A semiconductor integrated circuit device characterized by:

6. A semiconductor integrated circuit device including a capacitive element, the capacitive element comprises at least one capacitive structure disposed between a first node and a second node; The capacitance structure comprises: a first transistor including a first nanosheet extending in a first direction and a first gate wiring extending in a second direction perpendicular to the first direction and formed so as to surround an outer periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions; a second transistor including a second nanosheet extending in the first direction and a second gate wiring extending in the second direction and formed so as to surround the periphery of the second nanosheet in the second and third directions; the first and second transistors are adjacent to each other in the first direction, and one node of each transistor is connected to each other; A surface of the first nanosheet on a first side in the second direction is exposed from the first gate wiring, and a surface of the second nanosheet on the first side in the second direction is exposed from the second gate wiring. A semiconductor integrated circuit device characterized by:

7. 7. The semiconductor integrated circuit device according to claim 6, The first gate wiring is connected to the first node, and the second gate wiring is connected to the second node. A semiconductor integrated circuit device characterized by:

8. 7. The semiconductor integrated circuit device according to claim 6, the capacitive element includes a plurality of the capacitive structures, the plurality of capacitance structures include first and second capacitance structures arranged side by side in the second direction; the first nanosheet of the first capacitor structure and the first nanosheet of the second capacitor structure face each other in the second direction, and the second nanosheet of the first capacitor structure and the second nanosheet of the second capacitor structure face each other in the second direction, In the first capacitance structure, the first side is the side of the second capacitance structure, and in the second capacitance structure, the first side is the side of the first capacitance structure. A semiconductor integrated circuit device characterized by:

9. 9. The semiconductor integrated circuit device according to claim 8, the first gate wiring of the first capacitance structure and the first gate wiring of the second capacitance structure are connected to each other by a first gate connection portion provided between the first gate wirings, The second gate wiring of the first capacitance structure and the second gate wiring of the second capacitance structure are connected to each other by a second gate connection portion provided between the second gate wirings. A semiconductor integrated circuit device characterized by:

10. 7. The semiconductor integrated circuit device according to claim 6, the capacitive element includes a plurality of the capacitive structures, the plurality of capacitance structures include first and second capacitance structures arranged side by side in the first direction; the second transistor of the first capacitance structure and the first transistor of the second capacitance structure share one node; The first gate wiring of the first capacitance structure and the first gate wiring of the second capacitance structure are electrically connected, and the second gate wiring of the first capacitance structure and the second gate wiring of the second capacitance structure are electrically connected. A semiconductor integrated circuit device characterized by:

11. A semiconductor integrated circuit device including a capacitive element, the capacitive element comprises at least one capacitive structure disposed between a first node and a second node; The capacitance structure comprises: a first transistor having a first nanosheet extending in a first direction; a second transistor having a second nanosheet extending in the first direction; the first and second transistors are adjacent to each other in a second direction perpendicular to the first direction; a first gate wiring extending in the second direction is formed so as to surround the periphery of the first and second nanosheets in the second direction and in a third direction perpendicular to the first and second directions; a surface of the second nanosheet opposite to the first nanosheet in the second direction is exposed from the first gate wiring; A semiconductor integrated circuit device characterized by:

12. 12. The semiconductor integrated circuit device according to claim 11, a surface of the first nanosheet opposite to the second nanosheet in the second direction is exposed from the first gate wiring; A semiconductor integrated circuit device characterized by:

13. 12. The semiconductor integrated circuit device according to claim 11, At least one node of the first transistor is connected to the first node, and at least one node of the second transistor is connected to the second node. A semiconductor integrated circuit device characterized by:

14. 12. The semiconductor integrated circuit device according to claim 11, the capacitive element includes a plurality of the capacitive structures, the plurality of capacitance structures include first and second capacitance structures arranged side by side in the second direction; The second nanosheet of the first capacitance structure and the second nanosheet of the second capacitance structure face each other in the second direction. A semiconductor integrated circuit device characterized by:

15. 15. The semiconductor integrated circuit device according to claim 14, at least one node of the second transistor of the first capacitance structure and the second transistor of the second capacitance structure is connected to each other; At least one node of the first transistor of the first capacitance structure is connected to the first node, and at least one node of the first transistor of the second capacitance structure is connected to the second node. A semiconductor integrated circuit device characterized by:

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