Designing overlay targets to improve target placement accuracy

Abstract

A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and depositing a second film layer overlying the first film layer. The first and second film layers are patterned by projecting optical radiation onto the semiconductor substrate through at least one mask using a projection system having a predetermined resolution limit to create an overlay target having a specified geometric shape. The mask includes target features having target feature dimensions equal to or greater than the predetermined resolution limit and assist features interleaved with the target features and having at least one assist feature dimension less than the predetermined resolution limit in an arrangement corresponding to the specified geometric shape of the overlay target.

Description

[Technical field]

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 290,651, filed December 17, 2021, which is incorporated herein by reference.

[0002] The present invention relates generally to semiconductor device manufacturing, and more particularly to methods and target features for semiconductor circuit metrology. [Background technology]

[0003] Semiconductor circuits are commonly fabricated using photolithography methods. In the photolithography process, a thin layer of a light-sensitive polymer (photoresist) is deposited on a semiconductor substrate. The photoresist is patterned by an exposure apparatus, typically including a scanner or stepper, that projects an image of a mask (also called a "photomask" or "reticle") onto the photoresist, typically using ultraviolet (UV) or extreme ultraviolet (EUV) radiation. After patterning, the substrate is modified by methods such as etching and ion bombardment, changing the material properties and / or topography of the substrate, while the portions of the substrate covered by the photoresist are unaffected.

[0004] Semiconductor circuit metrology is used to measure the characteristics of the patterned photoresist, such as the topography and location of the patterned features. To achieve high yields in the photolithography process, accurate positioning of the patterned features in the photoresist with respect to the previously patterned process layer is important. The error (misregistration) in the alignment of the patterned photoresist with respect to the underlying process layer is called "overlay error". As an example, for a typical semiconductor circuit with a minimum line width (critical dimension, CD) of 10-14 nm (the so-called 10 nm design rule), the maximum allowed overlay error is 2-3 nm. In state-of-the-art semiconductor circuits, the line width is shrinking to 5 nm, with a corresponding decrease in the maximum allowed overlay error.

[0005] Because optical radiation at visible and infrared wavelengths can penetrate photoresist layers and dielectric layers below the photoresist, overlay error is typically measured using optical overlay metrology equipment (commonly referred to as optical overlay metrology tools). In addition, infrared wavelengths can penetrate semiconductor substrates such as silicon, allowing measurements through the substrate. Overlay error is measured from overlay targets located at the scribe lines (lines separating adjacent dies) and / or within the dies of the semiconductor substrate.

[0006] Commonly used overlay metrology tools fall into two categories: scatterometry tools and imaging tools. Scatterometry tools, such as the ATL100™ tool by KLA Corporation (Milpitas, CA, USA), capture diffractive (scatterometry) images of periodic target features of an overlay target from the exit pupil of the metrology tool's objective lens. The scatterometry images, which show the angular distribution of optical radiation scattered from the target features, are processed to measure the overlay error.

[0007] An imaging tool, such as an Archer™ series tool by KLA Corporation, images an overlay target, such as an AIM™ overlay target by KLA. Image analysis algorithms are applied to the acquired image to determine the location of the center of symmetry of the target feature in the process layer and the center of symmetry of the target feature in the photoresist layer. The overlay error is calculated based on the displacement between the centers of symmetry of the target feature in the two layers.

[0008] As used in this specification and claims, the terms "optical radiation" and "light" generally refer to any and all of visible, infrared, ultraviolet, and extreme ultraviolet radiation. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] US Patent Application Publication No. 2019 / 0049373 Summary of the Invention [Problem to be solved by the invention]

[0010] The embodiments of the present invention described below provide improved methods and systems for patterning overlay targets. [Means for solving the problem]

[0011] Thus, according to one embodiment of the present invention, there is provided a method for semiconductor metrology comprising depositing a first film layer on a semiconductor substrate and depositing a second film layer overlying the first film layer. The method further comprises patterning the first and second film layers to create an overlay target having a specified geometric shape by projecting optical radiation onto the semiconductor substrate through at least one mask using a projection system having a predetermined resolution limit. The mask includes target features having target feature dimensions equal to or greater than the predetermined resolution limit and assist features interleaved with the target features and having at least one assist feature dimension less than the predetermined resolution limit in an arrangement corresponding to the specified geometric shape of the overlay target.

[0012] In a disclosed embodiment, the specified geometric shape includes a plurality of parallel equally spaced bars. Alternatively, the specified geometric shape includes a frame-in-frame target.

[0013] In some embodiments, the target feature includes a plurality of parallel linear segments oriented along a first direction, and the assist features include a linear grid oriented along a second direction that is not parallel to the first direction. In disclosed embodiments, the second direction is perpendicular to the first direction. Additionally or alternatively, the at least one mask further includes a circuit feature having a predetermined critical dimension, and the linear segments have respective widths equal to the predetermined critical dimension. In disclosed embodiments, the parallel linear segments are grouped together to define at least one bar, and the assist features are disposed on either side of the at least one bar. Additionally or alternatively, the parallel linear segments are grouped together to define a plurality of parallel bars, and the assist features are disposed between the plurality of parallel bars. In some embodiments, the linear grid of assist features has a pitch of less than 10 nm.

[0014] Also in accordance with one embodiment of the present invention, there is provided a mask for patterning a semiconductor wafer in a photolithographic projection system having a predetermined resolution limit, the mask including a transparent substrate and features disposed on the transparent substrate, the features including target features having target feature dimensions equal to or greater than the predetermined resolution limit in an arrangement corresponding to a specified geometry of the overlay target, and assist features interleaved with the target features and having at least one assist feature dimension less than the predetermined resolution limit. The present invention will be more fully understood from the following detailed description of the embodiments taken in conjunction with the drawings. [Brief description of the drawings]

[0015] [Figure 1] 1 is a schematic side view of an exposure apparatus for patterning a photoresist layer on a semiconductor substrate, in accordance with one embodiment of the present invention; [Diagram 2] 1 is a schematic side view of an imaging metrology apparatus, in accordance with an embodiment of the present invention; [Figure 3A] FIG. 2 is a schematic front view of a segmented overlay target, in accordance with one embodiment of the present invention; [Figure 3B] FIG. 3B is a schematic detailed view of a portion of a mask for patterning the segmented bars in the overlay target of FIG. 3A, in accordance with one embodiment of the present invention. [Figure 4A] FIG. 13 is a schematic front view of a segmented frame-in-frame overlay target in accordance with another embodiment of the present invention. [Figure 4B] FIG. 4B is a schematic detailed view of a portion of a mask for patterning the segmented bars in the overlay target of FIG. 4A, in accordance with one embodiment of the present invention. [Figure 5A] 1 is a simulated plot of aerial image amplitude of a segmented mask printed without sub-resolution assist features (SRAF), in accordance with one embodiment of the present invention. [Figure 5B] 1 is a simulated plot of aerial image amplitude of a segmented mask printed with sub-resolution assist features (SRAF) in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] overview The optical properties of overlay metrology tools known in the art place a lower limit on the feature size and periodicity of the overlay targets. For example, the numerical aperture (NA coll ) is 0.9, and the wavelength λ metr For an overlay metrology tool having an optical emission of 500 nm, the pitch P of the periodic target features is P=λ metr / NA coll ≈550 nm. metr is used to denote the wavelength of the optical overlay metrology tool, and λ exp( is used to indicate the wavelength of the exposure tool.) In order for an overlay target to have appreciable diffraction efficiency in such an overlay metrology tool, the feature size of such a target must be on the order of at least 100 nm. Thus, both the pitch and feature size of an overlay target are much larger than the critical dimensions of semiconductor circuits, which are typically on the order of 10-14 nm using current technology.

[0017] Since the dimensions of the overlay target are much larger than the dimensions of the circuit features, the target features of the photolithography mask are segmented, i.e., divided into linear segments that are sized to match the circuit features but cannot be resolved by the optics of the overlay metrology tool. Nevertheless, optical aberrations of the photolithography system can cause the target features to shift by an amount different from that experienced by the circuit features. This shift causes a measurement error, known as the pattern placement error (PPE), between the overlay error measured by the optical metrology system and the actual overlay error of the circuit features. The source of this PPE is the difference in the respective linewidths of the extreme segments of the segmented target feature. This difference can arise due to a differential shift between the so-called aerial image of the segment and the aerial image of the entire target feature, due to residual optical aberrations of the exposure tool. Typical values ​​of the linewidth difference are on the order of 1 nm, which leads to the same order of PPE value.

[0018] The embodiments described herein address this problem by interleaving sub-resolution assist features (SRAFs) with target features in a lithography mask. (The term "interleaved" in the context of this specification and claims means that at least one SRAF is included between two adjacent target features and / or at least one target feature is included between two adjacent SRAFs.) The dimensions of the SRAFs are below the resolution limit of the exposure tool, and therefore the SRAFs are not patterned into the photoresist layer on the wafer. However, by interleaving the SRAFs with the target features, the amplitude variations of the aerial image at the edges of the target features are reduced. Reducing these amplitude variations reduces the dimensional difference between the extreme segments of the target feature, thus mitigating the PPE.

[0019] In some embodiments, each SRAF includes, for example, parallel and equally spaced lines, and the pitch of the lines in the SRAF is less than the resolution limit of the exposure tool. The lines of the SRAF can be oriented in a perpendicular or otherwise non-parallel direction to the segments of the segmented target feature to avoid modulation and distortion of the aerial image of the segments. The inventors have found that by applying SRAF to the segmented target feature, the typical dimensional difference between the extreme segments is reduced from about 1 nm to about 0.1 nm, thus improving the accuracy of the optical overlay error metrology. The resolution limit can vary from system to system. For example, pitches less than about 60-70 nm are not resolved by an immersion scanner with an illumination wavelength of 193 nm and a numerical aperture (NA) of about 1.4. Mask fabrication can also affect the minimum pitch size, which can be about 20 nm. Thus, the resolution limit can include structures with pitches greater than about 20 nm and less than about 60 nm, pitches greater than about 20 nm and less than about 70 nm, or other unresolved ranges, depending on the system.

[0020] Thus, in a disclosed example, a first film layer is deposited on a semiconductor substrate and a second film layer is deposited on the first film layer. The first and second film layers are patterned by projecting optical radiation onto the semiconductor substrate through at least one mask using a photolithographic projection system having a predetermined resolution limit to create an overlay target having a specified geometric shape. The mask includes target features having dimensions equal to or greater than the predetermined resolution limit in an arrangement corresponding to the specified geometric shape of the overlay target. The mask further includes assist features, referred to herein as SRAFs, interleaved with the target features and having at least one assist feature dimension less than the predetermined resolution limit. These assist features are useful, among other things, in reducing PPE as described above.

[0021] Patterning and Metrology Systems 1 is a schematic side view of an exposure apparatus 20 for patterning a photoresist layer 22 on a semiconductor substrate 24, such as a silicon wafer, in accordance with one embodiment of the present invention. The exposure apparatus 20 is shown by way of example and other types of exposure apparatus may be used instead.

[0022] The exposure apparatus 20, which is a simplified representation of a scanner or stepper, comprises an exposure source 26, a mask stage 28, projection optics 30, a wafer stage 32, and an exposure apparatus controller 34. A semiconductor substrate 24 having one or more process layers 38 and a photoresist layer 22 deposited on top of it is positioned on the wafer stage 32. The orientation of the exposure apparatus 20, as well as the orientation of items in the following figures, is referenced to Cartesian coordinates 40.

[0023] A mask 36 defining a pattern in photoresist layer 22 is positioned on mask stage 28. Mask 36 includes both patterns for forming electronic circuit features and patterns for forming overlay targets, as described in more detail below. As previously described, these overlay target patterns include target features having target feature dimensions equal to or greater than a predetermined resolution limit of apparatus 20, and assist features having at least one assist feature dimension below the resolution limit. Different embodiments of the invention, such as those shown in Figures 3A / 3B and 4A / 4B, use masks with different features.

[0024] Exposure source 26 emits optical radiation, indicated by arrows 42, to illuminate mask 36. The optical radiation typically comprises wavelengths in the UV or EUV spectral regions. Although the emitted optical radiation in the figure is shown as uniform, collimated radiation, it may alternatively comprise radiation having a different spatial and / or angular distribution.

[0025] The mask stage 28 comprises actuators controlled by the exposure apparatus controller 34 which can move the stage (and thus the mask 36) linearly in the x, y and z directions as well as rotate the stage about the z axis and tilt the stage about the x and y axes. The mask 36 typically comprises a substrate such as quartz which is transparent to the optical radiation emitted by the exposure source 26, with a pattern formed on the substrate with a thin film of a suitable material for modulating the amplitude and / or phase of the optical radiation transmitted by the mask.

[0026] The projection optics 30 is shown as a single lens for simplicity, but typically comprises multiple lenses and / or mirrors, whose positions and orientations may be controlled by the exposure apparatus controller 34 for optimal optical performance. The resolution limit of the projection optics 30, and therefore of the exposure apparatus 20, is the critical dimension CD that the exposure apparatus can pattern. min This minimum line width is defined by the minimum line width known as the CDmin =k 1 ×λ exp / NA proj is approximately given by, where k 1 (Generally, k 1 λ factor) is a coefficient that encompasses process-related factors and typically has a value of about 0.4; exp is the wavelength emitted by the exposure light source 26, and NA proj is the numerical aperture of the projection optical system 30.

[0027] The wafer stage 32 is equipped with an actuator controlled by the exposure apparatus controller 34 that can move the stage (and thus the semiconductor substrate 24) linearly in the x, y and z directions as well as rotate the stage about the z axis.

[0028] The exposure apparatus controller 34 is coupled to the light source 26, the mask stage 28, the projection optics 30, and the wafer stage 32. The controller 34 typically comprises a programmable processor, programmed with software and / or firmware to perform the functions described herein, along with suitable digital and / or analog interfaces for connecting to other elements of the exposure apparatus 20. Alternatively or additionally, the controller 34 includes hardwired and / or programmable hardware logic circuitry that performs at least some of the functions of the controller. Although the controller 34 is shown in FIG. 1 as a single monolithic functional block for simplicity, in practice the controller may comprise multiple interconnected control units having suitable interfaces for receiving and outputting the signals shown in the figures and described herein.

[0029] To pattern the photoresist layer 22, the exposure apparatus controller 34 moves the wafer stage 32 under the projection optics 30 so that the photoresist layer 22 on the semiconductor substrate 24 is at a desired position and orientation relative to the optics. The exposure source 26 emits optical radiation to illuminate a mask 36. The optical radiation that impinges on the mask 36 is transmitted and / or diffracted by the mask and projected towards the projection optics 30, which focuses the radiation onto the photoresist layer 22, thus exposing the photoresist. The spatial distribution of the intensity of the optical radiation illuminating the photoresist 22 is called the "aerial image."

[0030] The exposed photoresist layer 22 is developed to remove the exposed pattern. To assess the overlay error between the photoresist layer 22 and the process layer 38, the displacement between the overlay target features of the photoresist layer 22 and the corresponding target features previously formed in the underlying process layer 38 is measured using an optical metrology tool as described in detail below. Provided that the overlay error meets a preset tolerance, the process layer 38 is modified by methods such as etching and ion bombardment to change the material properties and / or topography of the process layer, while the portions of the process layer covered by the remaining portions of the photoresist layer 22 are unaffected.

[0031] 2 is a schematic side view of an imaging metrology apparatus 50 according to an embodiment of the present invention. Apparatus 50 is shown as an example to illustrate a method of overlay error measurement using patterned overlay targets according to an embodiment of the present invention. Alternatively, such targets may be used in other types of metrology systems.

[0032] The imaging metrology apparatus 50 includes an imaging assembly 52, an illumination assembly 54, a metrology processor 56, and a table 58 on which a semiconductor substrate, such as substrate 24 to be exposed by the exposure apparatus 20, is mounted. The imaging assembly 52 has a numerical aperture NA collThe illumination assembly 54 includes an objective lens 60 of wavelength λ, a cube beam splitter 62, and an imaging lens 64. The imaging assembly 52 further includes a two-dimensional sensor array 66 including, for example, a complementary metal-oxide semiconductor (CMOS) detector having a two-dimensional array of pixels 68. The imaging lens 64 images the top surface of the semiconductor substrate 24 onto the sensor array 66. The illumination assembly 54 is configured to receive a first light beam having a wavelength λ metr and a lens 72. As mentioned above, the imaging resolution limit of the metrology device 50 is the wavelength λ metr and is determined by the characteristics of the imaging lens 64 and is typically on the order of at least a few hundred nanometers.

[0033] Table 58 is positioned adjacent to objective lens 60 and includes actuators controlled by metrology processor 56 that can move the table linearly in the x, y and z directions as well as rotate the table about the z axis. A semiconductor substrate 24 having a process layer 38 and a photoresist layer 22 deposited on its upper surface is placed on table 58. Photoresist layer 22 has been patterned by exposure apparatus 20 as described above.

[0034] The metrology processor 56 is coupled to the sensor array 66 and the table 58. The metrology processor 56 typically comprises a programmable processor programmed with software and / or firmware to perform the functions described herein, along with suitable digital and / or analog interfaces for connection to other elements of the apparatus 50. Alternatively or additionally, the processor 56 includes hardwired and / or programmable hardware logic circuitry that performs at least some of the functions of the processor. Although the processor 56 is shown in FIG. 2 as a single monolithic functional block for simplicity, in practice the processor may comprise multiple interconnected control units having suitable interfaces for receiving and outputting the signals shown in the figure and described herein.

[0035] To capture an image of a metrology target in the photoresist layer 22, the semiconductor substrate 24 is placed on the table 58 and the table is moved so that the target is in the field of view (FOV) of the objective lens 60. A light source 70 projects a beam of optical radiation onto a lens 72, which further projects the beam onto a cube beam splitter 62. The beam splitter 62 reflects the beam to the objective lens 60, which projects the beam onto the semiconductor substrate 24 to illuminate the metrology target. Radiation that strikes the semiconductor substrate 24 is reflected back into the objective lens 60 and further focused by a lens 64 onto a sensor array 66.

[0036] The metrology processor 56 captures and processes the images to measure the overlay error. Specifically, the processor 56 processes the images of the metrology target to find the centers of symmetry in both the x- and y-directions of the target features in the process and photoresist layers. The two-dimensional displacement between the centers of symmetry is the overlay error.

[0037] Overlay target patterns and masks Reference is now made to Figures 3A and 3B, which show generally a segmented overlay target 100 and details of a mask 200 for patterning the target 100 in photoresist layer 22, in accordance with one embodiment of the present invention.

[0038] The overlay target 100 has the form of an AIM™ target and includes four target features 102a, 102b, 102c, and 102d formed in the process layer 38 (FIG. 1) and four target features 104a, 104b, 104c, and 104d formed in the photoresist layer 22. Each of the target features 104a, 104b, 104c, and 104d includes four parallel equally spaced segmented bars. The width of the linear segments that make up each bar matches the width of a circuit feature, but cannot be resolved by an overlay metrology tool. The specific features of the target 100 are shown by way of example, and the principles of the present embodiment may alternatively be applied, mutatis mutandis, to other target shapes.

[0039] For example, target feature 104a includes bars 106a, 106b, 106c, and 106d, each of which is further segmented into seven linear segments 110a, 110b, 110c, 110d, 110e, 110f, and 110g. For clarity, the segmentation is not shown in the overall view of target 100, but rather in inset 108. Thus, the overall view of target 100 represents the image of the target that an optical metrology tool would capture. (Alternatively, target features may include fewer or more bars, and the bars may be segmented into fewer or more segments. AIM™ targets may alternatively include unsegmented bars.)

[0040] As previously mentioned, typical widths of the four bars in each of target features 102a-102d and 104a-104d are on the order of a few hundred nanometers to allow for resolving an optical image of target 100 captured by an optical overlay metrology tool. An example of segmentation of three of the four bars (bars 106a, 106b, and 106c) of vertical target feature 104a is shown in inset 108. (The terms "vertical" and "horizontal" are used to refer to the y-axis and x-axis, respectively, of Cartesian coordinate system 40.) Bar 106a is segmented into equal width and spacing vertical segments 110a, 110b, 110c, 110d, 110e, 110f, 110g. The common width of segments 110a-110g is selected to match the circuit features of mask 36 but not be resolvable by an overlay metrology tool (such as apparatus 50 of FIG. 2) while an image of the bar 106a, which is the collective feature of the segments, can be captured by the tool. For example, the width of the segments may be selected to be 10 nm or 20 nm, or any other suitable value that matches the circuit features while the collective width of the segments forms an optically resolvable bar.

[0041] Target features 104a-104d of target 100 are patterned in photoresist layer 22 through mask 200 by exposure apparatus 20. (Target features 102a-102d of target 100 have been patterned in process layer 38 using appropriate patterns in a different mask at an earlier stage of the photolithography process.) Mask 200, which includes segmented vertical bars 202a, 202b, and 202c, is used to pattern segmented vertical bars 106a, 106b, and 106c in inset 108. For example, segmented bar 202a includes linear segments 204a, 204b, 204c, 204d, 204e, 204f, and 204g, which pattern corresponding segments 110a, 110b, 110c, 110d, 110e, 110f, and 110g of segmented bar 106a.

[0042] In addition to including vertical segmented bars 202a, 202b, and 202c, mask 200 includes SRAFs 206 interleaved on either side of the segmented bars. Each SRAF in the illustrated example includes a linear grid including nine parallel equally spaced bars 208 oriented horizontally (perpendicular to the vertical segmented bars). The vertical orientation is useful to avoid modulation and distortion of the aerial image of the segments. The width and spacing of the bars 208 of SRAF 206 are selected to be below the resolution limit of exposure tool 20, and therefore are not patterned in photoresist layer 22. For example, the pitch of bars 208 may be less than 10 nm (meaning that the width of the bars is less than 5 nm, below the resolution of exposure tool 20). However, as will be described in more detail below, these bars reduce the amplitude of the aerial image between the segmented features, and thus reduce the variation between the widths of extreme segments 110a and 110g, typically to within 0.1 nm.

[0043] Reference is now made to Figures 4A and 4B, which show generally a segmented overlay target 300 and details of a mask 400 for patterning the target 300 in the photoresist layer 22, in accordance with another embodiment of the present invention.

[0044] Overlay target 300 is a frame-in-frame target that includes four segmented bars 302a, 302b, 302c, and 302d formed in process layer 38 (FIG. 1) and four segmented bars 304a, 304b, 304c, and 304d formed in photoresist layer 22. Each bar in the illustrated example is segmented into seven linear segments 308a, 308b, 308c, 308d, 308e, 308f, and 308g. (The bars may alternatively be segmented into other numbers of segments. The bars of a frame-in-frame target may alternatively be unsegmented.) The segments of the bars match circuit features of mask 400 but cannot be resolved by an overlay metrology tool such as apparatus 50 (FIG. 2).

[0045] For clarity, the segmentation of the bars 304 is not shown in the overall view of the target 300, but rather in the inset 306. The overall view of the target 300 is therefore a schematic representation of an image captured by an optical metrology tool such as the apparatus 50. The overlay error between the process layer 38 and the photoresist layer 22 is measured in the apparatus 50 by capturing an image of the target 300 and processing the image to find the respective centers of symmetry in both the x- and y-directions of the target features in the process layer and the photoresist layer. The two-dimensional displacement between the centers of symmetry is the overlay error.

[0046] As previously mentioned, typical widths of bars 302a-302d and 304a-304d are on the order of a few hundred nanometers to allow apparatus 50 to resolve an optical image of target 300. An example of bar segmentation is shown using a portion of bar 304d shown in inset 306. Vertically oriented bar 304d is segmented into linear segments 308a, 308b, 308c, 308d, 308e, 308f, 308g of equal width and spacing. The common width of segments 308a-308g is selected to match the circuit features but not be resolvable by an overlay metrology tool such as apparatus 50 (FIG. 2), while an image of bar 304d, which is a collective feature of the segments, can be captured by the tool. Similar to target 100 (FIG. 2A), the width of the segments can be selected to be, for example, 10 nm or 20 nm, or any other suitable value that matches the circuit features and that collectively forms an optically resolvable bar.

[0047] The bars 304a-304d of the target 300 are patterned in the photoresist layer 22 through a mask 400 by the exposure apparatus 20. (The bars 302a-302d of the target 300 have been patterned in the process layer 38 using appropriate patterns in a different mask at a previous stage of the photolithography process.) The mask 400 includes vertical linear segments 402a, 402b, 402c, 402d, 402e, 402f, and 402g, which pattern the corresponding segments 308a, 308b, 308c, 308d, 308e, 308f, 308g in the inset 306.

[0048] In addition to the vertical segments 402a-g, the mask 400 includes SRAFs 404a and 404g adjacent to the respective segments 402a and 402g. Each SRAF includes a linear grating including nine parallel equally spaced bars 406 oriented horizontally (perpendicular to the segmented bars) in the illustrated example. As with the SRAF 206 (FIG. 2B), the width and spacing of the bars 406 are selected to be below the resolution limit of the exposure apparatus 20 and therefore are not patterned into the photoresist layer 22. However, as will be explained in more detail below, they reduce the amplitude of the aerial image adjacent the extreme segments 308a and 308g, thus reducing the variation between the widths of these extreme segments.

[0049] 5A and 5B respectively show simulated plots 500 and 540 of aerial image amplitude along with details of a segmented mask 502 without SRAF and a segmented mask 542 with SRAF for patterning segmented bars according to one embodiment of the present invention. Simulations were performed using KLA's Prolith™ lithography simulation tool. Cartesian coordinates 40 are used as the reference for masks 502 and 542. In FIG. 5A, the y-axis ranges from 0.0 to 0.4.

[0050] 5A, the mask 502 includes seven vertical bars 504a, 504b, 504c, 504d, 504e, 504f, and 504g having a pitch P for patterning seven segments in the photoresist layer 22 without SRAF. The plot 500 includes a curve 506 that shows the amplitude of an aerial image generated by the exposure apparatus 20 for exposing the photoresist layer 22 using the mask 502. The curve 506 is calculated along a line 508 that intersects the mask 502 projected onto the photoresist layer 22 and includes seven valleys 510a, 510b, 510c, 510d, 510e, 510f, and 510g that correspond to the seven segments 504a, 504b, 504c, 504d, 504e, 504f, and 504g. Horizontal line 512 indicates the patterning threshold of the photoresist development process, i.e., the aerial image amplitude above which exposed photoresist becomes soluble. Thus, valleys 510a-510g form, after photoresist development, seven segments of a segmented bar having width W, similar to bar 304d (FIG. 4A).

[0051] Because optical aberrations in an optical system (such as the projection optics 30 of the exposure apparatus 20) are typically low at the center of an optical aperture and increase toward its edges, these aberrations tend to shift patterning features that transmit through the edges of the aperture more than those that transmit near the center. Thus, in this example, valleys 510a-510g are shifted in the x-direction relative to the aerial image of the entire segmented bar, and their widths W are governed by the steep slopes 514a and 514b on either side of curve 506. If we assume that optical aberrations shift valleys 510a-510g in the positive x-direction relative to the aerial image of the bar, as shown by arrow 516, valley 510g moves closer to slope 514b and valley 510a moves away from slope 514a. These shifts have the effect of narrowing valley 510g but widening valley 510a, such that the segments patterned by valley 510g are slightly narrower than the segments patterned by valley 510a. The resulting difference ΔCD between the widths of the extreme segments of the patterned segmented bar introduces an error into the measurement of the overlay error due to PPE.

[0052] As shown in FIG. 5B, mask 542 includes seven vertical bars 544a, 544b, 544c, 544d, 544e, 544f, and 544g with pitch P for patterning seven segments in photoresist layer 22. The y-axis in FIG. 5B ranges from 0.0 to 0.5. Unlike mask 502, mask 542 also includes two SRAFs 546, each of which includes nine parallel equally spaced lines 548, in this example oriented perpendicular to vertical bars 544a-544g. As with mask 400, the width and spacing of lines 548 are selected to be below the resolution limit of exposure tool 20 and therefore are not patterned in photoresist layer 22.

[0053] Similar to FIG. 5A, plot 540 includes curve 550 which shows the amplitude of the aerial image produced by exposure apparatus 20 to expose photoresist layer 22 using mask 542. Curve 550 is calculated along line 552 of section 542 projected onto photoresist layer 22 and similar to curve 506 shows seven valleys 554a, 554b, 554c, 554d, 554e, 554f, and 554g which correspond to seven segments 544a, 544b, 544c, 544d, 544e, 544f, and 544g. Horizontal line 556 shows the patterning threshold of the photoresist development process, which is approximately the same value as horizontal line 512. Thus, similar to FIG. 5A, valleys 554a-554g form, after photoresist development, seven segments of a segmented bar having a width W similar to bar 304d.

[0054] Valleys 554a-554g, like valleys 510a-510g, are shifted due to optical aberrations of the projection optics 30, as indicated by arrows 558. However, SRAF 546 scatters some of the optical radiation exposing photoresist layer 22 away from areas adjacent the segmented bars, thus lowering the amplitude of the aerial images outside of valleys 510a-510g and reducing the amplitude slopes 560a and 560b of the aerial images adjacent valleys 554a and 554g. (Note the difference in image amplitude scale between plots 500 and 540 to appreciate the reduced slopes 560a and 560b compared to slopes 514a and 514b.) The image amplitude is still sufficient to expose photoresist layer 22 outside of valleys 554a-554g, but the effect of slopes 560a and 560b on the extreme valleys 554a and 554g is reduced, thus reducing the width variation ΔCD between the extreme segments of the patterned bar, and consequently reducing the PPE.

[0055] It will be understood that the above-described embodiments have been cited by way of example, and that the present invention is not limited to what has been particularly shown and described above. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described above, as well as variations and modifications thereof not disclosed in the prior art that will occur to those skilled in the art upon reading the foregoing description.

Claims

1. depositing a first film layer over a semiconductor substrate and a second film layer overlying the first film layer; patterning the first and second film layers to create an overlay target having a specified geometric shape by projecting optical radiation onto the semiconductor substrate through at least one mask using a projection system having a predetermined resolution limit, the mask comprising: target features in an arrangement corresponding to the specified geometric shape of the overlay target, the target features having a target feature dimension equal to or greater than the predetermined resolution limit; and an assist feature interleaved with the target feature and having at least one assist feature dimension less than the predetermined resolution limit; Steps and wherein the target feature comprises a plurality of parallel line segments oriented along a first direction and the assist feature comprises a linear grating oriented along a second direction that is not parallel to the first direction.

2. 2. The method of claim 1, wherein the specified geometric shape comprises a plurality of parallel equally spaced bars.

3. 2. The method of claim 1, wherein the specified geometric shape comprises a frame-in-frame target.

4. 2. The method of claim 1, wherein the second direction is perpendicular to the first direction.

5. 2. The method of claim 1, wherein said at least one mask further includes a circuit feature having a predetermined critical dimension, and wherein said linear segments have respective widths equal to said predetermined critical dimension.

6. 2. The method of claim 1, wherein the plurality of parallel straight segments are grouped together to define at least one bar, and the assist features are disposed on either side of the at least one bar.

7. 7. The method of claim 6, wherein the plurality of parallel straight segments are grouped together to define a plurality of parallel bars, and the assist features are disposed between the plurality of parallel bars.

8. 10. The method of claim 1, wherein the linear grid of assist features has a pitch of less than 10 nm.

9. 1. A mask for patterning a semiconductor wafer in a photolithographic projection system having a predetermined resolution limit, comprising: A transparent substrate; a feature disposed on the transparent substrate; target features in an arrangement corresponding to a designated geometric shape of the overlay target, the target features having a target feature dimension equal to or greater than the predetermined resolution limit; and an assist feature interleaved with the target feature and having at least one assist feature dimension less than the predetermined resolution limit; and wherein the target features include a plurality of parallel linear segments oriented along a first direction and the assist features include a linear grating oriented along a second direction that is not parallel to the first direction.

10. 10. The mask of claim 9, wherein the specified geometric shape comprises a plurality of parallel equally spaced bars.

11. 10. The mask of claim 9, wherein the specified geometric shape comprises a frame-in-frame target.

12. 10. The mask of claim 9, wherein the second direction is perpendicular to the first direction.

13. 10. The mask of claim 9, wherein said features on said transparent substrate further comprise circuit features having a predetermined critical dimension, said linear segments having respective widths equal to said predetermined critical dimension.

14. 10. The mask of claim 9, wherein the plurality of parallel linear segments are grouped together to define at least one bar, and the assist features are disposed on either side of the at least one bar.

15. 15. The mask of claim 14, wherein the plurality of parallel linear segments are grouped together to define a plurality of parallel bars, and the assist features are disposed between the plurality of parallel bars.

16. 10. The mask of claim 9, wherein the linear grating of assist features has a pitch of less than 10 nm.

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