Multi-chip structure including a memory die stacked on a die having a programmable integrated circuit - Patents.com

Abstract

Some examples described herein provide a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In one example, the multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, which includes a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

Description

Technical Field

[0004] , , ,

[0001] The present disclosure relates to a multi-chip structure and a method of forming such a structure, and more particularly, to a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit, and a method of forming such a structure.

Background Art

[0002] A programmable integrated circuit (IC) refers to a type of IC that includes programmable circuits. An example of a programmable IC is a field programmable gate array (FPGA). An FPGA is characterized by including programmable circuit blocks. Circuit designs may be physically implemented within the programmable circuits of a programmable IC by causing configuration data, sometimes referred to as a configuration bitstream, to be read into the device. The configuration data may be read into internal configuration memory cells of the device. The overall state of the individual configuration memory cells determines the functionality of the programmable IC. For example, the specific operations performed by various programmable circuit blocks and the connections between the programmable circuit blocks of the programmable IC are determined by the overall state of the configuration memory cells into which the configuration data has been read.

Summary of the Invention

[0003] Some examples described herein provide a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). Some examples described herein can eliminate the use of an interposer and / or a physical layer (PHY) interface, thereby reducing processing costs, power consumption, and / or die area usage.

[0004] One example is a multi-chip structure. This multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit, which includes a memory controller. The first die is located on and mounted to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

[0005] Another example is a method for forming a multi-chip structure. A first die is stacked on a second die. The first die contains memory. The second die contains a programmable integrated circuit, which includes a memory controller. The memory controller is communicatively coupled to the memory by the first die stacked on the second die. The first die is mounted on a package substrate.

[0006] A further example is a multi-chip structure. This multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a field-programmable gate array (FPGA) and a memory controller. The first die is located on and mounted to the package substrate. The second die contains memory. The second die is stacked on the side of the first die opposite to the package substrate. The memory is communicatively coupled to the memory controller.

[0007] These and other embodiments can be understood by referring to the detailed description below.

[0008] To gain a more detailed understanding of the features listed above, a more concrete explanation can be provided by referring to the illustrative implementations, which are briefly summarized above and some of which are shown in the attached diagrams. However, it should be noted that the attached diagrams only show typical illustrative implementations and should therefore not be considered limiting in scope. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing several examples of programmable integrated circuits (ICs) connected to external memory. [Figure 2] This section shows several examples of field-programmable gate arrays (FPGAs) for programmable ICs. [Figure 3] These are schematic circuit diagrams of multi-chip structures, based on several examples. [Figure 4] This is a schematic circuit diagram of one of several multi-chip structures, with some examples. [Figure 5] Here is a schematic circuit diagram of one of the further multi-chip structures, with several examples. [Figure 6] This shows the configuration of a multi-chip structure on a printed circuit board (PCB) using several examples. [Figure 7] This is another configuration of a multi-chip structure on a printed circuit board (PCB), with several examples. [Figure 8] This is another configuration of a multi-chip structure on a printed circuit board (PCB), with several examples. [Figure 9] This is a flowchart illustrating a method for forming a multi-chip structure using several examples. [Modes for carrying out the invention]

[0010] To facilitate understanding, common elements in the diagrams are shown with the same reference number where possible. It is anticipated that elements from one example may be usefully incorporated into another.

[0011] Some examples described herein provide a multi-chip structure comprising one or more memory dies stacked on a die having a programmable integrated circuit (IC). In some examples, these memory dies can implement memory for high-bandwidth memory (HBM). In some examples, the programmable IC includes a programmable logic area, such as a fabric for a field-programmable gate array (FPGA). The programmable IC enables user-configurable front-end processing of data read from or written to the memory of any of the memory dies.

[0012] Several examples described herein can eliminate the need for an interposer. By stacking the memory die on a base die containing the programmable IC, an interposer is not implemented (otherwise, the base die and memory die stack would be individually mounted to the interposer). Eliminating the interposer also avoids the costs associated with fabricating and including the interposer in the multi-chip stack. Furthermore, the absence of an interposer enables the formation of multi-chip stacks with less fabrication, resulting in reduced fabrication cycle time in addition to cost savings. By eliminating the interposer and stacking the memory die on the base die, it is also possible to create packages with a smaller footprint and smaller vertical profile.

[0013] Several examples described herein can eliminate the need for physical layer (PHY) interfaces, such as HBM interfaces, in multi-chip structures. Physical layer interfaces can consume power and die area. By avoiding the use of physical layer interfaces such as HBM interfaces, physical layer interfaces on two dies (e.g., dies on both sides of an HBM physical layer connection) can be avoided, thereby reducing power consumption and the area usage of the two dies. Furthermore, the reduced die area usage can lower the manufacturing costs required to form the dies.

[0014] Several examples demonstrate the potential for further benefits. For instance, composite devices formed by multi-chip structures are easier to test and, for example, easier to deploy than multi-chip modules with other packages and / or dies. Furthermore, multi-chip structures with programmable ICs as described herein can enable customization of logic and functionality adjacent to one or more memory dies (e.g., adjacent to one or more HBM dies). Such multi-chip structures can, for example, enable users to create deployable custom devices with high memory bandwidth and low power consumption in a single package. Moreover, such multi-chip structures can maintain programmability and flexibility of programmability in the programmable logic areas, as well as in boundary circuits such as input / output circuits, transceiver circuits, and / or other circuits.

[0015] The following describes various features with reference to the figures. Note that these figures may or may not be drawn to a fixed scale, and that elements of similar structure or function are represented by similar reference numbers throughout the figures. Note that these figures are intended only to facilitate the description of the features. These figures are not intended to be an exhaustive description of the claimed invention or to limit the scope of the claimed invention. In addition, the examples described do not necessarily have all the embodiments or advantages presented. An embodiment or advantage described in conjunction with a particular example is not necessarily limited to that example and may be practiced in any other example, even if not described or explicitly stated as being practiced. Furthermore, while the methods described herein may be described in a specific order of operations, other methods in other examples may be carried out in various other orders, including more or fewer operations (e.g., various sequential or parallel operations of various operations).

[0016] Figure 1 is a block diagram showing a programmable integrated circuit (IC) 102 connected to an external memory in several examples. The programmable IC 102 may be a system-on-a-chip (SoC) and may include or be an IC that is a programmable logic device such as a field-programmable gate array (FPGA). The programmable IC 102 comprises a processing system 104, a network-on-a-chip (NoC) 106, a configuration interconnect 108, one or more programmable logic areas 110a to 110n (collectively, individually, or collectively, "programmable logic area 110"), a memory controller 112, a multi-gigabit transceiver (MGT) 114, an input / output block (IO) 116, and other IP circuits 118. The NoC 106 includes a routing network 120 and a NoC peripheral interconnect (NPI) 122.

[0017] Generally, the processing system 104 is connected to the programmable logic area 110 through the configuration interconnect 108. The processing system 104, the programmable logic area 110, the memory controller 112, MGT 114, IO 116, and other IP circuits 118 are also connected to NoC 106 (e.g., the routing network 120), and therefore can be coupled to communicate with each other through NoC 106 (e.g., the routing network 120). The processing system 104, the memory controller 112, MGT 114, IO 116, and other IP circuits 118 are also connected to each subset of the programmable logic area 110. For example, each of the processing system 104, IO 116, and other IP circuits 118 is connected to the programmable logic area 110a, and each of the memory controller 112 and MGT 114 is connected to the programmable logic area 110n. Various circuits may be connected to any subset of the programmable logic area 110, and circuits may be connected to a given subset of the programmable logic area 110 in any combination with any other circuits. In addition, in some examples, a memory controller 112 may be connected to at least one of the IO 116.

[0018] The processing system 104 may include one or more processor cores. For example, the processing system 104 may include several ARM-based embedded processor cores.

[0019] The programmable logic area 110 may include any number of configurable logic blocks, lookup tables (LUTs), digital signal processing blocks, random access memory blocks, and other programmable interconnect elements as described below. The programmable logic area 110 may be programmed or configured through the configuration interconnect 108 using the processing system 104. For example, the configuration interconnect 108 may enable frame-based programming of the fabric of the programmable logic area 110 by the processor core of the processing system 104 (such as a platform management controller (PMC)).

[0020] The routing network 120 of the NoC 106 provides routing of NoC packets among various systems or circuits. The routing network 120 includes NoC packet switches interconnected by line segments between a NoC master unit (NMU) and a NoC slave unit (NSU). Each NMU is an ingress circuit that connects a master circuit to the NoC 106. Each NSU is an egress circuit that connects the NoC 106 to a slave endpoint circuit. Each NoC packet switch performs switching of NoC packets. Thus, the NMU, NoC packet switches, and NSU may be configured to provide a channel for communication between the master endpoint circuit and the slave endpoint circuit through the NMU, NoC packet switches interconnected by line segments, and NSU. The NMU, NoC packet switches, and NSU also include register blocks that are written to configure the respective NMU, NoC packet switches, and NSU. The register blocks may be written through the NPI 122. For example, the PMC of the processing system 104 can send memory-mapped write requests to the NMU, NoC packet switches, and NSU through the NPI 122 to write to the register blocks to configure the NMU, NoC packet switches, and NSU. The NPI 122 may include an interconnected NPI switch that can distribute the memory-mapped write requests to the appropriate register blocks.

[0021] IO116 may be any input / output circuit for enabling communication between the programmable IC 102 and other circuits and / or systems. In some examples, IO116 may include high-bandwidth memory (HBM) interface circuits, high-density input / output (HDIO) circuits, peripheral component interconnect express (PCIe) circuits, extreme performance input / output (XPIO) circuits, and / or similar. Other IP circuits 118 may be, for example, a digital clock manager, an analog-to-digital converter, system monitoring logic, and / or any circuit for a given implementation. In some examples, at least some of the memory controller 112, MGT114, IO116, and / or other IP circuits 118 are configurable. For example, the memory controller 112, MGT114, IO116, and / or other IP circuits 118 may be configurable through NPI122 of NoC106.

[0022] In some examples, the programmable IC 102 includes an interface and control logic circuit 124. In other examples, the interface and control logic circuit 124 is located on a separate IC from the programmable IC 102 (for example, as shown by a dashed line). The interface and control logic circuit 124 is connected to an external memory 126. The external memory 126 may be, for example, memory on one or more dies. In some examples, the external memory 126 is random access memory (RAM), such as dynamic RAM (DRAM), which may be implemented as high-bandwidth memory (HBM).

[0023] In some examples, interface and control logic circuit 124 is directly connected to memory controller 112, while in other examples, interface and control logic circuit 124 (as shown by the dashed arrow in FIG. 1, for example) is communicatively coupled to memory controller 112 through IO116 of programmable IC 102 and IO128 of another IC. In some examples where programmable IC 102 includes interface and control logic circuit 124, memory controller 112 is directly connected to interface and control logic circuit 124 (e.g., without an intervening physical layer (PHY) interface), and then interface and control logic circuit 124 is connected to external memory 126. In some examples where interface and control logic circuit 124 is within an IC separate from programmable IC 102, memory controller 112 is directly connected to interface and control logic circuit 124 (e.g., without an intervening physical layer (PHY) interface), and then interface and control logic circuit 124 is connected to external memory 126. In some examples where interface and control logic circuit 124 is within an IC separate from programmable IC 102, memory controller 112 is directly connected to IO116 (e.g., a HBM interface), and IO116 is connected to IO128 (e.g., a HBM interface) of a separate IC connected to interface and control logic circuit 124. Then, interface and control logic circuit 124 is connected to external memory 126. Thus, in these examples, memory controller 112 is communicatively coupled to external memory 126.

[0024] In some examples, as detailed below, programmable IC 102, interface and control logic circuit 124 (when on a separate IC), and external memory 126 may be included in stacked dies to form a multi-chip structure. Such a multi-chip structure can have a smaller package size and can be manufactured using reduced processing, thereby increasing yield and shortening the manufacturing time of the multi-chip structure.

[0025] Figure 2 shows a field-programmable gate array (FPGA) of programmable IC 200, which can be implemented as programmable IC 102 in Figure 1, in several examples. Programmable IC 200 includes a number of different programmable tiles, including configurable logic blocks (CLBs) 202, random access memory blocks (BRAMs) 204, signal processing blocks (DSPs) 206, input / output blocks (IOBs) 208, configuration and clocking logic (CONFIG / CLOCKS) 210, special input / output blocks (I / O) 212 (e.g., configuration ports and clock ports), and other programmable logic 214 such as a digital clock manager and system monitoring logic. Programmable IC 200 may also include boundary circuits such as MGT 216, memory controller (MC) 218, interface and control logic circuits (INT / CNTL) 220, and other IP circuits 222 such as PCIe interfaces and analog-to-digital converters (ADCs). Boundary circuits may also be programmable.

[0026] In some FPGAs, as shown in the example in Figure 2, each programmable tile may include at least one programmable interconnect element (INT) 230 having connections to the input and output terminals 232 of a programmable logic element within the same tile. Each programmable interconnect element 230 may also include connections to the interconnect segment 234 of an adjacent programmable interconnect element within the same tile or another tile. Each programmable interconnect element 230 may also include connections to the interconnect segment 236 of a general routing resource between logic blocks (not shown). A general routing resource may include a routing channel between a logic block (not shown) having a track of the interconnect segment (e.g., interconnect segment 236) and a switch block (not shown) connecting the interconnect segments. The interconnect segment of a general routing resource (e.g., interconnect segment 236) may span one or more logic blocks. The programmable interconnect element 230 implements the programmable interconnect structure for the FPGA shown, along with general routing resources.

[0027] In one exemplary implementation, CLB202 may include a configurable logic element (CLE) 240 that can be programmed to implement user logic, and a single programmable interconnect element 230. BRAM204 may include one or more programmable interconnect elements 230, in addition to BRAM logic elements (BRL) 242. Typically, the number of programmable interconnect elements 230 included in a single tile depends on the height of the tile. In the illustrated example, BRAM204 has the same height as five CLB202s, but a different number (e.g., four) may be used. Signal processing block 206 may include a suitable number of programmable interconnect elements 230, in addition to DSP logic elements (DSPL) 244. IOB208 may include, for example, one programmable interconnect element 230, in addition to two input / output logic elements (IOL) 246. As will be obvious to those skilled in the art, for example, the actual I / O pads connected to the input / output logic element 246 are not typically limited by the area of ​​the input / output logic element 246.

[0028] In the illustrated example, a horizontal area near the center of the die is used for the configuration and clocking logic (CONFIG / CLOCKS) 210, and possibly other control logic. A vertical column 248 extending from this horizontal area or column is used to distribute clock and configuration signals across the entire width of the FPGA.

[0029] Some FPGAs utilizing the architecture shown in Figure 2 may include additional logic blocks that disrupt the regular column structure that makes up the majority of the FPGA. These additional logic blocks may be programmable blocks and / or dedicated logic.

[0030] It should be noted that Figure 2 is intended solely to illustrate an exemplary FPGA architecture. For example, the number of logic blocks in a row, the relative width of the row, the number and order of the rows, the types of logic blocks contained in the row, the relative size of the logic blocks, and the interconnect / logic implementation included at the top of Figure 2 are merely examples. For example, in a real FPGA, to facilitate the efficient implementation of user logic, there are usually two or more adjacent CLB rows wherever CLBs appear, but the number of adjacent CLB rows will vary depending on the overall size of the FPGA.

[0031] Figure 3 is a schematic circuit diagram of a multi-chip structure in several examples. The multi-chip structure in Figure 3 includes a programmable IC 102 and a memory 302, the memory 302 may be located in multiple dies stacked on the die containing the programmable IC 102. As simplified in Figure 3, the programmable IC 102 includes a programmable logic area 110, a bus 304, a memory controller 112, and an interface and control logic circuit 124. The programmable logic area 110 (or processing system 104 and / or other subsystems such as NoC 106) is connected to the memory controller 112 via the bus 304, which may be, for example, an Advanced Extensible Interface (AXI) bus. The memory controller 112 is connected to the interface and control logic circuit 124.

[0032] Each of the memory 302 contains multiple memory slices 306. In some examples, each memory slice 306 may be 2 gigabytes (Gb) of memory or of other sizes. Each of the memory 302 can implement DRAM, and furthermore, HBM. In some examples, each of the memory 302 can implement 32 Gb of HBM DRAM. The interface and control logic circuit 124 is connected to the memory slices 306 of the memory 302. The interface and control logic circuit 124 can decode read and write requests from the memory controller 112 and, accordingly, send native signals to the memory 302 to read from or write to it. There is no standard physical layer interface circuit between the memory controller 112 and the memory slices 306 of the memory 302 for packaging read and write requests in a standard form, and for unpackaging read and write requests from a standard form. For example, if the memory 302 implements HBM, there is no HBM interface between the memory controller 112 and the memory slices 306.

[0033] Figure 4 is a schematic circuit diagram of another multi-chip structure with several examples. The multi-chip structure in Figure 4 is similar to the multi-chip structure in Figure 3, except that two die stacks containing memory 302 are stacked on the die containing the programmable IC 102. To accommodate the additional die stack containing memory 302, the programmable IC 102 further includes an additional bus 304, a memory controller 112, and interface and control logic circuits 124.

[0034] In the examples in Figures 3 and 4, the interface and control logic circuitry 124 is included in each die containing the programmable IC 102. In other examples, a separate control die (separate from the die containing the programmable IC 102) may contain the interface and control logic circuitry 124 and may be placed between the die containing the programmable IC 102 and the die stack containing the memory 302. The schematic circuit diagrams for such examples are the same as in Figures 3 and 4, except that they show a separate control die.

[0035] Figure 5 is a schematic schematic of a further multi-chip structure with several examples. The multi-chip structure of Figure 5 implements an HBM interface (for example, as a PHY interface) between the memory controller 112 and the memory slice 306. The multi-chip structure of Figure 5 includes a programmable IC 102, a control IC 502, and memory 302, wherein the control IC 502 is located in a separate die stacked on the die containing the programmable IC 102, and the memory 302 may be located in multiple dies stacked on the die containing the control IC 502. As simplified in Figure 5, the programmable IC 102 includes a programmable logic area 110, a bus 304, a memory controller 112, and an HBM interface (HBM PHY) 504. The programmable logic area 110 (or processing system 104 and / or other subsystems such as NoC 106) is connected to the memory controller 112 via the bus 304, and the memory controller 112 is connected to the HBM interface 504. The HBM interface 504 is configured to package read and write requests from the memory controller 112 into, for example, a standard HBM format, and to unpack responses from the memory 302 from the standard HBM format into a format usable by the memory controller 112.

[0036] The control IC 502 includes an HBM interface (HBM PHY) 506 and an interface and control logic circuit 124. The HBM interface 506 of the control IC 502 is connected to the HBM interface 504 of the programmable IC 102. The HBM interface 506 is configured to unpack read and write requests from the HBM interface 504, for example, from standard HBM format to a native format usable by the interface and control logic circuit 124, and to package responses from memory 302 into standard HBM format for transmission to the HBM interface 504 of the programmable IC 102. The interface and control logic circuit 124 can decode read and write requests from the HBM interface 506 and, accordingly, send native signals to memory 302 for reading or writing to memory 302 on various memory dies. The schematic circuit diagram in Figure 5 can be modified to implement a single memory die stack, as well as the differences in Figures 3 and 4.

[0037] Figure 6 shows the configuration of a multi-chip structure on a printed circuit board (PCB) 602 in several examples. This multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, and a memory die 608 stacked on the base die 606. The base die 606 includes a programmable IC 102, as shown in Figures 3 and / or 4, and the memory die 608 includes a memory 302, as shown in Figures 3 and / or 4.

[0038] This multi-chip structure includes a stack of four stacked memory dies 608, but other examples may implement any number of memory dies 608 in any number of stacks. Each memory die 608 has an external connector 610, such as a microbump, mounted on the active side of the memory die 608 and also on the back side of the lower die. Each memory die 608 may include through-substrate vias (TSVs) that pass through the semiconductor substrate on which the memory 302 of each memory die 608 is formed. These TSVs may be implemented to electrically connect the memory 302 of the upper memory die 608 to each memory die 608 and / or to the lower die.

[0039] The programmable IC 102 on the base die 606 includes an interface and control logic circuit 124 as shown in Figures 3 and / or 4. The bottom memory die 608 of the stack of memory dies 608 has an external connector 610 attached to the active side of the bottom memory die 608 and the back side of the base die 606. The base die 606 may include, for example, a TSV (Total Stationary Via) that passes through a semiconductor substrate on which the programmable IC 102 is formed. These TSVs may be implemented to electrically connect the memory 302 of the upper memory die 608 to the programmable IC 102. The base die 606 further has an external connector 612, such as a controlled collapse chip connection (C4) bump, attached to the active side of the base die 606 and also attached to the first side of the package substrate 604. The second side of the package substrate 604 opposite to the first side has an external connector 614 attached, such as a ball grid array (BGA) ball, which is further attached to the PCB 602.

[0040] Figure 7 shows another configuration of a multi-chip structure on PCB 602 by example. This multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, a control die 702 on the base die 606, and a memory die 608 stacked on the control die 702. The base die 606 includes a programmable IC 102, such as in Figures 3 and / or 4, which lacks the interface and control logic circuitry 124. The control die 702 includes a control IC, such as in Figures 3 and / or 4, which includes the interface and control logic circuitry 124. The memory die 608 each includes a memory 302, such as in Figures 3 and / or 4.

[0041] As shown in Figure 6, the multi-chip structure of Figure 7 includes a stack consisting of four stacked memory dies 608, but other examples may implement any number of memory dies 608 in any number of stacks. The bottom memory die 608 of the memory die 608 stack has an external connector 610 attached to the active side of the bottom memory die 608 and the back side of the control die 702. The control die 702 may include, for example, a TSV (Through-Side Via) through which the logic structure of the control die 702 (e.g., transistors) is formed on a semiconductor substrate. These TSVs may be implemented to electrically connect the memory 302 of the upper memory die 608 to the control IC (e.g., interface and control logic circuit 124) and / or programmable IC 102 of the control die 702. The active side of the control die 702 is attached to the back side of the base die 606. For example, the active side of the control die 702 may be bonded to the back side of the base die 606 by oxide-oxide and / or metal-metal bonding, for example, by wafer bonding or other bonding techniques. The base die 606 has an external connector 612 that is mounted on the active side of the base die 606 and also on the first side of the package substrate 604. The second side of the package substrate 604, opposite to the first side, is mounted on the external connector 614, which is further mounted on the PCB 602.

[0042] Figure 8 shows another configuration of a multi-chip structure on PCB 602, with some examples. This multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, a control die 802 on the base die 606, and a memory die 608 stacked on the control die 802. The base die 606 includes a programmable IC 102, as shown in Figure 5. More specifically, the programmable IC 102 also includes the HBM interface 504 shown in Figure 5. The control die 802 includes a control IC 502, as shown in Figure 5. More specifically, the control IC 502 on the control die 802 includes the interface and control logic circuit 124 and the HBM interface 506 shown in Figure 5. The memory die 608 each includes a memory 302, as shown in Figure 5.

[0043] As shown in Figure 6, the multi-chip structure in Figure 8 includes a stack consisting of four stacked memory dies 608, but other examples may implement any number of memory dies 608 in any number of stacks. The bottom memory die 608 of the memory die 608 stack has an external connector 610 attached to the active side of the bottom memory die 608 and the back side of the control die 802. The control die 802 may include, for example, a TSV (Through-Side Via) that passes through a semiconductor substrate on which the logic structure (e.g., transistors) of the control IC 502 is formed. These TSVs may be implemented to electrically connect the memory 302 of the upper memory die 608 to the control IC 502 and / or programmable IC 102 of the control die 802. The control die 802 has an external connector 804, such as a microbump, attached to the active side of the control die 802 and also attached to the back side of the base die 606. The base die 606 has an external connector 612 that is mounted on the active side of the base die 606 and also on the first side of the package substrate 604. The second side of the package substrate 604, opposite to the first side, is mounted on the external connector 614, which is further mounted on the PCB 602.

[0044] Various multi-chip structures have been described with respect to Figures 6 to 8, along with various dies having predetermined orientations (e.g., a specific active surface of a die mounted on the back of another die), but such orientations are provided as examples. Any die (e.g., any of the base die 606, memory die 608, control die 702, and / or control die 802) can be reversed relative to the descriptions provided above, or have any other orientation.

[0045] The multi-chip structure described above may be a programmably accessible high-density memory device. A programmable device with high-density memory utilizing HBM logic and stacking technology can be implemented using the structure described above. The performance advantages associated with programmable ICs (e.g., FPGAs) can be maintained while enabling faster, simpler, and lower-cost manufacturing, and consuming less power.

[0046] Several examples can be implemented using various programmable ICs. For example, the programmable IC may be an application-specific standard (ASSP) IC with configurable input / output circuits and interfaces. Some examples can be implemented using multi-port memory with host interfaces such as nx PCIe Genx, nx 100GE, nx 40G, nx 10GE, and 112G PAM4.

[0047] Figure 9 is a flowchart of method 900 for forming a multi-chip structure with some examples. In block 902, a base die is formed. This base die may be, for example, the base die 606 in Figures 6 to 8, and may be formed by front and back surface semiconductor processing on which a programmable IC and TSV are mounted.

[0048] Optionally, in block 904, a control die is formed. This control die may be, for example, the control dies 702 and / or 802 in Figures 7 and / or 8, and may be formed by front and back semiconductor processing to mount the control IC and TSV on the control die. Optionally, in block 906, the control die is mounted to the base die. For example, the control die may be bonded to the base die by wafer-to-wafer bonding during the processing of the control die and the base die (e.g., before the dies are separated). In another example, the control die may be mounted to the base die using an external connector such as a microbump, which may involve reflowing the external connector to mount the control die to the base die. In some examples, the control die is not mounted, such as to form the multi-chip structure in Figure 6, and therefore, the formation of the control die in block 904 and the mounting of the control die to the base die in block 906 may be omitted.

[0049] In block 908, a stack of memory dies is formed. This stack of memory dies may be, for example, the memory die 608 shown in Figures 6 to 8, and each memory die may be formed by front and back semiconductor processing to mount memory and TSVs on the memory die, except that the topmost memory die may omit back semiconductor processing and TSVs. The memory dies may be attached to each other within the stack using external connectors such as microbumps, which may include reflowing the external connectors to attach the memory dies together.

[0050] In block 910, the stack of memory dies is mounted to the base die, or to the control die if a control die is mounted. The stack of memory dies may be mounted to the base die (for example, as shown in Figure 6) or to the control die (for example, as shown in Figure 7 or 8) using external connectors such as microbumps, which may include reflowing the external connectors to mount the stack of memory dies to the base die or the control die. As noted above, the order of operations may be changed. For example, if a control die is mounted as shown in Figure 8, the stack of memory dies may be mounted to the control die before the control die is mounted to the base die.

[0051] In block 912, the base die is mounted to a package substrate. This package substrate may be, for example, the package substrate 604 shown in Figures 6 to 8, and may be mounted to the base die using an external connector such as a C4 bump, which may include reflowing the external connector to mount the base die to the package substrate.

[0052] In block 914, the package substrate is mounted to the PCB. This PCB substrate may be, for example, PCB 602 in Figures 6 to 8, and may be mounted to the package substrate using external connectors such as BGA balls, which may include reflowing the external connectors to mount the package substrate to the PCB.

[0053] According to some examples, a multi-chip structure includes a package substrate, a first die, and a second die. The first die contains a programmable integrated circuit. The programmable integrated circuit contains a memory controller. The first die is located on the package substrate and is mounted to the package substrate. The second die contains memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

[0054] In some of the examples of the multi-chip structures described above, the first die may include a semiconductor substrate. Through-substrate vias (TSVs) may pass through this semiconductor substrate. A memory controller may be communicatively coupled to the memory via the TSVs.

[0055] In some of the above examples of multi-chip structures, the second die may be attached to the side of the first die opposite to the package substrate by an external electrical connector.

[0056] In some of the multi-chip structures described above, the physical layer interface does not need to be electrically arranged to enable communication between the memory controller and the memory.

[0057] In some of the above examples of multi-chip structures, the first die may include control logic circuitry, which may be arranged to communicate between the memory controller and the memory.

[0058] In some examples, the multi-chip structure described above may further include a third die containing control logic circuitry. The third die may be stacked and mounted on the surface of the first die opposite to the package substrate. The second die may be stacked and mounted on the surface of the third die opposite to the first die. The control logic circuitry may be arranged to communicate between the memory controller and the memory. The third die may be bonded to the first die. The third die may be mounted to the surface of the first die opposite to the package substrate by an external electrical connector. The second die may be mounted to the surface of the third die opposite to the first die by an external electrical connector. The physical layer interface does not have to be electrically arranged to communicate between the memory controller and the memory. The first die may include a first physical layer interface that is communicatively coupled to the memory controller. The third die is communicatively coupled to the first physical layer interface and the control logic circuitry, and may include a second physical layer interface between the first physical layer interface and the control logic circuitry.

[0059] In some of the examples of the multi-chip structures described above, the programmable integrated circuit includes a field-programmable gate array (FPGA).

[0060] According to some examples, a method for forming a multi-chip structure includes stacking a first die on a second die and mounting the first die on a package substrate. The first die includes memory. The second die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The memory controller is communicatively coupled to the memory by the first die stacked on the second die.

[0061] In some examples of the above methods, stacking the first die on the second die may include attaching the first die to the second die by an external electrical connector, the second die may include control logic circuitry, the control logic circuitry may be arranged to communicate between the memory controller and the memory, and the physical layer interface may not need to be electrically arranged to communicate between the memory controller and the memory.

[0062] In some examples, the above method may further include mounting a third die onto a second die. The first die may be mounted onto the third die. The third die may include control logic circuitry. The control logic circuitry may be arranged to communicate between the memory controller and the memory.

[0063] According to some examples, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a field-programmable gate array (FPGA) and a memory controller. The first die is located on and mounted to the package substrate. The second die contains memory. The second die is stacked on the side of the first die opposite to the package substrate. The memory is communicatively coupled to the memory controller.

[0064] In some of the multi-chip structures described above, the physical layer interface does not need to be electrically arranged to enable communication between the memory controller and the memory.

[0065] In some of the examples of the multi-chip structures described above, the first die may include control logic circuitry. This control logic circuitry may be arranged to communicate between the memory controller and the memory.

[0066] In some examples, the multi-chip structure described above may further include a third die comprising control logic circuitry. The third die may be stacked and mounted on the surface of the first die opposite to the package substrate. The second die may be stacked and mounted on the surface of the third die opposite to the first die. The control logic circuitry may be arranged communicatively between the memory controller and the memory. The first die may include a first physical layer interface communicatively coupled to the memory controller. The third die may include a second physical layer interface communicatively coupled to the first physical layer interface and the control logic circuitry, and located between the first physical layer interface and the control logic circuitry.

[0067] While the above describes specific examples, further examples can be devised without deviating from the basic scope of those examples, and the scope of those examples is determined by the following claims.

Claims

1. A package substrate; a first die comprising a programmable integrated circuit, the programmable integrated circuit including a memory controller, the first die being on and attached to the package substrate; a second die comprising a memory, the second die being stacked on the first die, the memory being communicatively coupled to the memory controller; and A multi-chip structure comprising:

2. 2. The multi-chip structure of claim 1, wherein the first die includes a semiconductor substrate having through-substrate vias (TSVs) extending through the semiconductor substrate, and the memory controller is communicatively coupled to the memory through the TSVs.

3. 10. The multi-chip structure of claim 1, wherein the second die is attached to a side of the first die opposite the package substrate by an external electrical connector.

4. 2. The multi-chip structure of claim 1, wherein a physical layer interface is not communicatively electrically disposed between said memory controller and said memory.

5. 2. The multi-chip structure of claim 1, wherein the first die includes a control logic circuit, the control logic circuit being communicatively disposed between the memory controller and the memory.

6. 10. The multi-chip structure of claim 1, further comprising: a third die comprising a control logic circuit, the third die stacked on and attached to a side of the first die opposite the package substrate; the second die stacked on and attached to a side of the third die opposite the first die; and the control logic circuit disposed in communication between the memory controller and the memory.

7. The multi-chip structure of claim 6 , wherein the third die is bonded to the first die.

8. 7. The multi-chip structure of claim 6, wherein the third die is attached to the side of the first die opposite the package substrate by an external electrical connector.

9. 7. The multi-chip structure of claim 6, wherein the second die is attached to the face of the third die opposite the first die by an external electrical connector.

10. 7. The multi-chip structure of claim 6, wherein a physical layer interface is not communicatively electrically disposed between the memory controller and the memory.

11. the first die includes a first physical layer interface communicatively coupled to the memory controller; the third die is communicatively coupled to the first physical layer interface and the control logic circuit, and includes a second physical layer interface between the first physical layer interface and the control logic circuit; 7. The multi-chip structure of claim 6.

12. 10. The multi-chip structure of claim 1, wherein the programmable integrated circuit comprises a field programmable gate array (FPGA).

13. 1. A method of forming a multi-chip structure, the method comprising: stacking a first die over a second die, the first die comprising a memory, the second die comprising a programmable integrated circuit, the programmable integrated circuit including a memory controller, the memory controller communicatively coupled to the memory by the first die stacked over the second die; and attaching the first die to a package substrate.

14. stacking the first die on the second die includes attaching the first die to the second die by an external electrical connector; the second die includes a control logic circuit, the control logic circuit being communicatively disposed between the memory controller and the memory; a physical layer interface is not communicatively electrically disposed between the memory controller and the memory; The method of claim 13.

15. 14. The method of claim 13, further comprising attaching a third die to the second die, the first die attached to the third die, the third die comprising control logic circuitry, the control logic circuitry disposed in communication between the memory controller and the memory.

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