Semiconductor device and method for manufacturing the same

Abstract

This semiconductor device comprises an insulating substrate (3), a semiconductor element (4) joined to the insulating substrate (3), and an internal wiring member (5) joined to the semiconductor element (4). The insulating substrate (3) has a conductive pattern (2) on the upper surface thereof. The semiconductor element (4) has an upper surface electrode on the upper surface thereof and a lower surface electrode on the lower surface thereof, wherein the lower surface electrode is joined to the conductive pattern (2) of the insulating substrate (3). The internal wiring member (5) is joined to the upper surface electrode of the semiconductor element (4). The lower surface electrode and the conductive pattern (2), and the upper surface electrode and the internal wiring member (5) are each joined together by means of an Al brazing material (81, 82).

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device, and more particularly to a technique for simultaneously connecting wiring members to a plurality of semiconductor elements mounted on a substrate.

[0002] BACKGROUND ART Semiconductor devices are known that have a configuration in which a plurality of semiconductor elements, such as insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field-effect transistors (MOSFETs), and diodes, are mounted on a substrate. Metallic upper and lower electrodes are formed on the front and back surfaces (hereinafter referred to as "top and bottom surfaces") of the semiconductor elements, respectively. The top electrodes are bonded to wiring members, and the bottom electrodes are bonded to the substrate, typically using a brazing filler metal such as solder (see, for example, Patent Document 1 listed below). It has also been proposed to bond the bottom electrodes to the substrate using a brazing filler metal (hereinafter referred to as "Al brazing filler metal") primarily composed of aluminum (Al), which has better heat dissipation and heat resistance than solder (see, for example, Patent Document 2 listed below).

[0003] JP 2016-72575 A JP 2013-71873 A

[0004] When using solder to join the upper electrode of a semiconductor element to a wiring member and the lower electrode to a substrate, it is necessary to first join the lower electrode to the substrate and then join the upper electrode to the wiring member, which increases the takt time.

[0005] In recent years, there has been an increasing demand for improved performance and a wider operating temperature range for power control semiconductor devices, and semiconductor elements formed from wide bandgap semiconductors such as SiC and GaN are increasingly being put to practical use. However, when applying a semiconductor element made of SiC to a semiconductor device having the above-mentioned structure, the following problems arise.

[0006] First, SiC semiconductor elements can increase current density, allowing chip sizes to be reduced, but reducing the chip size increases thermal resistance, necessitating measures to reduce the thermal resistance of the surrounding structure. Additionally, while SiC semiconductor elements can operate at high temperatures, the melting point of the solder is low, and the operating temperature is determined by the melting point of the solder.

[0007] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that can contribute to reducing the number of manufacturing steps, reducing thermal resistance, and expanding the operating temperature.

[0008] The semiconductor device according to the present disclosure comprises an insulating substrate having a conductive pattern on its upper surface, a semiconductor element having an upper electrode on its upper surface and a lower electrode on its lower surface, the lower electrode being bonded to the conductive pattern of the insulating substrate, and an internal wiring member bonded to the upper electrode of the semiconductor element, wherein the bonding between the lower electrode and the conductive pattern and the bonding between the upper electrode and the internal wiring member are achieved by an Al brazing filler metal, which is a brazing filler metal primarily composed of Al.

[0009] The present disclosure can contribute to reducing the number of manufacturing steps for a semiconductor device, reducing thermal resistance, and expanding the operating temperature range.

[0010] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0011] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment; FIG. 2 is a plan view showing an example of the overall configuration of a semiconductor device according to the first embodiment; FIG. 3 is a diagram showing an example of the configuration of a switching element; FIG. 4 is a diagram showing an example of the configuration of a free wheel diode; FIG. 5 is a flowchart for explaining a manufacturing method of a semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing method of a semiconductor device according to the first embodiment; FIG. 7 is a plan view showing a configuration of a semiconductor device according to a second embodiment; FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment; FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment;

[0012] <First Preferred Embodiment> Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first preferred embodiment. As shown in Fig. 1, the semiconductor device according to the first preferred embodiment includes a base plate 1, an insulating substrate 3 mounted on the base plate 1 and having conductive patterns 2 on its upper and lower surfaces, and a semiconductor element 4 mounted on the conductive patterns 2 of the insulating substrate 3. The base plate 1 shown in Fig. 1 is flat, but a base plate 1 with pin fins may also be used.

[0013] The semiconductor element 4 has an upper electrode (not shown) on its upper surface and a lower electrode (not shown) on its lower surface, and the lower electrode is joined to the conductive pattern 2 of the insulating substrate 3 using an Al brazing filler metal 81. Furthermore, the internal wiring member 5 is joined to the upper electrode of the semiconductor element 4 using an Al brazing filler metal 82. In other words, both the joining between the lower electrode and the conductive pattern 2 and the joining between the upper electrode and the internal wiring member 5 are achieved with an Al-based brazing filler metal.

[0014] The composition of the Al brazing filler metal 81 that joins the lower electrode and the conductive pattern 2 may be the same as the composition of the Al brazing filler metal 82 that joins the upper electrode and the internal wiring member 5. This allows the melting points of the Al brazing filler metal 81 and the Al brazing filler metal 82 to be the same. Furthermore, the conductive pattern 2 of the insulating substrate 3, the upper and lower electrodes of the semiconductor element 4, and the internal wiring member 5 are preferably made of a material containing Al as a main component.

[0015] 1, a portion of the internal wiring member 5 is connected to the conductive pattern 2 of the insulating substrate 3 using a brazing filler metal 83. This brazing filler metal 83 does not necessarily have to be an Al brazing filler metal, but is preferably an Al brazing filler metal.

[0016] A case 11 accommodating an insulating substrate 3, a semiconductor element 4, and an internal wiring member 5 is adhered to the base plate 1 using an adhesive 10, and the insulating substrate 3, the semiconductor element 4, and the internal wiring member 5 are sealed with a sealant 12 filled in the case 11. The case 11 is provided with an external wiring member 6 serving as an external connection terminal formed integrally with the case 11, and the external wiring member 6 is joined to the conductive pattern 2 of the insulating substrate 3 using a brazing filler metal 84. The brazing filler metal 84 does not necessarily have to be an Al brazing filler metal, but is preferably an Al brazing filler metal.

[0017] Furthermore, the portion of the internal wiring member 5 that connects to the semiconductor element 4 preferably has a size equal to or larger than the outer shape of the semiconductor element 4. In other words, the width of the joint portion of the internal wiring member 5 that connects to the top electrode of the semiconductor element 4 is preferably equal to or larger than the width of the semiconductor element 4.

[0018] Furthermore, in the semiconductor device according to the first embodiment, both the bonding between the conductive pattern 2 and the semiconductor element 4 and the bonding between the semiconductor element 4 and the internal wiring member 5 are achieved by using an Al brazing filler metal. The thermal conductivity of the Al brazing filler metal (170 W / m·K) is higher than that of conventional solder (55 W / m·K), which contributes to reducing the thermal resistance of the semiconductor device. Furthermore, the melting point of the Al brazing filler metal (approximately 600°C) is higher than that of conventional solder (approximately 220°C), which contributes to increasing the operating temperature of the semiconductor device. Therefore, the first embodiment is particularly effective for semiconductor devices including a semiconductor element 4 made of a wide bandgap semiconductor such as SiC or GaN, which can operate at high temperatures.

[0019] 2 is a plan view showing an example of the overall configuration of the semiconductor device according to the first embodiment. The cross-sectional view shown in FIG. 1 corresponds to the cross-section taken along line AB shown in FIG.

[0020] 2 constitutes a three-phase inverter circuit and includes, as semiconductor elements 4, six switching elements 4a-4f and six free wheel diodes 4g-4l. Also provided are internal wiring members 5, including an internal wiring member 5a joined to switching element 4a and free wheel diode 4g, an internal wiring member 5b joined to switching element 4b and free wheel diode 4h, an internal wiring member 5c joined to switching element 4c and free wheel diode 4i, an internal wiring member 5d joined to switching element 4d and free wheel diode 4j, an internal wiring member 5e joined to switching element 4e and free wheel diode 4k, and an internal wiring member 5f joined to switching element 4f and free wheel diode 4l. Also provided are external wiring members 6a and 6b serving as input terminals of the inverter, and external wiring members 6c, 6d, and 6e serving as output terminals of the inverter.

[0021] 2, all six internal wiring members 5 (5a to 5f) bonded to multiple semiconductor elements 4 (4a to 4l) have the same shape. This makes it possible to reduce costs (e.g., manufacturing costs and management costs) associated with the internal wiring members 5. All of the multiple internal wiring members 5 do not have to have the same shape; as long as two or more of the multiple internal wiring members 5 have the same shape, the cost reduction effect can be achieved.

[0022] 2 also includes a plurality of signal terminals 7 for inputting control signals for the switching elements 4a to 4f. Each of the signal terminals 7 is connected via bonding wires 9 to a signal pad (signal pad 14 in FIG. 3, which will be described later) of one of the switching elements 4a to 4f.

[0023] The switching elements 4a to 4f are, for example, IGBTs or MOSFETs. Fig. 3 shows a configuration example of the switching elements 4a to 4f, showing a top view and a cross-sectional view of the switching elements 4a to 4f. In the example of Fig. 3, an insulating layer 13 is formed on the ineffective regions of the switching elements 4a to 4f, and an electrode 15 made of an Al-based material (hereinafter referred to as "Al electrode") is formed as a top electrode on the entire top surface of the switching elements 4a to 4f except for the region of the signal pad 14, and the insulating layer 13 is covered by the Al electrode 15.

[0024] The freewheeling diodes 4g to 4l are, for example, Schottky barrier diodes or PN junction diodes. Fig. 4 shows a configuration example of the freewheeling diodes 4g to 4l, showing a top view and a cross-sectional view of the freewheeling diodes 4g to 4l. In the example of Fig. 4, an insulating layer 13 is formed on the ineffective region of the freewheeling diodes 4g to 4l, and an Al electrode 15 serving as a top electrode is formed on the entire top surface of the freewheeling diodes 4g to 4l, with the insulating layer 13 being covered by the Al electrode 15.

[0025] 1 to 4 show an example in which the semiconductor element 4 serving as a switching element and the semiconductor element 4 serving as a free wheel diode are separate elements, but the semiconductor element 4 may also be a MOSFET or an RC-IGBT (Reverse Conducting IGBT) that incorporates both the switching element and the free wheel diode.

[0026] Hereinafter, the method for manufacturing the semiconductor device according to the first embodiment, particularly the procedure for joining the semiconductor element 4 to the insulating substrate 3 and the internal wiring member 5, will be described with reference to the flowchart of FIG.

[0027] First, an insulating substrate 3 mounted on a base plate 1 is prepared, and a first Al brazing material 81 is placed on the conductive pattern 2 of the insulating substrate 3 (step S1). Next, a semiconductor element 4 is placed on the first Al brazing material (Al brazing material 81) (step S2). Next, a second Al brazing material 82 is placed on the semiconductor element 4 (step S3). Furthermore, an internal wiring member 5 is placed on the second Al brazing material (Al brazing material 82) (step S4). As a result, as shown in FIG. 6 , the Al brazing material 81, the semiconductor element 4, the Al brazing material 82, and the internal wiring member 5 are stacked in this order on the conductive pattern 2 of the insulating substrate 3. The Al brazing material 81, the semiconductor element 4, the Al brazing material 82, and the internal wiring member 5 placed in steps S1 to S4 may be temporarily fixed with an adhesive or the like to prevent misalignment.

[0028] Thereafter, a heat treatment is performed while applying pressure from above to the internal wiring member 5 (step S5). This heat treatment bonds the semiconductor element 4 and the conductive pattern 2 together with the first Al brazing material (Al brazing material 81), and bonds the semiconductor element 4 and the internal wiring member 5 together with the second Al brazing material (Al brazing material 82).

[0029] As described above, with the semiconductor device according to the first embodiment, the bonding between the conductive pattern 2 and the semiconductor element 4 and the bonding between the semiconductor element 4 and the internal wiring member 5 can be performed simultaneously, which contributes to reducing the number of manufacturing steps. Furthermore, when solder is used as the brazing material, it is necessary to provide a layer for solder bonding (for example, a Ni layer) on the surfaces of the upper and lower electrodes of the semiconductor element 4, but this is no longer necessary, which also contributes to reducing the number of manufacturing steps.

[0030] 1 , when a portion of the internal wiring member 5 is joined to the conductive pattern 2 of the insulating substrate 3, the brazing filler metal 83 for this joining is also preferably an Al brazing filler metal. In this way, the joining of the internal wiring member 5 and the conductive pattern 2 can be carried out simultaneously with step S5. In addition, the brazing filler metal 83 also preferably has the same composition as the Al brazing filler metals 81 and 82.

[0031] Similarly, the brazing filler metal 84 that joins the external wiring member 6 and the conductive pattern 2 of the insulating substrate 3 is preferably an Al brazing filler metal. This allows the joining of the external wiring member 6 and the conductive pattern 2 to be performed simultaneously with step S5, further contributing to reducing the number of manufacturing processes. In addition, the brazing filler metal 84 preferably has the same composition as the Al brazing filler metals 81 and 82.

[0032] Furthermore, the conductive pattern 2 of the insulating substrate 3 may be formed from a clad material of an Al brazing material and an Al alloy, making the Al brazing material 81 an integral part of the insulating substrate 3. A "clad material" refers to a material made by bonding two or more different metals together. This allows the omission of step S1, further contributing to a reduction in the manufacturing process. Furthermore, the reduction in the number of parts also contributes to a reduction in part management costs.

[0033] Similarly, the internal wiring member 5 may be formed from a clad material of an Al brazing material and an Al alloy, so that the Al brazing material 82 is an integral part of the internal wiring member 5. This makes it possible to omit step S3, further contributing to reducing the number of manufacturing processes. Furthermore, the reduction in the number of parts also contributes to reducing the cost of managing parts.

[0034] 3 and 4, it is preferable that an upper surface electrode is formed over almost the entire upper surface of the semiconductor element 4, and further that the width of the joint portion of the internal wiring member 5 with the upper surface electrode of the semiconductor element 4 is equal to or greater than the width of the semiconductor element 4. By doing so, pressure can be applied to the entire semiconductor element 4 in the heat treatment of step S5 described above, and the joint between the semiconductor element 4 and the conductive pattern 2 and the internal wiring member 5 can be stably performed.

[0035] 2, when a plurality of semiconductor elements 4 are arranged on the insulating substrate 3, the heat treatment in step S5 can be performed simultaneously on the plurality of semiconductor elements 4. Therefore, even if the number of semiconductor elements 4 increases, an increase in the takt time is suppressed.

[0036] As described above, the semiconductor device according to the first embodiment can contribute to reducing the number of manufacturing steps, reducing thermal resistance, and expanding the operating temperature range.

[0037] <Second Embodiment> Fig. 7 is a plan view showing the configuration of a semiconductor device according to a second embodiment. Fig. 7 corresponds to a part of the plan view of the semiconductor device shown in Fig. 2, but the signal pads 14 of the semiconductor element 4 and the signal terminals 7 are connected by signal wiring members 17 instead of bonding wires 9. Fig. 8 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment, showing a cross section taken along line CD shown in Fig. 7, i.e., a cross section including the signal wiring members 17.

[0038] 7 , the signal wiring member 17 and the semiconductor element 4 are joined by an Al brazing material 85, and the signal wiring member 17 and the signal terminal 7 are joined by an Al brazing material 86. The Al brazing material 85 and the Al brazing material 86 preferably have the same composition as the Al brazing material 81 and the Al brazing material 82. Similarly to the internal wiring member 5, the signal wiring member 17 is preferably formed from a material containing Al as its main component.

[0039] According to the semiconductor device of embodiment 2, the connection between the semiconductor element 4 and the signal terminal 7 (i.e., the joining between the semiconductor element 4 and the signal wiring member 17 and the joining between the signal terminal 7 and the signal wiring member 17) can be performed simultaneously with step S5 of FIG. 5, which can further contribute to reducing the manufacturing process.

[0040] 9 is a plan view showing the configuration of a semiconductor device according to embodiment 3. In embodiment 3, as shown in Fig. 9, a core material 19 of a certain thickness is inserted into a brazing material 81 between the lower electrode of semiconductor element 4 and conductive pattern 2, and into a brazing material 82 between the upper electrode of semiconductor element 4 and internal wiring member 5. The material of core material 19 may be, for example, Al or a clad material of an Al brazing material and an Al alloy.

[0041] According to the semiconductor device of the third embodiment, the core material 19 is inserted into the Al brazing filler metal 81 and the Al brazing filler metal 82, which ensures the thickness of the Al brazing filler metal 81 and the Al brazing filler metal 82 and makes the thickness of the Al brazing filler metal 81 and the Al brazing filler metal 82 uniform, thereby preventing tilt of the semiconductor element 4. Eliminating tilt of the semiconductor element 4 contributes to stabilizing the thermal resistance of the semiconductor device and stabilizing the manufacturing process.

[0042] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0043] The above description is illustrative in all respects, and it is understood that countless variations not illustrated can be envisioned.

[0044] REFERENCE SIGNS LIST 1 base plate, 2 conductive pattern, 3 insulating substrate, 4 semiconductor element, 5 internal wiring member, 6 external wiring member, 7 signal terminal, 81, 82 Al brazing material, 83, 94 brazing material, 85, 86 Al brazing material, 9 bonding wire, 10 adhesive, 11 case, 12 sealing material, 13 insulating layer, 14 signal pad, 15 Al electrode, 17 signal wiring member, 19 core material.

Claims

1. A semiconductor device comprising: an insulating substrate having a conductive pattern on its upper surface; a semiconductor element having an upper electrode on its upper surface and a lower electrode on its lower surface, the lower electrode being bonded to the conductive pattern of the insulating substrate; and an internal wiring member bonded to the upper electrode of the semiconductor element, wherein the bonding between the lower electrode and the conductive pattern, and the bonding between the upper electrode and the internal wiring member are achieved with an Al brazing filler metal, which is a brazing filler metal whose main component is Al.

2. The semiconductor device according to claim 1, wherein the conductive pattern of the insulating substrate, the upper and lower electrodes of the semiconductor element, and the internal wiring member are formed from a material containing Al as a main component.

3. The semiconductor device according to claim 1 or 2, wherein the width of the joint portion of the internal wiring member with the upper surface electrode is equal to or greater than the width of the semiconductor element.

4. A semiconductor device according to any one of claims 1 to 3, wherein the composition of the Al brazing material joining the lower electrode and the conductive pattern is the same as the composition of the Al brazing material joining the upper electrode and the internal wiring member.

5. The semiconductor device according to any one of claims 1 to 4, further comprising an external wiring member bonded to the conductive pattern, wherein the bonding between the conductive pattern and the external wiring member is also achieved by an Al brazing material.

6. A semiconductor device according to any one of claims 1 to 5, wherein the semiconductor element further has a signal pad on an upper surface, the semiconductor device further comprises: a signal terminal; and a signal wiring member connecting the signal pad and the signal terminal, and the bonding between the signal pad and the signal wiring member and the bonding between the signal terminal and the signal wiring member are also achieved by Al brazing material.

7. The semiconductor device according to any one of claims 1 to 6, wherein one or both of the conductive pattern and the internal wiring member are formed from a clad material of an Al brazing material and an Al alloy.

8. A semiconductor device according to any one of claims 1 to 7, wherein a core material of a certain thickness is inserted into the brazing material between the lower electrode and the conductive pattern, and into the brazing material between the upper electrode and the internal wiring member.

9. The semiconductor device according to any one of claims 1 to 8, comprising a plurality of the semiconductor elements.

10. The semiconductor device according to claim 9, wherein two or more of the plurality of internal wiring members bonded to the plurality of semiconductor elements have the same shape.

11. A method for manufacturing a semiconductor device, comprising the steps of: placing a first Al brazing material on a conductive pattern provided on an insulating substrate; placing a semiconductor element on the first Al brazing material; placing a second Al brazing material on the semiconductor element; placing an internal wiring member on the second Al brazing material; and applying pressure from above to the internal wiring member while performing heat treatment, thereby joining the semiconductor element and the conductive pattern with the first Al brazing material and joining the semiconductor element and the internal wiring member with the second Al brazing material.

12. The method for manufacturing a semiconductor device according to claim 11, wherein a plurality of the semiconductor elements are arranged on the insulating substrate, and the step of bonding the semiconductor elements to the conductive pattern and the internal wiring member is performed simultaneously for the plurality of semiconductor elements.

13. The method for manufacturing a semiconductor device according to claim 12, wherein two or more of the plurality of internal wiring members bonded to the plurality of semiconductor elements have the same shape.

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