Semiconductor device manufacturing method, semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device capable of reducing contact resistance between a silicon carbide layer and a metal electrode.SOLUTION: A manufacturing method of a semiconductor device includes: performing first ion implantation for implanting a p-type impurity into a silicon carbide layer; performing second ion implantation for implanting carbon (C) into the silicon carbide layer; performing first heat treatment for activating the p-type impurity; performing first oxidization processing for oxidizing the silicon carbide layer; performing etching processing for etching the silicon carbide layer in a hydrogen gas containing atmosphere; performing second heat treatment for forming a first metal film containing at least one metal element selected from among nickel (Ni), palladium (Pd), platinum (Pt) and chrome (Cr) on the silicon carbide layer and forming a metal silicide layer containing at least one metal element by reacting the silicon carbide layer and the first metal film; and forming a second metal film of a different chemical composition from that of the first metal film on the silicon carbide layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has excellent physical properties, such as a band gap about three times larger, a breakdown electric field strength about ten times larger, and a thermal conductivity about three times larger. By utilizing these properties, it is possible to realize semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] In devices using silicon carbide, it is desirable to reduce the contact resistance between a silicon carbide layer and a metal electrode in order to improve the device characteristics. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2021-145112 A [Patent Document 2] International Publication No. 2014 / 155651 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of reducing the contact resistance between a silicon carbide layer and a metal electrode. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to an embodiment includes: performing a first ion implantation step of implanting a p-type impurity into a silicon carbide layer at a first projected range and a first dose; performing a second ion implantation step of implanting carbon (C) into the silicon carbide layer at a second projected range and a second dose; performing a first heat treatment step of activating the p-type impurity; performing a first oxidation treatment step of oxidizing the silicon carbide layer; performing an etching treatment step of etching the silicon carbide layer in an atmosphere containing hydrogen gas; forming a first metal film on the silicon carbide layer, the first metal film including at least one metal element selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr); and reacting the silicon carbide layer with the first metal film to form a first metal film including at least one metal element selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr). of A second heat treatment is performed to form a metal silicide layer containing a metal element, and a second metal film having a different chemical composition from the first metal film is formed on the silicon carbide layer. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a process flow diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Diagram 3] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are explanatory views of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 5A to 5C are views showing the operation and effect of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 5A to 5C are views showing the operation and effect of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 5A to 5C are explanatory diagrams illustrating the operation and effect of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 21] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 22] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 23] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 24] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 25] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 26] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 27] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 28] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 29] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 30]5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 31] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 32] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 33] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 34] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 35] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 36] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 37] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 38] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Figure 39] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 40] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 41] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 42] 5A to 5C are schematic cross-sectional views showing a method for manufacturing the semiconductor device according to the second embodiment. [Diagram 43] FIG. 13 is a schematic diagram of a drive device according to a third embodiment. [Diagram 44] FIG. 13 is a schematic diagram of a vehicle according to a fourth embodiment. [Diagram 45] FIG. 13 is a schematic diagram of a vehicle according to a fifth embodiment. [Diagram 46] FIG. 13 is a schematic diagram of an elevator according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - And, p + , p, p - When the notation "n" is used, it indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The types are simply n-type and p-type. + type, p - The type may be simply referred to as p-type. The impurity concentration of each region is represented by, for example, the impurity concentration value at the center of each region, unless otherwise specified.

[0010] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained, for example, by SCM (Scanning Capacitance Microscopy). Distances such as the width and depth of the impurity region can be obtained, for example, by SIMS. Distances such as the width and depth of the impurity region can also be obtained, for example, from an SCM image.

[0011] The thickness of the insulating layer can be measured, for example, on an image of a SIMS or a TEM (Transmission Electron Microscope).

[0012] The magnitude relationship between the proportion of metal elements in a silicon carbide layer located at the silicon sites of the silicon carbide crystal structure, the proportion located at the carbon sites of the silicon carbide crystal structure, and the proportion located between the lattices of the silicon carbide crystal structure can be determined by using, for example, Raman spectroscopy or X-ray photoelectron spectroscopy (XPS).

[0013] To identify the silicide phase present in the metal silicide layer and to determine the magnitude relationship of the amount of the silicide phase present in the metal silicide layer, for example, X-ray photoelectron spectroscopy (XPS), infrared spectroscopy, or Raman spectroscopy is used.

[0014] (First embodiment) A method for manufacturing a semiconductor device according to a first embodiment includes a first ion implantation step of implanting a p-type impurity into a silicon carbide layer with a first projected range and a first dose, a second ion implantation step of implanting carbon (C) into the silicon carbide layer with a second projected range and a second dose, a first heat treatment step of activating the p-type impurity, a first oxidation treatment step of oxidizing the silicon carbide layer, an etching treatment step of etching the silicon carbide layer in an atmosphere containing hydrogen gas, forming a first metal film on the silicon carbide layer, the first metal film containing at least one metal element selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr), and a second heat treatment step of reacting the silicon carbide layer with the first metal film to form a metal silicide layer containing at least one metal element, and forming a second metal film on the silicon carbide layer, the second metal film having a different chemical composition from the first metal film.

[0015] 1 is a schematic cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a semiconductor device including a contact structure 100.

[0016] The contact structure 100 includes a silicon carbide layer 10 , a contact electrode 11 , a metal silicide layer 13 , and an insulating layer 15 .

[0017] The silicon carbide layer 10 includes a low concentration p-type region 16 and a high concentration p-type region 17 .

[0018] The silicon carbide layer 10 is, for example, a single crystal of 4H-SiC. The silicon carbide layer 10 has a first face F1 and a second face F2. The second face F2 faces the first face F1. The first face F1 is a front face of the silicon carbide layer 10, and the second face F2 is a back face of the silicon carbide layer 10.

[0019] In the first embodiment, the “depth” refers to the depth based on the first plane F1. Here, the first plane F1 is an imaginary plane including the interface between the silicon carbide layer 10 and the insulating layer 15.

[0020] Hereinafter, an example will be described in which the first face F1 of the silicon carbide layer 10 is inclined at an angle of 0 to 10 degrees with respect to the silicon face, and the second face F2 is inclined at an angle of 0 to 10 degrees with respect to the carbon face. The first face F1 of the silicon carbide layer 10 has an off angle of 0 to 10 degrees with respect to the silicon face.

[0021] The p-type low concentration region 16 is made of p-type SiC. The p-type low concentration region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-type low concentration region 16 is, for example, 1×10 15 cm -3 5×10 or more 17 cm -3 The following is the result.

[0022] The p-type high concentration region 17 is + The p-type high concentration region 17 is provided between the p-type low concentration region 16 and the first face F1.

[0023] The p-type high concentration region 17 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-type high concentration region 17 is higher than the p-type impurity concentration of the p-type low concentration region 16. The p-type impurity concentration of the p-type high concentration region 17 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0024] The p-type high concentration region 17 contains at least one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr). The concentration of the metal element (M) in the p-type high concentration region 17 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0025] Of the metal elements (M) contained in the p-type high concentration region 17, for example, the proportion of the metal elements (M) located between the lattices of the silicon carbide crystal structure is higher than the proportion of the metal elements (M) located at the carbon sites of the silicon carbide crystal structure.

[0026] The insulating layer 15 is formed on the silicon carbide layer 10. The insulating layer 15 is, for example, silicon oxide.

[0027] The contact electrode 11 is located on the first face F1 side of the silicon carbide layer 10. The contact electrode 11 is electrically connected to the p-type high concentration region 17. The contact electrode 11 is in contact with the metal silicide layer 13.

[0028] The contact electrode 11 includes a metal, such as aluminum, an aluminum alloy, tungsten, or copper.

[0029] The contact electrode 11 may include, for example, a barrier metal film (not shown) between the contact electrode 11 and the metal silicide layer 13. The barrier metal film is, for example, titanium or titanium nitride.

[0030] The metal silicide layer 13 is provided between the silicon carbide layer 10 and the contact electrode 11. The metal silicide layer 13 is in contact with the silicon carbide layer 10. The metal silicide layer 13 is in contact with the contact electrode 11.

[0031] The metal silicide layer 13 includes a silicide of at least one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr). The metal silicide layer 13 includes nickel silicide, palladium silicide, platinum silicide, or chromium silicide. The metal silicide layer 13 is, for example, nickel silicide, palladium silicide, platinum silicide, or chromium silicide.

[0032] The thickness of the metal silicide layer 13 in the normal direction to the first face F1 of the silicon carbide layer 10 is, for example, not less than 50 nm and not more than 500 nm.

[0033] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0034] Fig. 2 is a process flow diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment. Figs. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16 are explanatory diagrams of the method for manufacturing a semiconductor device according to the first embodiment. Figs. 3 to 5 and 7 to 16 are cross-sectional views during the manufacturing process. Fig. 6 is a diagram showing element distribution immediately after ion implantation.

[0035] Hereinafter, an example will be described in which the metal element (M) is nickel (Ni).

[0036] As shown in FIG. 2, the method for manufacturing a semiconductor device includes silicon carbide layer preparation (step S100), aluminum ion implantation (step S101), carbon ion implantation (step S102), carbon film formation (step S103), activation annealing (step S104), carbon film removal (step S105), insulating layer formation (step S106), contact hole formation (step S107), sacrificial oxidation (step S108), hydrogen etching treatment (step S109), nickel film formation (step S110), silicidation annealing (step S111), unreacted nickel film removal (step S112), and aluminum film formation (step S113).

[0037] In step S100, a silicon carbide layer 10 is prepared (FIG. 3). The silicon carbide layer 10 includes a p-type low concentration region 16. The silicon carbide layer 10 has a first face F1 and a second face F2.

[0038] In step S101, aluminum (Al) which is a p-type impurity is ion-implanted into the silicon carbide layer 10. By the ion implantation, a p-type high concentration region 17 is formed (FIG. 4).

[0039] The aluminum ion implantation to form the p-type high concentration region 17 is an example of the first ion implantation. The aluminum ion implantation is performed in a first projected range and at a first dose. The projected range is the average projected range.

[0040] The first projected range is, for example, 0.05 μm or more and 0.2 μm or less. The first dose is, for example, 1×10 15 cm -2 More than 1×10 16 cm -2 The following is the result.

[0041] In step S102, carbon is ion-implanted into the p-type high concentration region 17 (FIG. 5). The ion implantation of carbon into the p-type high concentration region 17 is an example of a second ion implantation. The ion implantation of carbon is performed in a second projected range and with a second dose.

[0042] The second projected range is, for example, 0.05 μm to 0.2 μm, and the second projected range is, for example, 80% to 120% of the first projected range.

[0043] The second dose is, for example, larger than the first dose. The second dose is, for example, 10 times or more the first dose. The second dose is, for example, 100 times or less the first dose. The second dose is, for example, 1×10 16 cm -2 More than 1×10 18 cm -2 The following is the result.

[0044] Fig. 6 shows the concentration distribution of aluminum implanted into silicon carbide layer 10 by the first ion implantation, and the concentration distribution of carbon implanted into silicon carbide layer 10 by the second ion implantation. Fig. 6 shows the element distribution immediately after ion implantation.

[0045] 6, the second projected range Rp2 of the carbon ion implantation is located near the first projected range Rp1 of the aluminum ion implantation. Since the second dose of the carbon ion implantation is larger than the first dose of the aluminum ion implantation, the carbon concentration distribution after the ion implantation completely covers, for example, the aluminum concentration distribution after the ion implantation.

[0046] The peak concentration of the aluminum distribution is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The peak concentration of the carbon distribution is, for example, 1×10 20 cm -3 More than 1×10 22 cm -3 The following is the result.

[0047] In step S103, a carbon film 60 is formed on the silicon carbide layer 10 (FIG. 7).

[0048] In step S104, a first heat treatment is performed. The first heat treatment is activation annealing for activating the implanted aluminum ions.

[0049] The first heat treatment is performed, for example, at 1600° C. or higher. The first heat treatment is performed, for example, at 2000° C. or lower. The first heat treatment is performed, for example, in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The first heat treatment is performed, for example, in an argon gas atmosphere.

[0050] By the first heat treatment, interstitial carbon formed by the carbon ion implantation into the silicon carbide layer 10 fills carbon vacancies in the silicon carbide layer 10.

[0051] The carbon film 60 suppresses desorption of silicon and carbon from the silicon carbide layer 10 into the atmosphere during the first heat treatment. In addition, the carbon film 60 absorbs excess interstitial carbon in the silicon carbide layer 10 during the first heat treatment.

[0052] The first heat treatment is composed of a first step at a temperature of, for example, 1600° C. or higher and a second step at a temperature lower than the first step. The second step is, for example, at a temperature of 1000° C. or lower.

[0053] For example, in a first step, aluminum ions implanted into silicon carbide layer 10 are activated, and interstitial carbon fills carbon vacancies. In a second step, for example at a low temperature, excess interstitial carbon is expelled from silicon carbide layer 10 and absorbed into carbon film 60.

[0054] In step S105, the carbon film 60 is removed (FIG. 8). The carbon film 60 is removed by an ashing process using oxygen plasma. The carbon film 60 is removed in the oxygen plasma.

[0055] During the ashing treatment using oxygen plasma, the surface of the silicon carbide layer 10 is oxidized. The ashing treatment using oxygen plasma is an example of a first oxidation treatment.

[0056] In step S106, the insulating layer 15 is formed on the silicon carbide layer 10 (FIG. 9). The insulating layer 15 is formed by using, for example, a chemical vapor deposition method (CVD method). The insulating layer 15 is, for example, silicon oxide.

[0057] In step S107, a contact hole 61 is formed in the insulating layer 15 (FIG. 10). The contact hole 61 is an example of an opening. The silicon carbide layer 10 is exposed at the bottom of the contact hole 61. The p-type high concentration region 17 is exposed at the bottom of the contact hole 61.

[0058] The contact holes 61 are formed by patterning using, for example, photolithography and etching.

[0059] In step S108, sacrificial oxidation is performed on the silicon carbide layer 10. The sacrificial oxidation is thermal oxidation. A sacrificial oxide film 62 is formed on the silicon carbide layer 10 by the sacrificial oxidation (FIG. 11). The sacrificial oxidation is an example of a second oxidation treatment.

[0060] The sacrificial oxide film 62 is a silicon oxide film. By forming the sacrificial oxide film 62, for example, impurities and damage on the surface of the silicon carbide layer 10 are removed.

[0061] Next, the sacrificial oxide film 62 is removed. The sacrificial oxide film 62 is removed by using, for example, a wet etching method.

[0062] In step S109, a hydrogen etching process is performed to etch the surface of the silicon carbide layer 10 in an atmosphere containing hydrogen gas (FIG. 12). The temperature of the hydrogen etching process is, for example, 1300° C. or more and 1500° C. or less. By the hydrogen etching process, the surface of the silicon carbide layer 10 is etched by, for example, 25 nm or more and 100 nm or less.

[0063] The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 90% or more. The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 95% or more. The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 100%. The atmosphere of the hydrogen etching process may contain, for example, argon gas.

[0064] In step S110, a nickel film 48 is formed on the silicon carbide layer 10 (FIG. 13). The nickel film 48 is an example of a first metal film. Nickel (Ni) is an example of a metal element. The nickel film 48 is formed by using, for example, a sputtering method.

[0065] In step S111, silicidation annealing is performed. The silicidation annealing causes the silicon carbide layer 10 and the nickel film 48 to react with each other to form a nickel silicide layer 50 (FIG. 14). The nickel silicide layer 50 is an example of the metal silicide layer 13.

[0066] The silicidation annealing is performed, for example, in an atmosphere containing nitrogen. The silicidation annealing is performed, for example, in an atmosphere containing nitrogen gas. The temperature of the silicidation annealing is, for example, 500° C. or more and less than 900° C.

[0067] During the silicidation annealing, nickel diffuses from the nickel film 48 into the silicon carbide layer 10. During the silicidation annealing, nickel diffuses into the p-type high concentration region 17.

[0068] In step S112, the unreacted nickel film 48 is removed (FIG. 15). The unreacted nickel film is removed by, for example, wet etching.

[0069] Thereafter, in step S113, an aluminum film 51 is formed on the nickel silicide layer 50 (FIG. 16). The aluminum film 51 is an example of a second metal film. The second metal film has a different chemical composition from the first metal film. The aluminum film 51 is formed by, for example, a sputtering method.

[0070] The aluminum film 51 is patterned to finally become the contact electrode 11 .

[0071] By the above manufacturing method, the contact structure 100 shown in FIG. 1 is formed.

[0072] Next, the operation and effects of the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0073] In the method for manufacturing the contact structure 100 of the first embodiment, when forming the p-type high concentration region 17, in addition to aluminum ion implantation, carbon ion implantation is performed. Furthermore, after the oxidation process, and before the metal silicide layer 13 is formed, the surface of the p-type high concentration region 17 is etched by hydrogen etching. This method reduces the amount of carbon vacancies in the p-type high concentration region 17. As a result, the contact resistance between the p-type high concentration region 17 and the contact electrode 11 is reduced. This will be described in detail below.

[0074] In a semiconductor device using silicon carbide, it is desirable to reduce the contact resistance between a p-type impurity region and an electrode, and the contact resistance between an n-type impurity region and an electrode, in order to improve the characteristics of the semiconductor device.

[0075] In the contact structure 100, a metal silicide layer 13 is provided between the p-type high concentration region 17 and the contact electrode 11. By using the metal silicide layer 13, the contact resistance between the p-type high concentration region 17 and the contact electrode 11 is reduced.

[0076] It is generally known that the contact resistance between an n-type silicon carbide region and a metal silicide layer decreases as the silicidation annealing temperature increases, whereas the contact resistance between a p-type silicon carbide region and a metal silicide layer increases as the silicidation annealing temperature increases.

[0077] For this reason, it is difficult to simultaneously reduce both the contact resistance between the n-type silicon carbide region and the electrode and the contact resistance between the p-type silicon carbide region and the electrode.

[0078] When the metal element (M) contained in the metal silicide layer is one selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr), the inventors conducted first-principles calculations and found the following facts.

[0079] That is, it was revealed that the metal element (M) tends to enter the carbon site of the silicon carbide crystal structure at high temperatures of 900° C. or higher, and tends to enter the interstitial spaces of the silicon carbide crystal structure at low temperatures below 900° C. It was also revealed that the metal element (M) that enters the carbon site functions as a donor, and the metal element (M) that enters the interstitial spaces functions as an acceptor.

[0080] 17 and 18 are diagrams showing the operation and effect of the method for manufacturing the semiconductor device of the first embodiment, and are band diagrams of silicon carbide.

[0081] Fig. 17 is an explanatory diagram of a case where a metal element (M) is inserted into a carbon site of a silicon carbide crystal structure. Fig. 17(a) shows a case where a metal element (M) is not present in the silicon carbide layer, and Fig. 17(b) shows a case where a metal element (M) is present in the silicon carbide layer.

[0082] As shown in Figure 17(b), when a metal element (M) enters a carbon site in the crystal structure of silicon carbide, a donor level due to the metal element (M) is formed at the bottom of the conduction band, and electrons are supplied to the conduction band. The metal element (M) functions as a donor.

[0083] Fig. 18 is an explanatory diagram of a case where a metal element (M) is inserted between the lattices of the silicon carbide crystal structure. Fig. 18(a) shows a case where the metal element (M) is not present in the silicon carbide layer, and Fig. 18(b) shows a case where the metal element (M) is present in the silicon carbide layer.

[0084] As shown in Figure 18(b), when a metal element (M) enters the lattice of the silicon carbide crystal structure, an acceptor level due to the metal element (M) is formed at the top of the valence band, electrons are supplied to the acceptor level, and holes are formed in the valence band. The metal element (M) functions as an acceptor.

[0085] From the above calculation results, the reason why the contact resistance between the n-type silicon carbide region and the metal silicide layer decreases as the temperature of the silicidation annealing increases is believed to be as follows. That is, when the temperature of the silicidation annealing is high, the metal elements diffused from the metal film into the n-type silicon carbide region when the metal silicide layer is formed enter the carbon sites of the crystal structure of silicon carbide and become donors. This increases the donor concentration in the n-type silicon carbide region. As a result, the Schottky barrier between the n-type silicon carbide region and the metal silicide layer decreases, making it easier for a tunnel current to flow and reducing the contact resistance.

[0086] From the above calculation results, the reason why the contact resistance between the p-type silicon carbide region and the metal silicide layer increases as the temperature of the silicidation annealing increases is considered as follows. That is, when the temperature of the silicidation annealing is high, the metal element diffused from the metal film into the p-type silicon carbide region when the metal silicide layer is formed enters the carbon site of the crystal structure of silicon carbide and becomes a donor. Therefore, the acceptor concentration of the p-type silicon carbide region is offset and becomes lower. Therefore, the Schottky barrier between the p-type silicon carbide region and the metal silicide layer rises, making it difficult for a tunnel current to flow, and the contact resistance increases.

[0087] In the method for manufacturing the contact structure 100 of the first embodiment, when forming the p-type high concentration region 17, in addition to aluminum (Al) ion implantation, carbon (C) ion implantation is performed. Due to the carbon (C) ion implantation, a large amount of excess interstitial carbon is present in the p-type high concentration region 17. Due to the heat treatment performed after the carbon ion implantation, the carbon vacancies generated by the aluminum ion implantation are filled with the excess interstitial carbon. Therefore, the amount of carbon vacancies in the p-type high concentration region 17 is reduced. Therefore, the metal element (M) of the p-type high concentration region 17 is more likely to enter between the lattices of the crystal structure of silicon carbide. Therefore, the acceptor concentration of the p-type high concentration region 17 is increased.

[0088] From the viewpoint of reducing the amount of carbon vacancies in the p-type high concentration region 17, the second dose of carbon is preferably 10 times or more the first dose of aluminum.

[0089] From the viewpoint of reducing the amount of carbon vacancies in the p-type high concentration region 17, the second projected range Rp2 of the carbon ion implantation is preferably 80% or more and 120% or less of the first projected range Rp1 of the aluminum ion implantation, and more preferably 90% or more and 110% or less.

[0090] By bringing the first projected range Rp1 and the second projected range Rp2 closer to each other, the carbon concentration distribution after ion implantation can easily completely cover the aluminum concentration distribution after ion implantation. The carbon concentration distribution after ion implantation completely covers the aluminum concentration distribution after ion implantation, thereby reducing the amount of carbon vacancies in the p-type high concentration region 17.

[0091] Fig. 19 is an explanatory diagram of the operation and effect of the method for manufacturing a semiconductor device according to the first embodiment, and is a diagram showing the relationship between the depth from the surface of a silicon carbide layer and the density of carbon vacancies.

[0092] As shown in FIG. 19, when carbon ion implantation is performed in addition to aluminum ion implantation, the carbon vacancy density can be reduced to 1E11 cm unless the silicon carbide layer is oxidized.-3 However, when an oxidation treatment is performed after the ion implantation, the carbon vacancy density increases, for example, from the surface of the silicon carbide layer to a depth of 25 nm. This is believed to be because carbon vacancies are generated by strain generated on the surface of the silicon carbide layer due to the oxidation treatment.

[0093] 19, when carbon ion implantation is not performed in addition to aluminum ion implantation, the carbon vacancy density increases, for example, from the surface of the silicon carbide layer to a depth of 200 nm when an oxidation treatment is performed after the ion implantation. When carbon ion implantation is not performed, damage from the aluminum ion implantation remains, and the carbon vacancy density of the silicon carbide layer before the oxidation treatment is 1E14 cm -3 This is believed to be because the diffusion of oxygen through carbon vacancies is promoted due to the high degree of diffusion, and distortion of silicon carbide occurs deep in the silicon carbide layer.

[0094] In the method for manufacturing the contact structure 100 of the first embodiment, after performing an oxidation treatment on the silicon carbide layer 10, the surface of the silicon carbide layer 10 is etched by a hydrogen etching treatment. The oxidation treatment is, for example, an ashing treatment using oxygen plasma for removing the carbon film 60, and a thermal oxidation treatment for forming the sacrificial oxide film 62. In particular, it is difficult to omit the ashing treatment using oxygen plasma for removing the carbon film 60 from the viewpoint of suppressing the desorption of silicon and carbon from the silicon carbide layer 10 into the atmosphere during the first heat treatment.

[0095] The hydrogen etching process removes the regions with high carbon vacancy density, thereby reducing the carbon vacancy density on the surface of the silicon carbide layer 10. Thus, the amount of carbon vacancies in the p-type high concentration region 17 directly below the nickel silicide layer is reduced.

[0096] Therefore, when the nickel silicide layer is formed, the metal element (M) of the p-type high concentration region 17 easily enters between the lattices of the crystal structure of silicon carbide, and the acceptor concentration of the p-type high concentration region 17 becomes high.

[0097] From the viewpoint of reducing the carbon vacancy density on the surface of silicon carbide layer 10, the amount of etching of the surface of silicon carbide layer 10 by the hydrogen etching treatment is preferably equal to or greater than 25 nm.

[0098] From the viewpoint of increasing the acceptor concentration in the p-type high concentration region 17, the temperature of the silicidation annealing is preferably less than 900°C.

[0099] According to the manufacturing method of the contact structure 100 of the first embodiment, the contact resistance between the p-type high concentration region 17 and the contact electrode 11 is reduced.

[0100] It is also possible to remove the nickel silicide layer after forming the nickel silicide layer and before forming the aluminum film 51. In this case, the aluminum film 51 comes into contact with the p-type high concentration region 17.

[0101] The manufacturing method of the contact structure 100 of the first embodiment can increase the acceptor concentration in the p-type high concentration region 17. Therefore, even in a structure in which the aluminum film 51 contacts the p-type high concentration region 17, the contact resistance between the p-type high concentration region 17 and the contact electrode 11 can be reduced.

[0102] As described above, according to the first embodiment, a semiconductor device capable of reducing the contact resistance between the silicon carbide layer and the metal electrode can be provided.

[0103] Second Embodiment A method for manufacturing a semiconductor device according to the second embodiment includes performing a first ion implantation for ion implanting a p-type impurity into a first region of a silicon carbide layer, performing a second ion implantation for ion implanting carbon (C) into the first region, performing a third ion implantation for ion implanting an n-type impurity into a second region of the silicon carbide layer, performing a first heat treatment for activating the n-type impurity and the p-type impurity, forming a gate insulating layer on the silicon carbide layer, forming a gate electrode on the gate insulating layer, and, after forming the gate electrode, performing a first heat treatment in an atmosphere containing at least hydrogen gas. In both cases, an etching process is performed to etch the first region, a first metal film containing at least one metal element selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) is formed on the first region and the second region, and a second heat treatment is performed to react the first region and the second region with the first metal film to form a metal silicide layer containing at least one metal element, and a second metal film having a different chemical composition from the first metal film is formed on the first region and the second region. The manufacturing method of the semiconductor device of the second embodiment is different from the first embodiment in that an n-type impurity is ion-implanted into the second region of the silicon carbide layer to form a metal silicide layer in the second region. Hereinafter, some of the contents that overlap with the first embodiment may be omitted.

[0104] The semiconductor device of the second embodiment includes a silicon carbide layer including a p-type first silicon carbide region containing at least one metal element selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt) and chromium (Cr), and an n-type second silicon carbide region containing a metal element, and a metal layer electrically connected to the first silicon carbide region and the second silicon carbide region. -1 Infrared absorption intensity at wavenumber 970cm -1 to infrared absorption intensity has a first value near the surface of the first silicon carbide region, and the ratio has a second value higher than the first value near the surface of the second silicon carbide region.

[0105] 20 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a vertical MOSFET 200. The MOSFET 200 is an n-channel transistor that uses electrons as carriers.

[0106] The MOSFET 200 includes a silicon carbide layer 10, a source electrode 12 (metal layer), a metal silicide layer 13 (conductive layer), a drain electrode 14, a gate insulating layer 18, a gate electrode 20, and an interlayer insulating layer 22.

[0107] The source electrode 12 is an example of a metal layer, and the metal silicide layer 13 is an example of a conductive layer.

[0108] The silicon carbide layer 10 includes a drain region 24, a drift region 26, a p-well region 28, a source region 30 (second silicon carbide region), and a p-well contact region 32 (first silicon carbide region).

[0109] The silicon carbide layer 10 is, for example, a single crystal of 4H-SiC. The silicon carbide layer 10 has a first face F1 and a second face F2. The second face F2 faces the first face F1. The first face F1 is a front face of the silicon carbide layer 10, and the second face F2 is a back face of the silicon carbide layer 10.

[0110] In the second embodiment, the “depth” refers to the depth based on the first plane F1. Here, the first plane F1 is an imaginary plane including the interface between the silicon carbide layer 10 and the gate insulating layer 18.

[0111] Hereinafter, an example will be described in which the first face F1 of the silicon carbide layer 10 is inclined at an angle of 0 to 10 degrees with respect to the silicon face, and the second face F2 is inclined at an angle of 0 to 10 degrees with respect to the carbon face. The first face F1 of the silicon carbide layer 10 has an off angle of 0 to 10 degrees with respect to the silicon face.

[0112] The drain region 24 is + The drain region 24 is made of SiC of the n-type. The drain region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 24 is, for example, 1×10 18cm -3 More than 1×10 21 cm -3 The following is the result.

[0113] The drift region 26 is - The drift region 26 is made of type SiC. The drift region 26 is located between the drain region 24 and the first face F1. A part of the drift region 26 is in contact with the first face F1.

[0114] The drift region 26 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 26 is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The n-type impurity concentration of the drift region 26 is lower than the n-type impurity concentration of the drain region 24.

[0115] The drift region 26 is, for example, an epitaxially grown layer of SiC formed by epitaxial growth on the drain region 24. The drift region 26 has a thickness of, for example, 5 μm or more and 100 μm or less.

[0116] The p-well region 28 is made of p-type SiC. The p-well region 28 is located between the drift region 26 and the first face F1. A portion of the p-well region 28 contacts the first face F1.

[0117] The p-well region 28 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 28 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0118] The depth of the p-well region 28 is, for example, not less than 0.4 μm and not more than 0.8 μm. The p-well region 28 functions as a channel region of the MOSFET 200.

[0119] The source region 30 is +The source region 30 is a type SiC. The source region 30 is located between the p-well region 28 and the first face F1. A portion of the source region 30 contacts the first face F1. The source region 30 extends in a first direction.

[0120] The source region 30 contains phosphorus (P) or nitrogen (N) as an n-type impurity. The n-type impurity concentration of the source region 30 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The n-type impurity concentration of the source region 30 is higher than the n-type impurity concentration of the drift region 26.

[0121] The depth of the source region 30 is shallower than the depth of the p-well region 28. The depth of the source region 30 is, for example, not less than 0.1 μm and not more than 0.4 μm.

[0122] The source region 30 includes at least one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr). The concentration of the metal element (M) in the source region 30 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0123] Of the metal elements (M) contained in the source region 30, the proportion of the metal elements (M) located at the carbon sites of the silicon carbide crystal structure is higher than the proportion of the metal elements (M) located between the lattices of the silicon carbide crystal structure. Of the metal elements (M) contained in the source region 30, it is preferable that 90% or more are located at the carbon sites of the silicon carbide crystal structure. The above structure can be realized by taking measures to increase carbon vacancies.

[0124] The p-well contact region 32 is + The p-well contact region 32 is a type of SiC. The p-well contact region 32 is located between the p-well region 28 and the first face F1. The p-well contact region 32 is adjacent to the source region 30. The p-well contact region 32 is in contact with the source region 30.

[0125] The p-well contact region 32 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the p-well contact region 32 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The p-type impurity concentration of the p-well contact region 32 is higher than the p-type impurity concentration of the p-well region .

[0126] The depth of the p-well contact region 32 is shallower than the depth of the p-well region 28. The depth of the p-well contact region 32 is, for example, not less than 0.1 μm and not more than 0.4 μm.

[0127] The p-well contact region 32 includes at least one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr). The concentration of the metal element (M) in the p-well contact region 32 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0128] Of the metal elements (M) contained in the p-well contact region 32, the proportion of the metal elements (M) located between the lattices of the silicon carbide crystal structure is higher than the proportion of the metal elements (M) located at the carbon sites of the silicon carbide crystal structure. Of the metal elements (M) contained in the p-well contact region 32, it is preferable that 90% or more are located between the lattices of the silicon carbide crystal structure. The above structure can be realized by taking measures to reduce carbon vacancies.

[0129] Measured by Attenuated Total Reflection (ATR) measurement using Fourier transform infrared spectroscopy (FTIR) at a wave number of 838 cm -1 Infrared absorption intensity at wavenumber 970cm -1The ratio of the infrared absorption intensity of the 838 cm wavenumber measured by the attenuated total reflection method (ATR method) of the Fourier transform infrared spectroscopy (FTIR method) to the infrared absorption intensity is a first value in the vicinity of the surface of the p-well contact region 32. -1 Infrared absorption intensity at wavenumber 970cm -1 to the infrared absorption intensity is a second value near the surface of the source region 30.

[0130] The second value is higher than the first value, for example, the second value is more than twice the first value.

[0131] The gate insulating layer 18 is located between the silicon carbide layer 10 and the gate electrode 20. The gate insulating layer 18 is located between the p-well region 28 and the gate electrode 20.

[0132] The gate insulating layer 18 is, for example, an oxide or an oxynitride. The gate insulating layer 18 is, for example, a silicon oxide. The thickness of the gate insulating layer 18 is, for example, 30 nm or more and 100 nm or less.

[0133] The gate insulating layer 18 is in contact with the p-well region 28. The p-well region 28 in the vicinity of the gate insulating layer 18 becomes the channel region of the MOSFET 200.

[0134] The gate electrode 20 is located on the first face F1 side of the silicon carbide layer 10. The gate electrode 20 is provided on the gate insulating layer 18. The gate electrode 20 sandwiches the gate insulating layer 18 between the drift region 26, the source region 30, and the p-well region 28.

[0135] The gate electrode 20 is a conductor. The gate electrode 20 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The gate electrode 20 may be, for example, a metal such as titanium nitride, tungsten nitride, tungsten, aluminum, copper, ruthenium, cobalt, nickel, cobalt silicide, or nickel silicide. The gate electrode 20 may have a stacked structure of any one of the above metals and polycrystalline silicon containing n-type impurities or p-type impurities.

[0136] The interlayer insulating layer 22 is formed on the gate electrode 20. The interlayer insulating layer 22 electrically separates the gate electrode 20 from the source electrode 12. The interlayer insulating layer 22 is, for example, silicon oxide.

[0137] The source electrode 12 is located on the first face F1 side of the silicon carbide layer 10. The source electrode 12 is electrically connected to the source region 30 and the p-well contact region 32. The source electrode 12 also functions as a p-well electrode that applies a potential to the p-well region 28. The source electrode 12 is in contact with the metal silicide layer 13.

[0138] The source electrode 12 includes a metal, such as aluminum, an aluminum alloy, tungsten, or copper.

[0139] The source electrode 12 may include, for example, a barrier metal film (not shown) between the source electrode 12 and the metal silicide layer 13. The barrier metal film is, for example, titanium or titanium nitride.

[0140] The metal silicide layer 13 is provided between the silicon carbide layer 10 and the source electrode 12. The metal silicide layer 13 is an example of a conductive layer. The metal silicide layer 13 is in contact with the silicon carbide layer 10. The metal silicide layer 13 is in contact with the source electrode 12.

[0141] The metal silicide layer 13 includes a silicide of at least one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr). The metal silicide layer 13 includes nickel silicide, palladium silicide, platinum silicide, or chromium silicide. The metal silicide layer 13 is, for example, nickel silicide, palladium silicide, platinum silicide, or chromium silicide.

[0142] The thickness of the metal silicide layer 13 in the normal direction to the first face F1 of the silicon carbide layer 10 is, for example, not less than 50 nm and not more than 500 nm.

[0143] The drain electrode 14 is located on the second face F2 side of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 24. The drain electrode 14 is electrically connected to the drain region 24.

[0144] The drain electrode 14 is, for example, nickel. Nickel may react with the silicon carbide layer 10 to form nickel silicide. The nickel silicide is, for example, NiSi or Ni2Si.

[0145] Next, an example of a method for manufacturing the semiconductor device according to the second embodiment will be described.

[0146] Figures 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, and 42 are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the second embodiment. Figures 21 to 42 show cross sections corresponding to Figure 20.

[0147] First, a silicon carbide layer 10 is prepared (FIG. 21). The silicon carbide layer 10 is + The drain region 24 and the n - The drift region 26 is, for example, + The silicon carbide layer 10 is formed by epitaxial growth on the N-type drain region 24. The silicon carbide layer 10 has a first face F1 and a second face F2.

[0148] Next, a first mask material 40 made of, for example, silicon oxide is formed by patterning using photolithography and etching. Next, using this first mask material 40 as an ion implantation mask, aluminum (Al) which is a p-type impurity is ion-implanted into the drift region 26 to form the p-well region 28 (FIG. 22).

[0149] Next, using the first mask material 40 as an ion implantation mask, carbon (C) is ion-implanted into the p-well region 28 (FIG. 23). The ion implantation of carbon into the p-well region 28 reduces carbon vacancies in the p-well region 28. The ion implantation of carbon fills the carbon vacancies in the p-well region 28 with carbon, reducing the carbon vacancies.

[0150] Next, a second mask material 42 made of, for example, silicon oxide is formed by patterning using photolithography and etching. Using the second mask material 42 as an ion implantation mask, aluminum (Al) is ion-implanted into the p-well region 28 to form the p-well contact region 32 (FIG. 24).

[0151] The region in which the p-well contact region 32 is formed is an example of a first region. The ion implantation to form the p-well contact region 32 is an example of a first ion implantation.

[0152] Next, using the second mask material 42 as an ion implantation mask, carbon (C) is ion-implanted into the p-well contact region 32 (FIG. 25). Carbon ion implantation into the p-well contact region 32 reduces carbon vacancies in the second region. Carbon ion implantation fills the carbon vacancies in the p-well contact region 32 with carbon, reducing the carbon vacancies.

[0153] Carbon ion implantation into the p-well contact region 32 is an example of the second ion implantation.

[0154] Next, a third mask material 44 made of, for example, silicon oxide is formed by patterning using photolithography and etching. Using the third mask material 44 as an ion implantation mask, phosphorus (P), which is an n-type impurity, is ion-implanted into the p-well region 28 to form the source region 30 (FIG. 26).

[0155] The region in which the source region 30 is formed is an example of a second region. The ion implantation to form the source region 30 is an example of a third ion implantation.

[0156] Next, argon (Ar) ions are implanted into the source region 30 using the third mask material 44 as an ion implantation mask (FIG. 27). The argon ion implantation into the source region 30 increases carbon vacancies in the source region 30. The argon ion implantation breaks the bonds of silicon carbide in the source region 30, and the carbon vacancies in the source region 30 increase.

[0157] Next, a carbon film 60 is formed on the silicon carbide layer 10 (FIG. 28).

[0158] Next, a first heat treatment is performed. The first heat treatment is an activation anneal for activating the implanted aluminum ions. The p-type impurities in the p-well region 28 and the p-well contact region 32, and the n-type impurities in the source region 30 are activated.

[0159] The first heat treatment is performed, for example, at 1600° C. or higher. The first heat treatment is performed, for example, at 2000° C. or lower. The first heat treatment is performed in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The first heat treatment is performed, for example, in an argon gas atmosphere.

[0160] By the first heat treatment, interstitial carbon formed by carbon ion implantation into the silicon carbide layer 10 fills carbon vacancies in the silicon carbide layer 10 .

[0161] Next, the carbon film 60 is removed (FIG. 29). The carbon film 60 is removed by an ashing process using oxygen plasma. The carbon film 60 is removed in the oxygen plasma. During the ashing process using oxygen plasma, the surface of the silicon carbide layer 10 is oxidized. The ashing process using oxygen plasma is an example of an oxidation process.

[0162] Next, a field oxide film 65 is formed on the silicon carbide layer 10 (FIG. 30). The field oxide film 65 contains oxygen. The field oxide film 65 is, for example, a silicon oxide film. The field oxide film 65 is deposited by, for example, a vapor phase growth method. The field oxide film 65 is formed by, for example, a CVD method or a Physical Vapor Deposition method (PVD method).

[0163] When depositing the field oxide film 65, the surface of the silicon carbide layer 10 is oxidized. The deposition process for depositing the field oxide film 65 is an example of an oxidation process. The field oxide film 65 functions as, for example, an element isolation region in a peripheral region (not shown).

[0164] Next, the field oxide film 65 is removed by using, for example, a wet etching method.

[0165] Next, a sacrificial oxide film 66 is formed on the silicon carbide layer 10 (FIG. 31). The sacrificial oxide film 66 is, for example, a silicon oxide film. The sacrificial oxide film 66 is formed by thermal oxidation of the surface of the silicon carbide layer 10.

[0166] When the sacrificial oxide film 66 is formed, the surface of the silicon carbide layer 10 is oxidized. The thermal oxidation process for forming the sacrificial oxide film 66 is an example of an oxidation process. By forming the sacrificial oxide film 66, for example, impurities and damage on the surface of the silicon carbide layer 10 are removed.

[0167] Next, the sacrificial oxide film 66 is removed. The sacrificial oxide film 66 is removed by using, for example, a wet etching method.

[0168] Next, a gate insulating layer 18 is formed on the silicon carbide layer 10 by a CVD method or a thermal oxidation method. The gate insulating layer 18 is, for example, silicon oxide. When forming the gate insulating layer 18, the surface of the silicon carbide layer 10 is oxidized. The process of forming the gate insulating layer 18 is an example of an oxidation process.

[0169] Next, the gate electrode 20 is formed on the gate insulating layer 18 (FIG. 32). The gate electrode 20 is, for example, polycrystalline silicon. The gate electrode 20 is formed, for example, by depositing a film by a CVD method and patterning it by photolithography and etching.

[0170] Next, an insulating layer 67 is formed on the gate electrode 20 (FIG. 33). A part of the insulating layer 67 will eventually become the interlayer insulating layer 22. The insulating layer 67 is, for example, silicon oxide. The insulating layer 67 is formed by, for example, a CVD method.

[0171] Next, a contact hole 61 is formed in the insulating layer 67 (FIG. 34). The contact hole 61 is an example of an opening. The silicon carbide layer 10 is exposed at the bottom of the contact hole 61. The p-well contact region 32 and the source region 30 are exposed at the bottom of the contact hole 61.

[0172] The contact holes 61 are formed by patterning using photolithography and etching.

[0173] Next, sacrificial oxidation is performed on the silicon carbide layer 10. The sacrificial oxidation is thermal oxidation. A sacrificial oxide film 62 is formed on the silicon carbide layer 10 by the sacrificial oxidation (FIG. 35). The sacrificial oxide film 62 is formed on the p-well contact region 32 and the source region 30. The sacrificial oxidation is an example of an oxidation process.

[0174] The sacrificial oxide film 62 is a silicon oxide film. By forming the sacrificial oxide film 62, for example, impurities and damage on the surface of the silicon carbide layer 10 are removed.

[0175] Next, the sacrificial oxide film 62 is removed. The sacrificial oxide film 62 is removed by using, for example, a wet etching method.

[0176] Next, a sidewall 68 is formed on the side surface of the contact hole 61 (FIG. 36). The sidewall 68 is formed by depositing a film by a CVD method and etching the film. The sidewall 68 is made of, for example, silicon nitride.

[0177] Next, a hydrogen etching process is performed to etch the surface of the silicon carbide layer 10 in an atmosphere containing hydrogen gas (FIG. 37). The temperature of the hydrogen etching process is, for example, 1300° C. or more and 1500° C. or less. By the hydrogen etching process, the surface of the silicon carbide layer 10 is etched by, for example, 25 nm or more and 100 nm or less.

[0178] The source region 30 covered by the sidewall 68 is not etched, and the p-well contact region 32 exposed from the sidewall 68 is etched.

[0179] The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 90% or more. The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 95% or more. The partial pressure of hydrogen gas in the atmosphere of the hydrogen etching process is, for example, 100%. The atmosphere of the hydrogen etching process may contain, for example, argon gas.

[0180] Next, the sidewall 68 is removed (FIG. 38). The sidewall 68 is removed by, for example, wet etching.

[0181] Next, a nickel film 48 is formed on the silicon carbide layer 10 (FIG. 39). The nickel film 48 is formed on the p-well contact region 32 and the source region 30. The nickel film 48 is an example of a first metal film. The nickel film 48 is formed by using, for example, a sputtering method.

[0182] Next, silicidation annealing is performed. The silicidation annealing causes the silicon carbide layer 10 and the nickel film 48 to react with each other to form a nickel silicide layer 50 (FIG. 40). The p-well contact region 32 and the source region 30 cause the nickel film 48 to react with each other to form the nickel silicide layer 50. The nickel silicide layer 50 is an example of a metal silicide layer 13.

[0183] The silicidation annealing is performed, for example, in an atmosphere containing nitrogen. The silicidation annealing is performed, for example, in an atmosphere containing nitrogen gas. The temperature of the silicidation annealing is, for example, 500° C. or more and less than 900° C.

[0184] During the silicidation anneal, nickel diffuses from the nickel film 48 into the silicon carbide layer 10. Nickel diffuses into the source region 30 and the p-well contact region 32.

[0185] Next, the unreacted nickel film 48 is removed (FIG. 41). The unreacted nickel film is removed by, for example, wet etching.

[0186] Thereafter, an aluminum film 51 is formed on the nickel silicide layer 50. The aluminum film 51 is an example of a second metal film. The second metal film has a different chemical composition from the first metal film. The aluminum film 51 is formed by, for example, a sputtering method.

[0187] The aluminum film 51 is patterned to finally become the source electrode 12 .

[0188] Next, a conductive drain electrode 14 is formed on the silicon carbide layer 10 on the side opposite to the source electrode 12 (FIG. 42). In other words, the drain electrode 14 is formed with the drift region 26 sandwiched between it and the source electrode 12. The drain electrode 14 is formed by, for example, sputtering a nickel film.

[0189] By the above manufacturing method, the MOSFET 200 shown in FIG. 20 is formed.

[0190] Next, the operation and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the second embodiment will be described.

[0191] In the MOSFET 200 using silicon carbide, in order to reduce the on-resistance, it is desirable to reduce the contact resistance between the n-type source region 30 and the source electrode 12. Also, in order to realize stable operation, it is desirable to reduce the contact resistance between the p-type p-well contact region 32 and the source electrode 12. It is desirable to simultaneously reduce both the contact resistance between the n-type source region 30 and the source electrode 12 and the contact resistance between the p-type p-well contact region 32 and the source electrode 12.

[0192] In the MOSFET 200, a metal silicide layer 13 is provided between the source region 30 and the source electrode 12, and between the p-well contact region 32 and the source electrode 12. By using the metal silicide layer 13, the contact resistance between the source region 30 and the source electrode 12, and the contact resistance between the p-well contact region 32 and the source electrode 12 are reduced.

[0193] As described above, it is known that the contact resistance between an n-type silicon carbide region and a metal silicide layer decreases as the silicidation annealing temperature increases, whereas the contact resistance between a p-type silicon carbide region and a metal silicide layer increases as the silicidation annealing temperature increases.

[0194] For this reason, it is difficult to simultaneously reduce both the contact resistance between the n-type source region and the source electrode, and the contact resistance between the p-type p-well contact region and the source electrode.

[0195] In the method for manufacturing the MOSFET 200 of the second embodiment, in addition to the ion implantation of aluminum, carbon ions are implanted when forming the p-well contact region 32. Furthermore, after the oxidation treatment, the surface of the p-well contact region 32 is etched by a hydrogen etching treatment before forming the metal silicide layer 13. With the above method, the amount of carbon vacancies in the silicon carbide layer 10 of the p-well contact region 32 is reduced by the same action as in the contact structure 100 of the first embodiment.

[0196] This reduces the contact resistance between the p-well contact region 32 and the contact electrode 11. This makes it possible to simultaneously reduce both the contact resistance between the n-type source region 30 and the source electrode 12 and the contact resistance between the p-type p-well contact region 32 and the source electrode 12.

[0197] From the viewpoint of reducing the contact resistance between the n-type source region 30 and the source electrode 12, it is preferable not to etch the source region 30 in the hydrogen etching process.

[0198] From the viewpoint of reducing the contact resistance between the n-type source region 30 and the source electrode 12, it is preferable to perform a process for increasing carbon vacancies in the first region in which the source region 30 is to be formed. Specifically, it is preferable to perform ion implantation of argon into the source region 30.

[0199] By carrying out a process to increase the carbon vacancies in the source region 30, the metal element (M) in the source region 30 becomes more likely to enter the carbon sites of the crystal structure of silicon carbide. Therefore, even if the silicidation annealing is performed at a low temperature of less than 900°C, for example, the metal element (M) becomes more likely to enter the carbon sites of the crystal structure of silicon carbide. This increases the donor concentration of the source electrode 12, and reduces the contact resistance between the n-type source region 30 and the source electrode 12. It is also possible to perform ion implantation of argon (Ar) into the source region 30 after the activation annealing.

[0200] From the viewpoint of increasing the donor concentration in the source region 30, the temperature of the silicidation annealing is preferably 500° C. or higher, more preferably 600° C. or higher, even more preferably 700° C. or higher, and most preferably 800° C. or higher.

[0201] From the viewpoint of increasing the acceptor concentration in the p-well contact region 32, the temperature of the silicidation annealing is preferably less than 900.degree.

[0202] Measured by Attenuated Total Reflection (ATR) measurement using Fourier transform infrared spectroscopy (FTIR) at a wave number of 838 cm -1 The infrared absorption intensity at 838 cm corresponds to the density of carbon vacancies. -1 The infrared absorption at 838 cm corresponds to a residual product that is generated in the silicon carbide layer when the silicon carbide layer is oxidized. The residual product has Si-O bonds. -1 The infrared absorption of is due to the presence of Si-O bonds.

[0203] When the silicon carbide layer is oxidized, the silicon carbide lattice is distorted and carbon vacancies are formed, so that the density of carbon vacancies is high in the silicon carbide layer in the portion having a high density of residual products.

[0204] The MOSFET 200 of the second embodiment has a wavelength of 838 cm measured by the attenuated total reflection method (ATR method) of Fourier transform infrared spectroscopy (FTIR method). -1 Infrared absorption intensity at wavenumber 970cm -1 The ratio of the infrared absorption intensity of the 838 cm wavenumber measured by the attenuated total reflection method (ATR method) of the Fourier transform infrared spectroscopy (FTIR method) to the infrared absorption intensity is a first value in the vicinity of the surface of the p-well contact region 32. -1 Infrared absorption intensity at wavenumber 970cm -1 The ratio of the infrared absorption intensity to the intensity of the infrared absorption at the wave number of 970 cm is the second value near the surface of the source region 30. -1 The infrared absorption at 970 cm corresponds to the longitudinal optical phonon mode of silicon carbide. -1 The infrared absorption intensity at wavenumber 838 cm -1 It is used to normalize the intensity of infrared absorption.

[0205] The second value is higher than the first value. In other words, the carbon vacancy density near the surface of the source region 30 is higher than the carbon vacancy density near the surface of the p-well contact region 32. Therefore, according to the MOSFET 200, the contact resistance between the n-type source region 30 and the source electrode 12 and the contact resistance between the p-type p-well contact region 32 and the source electrode 12 are both reduced simultaneously.

[0206] From the viewpoint of simultaneously reducing both the contact resistance between the n-type source region 30 and the source electrode 12 and the contact resistance between the p-type p-well contact region 32 and the source electrode 12, the second value is preferably at least twice the first value, and more preferably at least five times the first value.

[0207] According to the MOSFET 200 of the second embodiment and the manufacturing method thereof, both the contact resistance between the source region 30 and the source electrode 12 and the contact resistance between the p-well contact region 32 and the source electrode 12 are reduced simultaneously. Therefore, the on-resistance of the MOSFET 200 is reduced, and stable operation is achieved.

[0208] It is also possible to etch the source region 30 and the p-well contact region 32 in the hydrogen etching process without forming the sidewall 68 before the etching process.

[0209] Moreover, after forming the nickel silicide layer, it is also possible to remove the nickel silicide layer before forming the aluminum film 51. In this case, the aluminum film 51 comes into contact with the source region 30 and the p-well contact region 32.

[0210] As described above, according to the second embodiment, a semiconductor device capable of reducing the contact resistance between the silicon carbide layer and the metal electrode can be provided.

[0211] (Third embodiment) The inverter circuit and the drive device of the third embodiment are an inverter circuit and a drive device including the semiconductor device of the second embodiment.

[0212] 43 is a schematic diagram of a driving device of the third embodiment. The driving device 700 includes a motor 140 and an inverter circuit 150.

[0213] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, each of which uses the MOSFET 200 of the second embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

[0214] According to the third embodiment, the MOSFET 200 with improved characteristics is provided, and thus the characteristics of the inverter circuit 150 and the driving device 700 are improved.

[0215] (Fourth embodiment) The vehicle of the fourth embodiment is a vehicle equipped with the semiconductor device of the second embodiment.

[0216] 44 is a schematic diagram of a vehicle according to the fourth embodiment. The vehicle 800 according to the fourth embodiment is a railcar. The vehicle 800 includes a motor 140 and an inverter circuit 150.

[0217] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 200 of the second embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 800 are rotated by the motor 140.

[0218] According to the fourth embodiment, the vehicle 800 is provided with the MOSFET 200 having improved characteristics, thereby improving the characteristics of the vehicle 800.

[0219] Fifth embodiment The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the second embodiment.

[0220] 45 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 900 according to the fifth embodiment is an automobile. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0221] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 200 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0222] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 causes the wheels 90 of the vehicle 900 to rotate.

[0223] According to the fifth embodiment, the vehicle 900 is provided with the MOSFET 200 having improved characteristics, thereby improving the characteristics of the vehicle 900.

[0224] Sixth embodiment The elevator of the sixth embodiment is an elevator including the semiconductor device of the second embodiment.

[0225] 46 is a schematic diagram of an elevator according to the sixth embodiment. The elevator 1000 according to the sixth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0226] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 200 of the second embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0227] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoist 616, causing the car 610 to rise and fall.

[0228] According to the sixth embodiment, the elevator 1000 has improved characteristics by including the MOSFET 200 with improved characteristics.

[0229] In the above, the first and second embodiments have been described taking as an example the case of 4H—SiC as the crystal structure of silicon carbide, but the present invention can also be applied to silicon carbide having a 3C—SiC or 6H—SiC crystal structure.

[0230] The present invention can also be applied to other semiconductor devices using silicon carbide, such as diodes and IGBTs (Insulated Gate Bipolar Transistors).

[0231] Moreover, the present invention can be applied not only to a planar gate type transistor, but also to a transistor having a trench gate structure in which a gate electrode is provided inside a trench.

[0232] Moreover, the present invention can be applied not only to a vertical transistor but also to a lateral transistor in which a source electrode and a drain electrode are provided on the same surface of a silicon carbide layer.

[0233] In the first and second embodiments, the n-type impurity is nitrogen or phosphorus. However, it is also possible to use arsenic (As) or antimony (Sb) as the n-type impurity.

[0234] In addition, in the first and second embodiments, the case where the p-type impurity is aluminum has been described as an example, but boron (B), gallium (Ga), and indium (In) can also be used as the p-type impurity.

[0235] In addition, in the third to sixth embodiments, the semiconductor device of the present invention is described as being applied to a vehicle or an elevator, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0236] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0237] 10 Silicon carbide layer 12 Source electrode (metal layer) 13 Metal silicide layer (conductive layer) 15 Insulating layer 16 Gate insulating layer 20 Gate electrode 30 source region (second silicon carbide region) 32 p-well contact region (first silicon carbide region) 48 Nickel film (first metal film) 50 Metal silicide layer 51 Aluminum film (second metal film) 60 Carbon Film 61 Contact hole (opening) 67 Insulating Layer 100 Contact structure (semiconductor device) 150 Inverter circuit 200 MOSFET (semiconductor device) 700 Drive Unit 800 vehicles 900 vehicles 1000 Elevators

Claims

1. performing a first ion implantation to implant a p-type impurity into the silicon carbide layer in a first projected range and at a first dose; performing a second ion implantation of carbon (C) into the silicon carbide layer in a second projected range and at a second dose; performing a first heat treatment for activating the p-type impurity; performing a first oxidation treatment for oxidizing the silicon carbide layer; performing an etching process for etching the silicon carbide layer in an atmosphere containing hydrogen gas; forming a first metal film containing at least one metal element selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) on the silicon carbide layer; performing a second heat treatment to react the silicon carbide layer with the first metal film to form a metal silicide layer containing the at least one metal element; A method for manufacturing a semiconductor device further comprising the steps of: forming, on the silicon carbide layer, a second metal film having a different chemical composition from the first metal film.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the silicon carbide layer is etched by 25 nm or more during the etching treatment.

3. forming a carbon film on the silicon carbide layer after performing the first ion implantation and before performing the first heat treatment; 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first oxidation treatment is an ashing treatment for removing the carbon film in oxygen plasma.

4. forming an insulating layer on the silicon carbide layer after performing the first oxidation treatment and before the etching treatment; forming an opening in the insulating layer to expose the silicon carbide layer; 4. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon carbide layer exposed in the opening is etched during the etching treatment.

5. 5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of: performing a second oxidation process for oxidizing the silicon carbide layer exposed in the opening after forming the opening and before the etching process.

6. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the p-type impurity is aluminum (Al).

7. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the second dose is larger than the first dose.

8. The first dose is 1×10 １５ cm －２ The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

9. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the second projected range is 80% or more and 120% or less of the first projected range.

10. 10. The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: removing the metal silicide layer after forming the metal silicide layer and before forming the second metal film.

11. performing a first ion implantation step of ion-implanting a p-type impurity into a first region of the silicon carbide layer; performing a second ion implantation step of ion-implanting carbon (C) into the first region; performing a third ion implantation step of ion-implanting an n-type impurity into the second region of the silicon carbide layer; performing a first heat treatment for activating the n-type impurities and the p-type impurities; forming a gate insulating layer on the silicon carbide layer; forming a gate electrode on the gate insulating layer; After forming the gate electrode, an etching process is performed in an atmosphere containing hydrogen gas to etch at least the first region; forming a first metal film containing at least one metal element selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr) on the first region and the second region; performing a second heat treatment to react the first region and the second region with the first metal film to form a metal silicide layer containing the at least one metal element; A method for manufacturing a semiconductor device, comprising forming a second metal film having a different chemical composition from that of the first metal film on the first region and the second region.

12. The method for manufacturing a semiconductor device according to claim 11 , further comprising the step of: performing an oxidation treatment for oxidizing said silicon carbide layer after performing said first heat treatment and before performing said etching treatment.

13. forming an insulating layer on the silicon carbide layer after forming the gate electrode and before the etching process; forming an opening in the insulating layer through which at least the first region is exposed; 13. The method for manufacturing a semiconductor device according to claim 11, wherein the first region exposed in the opening is etched during the etching process.

14. 14. The method for manufacturing a semiconductor device according to claim 11, wherein the first region and the second region are etched in the etching process.

15. 15. The method for manufacturing a semiconductor device according to claim 11, wherein the first region is etched by 25 nm or more during the etching process.

16. 16. The method for manufacturing a semiconductor device according to claim 11, further comprising the step of: implanting argon ions into the second region before the first heat treatment.

17. 17. The method for manufacturing a semiconductor device according to claim 11, wherein the temperature of the second heat treatment is less than 900.degree.

18. a silicon carbide layer including: a p-type first silicon carbide region including at least one metal element selected from the group consisting of nickel (Ni), palladium (Pd), platinum (Pt), and chromium (Cr); and an n-type second silicon carbide region including the at least one metal element; a metal layer electrically connected to the first silicon carbide region and the second silicon carbide region; Equipped with Measured by the attenuated total reflection method (ATR method) of Fourier transform infrared spectroscopy (FTIR method), wave number 838 cm －１ Infrared absorption intensity at wave number 970 cm －１ to an infrared absorption intensity has a first value in the vicinity of a surface of the first silicon carbide region, the ratio is a second value higher than the first value in the vicinity of a surface of the second silicon carbide region.

19. The semiconductor device according to claim 18 , further comprising a conductive layer located between the silicon carbide layer and the metal layer, the conductive layer including a silicide of the at least one metal element.

20. 20. The semiconductor device according to claim 18, wherein the second value is equal to or greater than twice the first value.

21. 21. An inverter circuit comprising the semiconductor device according to claim 18.

22. A driving device comprising the semiconductor device according to any one of claims 18 to 20.

23. A vehicle comprising the semiconductor device according to any one of claims 18 to 20.

24. An elevator comprising the semiconductor device according to any one of claims 18 to 20.

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