Control of metal contamination from metal-containing photoresists.

Abstract

Various techniques are provided herein for controlling metal-containing contamination on semiconductor substrates. Such techniques may involve one or more of post-development bake treatments, chemical treatments, plasma treatments, photo treatments, and backside and bevel cleaning. The techniques may be combined as desired for a particular application. In many cases, the techniques are used to address metal-containing contamination generated during photoresist development operations.

Description

[Technical field]

[0001] Incorporation by Reference A PCT Request Form is being filed contemporaneously herewith as a part of the present application. Each application to which this application claims benefit or priority identified in the contemporaneously filed PCT Request Form is hereby incorporated by reference in its entirety and for all purposes.

[0002] FIELD OF THE DISCLOSURE Embodiments herein relate to the field of semiconductor processing. In particular, various embodiments relate to patterning semiconductor substrates using photolithography and related processes. Various techniques for controlling metal contamination are discussed. [Background technology]

[0003] The fabrication of semiconductor devices, such as integrated circuits, is a multi-step process involving photolithography. In general, the process involves the deposition of materials onto a wafer and patterning the materials through lithographic techniques to form structural features of semiconductor devices (e.g., transistors and circuits). The steps of a typical photolithography process known in the art include preparing a substrate, applying photoresist, such as by spin-coating, exposing the photoresist to light in a desired pattern and causing the exposed areas of the photoresist to be more or less dissolved in a developer, developing the photoresist pattern by applying a developer to remove either the exposed or unexposed areas of the photoresist, and performing subsequent processing, such as by etching or material deposition, to create features on the areas of the substrate where the photoresist was removed.

[0004] The evolution of semiconductor design has created the need for, and been driven by, the ability to create ever-smaller features on semiconductor substrate materials. This technological advancement has been characterized by "Moore's Law," which states that the density of transistors in densely packed integrated circuits doubles every two years. In fact, advances in chip design and manufacturing mean that modern microprocessors can contain billions of transistors and other circuit features on a single chip. Individual features on such chips can be on the order of 22 nanometers (nm) or smaller, and in some cases less than 10 nm.

[0005] One challenge in manufacturing devices with such small features is the ability to reliably and reproducibly create photolithography masks with sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose the photoresist. A fundamental problem arises in that the light has a wavelength significantly larger than the desired size of the features to be produced on the semiconductor substrate. Achieving feature sizes smaller than the wavelength of the light requires the use of complex resolution enhancement techniques such as multi-patterning. Thus, there is significant interest and research effort in developing photolithography techniques using shorter wavelength light, such as extreme ultraviolet radiation (EUV), having a wavelength of 10 nm to 15 nm, e.g., 13.5 nm.

[0006] However, EUV photolithography processes may present challenges, including low power output and light loss during patterning. Conventional organic chemically amplified resists (CARs), similar to those used in 193 nm UV lithography, have potential drawbacks when used in EUV lithography, especially if they have low absorption coefficients in the EUV region, where diffusion of photoactivated chemical species may result in blurring or line edge roughness. Furthermore, to provide the etch resistance required to pattern underlying device layers, small features patterned in conventional CAR materials may result in high aspect ratios with the risk of pattern collapse. Thus, there remains a need for improved EUV photoresist materials with properties such as reduced thickness, greater absorbance, and greater etch resistance.

[0007] The background discussion provided herein is for the purpose of generally presenting the context of the present technology. The work of the inventors named herein is not admitted, expressly or impliedly, as prior art to the present technology, to the extent that it is described in this background section, as well as in a description manner that does not qualify as prior art at the time of filing. Summary of the Invention

[0008] Various embodiments herein relate to methods, apparatus, and systems for controlling contamination on a substrate. The substrate is typically a semiconductor substrate. In one aspect of the disclosed embodiments, a method for controlling contamination on a substrate is provided, the method comprising: (a) either (i) processing a front side of a substrate, thereby causing formation of contamination including metal on a back side of the substrate, or (ii) receiving a substrate with contamination on the back side of the substrate, and (b) after (a), heating the substrate in a post-processing bake process, where heating the substrate reduces the metal contamination on the back side of the substrate.

[0009] In some embodiments, treating the front side of the substrate may include at least one process selected from the group consisting of developing a layer of photoresist, in situ cleaning the substrate, withdrawing mandrels in patterning applications, smoothing features on the substrate, and descumming the layer of photoresist. In these or other embodiments, (a) may include either (i) developing a layer of photoresist on the substrate, or (ii) receiving the substrate with a layer of photoresist developed on the front side of the substrate and contamination on the back side of the substrate, the metal in the contamination originating from the layer of photoresist on the front side of the substrate, and the post-treatment bake process of (b) is a post-development bake process that occurs when the layer of photoresist is at least partially developed. In these or other embodiments, during the post-development bake process of (b), the substrate may be baked at a temperature of about 160-300° C. for a duration of about 1-10 minutes.

[0010] In these or other embodiments, the method may further include exposing the substrate to a processing gas, the processing gas being N 2 , H 2 , Ar, He, Xe, and combinations thereof. In these or other embodiments, the method may further include exposing the substrate to a reactive process gas to increase the volatility of the metal-containing material on the substrate, the metal-containing material comprising a metal. In some embodiments, the method may further include exposing the substrate to a reactive process gas to increase the stability of the metal-containing material on the substrate, the metal-containing material comprising a metal. In these or other ... 3 ), hydrogen iodide (HI), diatomic iodine (I 2 ), and combinations thereof. In some cases, the substrate may be exposed to a chlorine-containing gas, the chlorine-containing gas being selected from the group consisting of BCl 3 , Cl 2 , HCl, SiCl 4, SOCl 2 , PCl 3 In some cases, the substrate may be exposed to an oxygen-containing gas, the oxygen-containing gas being O 2 , O 3 , H 2 O, SO 2 , CO 2 , C.O., C.O.S., H. 2 O 2 , NO x In some cases, the substrate may be exposed to a fluorine-containing gas, the fluorine-containing gas being selected from the group consisting of HF, C x F y H z , N.F. 3 ,SCIENCE FICTION 6 , F 2 and combinations thereof.

[0011] In these or other embodiments, the method may further include exposing the substrate to a plasma to increase the volatility of the metal-containing material on the substrate, the metal-containing material comprising a metal. In some embodiments, the method may further include exposing the substrate to a plasma to increase the stability of the metal-containing material on the substrate, the metal-containing material comprising a metal. In these or other embodiments, the method may further include exposing the substrate to a plasma to increase the stability of the metal-containing material on the substrate, the metal-containing material comprising a metal. 2 ), diatomic nitrogen (N 2 ), argon, helium, krypton, methane (CH 4 ), an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a hydrogen halide, and combinations thereof. In some embodiments, the plasma generating gas can include an oxygen-containing gas, the oxygen-containing gas being O 2 , O 3 , CO, CO 2 , COS, SO 2 , NO x , H2 In some embodiments, the plasma generating gas may include at least one gas selected from the group consisting of NF, O, and combinations thereof. In some embodiments, the plasma generating gas may include a fluorine-containing gas, the fluorine-containing gas being NF 3 , C.F. 4 , C.H. 3 F 3 , C.H. 2 F 2 , CHF 3 , F 2 ,SCIENCE FICTION 6 In some embodiments, the plasma generating gas may include at least one gas selected from the group consisting of BCl, CBCl, CBN ... 3 , Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 In some embodiments, the plasma generating gas may include at least one gas selected from the group consisting of: (i) diatomic hydrogen (H 2 ), and (ii) diatomic nitrogen (N 2 ) or a noble gas.

[0012] In these or other embodiments, heating the substrate in a post-development bake process may reduce the concentration of the metal on the backside of the substrate by at least one order of magnitude. In these or other embodiments, the method may further include exposing the substrate to a plasma, where heating the substrate in a post-development bake process and exposing the substrate to the plasma reduces the concentration of the metal on the backside of the substrate by at least two orders of magnitude.

[0013] In these or other embodiments, the method may further include exposing the substrate to light to reduce the concentration of metal on the backside of the substrate. In some embodiments, the light may include at least one of a UV wavelength, a visible wavelength, or an IR wavelength. In some embodiments, the light may be provided by an IR lamp or a plurality of LEDs, and the substrate may be heated to a temperature of about 250-400° C. for a duration of about 60 seconds or less while the substrate is exposed to the light.

[0014] In these or other embodiments, heating the substrate in a post-development bake process may begin while the layer of photoresist is still being developed onto the substrate.

[0015] In these or other embodiments, the method may further include transferring the substrate from a first processing chamber to a second processing chamber after (a), such that (a) occurs in the first processing chamber and (b) occurs in the second processing chamber. In these or other embodiments, (a) may occur in the processing chamber, and the method may further include heating the processing chamber to a temperature of about 40° C. or greater while the layer of photoresist is developed in (a). In these or other embodiments, (a) may occur in the processing chamber, and the method may further include purging the processing chamber while maintaining the processing chamber at a temperature of about 100° C. or greater, and the purging occurs after (a). In some embodiments, the method may further include sweeping the processing chamber with an inert gas, and the purging and sweeping are part of a pump-purge sequence.

[0016] In these or other embodiments, the method may further include performing a wet clean on the backside of the substrate after (a) and (b). In these or other embodiments, performing a wet clean on the backside of the substrate may further reduce the concentration of metal on the backside of the substrate by at least an order of magnitude. In these or other embodiments, the wet clean may also clean the beveled edge region of the front side of the substrate. In these or other embodiments, performing a wet clean on the backside of the substrate may include exposing the backside of the substrate to dilute HF. In these or other embodiments, performing a wet clean on the backside of the substrate may include exposing the backside of the substrate to dilute HCl, or to NH 4 OH, H 2 O 2 , and H 2 This may include exposing the sample to a standard wash 1 solution containing O.

[0017] Various Embodiment In the present invention, the layer of photoresist may be formed using dry deposition. In other embodiments, the layer of photoresist may be formed using wet deposition. In various embodiments, the layer of photoresist may be developed using dry processing. In some embodiments, the layer of photoresist may be developed using halogen-containing chemistries. In some embodiments, the layer of photoresist may be developed using wet processing.

[0018] In various embodiments, the post-development bake process of (b) occurs in a processing chamber, and the following conditions may be used during the post-development bake process of (b): (i) the pressure in the processing chamber may be maintained at about 0.01-1 Torr, (ii) a chlorine-containing gas may be provided to the processing chamber at a rate of about 200-10,000 sccm for a duration of about 1-10 minutes, (iii) the temperature of one or more components of the processing chamber may be maintained at about 20-150° C., and (iv) the substrate may not be exposed to a plasma during (b).

[0019] In various embodiments, a layer of photoresist can be developed in (a) in a process chamber, and (b) can occur in the same process chamber as (a), and the method can be performed under the following conditions: (i) the pressure in the process chamber can be about 0.01-1 Torr, (ii) a flow of purge gas can be provided to the process chamber at a rate of about 200-10,000 sccm, and the purge gas can be diatomic nitrogen (N 2 ), a noble gas, and combinations thereof, wherein the purge gas is provided to the processing chamber for a duration of about 1-10 minutes, and (iii) one or more components of the processing chamber may be maintained at about 100-300° C., and a substrate support within the processing chamber may be maintained at about 120-300° C.

[0020] In various embodiments, (a) can occur in a first processing chamber and (b) can occur in a second processing chamber, and the following conditions can be met: (i) a pressure in the second processing chamber can be maintained at about 0.1-760 Torr; (ii) a flow of gas can be provided to the second processing chamber at a rate of about 200-10,000 sccm for a duration of about 1-10 minutes, and the substrate can be exposed to the flow of gas, the flow of gas being selected from the group consisting of diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), water (H 2 and (iii) the substrate may be baked at a temperature of about 140-300° C. may be used during the post-development bake process of (b).

[0021] In these or other embodiments, the method can be performed under the following conditions: (i) the pressure in the process chamber can be about 0.1 to 1 Torr; (ii) a plasma generating gas can be provided at a rate of about 50 to 5,000 for a duration of about 3 to 30 seconds, the plasma generating gas being: (a) H 2 , (b) H 2 and N 2 , (c) H 2 and noble gases, (d) H 2 N for None2 , (e) H 2 The method may further include exposing the substrate to a plasma in the processing chamber under (iii) a plasma generated from the plasma generating gas, and wherein the substrate is exposed to the plasma, and the gas mixture may include at least one gas or gas mixture selected from the group consisting of a noble gas, ...

[0022] In these or other embodiments, at least one of (a) and (b) may occur within a processing chamber, and the method may further include cleaning the processing chamber to remove metal from an interior surface of the processing chamber. In some embodiments, the processing chamber may be cleaned using the following conditions: (i) the pressure within the processing chamber may be about 0.1-10 Torr, (ii) a plasma including H radicals may be exposed to the processing chamber, where the H radicals react with metals on the interior surface of the processing chamber to form metal hydrides, (iii) the plasma may be generated using about 300-4,000 Watts of RF power, and (iv) the processing chamber may be maintained at about 25-250° C. In these or other embodiments, the processing chamber may be cleaned using the following conditions: (i) the pressure within the processing chamber may be about 0.1-10 Torr, and may be cycled between lower and higher pressures as part of the pumping and purging process, (ii) the processing chamber is not exposed to a plasma during cleaning, and (iii) a gas flow may be provided to the processing chamber during cleaning, where the gas flow may include diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), a noble gas, and combinations thereof, and (iv) the processing chamber can be maintained at about 25-250° C.

[0023] In these or other embodiments, the method may further include performing a wet clean on the backside of the substrate using the following conditions: (i) in a first step, the substrate may be exposed to a first cleaning solution provided at a rate of about 1-3 L / min, the first cleaning solution comprising dilute HF; (ii) in a second step, the substrate may be exposed to a second cleaning solution provided at a rate of about 1-3 L / min, the second cleaning solution comprising a solution selected from the group consisting of dilute HCl, standard clean 1, and combinations thereof; (iii) the first and second steps together may have a duration of about 20-300 seconds; and (iv) the substrate may be maintained at about 15-60° C.

[0024] In these or other embodiments, the concentration of metal in at least one of the backside or beveled edge regions of the substrate is about 1E11 atoms / cm 2 In these or other embodiments, the concentration of the metal in at least one of the backside or beveled edge regions of the substrate may be reduced by at least an order of magnitude to about 1E10 atoms / cm 2 This can be reduced by at least an order of magnitude to:

[0025] In these or other embodiments, the metal may be tin.

[0026] In another aspect of the disclosed embodiments, a system for processing a substrate is provided, the system including a processing chamber, an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber, an outlet to the processing chamber for removing material from the processing chamber, a heater, a substrate support, and a controller configured to cause any one or more of the claimed methods or methods otherwise described herein.

[0027] In another aspect of the disclosed embodiments, a system for processing a substrate is provided, the system including a processing chamber, an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber, an outlet to the processing chamber for removing material from the processing chamber, a heater, a substrate support, and a controller configured to: (a) either (i) process a front side of a substrate, thereby causing formation of contamination at a back side of the substrate, the contamination comprising a metal, or (ii) receive a substrate with contamination on a back side of the substrate, and (b) after (a), heat the substrate in a post-processing bake process, where heating the substrate reduces a concentration of the metal on the back side of the substrate.

[0028] In some embodiments, treating the front side of the substrate may include at least one process selected from the group consisting of developing a layer of photoresist, in-situ cleaning the substrate, withdrawing mandrels in patterning applications, smoothing features on the substrate, and descumming the layer of photoresist.

[0029] In these or other embodiments, the controller may be configured to cause (a) by either (i) developing a layer of photoresist on a substrate, or (ii) receiving a substrate with a layer of photoresist developed on a front side of the substrate and a back side of the substrate, where metal in the contamination originates from the layer of photoresist on the front side of the substrate, and (b) a post-processing bake process that occurs when the layer of photoresist is at least partially developed.

[0030] In various embodiments, (a) and (b) can both occur in the same processing chamber. In other embodiments, (a) can occur in a processing chamber and (b) can occur in a second processing chamber, which is a different processing chamber from the processing chamber.

[0031] In these or other embodiments, the system may further include a plasma generator configured to provide a plasma within the processing chamber.

[0032] In some cases, the plasma generator may be a remote plasma generator, such that the plasma is generated at a first location outside the processing chamber and delivered to a second location inside the processing chamber. These and other aspects are further described below with reference to the drawings. [Brief description of the drawings]

[0033] [Figure 1] FIG. 1 is a flow diagram of an example method for depositing, developing, and treating photoresist, according to some embodiments.

[0034] [Figure 2A] 1A-1D are cross-sectional schematic diagrams of various processing stages of a wet backside and bevel edge cleaning process, according to certain embodiments. [Figure 2B] 1A-1D are cross-sectional schematic diagrams of various processing stages of a wet backside and bevel edge cleaning process, according to certain embodiments. [Figure 2C] 1A-1D are cross-sectional schematic diagrams of various processing stages of a wet backside and bevel edge cleaning process, according to certain embodiments. [Figure 2D] 1A-1D are cross-sectional schematic diagrams of various processing stages of a wet backside and bevel edge cleaning process, according to certain embodiments.

[0035] [Figure 3A] 1A-1D are cross-sectional schematic diagrams of various processing stages of a dry backside and bevel edge cleaning process, according to certain embodiments. [Figure 3B] 1A-1D are cross-sectional schematic diagrams of various processing stages of a dry backside and bevel edge cleaning process, according to certain embodiments. [Figure 3C] 1A-1D are cross-sectional schematic diagrams of various processing stages of a dry backside and bevel edge cleaning process, according to certain embodiments.

[0036] [Figure 4] FIG. 2 is a schematic diagram of a processing chamber for performing dry backside and bevel edge cleaning according to some embodiments.

[0037] [Figure 5A] 1 illustrates a perspective view of a carrier ring for supporting a substrate in a processing chamber according to some embodiments.

[0038] [Figure 5B] 1 is a cross-sectional schematic diagram of a carrier ring supporting and contacting the backside of a substrate according to some embodiments.

[0039] [Figure 6] FIG. 2 is a schematic diagram of an example process station for maintaining a low pressure environment suitable for performing backside and bevel edge cleaning operations, according to some embodiments.

[0040] [Figure 7] FIG. 1 is a schematic diagram of an example multi-station processing tool suitable for implementing the various developing, cleaning, reworking, descumming, and smoothing operations described herein.

[0041] [Figure 8] 1 is a cross-sectional schematic diagram of an example inductively coupled plasma apparatus for implementing certain embodiments and operations described herein.

[0042] [Figure 9] FIG. 1 depicts a semiconductor process cluster tool architecture having a vacuum integrated deposition and patterning module interfaced with a vacuum transfer module, suitable for implementing the processes described herein.

[0043] [Figure 10] FIG. 2 depicts a wet processing chamber according to various embodiments herein.

[0044] [Figure 11]1 depicts experimental results showing the concentration of tin on the backside of a substrate after various processing steps described herein. [Figure 12] 1 depicts experimental results showing the concentration of tin on the backside of a substrate after various processing steps described herein.

[0045] [Figure 13A] FIG. 1 depicts experimental results showing the concentration of tin on the backside of a substrate for queue times of different durations. [Figure 13B] FIG. 1 depicts experimental results showing the concentration of tin on the backside of a substrate for queue times of different durations.

[0046] [Figure 14] 1 depicts experimental results showing the benefits of adding a plasma treatment during the post-develop bake step.

[0047] [Figure 15] 1 depicts experimental results showing that remaining tin contamination is concentrated after various processing steps described herein.

[0048] [Figure 16A] 1 depicts experimental results showing the effectiveness of a post-development bake process as described herein, particularly with respect to line critical dimensions. [Figure 16B] 1 depicts experimental results showing the effectiveness of a post-development bake process as described herein, particularly with respect to linewidth roughness.

[0049] [Figure 17A] FIG. 1 depicts experimental results showing the concentration of residual bromine on the front side of a substrate after processing in post-development bakes performed at various temperatures. [Figure 17B] FIG. 1 depicts experimental results showing the concentration of tin on the backside of a substrate after processing in post-development bakes performed at various temperatures.

[0050] [Figure 18A] 1 depicts experimental results showing the benefits of periodically cleaning the processing chamber used to perform the post-develop bake process. [Figure 18B] 1 depicts experimental results showing the benefits of periodically cleaning the processing chamber used to perform the post-develop bake process.

[0051] [Figure 19A] 1A-1D show experimental results related to optimizing plasma processing, in accordance with various embodiments. [Figure 19B] 1A-1D show experimental results related to optimizing plasma processing, in accordance with various embodiments.

[0052] [Figure 20] 1 is an example process flow according to various embodiments. [Figure 21] 1 is an example process flow according to various embodiments.

[0053] [Figure 22] FIG. 1 illustrates substrate-to-substrate contamination that can occur within a processing apparatus. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] The present disclosure generally relates to the field of semiconductor processing. In a particular embodiment, the present disclosure is directed to a process and apparatus for treating and cleaning photoresist (e.g., EUV-sensitive metal and / or metal oxide-containing photoresist) to remove unwanted photoresist and related materials such as metal and metal bromide deposited on the backside and beveled edge of a substrate, for example, in the context of photoresist patterning.

[0055] In this specification, detailed reference is made to certain embodiments of the present disclosure. Examples of certain embodiments are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the present disclosure to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0056] For example, the disclosure is provided primarily in the context of photoresist deposition, development, and processing, although the embodiments are not so limited. The various techniques described herein may be applied in other contexts as well, particularly where it is desired to limit outgassing of metal-containing species, such as metal halides, from the substrate and / or remove metal-containing species from the substrate (particularly, but not limited to, the backside and beveled edge regions of the substrate). Such techniques may be particularly useful where the metal is tin and / or the undesired material is tin bromide, although other metals and halogens may be used as well. Examples of other processes that may benefit from implementation of one or more of the disclosed techniques include, but are not limited to, in-situ cleaning, mandrel withdrawal, smoothing operations, and photoresist descum operations. Processes described herein as occurring "after development" may occur after other types of operations (e.g., deposition, etching, processing, etc.) in the contexts listed above. For example, a post-development bake (PDB) operation may instead be implemented as a post-deposition bake, a post-etch bake, a post-processing bake, etc. In some such cases, the photoresist layers described herein may be replaced with another metal-containing or metal halide-containing layer. For purposes of clarity and brevity, this disclosure focuses on embodiments in the context of photoresist deposition, development, and processing.

[0057] introduction Patterning of thin films in semiconductor processing is often a critical step in the fabrication of semiconductors. Patterning involves lithography. In conventional photolithography, such as 193 nm photolithography, a pattern is printed by emitting photons from a photon source onto a mask, printing the pattern onto a light-sensitive photoresist, thereby causing a chemical reaction in the photoresist that, after development, removes certain portions of the photoresist to form the pattern.

[0058] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include nodes 22 nm, 16 nm, and above. At the 16 nm node, for example, the width of a typical via or line in a damascene structure is typically about 30 nm or less. The scaling of features on advanced semiconductor integrated circuits (ICs) and other devices is driving lithography to improve resolution.

[0059] Extreme ultraviolet (EUV) lithography can expand lithography technology by moving to imaging source wavelengths smaller than achievable with conventional photolithography methods. EUV sources of approximately 10-20 nm, or 11-14 nm wavelength, e.g., 13.5 nm wavelength, can be used for state-of-the-art lithography tools, also called scanners. EUV radiation is strongly absorbed in a wide range of solid and fluid materials, including quartz and water vapor, and also operates in a vacuum.

[0060] EUV lithography utilizes an EUV resist that is patterned to form a mask for use in etching the underlying layer. The EUV resist can be a polymer-based chemically amplified resist (CAR) produced by a liquid-based spin-on technique. An alternative to CAR is available from Inpria, Corvallis, OR, and is also a directly photopatternable metal oxide-containing film, such as those described in, for example, U.S. Patent Publication Nos. 2017 / 0102612 and 2016 / 0116839, which are incorporated by reference herein at least for their disclosure of photopatternable metal oxide-containing films. Such films can be produced by spin-on techniques or dry deposition. Metal oxide-containing films can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum atmosphere providing sub-30 nm patterning resolution, as described, for example, in U.S. Patent No. 9,996,004, entitled "EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS," issued June 12, 2018, and / or application PCT / US19 / 31618, entitled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," filed May 9, 2019, the disclosures of which are incorporated by reference herein, at least with respect to the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks. Generally, patterning involves exposing an EUV resist to EUV radiation to form a photopattern in the resist, followed by development to remove portions of the resist with the photopattern to form a mask.

[0061] While the present disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, it should also be understood that the present disclosure is applicable to other next generation lithography techniques. In addition to EUV, which includes the standard 13.5 nm EUV wavelength currently in use and being developed, the most relevant radiation sources for such lithography are DUV (deep UV), which generally refers to the use of 248 nm or 193 nm excimer laser sources, X-ray, which includes EUV formally in the lower energy range of the X-ray range, and e-beam, which may cover a wide range of energies. The particular method may depend on the particular materials and applications used in the semiconductor substrate and the final semiconductor device. Thus, the methods described in this application are merely exemplary of methods and materials that may be used in the present technology.

[0062] Directly photopatternable EUV resists may consist of or contain metals and / or metal oxides mixed within an organic component. Metals / metal oxides are very promising in that they may enhance EUV photon absorption, generate secondary electrons, and / or exhibit increased etch selectivity to underlying film stacks and device layers.

[0063] During application of a photoresist film (e.g., EUV photoresist film) to a substrate, either by conventional wet processing, e.g., spin-on processing, or dry deposition, there may be some unintentional deposition of resist material on the wafer backside and / or bevel edges. Similarly, development of the photoresist film on the substrate may cause contamination (e.g., including metals and metal halides) in these same regions. This backside and bevel contamination may cause downstream processing problems, including contamination of patterning (scanner), development tools, and downstream processing and metrology tools. Such contamination may harm the performance of the tools, as well as the films deposited on the front side of the wafer. Often, removal of this backside and bevel deposition is done by wet cleaning techniques, although dry cleaning techniques may be used as well.

[0064] FIG. 22 illustrates a pair of semiconductor substrates loaded into a Front Opening Unified Pod (FOUP) and shows how metal contamination from the first substrate can be redeposited on the second substrate during the dry development step. Such redeposition can occur when multiple substrates are stored in a single FOUP or similar enclosure. A FOUP is a special container designed to securely hold semiconductor substrates in a controlled manner, allowing the substrates to be transferred between different equipment depending on the processing and / or metrology needs. In a first stage, prior to development of the photoresist, the first substrate is in a first slot of the FOUP and the second substrate is in a second slot of the FOUP. The substrates each include a layer of photoresist 2201 that includes both exposed and unexposed portions. In a second stage, the photoresist 2201 is developed. In this example, a dry development process is used. However, in various other embodiments, a wet development process can be used. The development process selectively removes the exposed or unexposed portions of the photoresist 2201, thereby forming a pattern in the photoresist. During the development process, development by-products (e.g., R-SnBr x , 1≦x≦3) is unnecessarily redeposited on the front side of the substrate. In a third stage, the substrate contaminated with development by-products is loaded into a first slot of the FOUP. Over time, contamination from the front side of the substrate in the first slot can be transferred to the back side of the substrate in the second slot. Such a spread of contamination is undesirable.

[0065] The present disclosure provides various techniques for minimizing outgassing of metal and / or metal halide species from metal-containing films on a substrate. In some cases, the methods involve treating the substrate to make the potentially contaminating species more volatile so that they can be removed from the substrate and processing chamber. In some cases, the methods involve treating the substrate to make the potentially contaminating species more stable so that they are less likely to outgas from the substrate during downstream processing. In various cases, the methods involve cleaning the backside and beveled edge areas of the substrate after photoresist development to address contamination generated during development. These techniques may be combined as desired for a particular application. In various embodiments, the techniques may also act to prevent or reduce undesired surface migration and / or undesired reactions on the substrate. Advantageously, the techniques herein have shown small or negligible impact on patterns defined in the photoresist. Furthermore, such techniques may provide improvements in line width roughness (LWR).

[0066] Certain operations provided herein may be limited to specific regions to ensure removal of material from the backside and beveled edge regions without film degradation on the frontside of the substrate. These operations may include, for example, backside and beveled edge cleaning operations. Other operations described herein may act on the frontside of the substrate, or the entire substrate, for example, to purposefully modify metal-containing species on one or more substrate surfaces.

[0067] In some embodiments, the undesired materials on the substrate include EUV resist material. In some embodiments, the undesired materials include metals, metal halides, and / or organometallic halides resulting from reactions of metals in the EUV resist material with halogens in the developer chemistry. These may be referred to as etch or developer by-products. Such by-products can include metal bromides and metal chlorides at up to about 1E16 atoms / cm, about 2-3 orders of magnitude higher than is typically acceptable for device fabrication. 2In some cases, the metal is tin and the metal halide is SnBr. x and / or the organometallic halide is RSnBrx. In these or other cases, the metal is tin, the metal halide is SnClx, and / or the organometallic halide is RSnClx. Other metals and halides may be used as well. Often, unwanted material is deposited on the backside and bevel edge areas of the substrate.

[0068] FIG. 1 presents a flow diagram of an example method for depositing and developing photoresist, according to some embodiments. The operations of process 100 may be performed in a different order and / or with different, fewer, or additional operations. One or more operations of process 100 may be performed using an apparatus illustrated in any one of FIGS. 6-9. In some embodiments, the operations of process 100 may be performed, at least in part, according to software stored on one or more non-transitory computer-readable media.

[0069] In block 102 of process 100, a layer of photoresist is deposited. This can be either a dry deposition process, such as an evaporation process, or a wet process, such as a spin-on deposition process.

[0070] The photoresist may be a metal-containing EUV resist. Generally speaking, conventional chemically amplified photoresist materials do not contain significant amounts of metals and do not suffer from the associated metal contamination problems to the same extent. As such, the methods herein may be practiced on any type of photoresist or other film, but they may have the greatest value in combating contamination from metal-containing EUV resists. The EUV-sensitive metal or metal oxide-containing film may be deposited on a semiconductor substrate by any suitable technique, including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the described process has been demonstrated for organotin oxide-based EUV photoresist compositions and is applicable to both commercially available spin-coatable formulations (such as those available from Inpria Corp, Corvallis, OR) and formulations applied using dry vacuum deposition techniques as further described below. Although the photoresists described in this disclosure are often described as metal-containing EUV resist materials, it should be understood that the process operations of the present disclosure may be applied to any other films, such as silicon-based or carbon-based films.

[0071] The semiconductor substrate may include any material structure suitable for photolithographic processing, particularly for the production of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer having irregular surface topography on which features are created ("underlying features"). As used herein, the front side of the substrate is the surface on which a film is intentionally deposited or that will be exposed to EUV during processing. The back side of the substrate is opposite the front side. The underlying features may include areas from which material has been removed (e.g., by etching) or areas from which material has been added (e.g., by deposition) during processing prior to performing the methods of the present disclosure. Such pre-processing may include the methods of the present disclosure or other processing methods in an iterative process in which two or more layers of features are formed on the substrate.

[0072] EUV-sensitive thin films can be deposited on semiconductor substrates, such films operable as resists for subsequent EUV lithography and processing. Such EUV-sensitive thin films include materials that undergo changes upon exposure to EUV, such as loss of bulky pendant substituents attached to metal atoms in low-density M-OH-rich materials, allowing their cross-linking into denser MOM-attached metal oxide materials. Through EUV patterning, regions of the film are created that have altered physical or chemical properties relative to unexposed regions. These properties can be exploited in subsequent processing, such as dissolving either the unexposed or exposed regions, or selectively depositing material in either the exposed or unexposed regions. In some embodiments, the unexposed film has a more hydrophobic surface than the exposed film under the conditions under which such subsequent processing is performed. For example, removal of material can be performed by exploiting differences in the chemical composition, density, and cross-linking of the film. Removal can be by wet or dry processing, as further described below.

[0073] The thin film, in various embodiments, is an organometallic material, such as an organotin material including tin oxide, or other metal oxide material / moiety. The organometallic compound can be made in a gas phase reaction of an organometallic precursor with a counter reactant. In various embodiments, the organometallic compound is formed through mixing a specific combination of organometallic precursors having bulky alkyl or fluoroalkyl groups with a counter reactant and polymerizing the mixture in the gas phase to produce a low density EUV sensitive material that is deposited on the semiconductor substrate.

[0074] In various embodiments, the organometallic precursors contain at least one alkyl group on each metal atom that may survive the gas phase reaction, while other ligands or ions coordinated to the metal atom may be replaced by counter reactants. Organometallic precursors include those of the formula: M a R b L c (Formula 1) where M is an element having a high patterned radiation absorption cross section and R is C n H 2n+1 etc., alkyl, preferably n≧3, L is a ligand, ion, or other moiety that reacts with a counterreactant, a≧1, b≧1, and c≧1.

[0075] In various embodiments, M is 1×10 7 cm 2 / mol. M can be, for example, selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, iodine, antimony, germanium, and combinations thereof. In some embodiments, M is tin. R can be fluorinated, for example, represented by the formula C n F x H (2n+1) In various embodiments, R has at least one beta hydrogen or beta fluorine. For example, R can be selected from the group consisting of i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L can be any moiety that is readily displaced by a counter reactant to generate an M-OH moiety, such as a moiety selected from the group consisting of amines (dialkylamino, monoalkylamino, etc.), alkoxy, carboxylate, halogen, and mixtures thereof.

[0076] The organometallic precursor can be any of a variety of candidate organometallic precursors. For example, when M is tin, such precursors include analogous alkyl(tris)(t-butoxy)tin compounds such as t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(diethylamino)tin, and t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0077] The counter reactant has the ability to replace a reactive moiety, ligand, or ion (e.g., L in Formula 1 above) to link at least two metal atoms by a chemical bond. Counter reactants may include water, peroxides (e.g., hydrogen peroxide), dihydric or polyhydric alcohols, fluorinated dihydric or polyhydric alcohols, fluorinated glycols, and other sources of hydroxy moieties. In various embodiments, the counter reactant reacts with the organometallic precursor by forming oxygen bridges between neighboring metal atoms. Other potential counter reactants include hydrogen sulfide and hydrogen disulfide, which may cross-link metal atoms via sulfur bridges.

[0078] The thin films may include optional materials in addition to the organometallic precursors and counter reactants to modify the chemical or physical properties of the film, such as to modify the film's sensitivity to EUV or to increase etch resistance. Such optional materials may be introduced, such as by doping during vapor phase formation, before deposition on the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, mild remote H 2 A plasma can be introduced to replace some Sn-L bonds with Sn-H, thereby increasing the reactivity of the resist under EUV.

[0079] In various embodiments, the EUV patternable film is made or deposited on the semiconductor substrate using deposition equipment and processes, among others known in the art. In such processes, polymerized organometallic materials are formed on the surface of the semiconductor substrate in the gas phase or in situ. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with CVD components, such as discontinuous ALD-like processes in which the metal precursor and the counter reactant are separated in either time or space.

[0080] In general, the method includes mixing a vapor flow of an organometallic precursor with a vapor flow of a counter-reactant to form a polymerized organometallic material, and depositing the organometallic material onto a surface of a semiconductor substrate. In some embodiments, two or more organometallic precursors are included in the vapor flow. In some embodiments, two or more counter-reactants are included in the vapor flow. As will be appreciated by one of skill in the art, the mixing and deposition aspects of the process can occur simultaneously in a substantially continuous process.

[0081] In an exemplary continuous CVD process, two or more gas streams of organometallic precursor and counter-reactant sources in separate inlet paths are introduced into a deposition chamber of a CVD apparatus, where they mix and react in the gas phase to form an aggregated polymerized material (e.g., by metal-oxygen-metal bond formation). The streams can be introduced, for example, using separate injection inlets or a dual plenum showerhead. The apparatus is configured to allow the organometallic precursor and counter-reactant streams to mix in the chamber, allowing the organometallic precursor and counter-reactant to react to form a polymerized organometallic material. Without limiting the mechanism, function, or utility of the present technology, it is believed that the products from such gas-phase reactions will be heavier in molecular weight because the metal atoms are bridged by the counter-reactant and then condensed or otherwise deposited onto a semiconductor substrate. In various embodiments, the steric hindrance of the bulky alkyl groups prevents the formation of a dense network, producing a porous, low-density film.

[0082] CVD processes are typically carried out at reduced pressure, such as between 10 mTorr and 10 Torr. In some embodiments, the process is carried out at between 0.5 and 2 Torr. In some embodiments, the temperature of the semiconductor substrate is at or below the temperature of the reaction stream. For example, the substrate temperature can be between 0° C. and 250° C., or between ambient temperature (e.g., 23° C.) and 150° C. In various processes, deposition of polymerized organometallic material onto the substrate occurs at a rate inversely proportional to the surface temperature.

[0083] In some embodiments, the EUV patternable film is fabricated or deposited on the semiconductor substrate using wet deposition equipment and processes, among others known in the art, for example, an organometallic material is formed by spin coating onto the surface of the semiconductor substrate.

[0084] The thickness of the EUV patternable film formed on the surface of the semiconductor substrate may vary according to the surface characteristics, the materials used, and the processing conditions. In various embodiments, the film thickness may range from 0.5 nm to 100 nm and may be thick enough to absorb most of the EUV light under the conditions of EUV patterning. For example, the overall absorbance of the resist film may be 30% or less (e.g., 10% or less, or 5% or less) so that the resist material at the bottom of the resist film is fully exposed. In some embodiments, the film thickness is 5 nm to 40 nm, or 10 nm to 20 nm. Without limiting the mechanism, function, or utility of the present disclosure, it is believed that, unlike wet spin-coat deposition processes, dry deposition processes present fewer limitations on the surface adhesion properties of the substrate and thus may be applied to a wide range of substrates. Furthermore, as discussed above, the deposited film conforms to surface features, providing the advantage of forming a mask over a substrate, such as a substrate having underlying features, without "filling" or otherwise planarizing such features.

[0085] At block 104, a cleaning process is performed to clean the backside and beveled edges of the semiconductor substrate. The backside and beveled edge cleaning may non-selectively etch the EUV resist film to equally remove films with different levels of oxidation or cross-linking at the substrate backside and beveled edges. During application of the EUV patternable film by either wet or dry deposition processes, there may be some unintentional deposition of resist material on the substrate beveled edges and / or backside. The unintentional deposition may lead to unwanted particles subsequently migrating to the top surface of the semiconductor substrate and becoming particle defects. Furthermore, this beveled edge and backside deposition may cause downstream processing issues including contamination of patterning tools (scanners), development tools, and metrology tools, which may subsequently act to contaminate other substrates. Removal of this beveled edge and backside deposition may be achieved using wet or dry cleaning techniques, alone or in combination with other techniques described herein.

[0086] The state of the art for cleaning spin-coated organometallic photoresist is by wet cleaning processes. An example is described below with reference to Figures 2A-2D. Edge bead removal (EBR) is performed on a wetting track on both the front and back side of the wafer. A nozzle is positioned over the edge of the wafer on both the front and back side of the wafer, and a solvent is dispensed while the wafer is spinning. An organic solvent (e.g., PGME, PGMEA, 2-heptanone) dissolves the photoresist on the edge and cleans the beveled edge area. If the backside is contaminated, the wafer can proceed to a separate wet cleaning station for backside cleaning of the wafer. In the case of spin coating, the wafer area in contact with the chuck is typically left clean, and a separate backside clean is not always used. Additional cleaning agents such as dilute hydrofluoric acid (dHF), dilute hydrochloric acid (dHCl), dilute sulfuric acid, or standard clean 1 (SC-1) are used. Cleaning solution may be necessary to reduce metal contamination. A backside scrub is typically performed before entering the EUV scanner.

[0087] Dry backside and beveled edge cleaning techniques may be used in place of wet techniques. The dry backside and beveled edge cleaning may be performed using an etching gas. The etching gas may be hydrogen gas, hydrogen halide, hydrogen gas and a halide gas, or boron trichloride. The processing chamber may be equipped with a substrate support having a plurality of minimum contact area (MCA) supports that tilt the substrate so that the etching gas can access the backside of the substrate. The substrate support may be a carrier ring, as described below in connection with FIG. 5A. The etching gas may be delivered in a first etching gas stream from below the substrate support. The gas distributor may deliver a curtain gas at the center of the frontside of the substrate to restrict the etching gas from reaching the center of the frontside. The gas distributor may also deliver the etching gas in a second etching gas stream at the periphery of the frontside of the substrate. A heat source, such as a radiant heat source, may be applied to the substrate during the dry backside and beveled edge cleaning. The radiant heat source may be positioned below the substrate support. Both the backside cleaning and the beveled edge cleaning are performed in the same processing chamber. In some embodiments, the deposition operation and the dry backside and beveled edge cleaning are performed in the same processing chamber. In some embodiments, the post-apply bake (PAB) and the dry backside and beveled edge cleaning are performed in the same processing chamber. Tool / chamber consolidation in a single chamber increases throughput, reduces costs, and reduces the possibility of contamination that would otherwise occur between transfers.

[0088] In some embodiments, the dry cleaning process uses the following gases: HBr, HCl, HI, BCl 3 , SOCl 2 , Cl 2 , BBr 3 , H 2 , O 2 , PCl 3 , C.H. 4 , Methanol, Ammonia, Formic Acid, NF 3, HF, or HF. In some embodiments, the dry cleaning process may use the same chemistry as the dry development process described herein. For example, the backside and bevel cleaning may use a hydrogen halide development chemistry. For the backside and bevel cleaning process, the vapor and / or plasma must be limited to specific areas of the substrate to ensure that only the backside and bevel deposits are removed without any film degradation on the front side of the substrate.

[0089] Process conditions may be optimized for backside and bevel cleaning. In some embodiments, higher temperatures, higher pressures, and / or higher reactant flows may result in increased etch rates. Suitable process conditions for dry bevel and backside cleaning include etching the photoresist. Membrane Depending on the composition and nature, reactant flows of 100 to 10,000 sccm (e.g., 500 sccm HCl, HBr, HI, or H 2 and Cl 2 , Br 2 , or I 2 , BCl 3 , or H 2 ), a temperature of 20° C. to 120° C. (e.g., 100° C.), a pressure of 20 mTorr to atmospheric pressure (e.g., 300 mTorr), a plasma power of 0 W to 500 W at high frequency (e.g., 13.56 MHz), and a time of about 10 to 150 seconds. These conditions are suitable for some process reactors, e.g., the Kiyo etch tool available from Lam Research Corporation, Fremont, Calif., but it should be understood that a wider range of process conditions may be used according to the capabilities of the process reactor.

[0090] Although the backside and bevel cleaning in block 104 is depicted before the PAB treatment in block 106, it should be understood that the backside and bevel cleaning in block 104 may be performed at any stage in the process 100 after the deposition of photoresist in block 102 and before the development in block 112. Thus, the backside and bevel cleaning in block 104 may be performed after photoresist deposition, after PAB treatment, after EUV exposure, or after PEB treatment. As discussed further below, additional backside and bevel cleaning may be performed later in the process 100, for example, as described in connection with block 118. The first backside and bevel cleaning operation in block 104 targets the removal of undesired deposition resulting from the photoresist deposition in block 102, while the second backside and bevel cleaning operation in block 118 targets the removal of undesired contamination generated during the photoresist development in block 112. In some embodiments, one or both of the backside and bevel edge cleaning operations 104 and 118 may be omitted.

[0091] The wet or dry backside and bevel cleaning operation may alternatively be extended to a complete photoresist removal or photoresist “rework” in which the applied EUV photoresist is removed and the semiconductor substrate is prepared for photoresist reapplication, such as when the original photoresist is damaged or otherwise defective. Because photoresist rework must be accomplished without damaging the underlying semiconductor substrate, oxygen-based etches should be avoided. Instead, variants of halide-containing chemistries as described herein may be used. It should be understood that the photoresist rework operation may be applied at any stage during the process 100. Thus, the photoresist rework operation may be applied after photoresist deposition, after first or second bevel and backside cleaning, after PAB treatment, after EUV exposure, after PEB treatment, after development, after PDB treatment, after chemical, plasma, and / or light treatment. In some embodiments, the photoresist rework may be performed for non-selective removal of exposed and unexposed areas of the photoresist, but selective to the underlying layers.

[0092] In some embodiments, the photoresist rework process is performed using the following gases: HBr, HCl, HI, BCl 3 , Cl 2 , BBr 3 , H 2 , PCl 3 , C.H. 4 , Methanol, Ammonia, Formic Acid, NF 3 , HF, or other suitable photoresist rework processes may involve vapors and / or plasmas having one or more of the following: 1) hydrogen halide, 2) hydrogen fluoride, 3) hydrogen fluoride, 4) hydrogen fluoride, 5) hydrogen fluoride, 6) hydrogen fluoride, 7) hydrogen fluoride, 8) hydrogen fluoride, 9) hydrogen fluoride, 10) hydrogen fluoride, 11) hydrogen fluoride, 12) hydrogen fluoride, 13) hydrogen fluoride, 14) hydrogen fluoride, 15) hydrogen fluoride, 16) hydrogen fluoride, 17) hydrogen fluoride, 18) hydrogen fluoride, 19) hydrogen fluoride, 12) hydrogen fluoride, 19) hydrogen fluoride, 18) hydrogen fluoride, 19 ...

[0093] The process conditions can be optimized for photoresist rework. In some embodiments, higher temperatures, higher pressures, and / or higher reactant flows can lead to increased etch rates. Suitable process conditions for photoresist rework include: Membrane Depending on the composition and nature, reactant flows of 100-500 sccm (e.g., 500 sccm HCl, HBr, HI, BCl 3 or H 2 and Cl 2 or Br 2 ), temperature from -10 to 140 °C (e.g., 80 °C), pressure from 20 to 1000 mTorr (e.g., 300 mTorr), plasma power from 300 W to 800 W at high frequency (e.g., 13.56 MHz) (e.g., 500 W), and voltage from 0 to 200 V. b (higher bias may be used with harder underlying substrate materials), and a time of about 20 seconds to 3 minutes, sufficient to completely remove the EUV photoresist. In some embodiments, the photoresist rework may be performed without the application of plasma. The photoresist rework may be performed thermally using a halide-containing gas, such as a hydrogen halide (e.g., HBr), at an elevated temperature (e.g., 80° C. to 120° C.). These conditions are suitable for some processing reactors, e.g., Kiyo etch tools available from Lam Research Corporation, Fremont, Calif., but it should be understood that a broader range of process conditions may be used according to the capabilities of the processing reactor.

[0094] In block 106 of process 100, an optional post-application bake (PAB) is performed after deposition of the EUV patternable film and before EUV exposure, and / or after performing backside and bevel edge cleaning. The PAB process may involve a combination of thermal treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV patternable film and reduce the EUV dose to develop a pattern in the EUV patternable film. The PAB process temperature may be adjusted and optimized to increase the sensitivity of the EUV patternable film. For example, the process temperature may be about 90° C. to about 200° C., or about 150° C. to about 190° C. In some embodiments, the PAB process may be performed with ambient gas flowing in the range of 100 to 10,000 sccm, moisture content in the amount of a few percent up to 100% (e.g., 20% to 50%), pressure between atmospheric and vacuum, and process duration of about 1 to 15 minutes, e.g., about 2 minutes. In some embodiments, the PAB treatment is carried out at a temperature of about 100° C. to 200° C. for about 1 to 2 minutes.

[0095] In block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally speaking, the EUV exposure causes changes in chemical composition and cross-linking within the metal-containing EUV resist film, creating a contrast in etch sensitivity that can be exploited for subsequent development.

[0096] The metal-containing EUV resist film can then be patterned by exposing certain areas of the film to EUV light, typically under a relatively high vacuum. Among other useful herein, the EUV devices and imaging methods include methods known in the art. In particular, as discussed above, exposed areas of the film with modified physical or chemical properties relative to non-exposed areas are created through EUV patterning. For example, in the exposed areas, metal-carbon bond cleavage can occur via beta hydrogen elimination, leaving reactive and accessible metal hydride functionalities that can be converted to hydroxides and cross-linked metal oxide moieties by metal-oxygen bridges, which can be used to create chemical contrast as either a negative resist or a template for a hard mask. In general, a larger number of beta Hs in the alkyl group results in a more sensitive film. After exposure, the metal-containing EUV resist film can be baked to cause additional cross-linking of the metal oxide film. The difference in properties between the exposed and non-exposed areas can be exploited in subsequent processing, such as dissolving the non-exposed areas or depositing materials on the exposed areas. For example, the pattern can be developed using a dry method to form a metal oxide-containing mask. Methods and apparatus, among others, useful in such processes are described in PCT patent application PCT / US2019 / 067540, filed December 19, 2019, which is incorporated herein by reference for its method and apparatus disclosure.

[0097] In particular, in various embodiments, the hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed regions of the imaging layer, particularly when the exposure is carried out in a vacuum using EUV. However, removing the exposed imaging layer from the vacuum into air or using oxygen, ozone, H 2 O 2or the controlled introduction of water can result in the oxidation of surface Sn-H to Sn-OH. The difference in properties between the exposed and unexposed regions can be exploited in subsequent processing, such as by reacting the irradiated regions, the unirradiated regions, or both, with one or more reagents to selectively add or remove material from the imaging layer.

[0098] Without limiting the mechanism, function, or utility of the present technology, for example, 10 mJ / cm 2 ~100mJ / cm 2 EUV exposure at doses of 1000 nm can relieve steric hindrance and provide space for the low-density film to collapse. In addition, the reactive metal-H bonds generated in the beta-hydrogen elimination reaction can react with nearby active groups, such as hydroxyls, in the film, leading to further cross-linking and densification, creating a chemical contrast between exposed and unexposed regions.

[0099] After exposure of the metal-containing EUV resist film to EUV light, a photopatterned metal-containing EUV resist is provided, which includes EUV exposed and unexposed areas.

[0100] At block 110 of process 100, an optional post-exposure bake (PEB) is performed to further increase the contrast in etch sensitivity of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist is thermally treated in the presence of various chemical species to promote cross-linking of the EUV-exposed regions of the photopatterned metal-containing EUV resist.

[0101] In various embodiments, the bake strategy involves careful control of the bake environment, introduction of reactive gases, and / or careful control of the ramping rate of the bake temperature. Examples of useful reactive gases include, for example, air, H 2 O, H 2 O 2 Steam, CO 2 , C.O., O 2 , O 3, C.H. 4 , C.H. 3 OH, N 2 , H 2 , N.H. 3 , N 2 The PEB process is designed to (1) promote complete vaporization of organic fragments generated during EUV exposure, (2) oxidize metal hydride species (other products from the beta-H elimination reaction during EUV exposure) to metal hydroxides, and (3) promote cross-linking of nearby -OH groups to form a cross-linked metal oxide network. The bake temperature is carefully selected to achieve optimal EUV lithography performance. Too low a PEB temperature leads to incomplete removal of organic fragments, as well as insufficient cross-linking and, consequently, less chemical contrast for development at a given dose. Too high a PEB temperature also leads to adverse effects, including severe oxidation and film shrinkage in unexposed areas (in this example, areas removed by development of the patterned film to form the mask), as well as undesirable interdiffusion at the interface between the photopatterned metal-containing EUV resist and the underlayer, both of which contribute to loss of chemical contrast and increased defect density due to insoluble scum. The PEB treatment temperature can be about 100° C. to about 300° C., about 170° C. to about 290° C., or about 200° C. to about 240° C. In some embodiments, the PEB treatment can be performed with ambient gas flowing in the range of 100 to 10,000 sccm, water content in the amount of a few percent up to 100% (e.g., 20% to 50%), pressure between atmospheric and vacuum, and treatment duration of about 1 to 15 minutes, e.g., about 2 minutes. In some embodiments, the PEB heat treatment can be repeated to further increase the etch selectivity.

[0102] In block 112 of process 100, the photopatterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, either the exposed areas are removed (positive tone) or the unexposed areas are removed (negative tone). In some embodiments, the development may include selective deposition on either the exposed or unexposed areas of the photopatterned metal-containing EUV resist, followed by an etching operation. In various embodiments, these processes may be dry or wet processes. An example of a process for development involves an organotin oxide-containing EUV sensitive photoresist film (e.g., 10-30 nm thick, such as 20 nm) being subjected to an EUV exposure dose and a post-exposure bake, and then developed. The photoresist film may be deposited based on a gas phase reaction of an organotin precursor, such as isopropyl(tris)(dimethylamino)tin, and water vapor, or may be a spin-on film containing tin clusters within an organic matrix.

[0103] The photopatterned metal-containing EUV resist is developed by exposure to a developing chemical structure. In some embodiments, the developing chemical structure includes a halide-containing chemical structure. For example, a bromine-containing chemical structure, a chlorine-containing chemical structure, and / or a fluorine-containing chemical structure may be used. In various embodiments, the halide-containing chemical structure is a hydrogen halide, such as HBr, HCl, HI, and HF. Dry development techniques are further discussed in PCT Patent Application No. PCT / US2020 / 039615, filed June 25, 2020, which is incorporated herein by reference in its entirety.

[0104] The development operation in block 112 may be optimized in certain embodiments. Such optimization may be particularly useful when dry development techniques are used. Optimization may be performed to reduce metal and / or metal halides outgassing from the photoresist on the substrate, which may deposit on the backside and beveled edge regions of the substrate. Certain optimization techniques may facilitate removal of potentially contaminating species, while other techniques may passivate contaminating species to reduce their ability to outgas during downstream outgassing. The various optimizations described herein may be combined as desired for a particular application.

[0105] In various embodiments, the photoresist development operation in block 112 may be optimized by performing the development in a heated processing chamber. Such heating reduces the overall by-product concentration / accumulation in the chamber, which results in less undesirable by-product deposition on the substrate. In various embodiments, the processing chamber and / or showerhead are maintained at an elevated temperature, for example, about 40° C. or more, or about 65° C. or more, or about 80° C. or more, or about 100° C. or more. In these or other cases, the processing chamber and showerhead may be maintained at a maximum temperature of about 300° C. or less, or about 250° C. or less, or about 200° C. or less, or about 150° C. or less, or about 100° C. or less, or about 80° C. or less. In some cases, the temperature is actively controlled and varied during dry development. In such cases, the temperature is actively increased during dry development. In other such cases, the temperature is actively decreased during dry development.

[0106] In these or other embodiments, the photoresist developing operation in block 112 may be optimized by performing a high temperature purge step in an inert atmosphere at reduced pressure. The purge step may be performed at the end of the photoresist developing operation in block 112, or shortly thereafter, in the same processing chamber in which the developing operation occurs. Exemplary gases that may be provided to establish the inert atmosphere include, for example, Ar, He, N 2, Kr, Xe, and H2. Combinations of such gases may also be used. Exemplary gas flow rates may be about 200-10,000 sccm. The purge may have a duration of about 1-10 minutes, in some cases at least about 2 minutes, or at least about 5 minutes. The purge step may be performed at a pressure of about 5 mTorr to about 10 Torr. In some cases, the pressure may be at least about 10 mTorr. In these or other embodiments, the pressure may be about 1 Torr or less. The temperature during the purge step (e.g., the temperature of the processing chamber, showerhead, and / or substrate support) may be maintained at an elevated temperature, e.g., about 100° C. or greater, or about 120° C. or greater. In some cases, the processing chamber may be maintained at a temperature of about 100-250° C., or about 100-300° C., and the substrate support may be maintained at a temperature of about 120-250° C., or about 120-300° C.

[0107] In these or other embodiments, a pump-purge sequence may be used toward the end of or shortly after the development process in block 112. Such a process may involve one or more cycles of pumping the processing chamber down to a reduced pressure and sweeping the processing chamber with an inert gas. This pumping and purging increases the efficiency of halogen and metal halide removal from the substrate and the chamber.

[0108] In these or other cases, optimization may involve thermal treatments, such as the bake step described below in connection with block 114. In these or other cases, optimization may involve chemical, plasma, and / or light treatments, such as the processing operations described below in connection with block 116. As such, the operations described in connection with blocks 114 and / or 116 may overlap with the photoresist developing operation in block 112, in some cases toward the end of the developing operation. In other embodiments, the operations of blocks 114 and / or 116 may occur after the photoresist developing operation of block 112 is completed.

[0109] In block 114, the substrate is exposed to a post-develop bake (PDB). The PDB occurs after some or all of the photoresist has been developed in block 112. Although this step is referred to as a "post-develop bake," it should be understood that this step may also overlap to some extent with the development step, as described above.

[0110] Much like the photoresist deposition step in block 102, the photoresist development step in block 112 can cause metal and metal halide contamination on the backside and beveled edges of the substrate. As noted above, development is often performed using halide-containing chemistries such as HBr. In some cases, the halide chemistries react with metals in the photoresist, partially dissolving the photoresist and causing the formation of metal halides and / or other metal-containing species that can redeposit on the substrate, for example, on the backside and beveled edges of the substrate. Such contamination is detrimental for reasons explained above, including continued outgassing and contamination of other substrates and downstream processing equipment and metrology tools.

[0111] PDB processing may involve a combination of thermal treatment, optional chemical exposure, optional plasma exposure, and optional light exposure (discussed further in connection with block 116) to reduce the possibility of metals and metal halides outgassing during downstream processing. Thermal treatment involves exposing the substrate to an elevated temperature. For example, the substrate may be baked at a temperature of about 160-300° C. for a duration of about 1-10 minutes. In some cases, the temperature may be maintained at about 160-250° C., or about 160-220° C. Such baking may involve heating the substrate support, processing chamber, showerhead, and / or processing gases. In some cases, the walls of the processing chamber may be heated and / or maintained at an elevated temperature. An exemplary temperature for the chamber walls may be about 20-120° C. In some cases, the pressure during PDB processing may be maintained at a minimum of about 0.01 Torr or 0.1 Torr and at a maximum of about 1 Torr, 10 Torr, or atmospheric pressure (e.g., about 760 Torr). Exemplary process gases that may be provided to the processing chamber during PDB processing include, but are not limited to, N 2 , N 2 / O 2 Mixture of He, Ar, Xe, H 2 , chlorine-containing gases, fluorine-containing gases, oxygen-containing gases, and combinations thereof. Exemplary chlorine-containing gases, fluorine-containing gases, and oxygen-containing gases are discussed below. Exemplary flow rates are about 200-10,000 sccm.

[0112] The PDB treatment removes physisorbed metal halide species (e.g., in various embodiments, SnBr xand / or other tin halides or metal halides) from the substrate surface. However, PDB treatment may be ineffective in completely removing metal halide species from relevant portions of the substrate (e.g., backside and beveled edge regions) and chemisorbed halide species (e.g., metal halide species) may remain on the substrate after PDB treatment. Furthermore, metal-containing photoresist on the frontside of the substrate continues to be a source of further outgassing and related contamination. In various embodiments, remaining chemisorbed species / contamination may be removed in a wet cleaning operation described below in block 118.

[0113] In some embodiments, the PDB process is a thermal process that does not involve exposing the substrate to a reactive chemical structure or plasma. When a reactive chemical structure or plasma is not used in conjunction with the PDB process in block 114, the use of the pumping and purging sequence described above is particularly beneficial in reducing contamination on the substrate. In embodiments where the PDB process is a thermal process and no additional cleaning steps are used (e.g., blocks 116 and 118 are omitted), outgassing can still be an issue over a longer time frame, e.g., several days. In such embodiments, the queue time for a particular substrate after it is exposed to the PDB process in block 114 and before the substrate is used for further processing can be controlled using a maximum queue time of, e.g., about 1 day, about 2 days, about 3 days, or about 5 days. Such control of the queue time limits the amount of outgassing / recontamination resulting from each substrate, thereby limiting contamination on the substrate, nearby substrates, and downstream processing equipment and metrology tools. Without wishing to be bound by theory or mechanism of action, it is believed that the mechanism of recontamination is a surface hopping or diffusion mechanism. Additional pump-purge sequences, as well as queue time control, can limit such recontamination. Of course, such techniques are particularly beneficial in embodiments in which the substrate is not subjected to further cleaning after PDB processing, although it should be understood that pump-purge sequences, as well as queue time control, can also be used in other embodiments in which additional cleaning steps are used. Moreover, such pump-purge sequences can be performed at any time during the method of FIG. 1, for example, in conjunction with the operations at blocks 112, 114, and / or 116.

[0114] In some embodiments, the PDB treatment of block 114 may involve exposing the substrate to a reactive chemical structure, plasma, and / or light, as described in connection with block 116. In some other embodiments, the operations described in connection with block 116 may occur after the PDB treatment of block 114. As noted above, the PDB treatment of block 114 may also overlap with the photoresist development step in block 112. As such, it should be understood that the operations of block 116 may also overlap with the operations of block 112. In other cases, the substrate may be subjected to a PDB treatment after the operations of blocks 112 and / or 114 are completed, e.g., in the same or a different processing chamber in which the operations of blocks 112 and / or 114 occur. Block 116 Operation The coated substrate may be exposed to chemical, plasma, and / or light treatments at .

[0115] Block 116 optionally involves exposing the substrate to a chemical, plasma, and / or light treatment. Such treatments may be combined as desired for a particular application. In some cases, the treatment is intended to modify the metal-containing species (e.g., metal or metal halide) so that it becomes more volatile, thereby allowing the metal-containing species to be removed from the substrate and processing chamber via a vacuum connection. Such treatments benefit from relatively high temperatures and low pressures (which may involve, for example, one or more purges) to facilitate removal of the volatile species.

[0116] One technique for achieving such increased volatility is to modify the substrate with a chlorine-containing chemical structure, such as BCl. 3 , Cl 2 , HCl, SiCl 4 , SOCl 2 , and PCl 3This technique is particularly useful if the photoresist was developed in block 112 using a bromine-based chemistry such as HBr. Exposure of the substrate to a chlorine-containing chemistry in block 116 results in the formation of species (e.g., metal chlorides) that are more volatile than pre-existing contaminating species (e.g., metals and metal bromides). Another technique for achieving increased volatility is to expose the substrate to hydrogen (e.g., H) at a relatively high temperature, e.g., at least about 200° C., or at least about 250° C. 2 ). The chemical exposure can have a duration of about 1-10 minutes. Increasing the volatility of the contaminating species facilitates removal of the contaminating species from the substrate and processing chamber. In various embodiments in which the substrate is exposed to chemical, plasma, and / or light treatments, the processing chamber can be purged after the treatment (e.g., using the purge and / or pump-purge sequences described above).

[0117] In some cases, the treatment of block 116 is intended to modify the metal-containing species so that it is more stable, thereby reducing the risk that such species will outgas and cause contamination. One technique for achieving such increased stability is to modify the substrate with oxygen-containing chemical structures (e.g., O 2 , O 3 , H 2 O, SO 2 , CO 2 , CO, COS, NO x (For example, NO 2 , NO, and N 2 O, etc.), and H 2 O 2 Another technique for achieving increased stability is to expose the substrate to a fluorine-containing chemical structure (e.g., HF, C vapor) to form a metal oxide from the metal halide. x F y H z , N.F. 3 ,SCIENCE FICTION 6 , and F 2(one or more of the following): to form metal fluorides from other metal halides, such as metal bromides or metal chlorides. Other chemical structures that may be used to promote the stability of metal-containing species include, but are not limited to, NH 3 (particularly useful at high temperatures, such as above about 200° C.), HI, and I 2 Examples include:

[0118] In certain implementations where block 116 involves chemical processing, process gases may flow at a rate of about 200-10,000 sccm. Exemplary exposure times are about 1-10 minutes. Exemplary temperatures (e.g., of one or more of the substrate support, chamber, showerhead, process gases, etc.) may be about 20-150° C.

[0119] In various embodiments, the treatment of block 116 involves exposing the substrate to a plasma. Plasma treatment can act to suppress outgassing and related contamination mechanisms. In many cases, the plasma is a remotely generated plasma that is delivered to the processing chamber. In other cases, a direct current plasma can be generated in situ with the substrate. The plasma is generated from a plasma generating gas, such as H 2 , N 2 , Ar, He, Kr, Xe, CH 4 , oxygen-based gas (e.g., O 2 , O 3 , CO, CO 2 , COS, SO 2 , NO x , H 2 O), fluorine gases (e.g., NF 3 , C x F y (For example, CF 4 etc.), C x H y F z (For example, 3 F 3 , C.H. 2 F 2 , CHF 3 etc.), F 2 ,SCIENCE FICTION 6 ), chlorine gases (e.g., BCl3 , Cl 2 , HCl, SiCl 4 , SOCl 2 , and PCl 3 A variety of plasma generating gases may be used, including one or more of hydrogen halides (e.g., HBr, HI, etc.). In some specific embodiments, the plasma generating gas is H 2 / N 2 A mixture of H 2 / Ar mixture, H 2 / He mixture, H 2 / Kr mixture, H 2 / Xe mixture, H 2 / CH 4 A mixture of CH 4 / O 2 The plasma generating gas may include a mixture of one or more oxygen-based gases and an inert gas, a mixture of one or more fluorine-based gases and an inert gas, or a mixture of one or more chlorine-based gases and an inert gas. Exemplary flow rates for the plasma generating gas may be about 50-10,000 sccm. In some cases, the flow rate is at least about 100 sccm. In these or other cases, the flow rate may be about 5,000 sccm or less. In some cases where an oxygen-containing plasma is used, the duration of the plasma exposure may be particularly short (e.g., about 1-30 seconds, or about 1-5 seconds), sometimes referred to as a flash, to prevent the oxygen-containing plasma from attacking any exposed carbon-based material, such as a carbon-containing underlayer.

[0120] During the plasma treatment of block 116, the pressure in the process chamber may be maintained as low as about 5 mTorr and as high as about 10 Torr. In some cases, the pressure is about 5 to 300 mTorr, for example, in embodiments where the process chamber includes or is in fluid communication with a turbo pump. In some cases, the pressure is about 100 mTorr to about 10 Torr, for example, in embodiments where the process chamber is or includes a coarse pump. Higher pressures (e.g., 100 mTorr to 10 Torr) may be beneficial in minimizing damage to the substrate as a result of plasma exposure. In some cases where the plasma treatment is targeted to passivate contaminating species, relatively higher pressures may be used, for example, about 0.1 to 10 Torr, or about 0.1 to 5 Torr. The substrate may be exposed to the plasma for a duration of about 1 to 120 seconds. The plasma may be generated at one or more frequencies, for example, a low frequency of about 13.6 kHz and a high frequency of about 10 MHz. Other frequencies may be used as well, e.g., 400 kHz, 1 MHz, 2 MHz, 27 MHz, 60 MHz, etc. For example, if the plasma is a transformer-coupled or capacitively-coupled plasma generated in situ, the plasma may be generated using an RF power of about 50-300 W. If the plasma is generated remotely, e.g., using a microwave plasma source in a microwave strip chamber, the plasma may be generated at these powers or even higher (e.g., up to about 3000 W, in some cases about 1000-3000 W). The duty cycle of the plasma (e.g., TCP plasma) may be about 10%-100% CW.

[0121] In some cases, for example, where the plasma is generated in situ (e.g., TCP or CCP), the pressure may be about 5-300 mTorr, the temperature of the process chamber, showerhead, substrate support, etc. may be about 20-140° C., and the plasma may be generated with an RF power of about 50-300 W. In some other cases, for example, where the plasma is generated remotely (e.g., in a microwave strip chamber, sometimes referred to as a MWS), the pressure may be as low as about 100 mTorr to as high as about 10 Torr or 1 Torr, the temperature of the process chamber, showerhead, substrate support, etc. may be about 100-300° C., and the plasma may be generated with an RF power of about 500-3000 W.

[0122] In various embodiments in which the plasma is remotely generated, the following conditions may be used: the pressure in the processing chamber is maintained at about 0.1-1 Torr, the process gas is flowed at a rate of about 50-5000 sccm, the substrate is exposed to the remote plasma for a duration of about 3-30 seconds, and the remote plasma is composed of a hydrogen-containing gas (e.g., H 2 , or N 2 , H in combination with one or more of Ar, He, Kr, or Xe 2 ). Example power levels, frequencies, and other plasma generating conditions are discussed further above and below.

[0123] In some cases, plasma treatment may promote the removal of metal or metal halide species. In some such cases, plasma treatment may modify contaminating species to form more volatile species. In other cases, plasma treatment may promote the formation of more stable species from metal or metal halide species. As explained above, the formation of more volatile species may reduce outgassing / contamination by removing contaminating species from the substrate / chamber, while the formation of more stable species may reduce outgassing / contamination by reducing the likelihood that such species can volatilize during downstream processing or queue times.

[0124] In various implementations, the plasma generating gas is at least H 2 (For example, in some cases, H 2 / N 2 , H 2 / Ar, H 2 / He, etc.) 2 The addition of a plasma treatment allows for a reduction in the amount of chemisorbed metal halides (e.g., in some cases, tin bromide) on the substrate backside and beveled edge regions. This allows for an increased maximum queue time after processing before the substrate is used for further processing. The maximum queue time is based on the rate at which the contaminating species are outgassing and the maximum allowable concentration of the contaminant. In some cases, H 2 / N 2 or H 2 Exposure of the substrate to a plasma generated from an inert gas, in conjunction with the wet cleaning operation described below in connection with block 118, produces a plasma density of approximately 1E10 atoms / cm 2 Such results are highly desirable. Moreover, such processes have been shown to achieve these results without causing undesirable damage to photoresist patterns and other materials on the front side of the substrate.

[0125] In some implementations, the plasma generating gas includes at least one oxygen-containing species, such as those described above. The oxygen-containing species may react with a metal or metal halide to form a metal oxide. In some implementations, the plasma generating gas includes at least one fluorine-containing species, such as those listed above. The fluorine-containing species may react with a metal or metal halide (e.g., in some cases, a metal bromide) to form a metal fluoride. Metal oxides and metal fluorides may be more stable than pre-existing contaminant species, thereby reducing the risk of outgassing and associated contamination.

[0126] In various embodiments, the processing in block 116 involves exposing the substrate to light. The duration of the light exposure can be about 1-120 seconds. In some cases, the light is provided as part of a rapid thermal anneal that involves exposing the substrate to a relatively high temperature (e.g., about 250-400° C.) for a relatively short period of time (e.g., about 60 seconds or less). In certain cases, a similar rapid thermal anneal process can be provided without substantial light exposure. The light can be provided by a lamp, or a collection of LEDs, any of which can provide light at UV, visible, and / or IR wavelengths. In some specific cases, a lamp that provides UV light is used. In these or other cases, LEDs that provide visible light are used. The LEDs can be provided within the substrate support or other structure. In some cases, the light exposure can occur using a module dedicated to such exposure. In other cases, the light exposure can occur within a processing chamber that is also used for other purposes, such as one or more of the operations in FIG. 1. In various embodiments, the light exposure of block 116 may be performed using a LUMIER™ module available from Lam Research of Fremont, Calif. In some cases, the PDB processing in block 114 may occur using such a module as well. Other devices may also be used.

[0127] Returning to the embodiment of Figure 1, the method continues with block 118 where wet cleaning is performed to remove contamination from the backside and bevel edge regions of the substrate. In general, the details provided above in connection with the wet cleaning in block 104 may also apply to the wet cleaning in block 118. While the wet cleaning in block 104 targets contamination generated during the deposition of photoresist in block 102, the wet cleaning in block 118 targets contamination generated during the deposition of photoresist in block 102. Block 112 It targets contamination that occurs during photoresist development.

[0128] In some embodiments, the wet cleaning in block 118 involves cleaning the relevant portion of the substrate with dilute HF, dilute HCl, or standard clean 1 (SC-1, NH 4 OH:H 2 O 2 :H 2 In many cases, a two-step wet cleaning process is used, where the first step involves exposing the substrate to dilute HF and the second step involves exposing the substrate to standard clean 1 or dilute HCl. The dilute HF can be up to about 49% (by weight) HF, which corresponds to commercially available HF solutions. This solution can be diluted, for example, with water up to about 1:1000 (by volume). The dilute HCl can be up to about 4% (by weight) HCl, which can be diluted up to about 1:100 (by volume) with water, and in some cases up to about 1:10 (by volume) with water. Each wet cleaning step can have a duration of about 20-300 seconds. The substrate, and / or the solution used to treat the substrate can be maintained at a temperature of about 15-60° C. An exemplary flow rate for this solution can be about 1-3 L / min.

[0129] Experimental results shown in the accompanying figures demonstrate that the wet cleaning process is highly effective in reducing the concentration of metals / metal halides on the backside of the substrate, thereby preventing such metals from outgassing and causing contamination problems. The wet cleaning process is particularly effective when combined with one or more of the optimizations described in connection with photoresist development in block 112, one or more of the baking strategies described in connection with PDB processing in block 114, and / or one or more of the processing strategies described in connection with block 116.

[0130] Another technique that may be used to minimize metal outgassing and contamination involves periodically cleaning the processing chambers used to process substrates. As described above, the various operations described in FIG. 1 may be performed in one or more apparatuses, each of which includes a processing chamber. Any or all of these processing chambers must be periodically cleaned to remove metal-containing contaminants from the interior surfaces of the processing chamber. Such chamber cleaning helps reduce redeposition of contaminating species onto subsequently processed substrates. In some cases, chamber cleaning may be as frequent as once per substrate. For example, the chamber may be cleaned after each substrate is processed. In other cases, the frequency may be less, for example, every two substrates, every five substrates, or every ten substrates. Different processing chambers may benefit from different frequencies of cleaning depending on the process occurring in the associated chamber. Methods for dry chamber cleaning are further discussed in PCT Application No. PCT / US2020 / 070187, filed June 25, 2020, which is incorporated herein by reference in its entirety.

[0131] In various embodiments, cleaning the associated processing chamber involves exposing the chamber to a gas chemistry and / or plasma that provides H radicals. The H radicals react with a metal to form, for example, a metal hydride. In a particular example, the metal is tin and exposure of the chamber to a plasma converts Sn x H yThe chamber cleaning typically occurs without a substrate present in the chamber to avoid damaging the substrate and the materials thereon. In some cases, the cleaning occurs automatically and may be referred to as a waferless automatic cleaning process (WAC). The chamber pressure during the chamber cleaning may be about 0.1-10 Torr, e.g., about 0.3-9 Torr. The pressure may be varied between multiple pressures while the process gas is provided. In some cases, the pressure is varied between a lower pressure (e.g., about 1 Torr or less, in some cases about 0.5 Torr) and a higher pressure (e.g., about 5 Torr or more, in some cases about 9 Torr). The pressure may be varied as part of a pump and purge sequence. Exemplary process gases include, but are not limited to, H 2 , other hydrogen-containing species that generate H radicals, N 2 , O 2 , N 2 +O 2 , Ar, and other inert gases. In some cases, the chamber is cleaned without exposure to a plasma. In other cases where a plasma is used, the plasma can be generated remotely and delivered to the chamber being cleaned, or it can be generated in situ directly within the chamber being cleaned. In some embodiments, the plasma is CH 4 and O 2 or NH 3 and O 2 The plasma is generated from a mixture of approximately 13.56 kHz Low frequencies and / or approx. MHzThe plasma may be generated at one or more frequencies, such as a high frequency. Other frequencies may be used as well, such as, for example, 400 kHz, 1 MHz, 2 MHz, 27 MHz, 60 MHz, etc. The plasma may be generated using RF power of about 300-4000 W. The plasma may have a duty cycle of about 10%-CW. The processing chamber, substrate support, showerhead, etc. may be maintained at a temperature of about 25-220° C. during cleaning. In some embodiments, one or more specific heat sources may be used to heat one or more of the processing chamber, substrate support, showerhead, etc. while the chamber is being cleaned. For example, in some cases, an IR heat source may be used. In these or other embodiments, an LED chuck / substrate support may be used. Other heat sources may be used where appropriate.

[0132] In some cases, for example, when the plasma is generated in situ (e.g., TCP or CCP), the pressure may be about 5-300 mTorr, the temperature of the process chamber, showerhead, substrate support, etc. may be about 20-140° C., and the plasma may be generated with an RF power of about 50-300 W. In some other cases, for example, when the plasma is generated remotely (e.g., in a MWS or other remote plasma chamber), the pressure may be about 100 mTorr to about 10 Torr, the temperature of the process chamber, showerhead, substrate support, etc. may be about 100-300° C., and the plasma may be generated with a power of about 1000-4000 W, e.g., about 1000-3000 W.

[0133] In some other embodiments, a dry cleaning process, such as that described above in connection with block 104, may be used instead of or in addition to the wet cleaning process in block 118.

[0134] In many cases, substrates processed using the techniques described herein have a deposition rate of about 1E11 atoms / cm on the backside and / or beveled edge regions of the substrate. 2 For example, about 1E10 atoms / cm 2The following metal concentrations are provided: In various embodiments, the techniques described herein can be used to reduce the concentration of metal on the backside and / or beveled edge regions of the substrate to levels one, two, or even three orders of magnitude lower than would otherwise be achieved without such techniques (e.g., the development operation at block 112 is a conventional dry development and the operations at blocks 114, 116, and 118 are omitted). In some cases, the operations described in blocks 114, 116, and 118 operate to reduce the concentration of metal on the backside and / or beveled edge regions of the substrate as compared to the concentration present after the development step at block 112.

[0135] In some cases, existing equipment may be modified to perform one or more of the processes described herein. For example, an equipment used to develop photoresist (e.g., using dry or wet techniques) may be modified to include any one or more of the following features: (1) a substrate support configured to reach the elevated temperatures described herein, (2) plumbing to provide suitable gases for processing the substrate by chemical or plasma processing, (3) a plasma generator configured to provide plasma to the processing chamber, (4) one or more light sources configured to provide UV, visible, and / or IR radiation onto the substrate, and / or (5) a controller configured to trigger any of the methods described herein. Similarly, an equipment used to bake a substrate may be modified to include any one or more of these features.

[0136] Referring to FIG. 1, in some embodiments, the photoresist is developed in a first processing chamber at block 112, the PDB processing is performed in a second processing chamber at block 114, the chemical, plasma, and / or light processing in block 116 is performed in a third processing chamber, and the wet cleaning is performed in a fourth processing chamber. In other embodiments, some of these steps are combined in a single processing chamber. For example, developing the photoresist in block 112 and performing PDB in block 114 may occur in a first processing chamber, the processing in block 116 may occur in a second chamber, and the wet cleaning may occur in a third chamber. In another embodiment, developing the photoresist in block 112, performing PDB in block 114, and performing processing in block 116 all occur in a first chamber, and the wet cleaning in block 118 occurs in a second chamber. The chamber used to perform PDB in block 114 may be the same or different from the chamber used to perform PAB in block 106 and / or PEB in block 110. In various embodiments, any two or more of the chambers described herein may be combined in a multi-chamber apparatus / tool ​​that serves multiple purposes. Appropriate substrate handling equipment, load locks, etc. may be provided to transfer substrates between chambers as needed. Additionally, a controller may be provided to control process operations as described herein. In certain embodiments, the multi-chamber apparatus includes at least one chamber configured for dry processing (e.g., to perform one or more of the operations in blocks 112, 114, and 116, e.g., vapor-based / plasma-based processing) and at least one chamber configured for wet processing (e.g., to perform the cleaning operation in block 118).

[0137] 2A-2D show cross-sectional schematic views of various processing stages for backside and bevel edge cleaning using wet cleaning techniques, which may be used, for example, in conjunction with the wet cleaning techniques described in connection with blocks 104 and 118.

[0138] As shown in FIG. 2A, EUV resist material may be deposited on the front side, back side, and beveled edge of the substrate. As described above, such deposition may occur through wet spin-on techniques or dry vapor / plasma-based techniques. The EUV resist material and associated metal and metal halide contamination deposited on the back side and beveled edge increases the likelihood of contamination on the front side of the substrate and contamination of downstream tools. Such EUV resist material and metal-containing contamination are undesirable. It is desirable to remove the EUV resist material and metal-containing contamination from the back side and beveled edge of the substrate. In some cases, it is desirable to remove any EUV resist material or other metal-containing contamination deposited on the front side of the substrate, including EUV resist material deposited on the periphery of the front side of the substrate.

[0139] As shown in FIG. 2B, the unwanted material deposited on the beveled edge of the substrate is removed by wet bevel cleaning. In a standard edge bead removal process, an organic solvent such as PGME, PGMEA, or 2-heptanone is dispensed to remove the EUV resist material deposited on the beveled edge in a first processing chamber (Chamber 1). The first processing chamber may be a spin clean tool. The organic solvent may be dispensed at a low / mild temperature such as about 20° C. Any heating of the flammable solvent poses a significant fire / explosion hazard. The substrate optionally undergoes a rinse / dry operation before proceeding to a second processing chamber (Chamber 2).

[0140] As shown in FIG. 2C, the undesired material deposited on the backside of the substrate is removed by wet backside cleaning. The wet backside cleaning may be performed in a second processing chamber. The second processing chamber may be another spin cleaning tool capable of cleaning the backside of the substrate. For example, the wet backside cleaning may use a cleaning agent such as dHF, dHCl, dilute sulfuric acid, or SC-1. The cleaning agent may be dispensed at a low / mild temperature such as about 20° C. Although the wet backside cleaning may also remove material on the beveled edge region, it is typically inefficient in uniformly or completely removing material on the beveled edge region. Therefore, the backside cleaning and beveled edge cleaning are sometimes split between the first processing chamber and the second processing chamber. The substrate undergoes a rinse / dry operation before proceeding to the third processing chamber (chamber 3).

[0141] As shown in FIG. 2D, the substrate is transferred to a third processing chamber to undergo an optional PAB thermal treatment. In some embodiments, the third processing chamber is an oven or includes a hot plate, which exposes the substrate to an elevated temperature. The PAB thermal treatment increases the substrate temperature to an elevated temperature, such as about 90° C. to 200° C., which stabilizes the lithographic properties of the EUV resist on the front side of the substrate for EUV exposure. The PAB thermal treatment is a dry process.

[0142] In contrast to wet backside and beveled edge cleaning techniques, dry backside and beveled edge cleaning techniques may be less expensive and more environmentally safe. Dry backside and beveled edge cleaning techniques may consolidate chambers so that dry processing steps may be performed in fewer tools / chambers. Dry backside and beveled edge cleaning techniques may address non-uniformity issues associated with wet backside and beveled edge cleaning techniques.

[0143] In some cases, dry backside and bevel cleaning techniques use plasma to remove material from the backside and bevel edges of a substrate. Existing hardware may confine the plasma to the backside and bevel edges of the substrate to remove material. In some other cases, dry backside and bevel cleaning may be accomplished without striking a plasma. For example, dry backside and bevel cleaning utilizes an etching gas that is confined to specific areas of the substrate to remove material (e.g., EUV resist material) from the backside and bevel edges of the substrate. Dry backside and bevel cleaning exposes the substrate to elevated temperatures to facilitate non-selective removal of material at the backside and bevel edges.

[0144] 3A-3C show cross-sectional schematic views of various processing stages of dry backside and bevel edge cleaning of photoresist material, according to some embodiments. Deposition of the photoresist material (e.g., EUV resist material) can be performed using wet or dry deposition techniques. Wet deposition techniques include spin coating. Dry deposition techniques include chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0145] As shown in FIG. 3A, EUV resist material and associated metal and metal halide contamination may be deposited on the front side, back side, and beveled edge of the substrate. Unwanted material deposited on the back side and beveled edge increases the possibility of contamination on the front side of the substrate and contamination of downstream tools. It is desirable to remove unwanted material from the back side and beveled edge of the substrate. In some cases, it is desirable to remove any unwanted material deposited on the front side of the substrate, including EUV resist material and associated metal and metal halide contamination deposited on the periphery of the front side of the substrate. For example, it may be desirable to remove unwanted material on the front side about a few millimeters (e.g., about 1.5 mm) from the edge. In some embodiments, the EUV resist material is an organometallic-containing resist material or an organometallic oxide. The EUV resist material may include an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. Unwanted metal or metal halide contamination may result from reaction of metals in the EUV resist material with halogen-based chemical structures. The metal in the EUV resist material may have a high patterned radiation absorption cross section. In some embodiments, the element may have a high EUV absorption cross section. In some embodiments, the EUV resist material may generally consist of Sn, O, and C. For example, the EUV resist material may include an organotin oxide.

[0146] As shown in FIG. 3B, the EUV resist material deposited on the backside and beveled edge of the substrate is removed by dry cleaning. The dry cleaning may expose the backside and beveled edge of the substrate to an etching gas. In some embodiments, the etching gas may be a hydrogen halide, hydrogen gas, hydrogen gas and a halide gas, or boron trichloride (BCl 3 In one example, the etching gas is a hydrogen halide, such as HCl, HBr, or HI. In another example, the etching gas is hydrogen gas (H 2 In yet another example, the etching gas is H 2 and Cl 2 , Br 2, or I 2 In yet another example, the etching gas is a mixture of BCl 3 Although the present disclosure is not limited to any particular theory or mechanism of operation, in some cases the present techniques involve the use of steam to react with EUV photoresist materials and associated contaminants and cleaning chemistries (e.g., HCl, HBr, HI, H) to form volatile products. 2 and Cl 2 , Br 2 , or I 2 , BCl 3 It is understood that the EUV photoresist material and associated contamination can be treated and / or removed using vapor and / or plasma at various temperatures. It is believed that higher temperatures, pressures, and / or reactant flows can further accelerate or enhance the reactivity. In some embodiments, the EUV resist material and / or associated contamination can be removed at an etch rate of up to 1 nm / sec. In some embodiments, the etching gas is activated by a remote plasma source. This can further accelerate or enhance the reactivity. In some embodiments, the etching gas is delivered with a carrier gas such as argon, helium, nitrogen, or other suitable carrier gas.

[0147] In some embodiments, the photoresist material is not an EUV resist material, but is a silicon-based material or a carbon-based material. The etching gas for removal of such materials may be different than that for removal of the EUV resist material. In some embodiments, the etching gas may be O for removal of the carbon-based material. 2 , CO 2 , N 2 In some embodiments, the etching gas includes an oxidizing gas such as C, O, and the like for removal of silicon-based materials. x F y Or C x F y H z These include fluorine-based gases such as fluorine gas, and chlorine-based gases.

[0148] An inert curtain gas may be delivered to the front side of the substrate to confine the etching gas to the backside and bevel edge of the substrate. The curtain gas may be nitrogen (N 2 ), oxygen (O 2 ), water (H 2 The curtain gas may include a gas such as fluorine (O), argon (Ar), helium (He), xenon (Xe), neon (Ne), or a mixture thereof. The curtain gas is flowed over the front side of the substrate to protect at least a central region of the front side of the substrate from the etching gas. As the curtain gas is flowed over the front side, the curtain gas spreads across the front side to protect the EUV resist material deposited on the front side.

[0149] The curtain gas may be flowed simultaneously with the etching gas. The first etching gas flow may be introduced to the backside of the substrate. The first etching gas flow may extend across the backside of the substrate, which may be accessible when the substrate is supported by the MCA support on the carrier ring. In some embodiments, the second etching gas flow may be introduced to the periphery of the frontside of the substrate. The second etching gas flow may flow along the periphery of the frontside and wrap around the beveled edge of the substrate. The first etching gas flow may be introduced from one or more bottom gas inlets positioned below the substrate support, and the second etching gas flow may be introduced from one or more peripheral gas inlets of a gas distributor positioned above the substrate support. The gas distributor may include a modular ring having one or more peripheral gas inlets. The modular ring may adjust the space between the one or more peripheral gas inlets and the frontside of the substrate. In some embodiments, the curtain gas is flowed from one or more central gas inlets of the gas distributor, and a first gap separating the one or more peripheral gas inlets from the front side is larger than a second gap separating the one or more central gas inlets from the front side.

[0150] The substrate may be heated to an elevated temperature during the dry cleaning, the elevated temperature being about 20°C to about 170°C, about 20°C to about 140°C, about 40°C to about 140°C, or about 100°C. In some embodiments, the dry cleaning may be performed at an elevated pressure. The pressure in the process chamber may be about 0.02 Torr to atmospheric pressure, 0.1 Torr to atmospheric pressure, or about 1 Torr to atmospheric pressure. In some embodiments, the dry cleaning may be performed using a high flow rate of etching gas. The etching gas flow rate may be about 50 sccm to about 10,000 sccm, about 100 sccm to about 10,000 sccm, or about 200 sccm to about 5,000 sccm. Unlike wet cleaning techniques, the non-plasma thermal cleaning techniques of the present disclosure can adjust process parameters such as temperature, pressure, and gas flow rates to control the etch rate. High etch rates may be achieved to remove unexposed EUV resist material using higher temperatures and / or pressures as well as flow rates.

[0151] Both the backside cleaning and the beveled edge cleaning are performed in the first processing chamber (Chamber 1) rather than in separate processing chambers. This reduces the possibility of tool contamination that may otherwise occur between cleaning operations. A single pass can be performed for essentially multiple process steps in a single tool. This also reduces costs and increases throughput. No wet cleaning or rinsing / drying operations are performed in the dry backside and beveled edge cleaning of the present disclosure.

[0152] In some embodiments, the dry backside and bevel edge cleaning includes exposure to an etching gas followed by purging. The purging introduces a purge gas to pump / purge residual etching gas from the first processing chamber. It should be understood that the purging can be useful to remove residual etching gas or etching by-products from the processing chamber to avoid undesired etching of the front side of the substrate during substrate transfer. The purging can flow an inert gas and / or a reactive gas. The reactive gas can react with the residual etching gas to facilitate ease of removal. The reactive gas can be, for example, a tin-based precursor, such as an organotin precursor. The inert gas can be Ar, He, Ne, Xe, or N. 2 The chamber pressure may be about 0.1 Torr to about 6 Torr. The purge gas flow may be about 10 sccm to about 10,000 sccm, or about 50 sccm to about 5,000 sccm. In some embodiments, the pumping / purging may proceed at a high temperature, such as about 20° C. to about 140° C. or about 80° C. to about 120° C. The high temperature may facilitate removal of residual etching gas from the first processing chamber. In some embodiments, the chamber walls and other components may be heated to release the residual etching gas. The residual etching gas (e.g., halide gas or halide-containing gas) may be exhausted through an exhaust line during the pumping / purging. In some embodiments, the pumping / purging operation may also be referred to as dehalogenation. The halogen compounds may easily stick to the chamber walls, chamber components, or the wafer. If the halogen compounds stick to the wafer, the risk of the halogen compounds (e.g., bromine) being released from the wafer during the EUV scan is increased, thereby corroding or damaging the scanner.

[0153] In some embodiments, the duration of the dry backside and bevel cleaning is from about 10 seconds to about 150 seconds. In some embodiments, the end point of the backside and bevel cleaning is detected by one or more sensors. The one or more sensors detect the amount of EUV resist deposited on the backside and bevel of the substrate. Presence or AbsenceThe one or more sensors may include an IR sensor and / or an optical sensor.

[0154] As shown in FIG. 3C, the substrate is exposed to an optional PAB heat treatment. In some embodiments, the PAB heat treatment is performed in the same processing chamber (i.e., the first processing chamber) as the dry backside and beveled edge cleaning. In such a manner, the dry backside and beveled edge cleaning are integrated with the PAB heat treatment. This may further reduce the possibility of contamination, reduce costs, and increase throughput. This may have a minimal or positive impact on lithography performance. In some embodiments, the PAB heat treatment is performed in a second processing chamber (chamber 2) different from the dry backside and beveled edge cleaning. The PAB treatment is a dry process.

[0155] The PAB heat treatment increases the substrate temperature to an elevated temperature, such as from about 100° C. to about 170° C. or from about 120° C. to about 150° C. In some embodiments, the substrate temperature can be controlled using a radiative heat source, such as an IR lamp or one or more LEDs. The radiative heat source can be positioned below the substrate. Alternatively, the radiative heat source can be positioned above the substrate. The substrate temperature can be actively controlled by a pyrometer in a feedback control loop established with the radiative heat source. The atmosphere during the PAB heat treatment is N 2 The inert gas may be controlled by flowing an inert gas such as O, Ar, He, Xe, or Ne. 2 and / or H 2 The inert gas may be mixed with O. The flow rate of the inert gas may be about 10 sccm to about 10,000 sccm, or about 50 sccm to about 5,000 sccm. The pressure during the PAB heat treatment may be controlled to be about 0.02 Torr to atmospheric pressure, about 0.1 Torr to atmospheric pressure, or about 1 Torr to atmospheric pressure.

[0156] Device The present disclosure provides various hardware implementations to achieve the methods described herein. In many cases, two or more of the operations described in FIG. 1 can occur in the same processing chamber. In various embodiments, at least two processing chambers are provided, one configured to perform a dry process and one configured to perform a wet process. Such chambers can be combined on a single tool as described herein.

[0157] FIG. 4 shows a schematic diagram of a processing chamber for performing dry backside and beveled edge cleaning, according to some embodiments. An apparatus or tool for performing dry backside and beveled edge cleaning may include a processing chamber. The processing chamber may be integrated to perform both backside and beveled edge cleaning, as well as one or more additional dry processing techniques, such as PAB processing deposition, PEB processing, EUV exposure, PDB processing, chemical / plasma / light processing, dry development, etc. The apparatus may include a substrate support in the processing chamber to support the substrate. In some embodiments, the substrate support may receive the substrate after deposition of material (e.g., EUV resist material) on the front side, back side, and beveled edge of the substrate. A plurality of minimum contact areas (MCAs) may be configured to extend from a major surface of the substrate support to lift the substrate so that etching gas can access the back side of the substrate. The apparatus further includes a gas distributor on the substrate support, which is coupled to the processing chamber to deliver a curtain gas to the front side of the substrate. The apparatus further includes an etching gas delivery source below the substrate support that is coupled to the processing chamber for delivering an etching gas to the backside of the substrate. The apparatus may further include a heat source, such as a radiative heat source, below the substrate support.

[0158] The substrate support may include a carrier ring. The carrier ring may have an annular body for supporting the substrate. FIG. 5A shows a perspective view of a carrier ring for supporting a substrate in a processing chamber according to some embodiments. Substrates in the semiconductor industry typically have a diameter of 200 mm, 300 mm, or 450 mm. The outer diameter of the carrier ring is larger than the diameter of the substrate, and the inner diameter of the annular body is smaller than the diameter of the substrate. The inner diameter may be about 280 mm or less, about 240 mm or less, or about 200 mm or less. In other words, the substrate may be gripped by a ring having a radius of about 140 mm or less. The multiple MCA supports may extend from a major surface of the carrier ring to contact the backside of the substrate. In some embodiments, the multiple MCA supports may be symmetrically arranged around a center of the carrier ring. For example, the multiple MCA supports may include three MCA supports, four MCA supports, five MCA supports, six MCA supports, or more. The MCA supports may be pins. The MCA supports may include any suitable insulating material. The insulating material may be a soft material such as perfluoroalkoxyalkane (PFA) to avoid scratching the substrate. Figure 5B shows a cross-sectional schematic of a carrier ring supporting and contacting the backside of the substrate according to some embodiments.

[0159] The position of the MCA support may be optimized with respect to a preceding deposition process to avoid contacting the substrate when the substrate has backside deposition. In other words, the MCA supports may be configured to contact regions of the backside of the substrate when there is little backside deposition (e.g., photoresist deposition). Such an arrangement may be determined based on knowledge or data ascertained from one or more previous deposition operations that indicate little backside deposition. For example, the MCA support may contact the backside of the substrate in an area closer to the center of the substrate than to the edge of the substrate. At the same time, the position of the MCA support does not prevent the etching gas from accessing the regions with backside deposition.

[0160] The multiple MCA supports provide minimal contact with the backside of the substrate. The multiple MCA supports can lift the substrate above the major surface of the carrier ring to a height that allows gas to flow to the backside of the substrate. In some embodiments, this height is about 0.025 mm to about 0.5 mm or about 0.05 mm to about 0.25 mm. In some embodiments, the MCA supports can be extended / retracted from the major surface of the substrate support. In some embodiments, this height is adjustable so that the gap size is controlled. In some embodiments, the backside of the substrate is supported by the MCA supports with a shifting or rotating mechanism so that the area directly touched by the MCA supports and the substrate can be cleaned. Etching gases can be blocked by accessing the area in direct contact with the MCA supports. Although this area is very small relative to the substrate, it can still have unacceptably high metal contamination. Therefore, this area needs to be cleaned as well. In other words, the MCA supports can shift or rotate their position to contact different points on the backside of the substrate. The shift mechanism can be incorporated into the lift pins used during substrate transfer. After the first part of the cleaning, which cleans the entire substrate except the area touched by the MCA support, the carrier ring can lower the substrate onto the lift pins. The lift pins move the substrate by approximately tens of um by a multiple of the MCA area. The carrier ring then moves back to the process position and a second cleaning is performed to clean the area first touched by the MCA support. In some embodiments, the backside of the substrate is supported by an area of ​​MCA support, and the carrier ring is split into two or more areas of X MCA supports each, where X is any integer value. In this case, the cleaning process can be divided into several steps. During each step, one or more of the parts of the split ring are moved away from the substrate surface to allow cleaning in that area. All areas must be lifted / cleaned at least once during cleaning. A minimum number of areas must remain in place to ensure that the substrate is held in the process position. For example, the carrier ring can be divided into two areas of three pins each.The carrier ring and the multiple MCA supports can be configured in a manner to regulate the etching gas flow at the backside of the substrate. Specifically, the height of the MCA supports, the inner diameter of the carrier ring, the positioning of the MCA supports, and other aspects of the carrier ring can be designed to regulate the gas flow between the curtain gas from above and the etching gas from below to ensure that both the backside and the beveled edge are etched, but that certain areas of the frontside of the substrate are not etched.

[0161] Returning to FIG. 4, the etching gas delivery source and the radiant heat source may be positioned below the substrate support (e.g., carrier ring). The etching gas delivery source may include one or more bottom gas inlets or nozzles for delivering the etching gas to the backside of the substrate. The radiant heat source may be spaced from the backside of the substrate, but may heat the substrate to an elevated temperature by radiant heating. The radiant heat source may provide controlled ramping capabilities, pulsing, and rapid temperature changes. In some embodiments, the radiant heat source includes one or more IR lamps or one or more LEDs. To enable rapid temperature changes, the heat source may be in the 1-10 kW range. In some embodiments, the substrate support may be configured to rotate. For controllability of the substrate temperature, the one or more IR lamps or one or more LEDs may be divided into zones for controlled heating of various regions of the substrate. Additionally, the one or more lamps or one or more LEDs may each be independently controllable. By pulsing the LEDs, the temperature ramp-up of the wafer may be controlled. The radiant heat source may also serve to prevent stray light from reaching the front side of the substrate. In some embodiments, the etching gas delivery source includes one or more holes through the radiant heat source. In some embodiments, the etching gas delivery source includes one or more holes positioned outside the radiant heat source. The positioning of the hole or holes may not be important since non-uniformity of the etching gas flow at the backside of the substrate is not important to the removal of material at the backside of the substrate. Thus, the etching gas delivery source may be positioned in any manner such that the etching gas can reach or otherwise access the backside of the substrate.

[0162] The gas distributor is positioned above the substrate support to deliver curtain gas to the front side of the substrate. The gas distributor may include one or more central gas inlets to direct the curtain gas flow to the center of the front side of the substrate. In some embodiments, the gas distributor may include one or more peripheral gas inlets to direct the etching gas flow to the periphery of the front side of the substrate. It should be understood that the periphery of the front side of the substrate may occupy an area of ​​15% or less, 10% or less, or 5% or less of the front side of the substrate. In some embodiments, the gas distributor includes a top plate that includes a plurality of holes disposed in a central region of the top plate and a plurality of holes disposed in a peripheral region of the top plate. In some embodiments, the gas distributor includes modular rings of different diameters. In some cases, the modular rings may have different shapes. The etching gas may be delivered through one of the modular rings and the curtain gas may be delivered through another of the modular rings. Thus, the gas distributor includes at least a modular ring for one or more peripheral gas inlets, and at least one modular ring is configured to adjust the spacing of the one or more peripheral gas inlets from the front side of the substrate. Removal at the beveled edge can be adjusted by adjusting the spacing of the one or more peripheral gas inlets in the modular ring. Additionally or alternatively, the gas distributor includes one or more nozzles for directing the etching gas flow toward the beveled edge of the substrate.

[0163] The gas distributor may be configured such that a first gap separating one or more peripheral gas inlets from the front side of the substrate is larger than a second gap separating one or more central gas inlets from the front side of the substrate. In some embodiments, the first gap is at least twice as large as the second gap. The second gap may be as small as possible without touching the EUV resist film on the front side of the substrate. As shown in FIG. 4, the gas distributor may have a stepped design. In such a manner, the curtain gas flow may be provided at a higher pressure and delivered across a smaller gap at the center of the substrate, and the etching gas flow may be provided at a lower pressure and delivered across a larger gap at the periphery of the substrate. The etching gas flow delivered from above the substrate support may be referred to as a "second etching gas flow," while the etching gas flow delivered from below the substrate support may be referred to as a "first etching gas flow." The second etching gas flow delivered at the periphery of the substrate may engulf a portion of the front side and beveled edge region of the substrate. For example, the etching gas flow may engulf 5 mm or less, 3 mm or less, or 1.5 mm or less of the front side of the substrate. The curtain gas flow prevents the etching gas from reaching the remainder of the front side of the substrate.

[0164] In addition to or in lieu of a radiative heat source, the apparatus may further include one or more heaters. The one or more heaters may provide substrate temperature control. In some embodiments, the one or more heaters are coupled to the gas distributor and above the substrate. The one or more heaters may be radiative heat sources. In some embodiments, the one or more heaters are configured to provide ambient heating within the processing chamber. In some embodiments, the one or more heaters provide substrate temperature control within a range of 20° C. to 170° C. or 20° C. to 140° C., or other temperature ranges described herein.

[0165] The apparatus may further include one or more sensors for detecting the presence of film deposition on the backside and / or beveled edge of the substrate. In some embodiments, the one or more sensors include an optical device, such as an IR sensor, that serves as an end point detector.

[0166] FIG. 6 depicts a schematic diagram of an embodiment of a process station 600 having a processing chamber body 602 for maintaining a low pressure environment suitable for the described dry backside and bevel edge cleaning embodiments. Multiple process stations 600 may be included in a typical low pressure process tool environment. For example, FIG. 7 depicts an embodiment of a multi-station processing tool 700, such as a VECTOR® processing tool available from Lam Research Corporation, Fremont, Calif. In some embodiments, one or more hardware parameters of the process station 600, including those discussed in detail below, are controlled by one or more computer controllers. 750 can be programmatically adjusted by

[0167] The process stations may be configured as modules within a cluster tool. Figure 9 depicts a semiconductor process cluster tool architecture having a vacuum integrated deposition and patterning module suitable for implementing the embodiments described herein. Such a cluster process tool architecture may include a resist deposition module, a resist exposure module (EUV scanner), a resist development module, and an etching module, as described above and further described below with reference to Figures 8 and 9. Furthermore, such a cluster tool architecture may include a processing chamber configured for wet processing, e.g., to perform backside and bevel area cleaning using wet techniques.

[0168] Returning to FIG. 6, the process station 600 is in fluid communication with a reactant delivery system 601a for delivering process gases to a distribution showerhead 606. The reactant delivery system 601a optionally includes a mixing vessel 604 for mixing and / or conditioning the process gases for delivery to the showerhead 606. One or more mixing vessel inlet valves 620 may control the introduction of process gases to the mixing vessel 604. If plasma exposure is used, the plasma may also be delivered to the showerhead 606 or generated within the process station 600. As described above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0169] 6 includes an optional evaporation point 603 for evaporating a liquid reactant to be delivered to the mixing vessel 604. In some embodiments, a liquid flow controller (LFC) upstream of the evaporation point 603 may be provided to control the mass flow of liquid for evaporation and delivery to the process station 600. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM.

[0170] 6, the substrate 612 is shown positioned directly below the showerhead 606 and resting on a pedestal 608. The showerhead 606 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gases to the substrate 612.

[0171] In some embodiments, the pedestal 608 can be raised or lowered to expose the substrate 612 to the volume between the substrate 612 and the showerhead 606. In some embodiments, the height of the pedestal can be adjusted using a suitable computer ControlsIt should be understood that the temperature of the showerhead 606 may be programmably adjusted by, for example, 1000 psi ...

[0172] In some embodiments, the pedestal 608 may be temperature controlled by a heater 610. Alternatively, the substrate 612 supported by a carrier ring may be heated by a radiative heat source positioned below the substrate 612. In some embodiments, the substrate 612 may be heated to a temperature greater than 0° C. up to 300° C. or more, e.g., 50-120° C., such as about 65-80° C., during non-plasma thermal exposure of the resist to a dry backside and bevel cleaning chemistry, such as HBr or HCl, as described in the disclosed embodiments. In some embodiments, the heater 610 of the pedestal 608 may include multiple independently controllable temperature control zones.

[0173] Additionally, in some embodiments, pressure control for the process station 600 may be provided by a butterfly valve 618. As shown in the embodiment of Figure 6, the butterfly valve 618 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the process station 600 may also be adjusted by varying the flow rate of one or more gases introduced to the process station 600.

[0174] In some embodiments, a portion of the showerhead 606 can be adjusted relative to the pedestal 608 to change the volume between the substrate 612 and the showerhead 606. Additionally, it should be understood that the vertical position of the pedestal 608 and / or the showerhead 606 can be changed by any suitable mechanism within the scope of this disclosure. In some embodiments, the pedestal 608 can include a rotation axis for rotating the orientation of the substrate 612. In some embodiments, one or more of these example adjustments can be adjusted using one or more suitable computers. Controls It should be understood that the method may be implemented programmatically by

[0175] Where plasma may be used, for example, in gentle plasma-based dry cleaning embodiments and / or etching operations performed in the same chamber, the showerhead 606 and pedestal 608 are in electrical communication with a radio frequency (RF) power source 614 and matching network 616 to power the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 614 and matching network 616 may be operated at any suitable power to form a plasma having a desired composition of radical species. An example of a suitable power is up to about 500 W.

[0176] In some embodiments, Controls Instructions for may be provided by input / output control (IOC) sequencing instructions. In one example, instructions for setting conditions for a process phase may be included in a corresponding recipe phase of a process recipe. In some cases, process recipe phases may be arranged sequentially such that all instructions for a process phase are executed simultaneously with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. For example, a recipe phase may include instructions for setting a flow rate of a dry cleaning chemistry reactant gas, such as HBr or HCl, and a time delay instruction for the recipe phase. In some embodiments, Controls may include any of the features described below with respect to system controller 750 of FIG.

[0177] As described above, one or more process stations may be included in a multi-station processing tool. Figure 7 shows a schematic diagram of an embodiment of a multi-station processing tool 700 having an inbound load lock 702 and an outbound load lock 704, either or both of which may include a remote plasma source. A robot 706 at atmospheric pressure is configured to move a wafer from a cassette loaded through a pod 708 into the inbound load lock 702 through an atmospheric port 710. The wafer is placed by the robot 706 on a pedestal 712 in the inbound load lock 702, the atmospheric port 710 is closed, and the load lock is pumped down. If the inbound load lock 702 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment to treat the silicon nitride surface in the load lock before being introduced into the processing chamber 714. Additionally, the wafer may also be heated in the inbound load lock 702 as well, for example to remove moisture and absorbed gases. A chamber transfer port 716 to the processing chamber 714 is then opened and another robot (not shown) places the wafer into the reactor on the pedestal of the first station shown in the reactor for processing. It should be understood that although the embodiment shown in Figure 7 includes a load lock, in some embodiments direct entry of the wafer into the process station may be effected.

[0178] The depicted processing chamber 714 includes four process stations, numbered 1-4 in the embodiment shown in FIG. 7. Each station has a heated pedestal (shown at 718 for station 1), and a gas line inlet. It should be understood that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between a dry cleaning process mode and a deposition process mode. Additionally or alternatively, in some embodiments, the processing chamber 714 may include one or more matched pairs of dry cleaning and deposition process stations. Although the depicted processing chamber 714 includes four stations, it should be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments, a processing chamber may have three or fewer stations.

[0179] FIG. 7 depicts an embodiment of a wafer handling system 790 for transferring wafers within the processing chamber 714. In some embodiments, the wafer handling system 790 may transfer wafers between various process stations and / or between process stations and load locks. It should be understood that any suitable wafer handling system may be used. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 7 also depicts an embodiment of a system controller 750 used to control the process conditions and hardware states of the process tool 700. The system controller 750 may include one or more memory devices 756, one or more mass storage devices 754, and one or more processors 752. The processor 752 may include a CPU or computer, analog and / or digital input / output connections, stepper motor control boards, etc.

[0180] In some embodiments, the system controller 750 controls all of the activity of the process tool 700. The system controller 750 executes system control software 758 that is stored on mass storage device 754, loaded into memory device 756, and executed on processor 752. Alternatively, control logic may be hard-coded into the controller 750. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), and the like may be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally equivalent hard-coded logic may be used therein. The system control software 758 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate stand, chuck and / or susceptor position, and other parameters of a particular process performed by the process tool 700. The system control software 758 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components used to perform the various process tool processes. The system control software 758 may be coded in any suitable computer readable programming language.

[0181] In some embodiments, the system control software 758 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored on the mass storage device 754 and / or memory device 756 associated with the system controller 750 may be used in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0182] The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal 718 and to control the spacing between the substrate and other parts of the process tool 700 .

[0183] The process gas control program may include code for controlling halide-containing gas components (e.g., HBr or HCl gas as described herein) and flow rates, and, optionally, code for flowing gas into one or more process stations prior to deposition to stabilize the pressure in the process station. The pressure control program may include code for controlling the pressure in the process station, for example, by adjusting a throttle valve in the exhaust system of the process station, gas flow into the process station, etc.

[0184] The heater control program may include code for controlling the current to a heating device used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0185] A plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations according to embodiments herein.

[0186] The pressure control program may include code for maintaining pressure in a reaction chamber according to embodiments herein.

[0187] In some embodiments, there may be a user interface associated with the system controller 750. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0188] In some embodiments, the parameters adjusted by the system controller 750 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to a user in the form of a recipe, which may be entered using a user interface.

[0189] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 750 from various process tool sensors. Signals for controlling the process may be output at analog and digital output connections of the process tool 700. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0190] The system controller 750 may provide program instructions for carrying out the deposition process described above. The program instructions may control various process parameters such as DC power levels, RF bias power levels, pressure, temperature, etc. The instructions may control parameters for operating a development and / or etching process according to various embodiments described herein.

[0191] System controller 750 typically includes one or more memory devices and one or more processors configured to execute instructions such that the apparatus performs methods according to the disclosed embodiments. Machine-readable media containing instructions for controlling process operations according to the disclosed embodiments may be coupled to system controller 750.

[0192] In some embodiments, the system controller 750 is part of a system that may be part of the examples described above. Such systems may include semiconductor processing equipment, including processing tool(s), chamber(s), platform(s) for processing, and / or specific processing components (wafer pedestal, gas flow systems, etc.). These systems may be integrated with electronics for controlling the operation of the system before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as a "controller" that may control various components or sub-parts of the system(s). The system controller 750 may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, tools connected to or interfaced with the particular system, and other transfer tools and / or wafer transfers in and out of load locks, depending on the process conditions and / or type of system.

[0193] Broadly speaking, the system controller 750 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable end point measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute the program instructions (e.g., software). The program instructions may be instructions communicated to the system controller 1450 in the form of various individual settings (or program files) that define the operating parameters for performing a particular process on or for a semiconductor wafer or for a system. The operating parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0194] The system controller 750 may, in some embodiments, be part of or coupled to a computer that is integrated with the system, coupled to the system, separately networked to the system, or a combination thereof. For example, the system controller 750 may be in the "cloud" or in all or part of a fab host computer system, thereby enabling remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, to examine the history of past fabrication operations, to examine trends or performance metrics from multiple fabrication operations, to vary parameters of a current process, to set processing steps to follow a current process, or to initiate a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings that are then communicated from the remote computer to the system. In some examples, the system controller 750 receives instructions in the form of data that specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller 750 is configured to interface with or control. Thus, as described above, the system controller 750 may be distributed, such as by including one or more separate controllers that are networked together and operate toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose is one or more integrated circuits on the chamber in communication with one or more remotely located (e.g., at the platform level or as part of a remote computer) integrated circuits that together control the process on the chamber.

[0195] Without limitation, example systems may include a plasma etch chamber or module, a wet deposition chamber or module, a dry deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a wet cleaning chamber or module, a dry cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a wet photoresist development chamber or module, a dry photoresist development chamber, a chemical, plasma, and / or light based processing chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0196] As described above, depending on the process step(s) to be performed by the tool, the system controller 750 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transfer to bring containers of wafers to or from the tool location and / or load ports within the semiconductor manufacturing factory.

[0197] In a particular embodiment, an inductively coupled plasma (ICP) reactor is now described that may be suitable for etching operations suitable for implementing some embodiments. Although an ICP reactor is described herein, it should be understood that in some embodiments, a capacitively coupled plasma reactor may also be used.

[0198] 8 illustrates generally a cross-sectional view of an inductively coupled plasma apparatus 800 suitable for carrying out certain embodiments or aspects of the disclosed embodiments, such as dry backside and bevel edge cleaning, an example of which is the Kiyo® Reactor produced by Lam Research Corp. of Fremont, Calif. In other embodiments, other tools or tool types having the functionality to perform the dry backside and bevel edge cleaning described herein may be used for implementation.

[0199] The inductively coupled plasma apparatus 800 includes an overall process chamber 802 structurally defined by a chamber wall 801 and a window 811. Chamber8. The chamber walls 801 may be made of stainless steel, aluminum, or plastic. The window 811 may be made of quartz or other dielectric materials. An optional internal plasma grid 850 divides the overall process chamber into an upper sub-chamber 802 and a lower sub-chamber 803. In most embodiments, the plasma grid 850 may be removed, thus utilizing the chamber space created by the sub-chambers 802 and 803. A chuck 817 is positioned within the lower sub-chamber 803 near the bottom inner surface. The chuck 817 is configured to receive and hold a semiconductor wafer 819 on which the etching and deposition processes are performed. The chuck 817 may be an electrostatic chuck for supporting the wafer 819 when present. In some embodiments, an edge ring (not shown) surrounds the chuck 817 and has an upper surface that is approximately planar with an upper surface of the wafer 819 when it is present on the chuck 817. The chuck 817 also includes an electrostatic electrode for chucking and dechucking the wafer 819. A filter and DC clamp power supply (not shown) may be provided for this purpose. Other control systems for lifting the wafer 819 from the chuck 817 may also be provided. The chuck 817 may be charged using an RF power supply 823. The RF power supply 823 is connected to a matching circuit 821 through connection 827. The matching circuit 821 is connected to the chuck 817 through connection 825. In this manner, the RF power supply 823 is connected to the chuck 817. In various embodiments, the bias power of the electrostatic chuck may be set to about 50V or may be set to a different bias power depending on the process being performed according to the disclosed embodiments. For example, the bias power may be set to about 50V. 20V up to about 100V, or from about 30V to about 150V.

[0200] The elements for plasma generation include a coil 833 positioned over the window 811. In some embodiments, a coil is not used in the disclosed embodiments. The coil 833 is fabricated from a conductive material and includes at least one complete turn. The example coil 833 shown in FIG. 8 includes three turns. A cross section of the coil 833 is shown with a notation, where the coil with an "X" rotatably extends into the page, while the coil with a "●" rotatably extends out of the page. The elements for plasma generation also include an RF power source 541 configured to provide RF power to the coil 833. Generally, the RF power source 841 is connected to a matching circuit 839 through a connection 845. The matching circuit 839 is connected to the coil 833 through a connection 843. In this manner, the RF power source 841 is connected to the coil 833. An optional Faraday shield 849a is positioned between the coil 833 and the window 811. Faraday shield 849a may be maintained in a spaced apart relationship to coil 833. In some embodiments, Faraday shield 849a is disposed directly above window 811. In some embodiments, Faraday shield 849b is between window 811 and chuck 817. In some embodiments, Faraday shield 849b is not maintained in a spaced apart relationship to coil 833. For example, Faraday shield 849b may be directly below window 811 with no gap. Coil 833, Faraday shield 849a, and window 811 are each configured to be substantially parallel to one another. Faraday shield 849a may be disposed in a spaced apart relationship to allow metal or other species to pass through the window 811 without any gap. Chamber This can prevent deposition on the window 811.

[0201] Process gases may be flowed into the processing chamber through one or more main gas inlets 860 positioned in the upper subchamber 802 and / or through one or more side gas inlets 870. Similarly, although not explicitly shown, similar gas inlets may be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one or two stage mechanical dry pump and / or a turbomolecular pump 840, pumps the process gases to the processing chamber. ChamberTo retrieve and process Chamber For example, a vacuum pump may be used to apply a vacuum to the lower sub-chamber 803 during the ALD purge operation. A valve-controlled conduit may be used to handle the vacuum pump to selectively control the application of the vacuum environment provided by the vacuum pump. Chamber A vacuum pump and a valve controlled fluid connection to the dose-coupled plasma processing chamber may be used to fluidly connect the dose-coupled plasma processing chamber to the plasma processing chamber. This may be done by using a closed-loop controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown) during operational plasma processing. Similarly, a vacuum pump and a valve controlled fluid connection to the dose-coupled plasma processing chamber may also be used.

[0202] During operation of the apparatus 800, one or more process gases may be supplied through gas inlets 860 and / or 870. In certain embodiments, process gases may be supplied only through the main gas inlet 860 or only through the side gas inlet 870. In some cases, the gas inlets shown in the figure may be replaced by more complex gas inlets, such as one or more showerheads. The Faraday shield 849a and / or optional grid 850 may be used to control the flow of gas through the process inlets. Chamber The liquid vaporization and delivery system may include internal channels and holes that allow for the delivery of process gases to the liquid reactants or precursors. Either or both of the Faraday shield 849a and optional grid 850 may act as a showerhead for the delivery of process gases. In some embodiments, the liquid vaporization and delivery system may be configured such that once the liquid reactants or precursors are vaporized, the vaporized reactants or precursors are introduced into the process chamber via gas inlets 860 and / or 870. Chamber As introduced in the processing Chamber It may be located upstream of

[0203] Radio frequency power is supplied from RF power supply 841 to coil 833, causing an RF current to flow through coil 833. The RF current flowing through coil 833 creates an electromagnetic field around coil 833. This electromagnetic field creates an induced current in upper subchamber 802. Physical and chemical interactions of the various generated ions and radicals with wafer 819 etch features on wafer 819 and selectively deposit layers on wafer 819.

[0204] When a plasma grid 850 is used such that both upper and lower subchambers 802 and 803 are present, induced currents act on the gas present in the upper subchamber 802 to generate an electron-ion plasma in the upper subchamber 802. The optional internal plasma grid 850 limits the amount of hot electrons in the lower subchamber 803. In some embodiments, the apparatus 800 is designed and operated such that the plasma present in the lower subchamber 803 is an ion-ion plasma.

[0205] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, but the ion-ion plasma has a greater proportion of negative ions to positive ions. Volatile etching and / or deposition byproducts may be removed from the lower subchamber 803 through port 822. The chuck 817 disclosed herein may operate at elevated temperatures ranging from about 10° C. to about 250° C. The temperature depends on the process operation and the particular recipe.

[0206] The apparatus 800 can be coupled to equipment (not shown) when installed in a cleaning chamber or fabrication facility. The equipment includes plumbing to provide process gases, vacuum, temperature control, and environmental particle control. These equipment are coupled to the apparatus 800 when the apparatus 800 is installed in a target fabrication facility. Additionally, the apparatus 800 can be coupled to a transfer chamber that allows a robot to transfer semiconductor wafers in and out of the apparatus 800 using typical automation.

[0207] In some embodiments, the system controller 830 (which may include one or more physical or logical controllers) controls the processing. Chamber The system controller 830 controls some or all of the operation of the system. The system controller 830 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 800 includes a switching system for controlling flow rates and durations when the disclosed embodiments are implemented. In some embodiments, the apparatus 800 may have a switching time of up to about 500 milliseconds or up to about 750 milliseconds. The switching time may depend on the flow chemistry, the recipe selected, the reactor architecture, and other factors.

[0208] In some embodiments, the system controller 830 is part of a system that may be part of the examples described above. The system controller 830 is further described above in connection with FIG.

[0209] EUVL patterning can be performed using any suitable tool, often referred to as a scanner, such as the TWINSCAN NXE:3300B® platform supplied by ASML, Veldhoven, NL. The EUVL patterning tool can be a standalone device into or out of which substrates are moved for deposition and etching as described herein. Or, as described below, the EUVL patterning tool can be a module on a larger multi-component tool. FIG. 9 depicts a semiconductor process cluster tool architecture with vacuum-integrated deposition, backside and bevel-edge cleaning, EUV patterning, and dry develop / etch modules interfaced with a vacuum transfer module, suitable for implementing the processes described herein. The processes can be performed without such vacuum-integrated equipment, although such equipment can be advantageous in some embodiments.

[0210] FIG. 9 depicts a semiconductor process cluster tool architecture with vacuum integrated deposition and patterning modules interfaced with a vacuum transfer module suitable for implementing the processes described herein. The arrangement of transfer modules for "transferring" wafers between multiple containment facilities and processing modules may be referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum integrated according to the requirements of the particular process. Other modules, such as for etching, may also be included on the cluster.

[0211] A vacuum transfer module (VTM) 938 interfaces with four processing modules 920a-920d, which may be individually optimized to perform various fabrication processes. By way of example, processing modules 920a-920d may be implemented to perform deposition, evaporation, ELD, dry develop, etch, strip, and / or other semiconductor processes. For example, module 920a may be an ALD reactor that may be operated to perform in a non-plasma thermal atomic layer deposition as described herein, such as a Vector tool available from Lam Research Corporation, Fremont, Calif., and module 920b may be a PECVD tool, such as a Lam Vector®. It should be understood that the figures are not necessarily drawn to scale.

[0212] Airlocks 942 and 946, also known as loadlocks or transfer modules, interface with the VTM 938 and the patterning module 940. For example, as described above, a suitable patterning module may be a TWINSCAN NXE:3300B® supplied by ASML of Veldhoven, NL. This tool architecture allows workpieces such as semiconductor substrates or wafers to be transferred under vacuum so they do not react prior to exposure. The integration of the deposition module with the lithography tool allows EUVL to also be used with H 2 O, O 2This is facilitated by the fact that, given the strong optical absorption of incident photons by surrounding gases such as , , a greatly reduced pressure is required.

[0213] As described above, this integrated architecture is only one possible embodiment of a tool for the implementation of the described process. The process can also be performed using a more conventional standalone EUVL scanner and deposition reactor, such as a Lam Vector tool, either standalone or integrated into a cluster architecture with other tools such as etch, strip, etc. (e.g., Lam Kiyo or Gamma tools), as a module as described with reference to FIG. 9, but without an integrated patterning module.

[0214] Airlock 942 may be an "outward" load lock, referring to the transfer of substrates from the VTM 938 serving the deposition module 920a to the patterning module 940, and airlock 946 may be an "inward" load lock, referring to the transfer of substrates from the patterning module 940 back to the VTM 938. The inward load lock 946 may also provide an interface to the outside of the tool for substrate access and egress. Each process module has a facet that interfaces with the module and the VTM 938. For example, deposition process module 920a has facet 936. Inside each facet, sensors, for example sensors 1-18 as shown, are used to detect the passage of wafer 926 as it is moved between the respective stations. Patterning module 940 and airlocks 942 and 946 may be similarly equipped with additional facets and sensors, not shown.

[0215] The main VTM robot 922 transfers wafers 926 between modules including airlocks 942 and 946. In one embodiment, the robot 922 has one arm, and in another embodiment, the robot 922 has two arms, each arm having an end effector 924 to pick up a wafer such as wafer 926 for transfer. The front end robot 944 is used to transfer wafers 926 from the outward airlock 942 into the patterning module 940 and from the patterning module 940 into the inward airlock 946. The front end robot 944 may also transfer wafers 926 between the inward loadlock and the outside of the tool for substrate access and egress. Because the inward airlock module 946 has the ability to match environments between atmosphere and vacuum, the wafers 926 can move between the two pressure environments without being damaged.

[0216] It should be noted that EUVL tools typically operate at a higher vacuum than deposition tools. In such cases, it is desirable to increase the vacuum environment of the substrate during transfer between the deposition and EUVL tools to allow the substrate to be degassed before entering the patterning tool. The outward airlock 942 holds the transferred wafer at a lower pressure, not exceeding the pressure in the patterning module 940, for a period of time, to allow the substrate to be degassed before entering the patterning tool. Module This function may be provided by venting any exhaust gases from the substrate so that the optical elements of 940 are not contaminated by the exhaust gases from the substrate. A suitable pressure for the outward exhaust gas airlock is no more than 1E-8 Torr.

[0217] In some embodiments, a system controller 950 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its separate modules. Note that the controller may be local to the cluster architecture or may be located outside the cluster architecture on the manufacturing floor or at a remote location connected to the cluster architecture via a network. The system controller 950 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor control boards, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the controller or they may be provided over a network. In certain embodiments, the system controller executes system control software.

[0218] The system control software may include instructions for controlling the timing and / or degree of application of any aspect of a tool or module operation. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components necessary to perform various process tool processes. The system control software may be coded in any suitable computer readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a semiconductor fabrication process may include one or more instructions for execution by the system controller. Instructions for setting process conditions for condensation, deposition, evaporation, patterning, and / or etching phases may be included in the corresponding recipe phase, for example.

[0219] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus may include a process chamber for patterning, depositing, and etching, and a controller including instructions for forming a negative pattern mask. The instructions may include code for patterning features in a chemically amplified (CAR) resist on a semiconductor substrate by EUV exposure to expose a surface of the substrate in the process chamber, developing the photopatterned resist, and etching an underlying layer or layer stack using the patterned resist as a mask. The development may be performed using a halide-containing chemistry.

[0220] Note that the computer controlling the wafer movement may be local to the cluster architecture or may be located outside the cluster architecture on the manufacturing floor or connected to the cluster architecture via a network at a remote location. A controller such as those described above with respect to any of Figures 6, 7, or 8 may be implemented with the tool in Figure 9.

[0221] 10 depicts a simplified diagram of a wet processing chamber 1000, according to various embodiments. The wet processing chamber 1000 may be used for one or more operations described herein, such as wet photoresist deposition, wet backside and bevel cleaning, and / or wet photoresist development. The wet processing chamber 1000 may include a substrate support 1002 configured to support a substrate 1001 during processing. In the embodiment of FIG. 10, the substrate support 1002 The substrate is located at its periphery. 1001The processing chamber 1000 includes a series of pins 1004 that support the substrate 1001. This allows processing on one side of the substrate with minimal substrate contact on the opposite side. Such an embodiment is particularly useful for processing the backside of a substrate, as the substrate can be loaded upside down (e.g., front side down) without damaging the front side of the substrate. The substrate support 1002 may be configured to rotate during processing, as indicated by the double arrow. Nozzles 1003 may be provided for dispensing processing liquids onto the surface of the substrate 1001. Appropriate plumbing (not shown) may be provided for providing associated processing liquids to the nozzles 1003 and for removing processing liquids from the processing chamber 1000. In some cases, the processing liquids may be recycled.

[0222] Experimental Results FIG. 11 depicts experimental results showing the concentration of tin on the backside of a substrate after various processing steps described herein. The results are shown at four different times: (A) after photoresist deposition, (B) after A and dry development of the photoresist, (C) after B, post-development bake, and H. 2 / N 2 After plasma treatment and (D) after wet cleaning on the backside and beveled edge of the substrate. At each time point, three different measurements were taken including (1) the center of the substrate, (2) 1 cm from the edge of the substrate, and (3) 0.5 cm from the edge of the substrate. As an example, vertical bar A1 in FIG. 11 shows the tin concentration on the substrate at location 1 at time A.

[0223] At time A, the concentration of tin is about 0.5E10 atoms / cm 2 ~1E10 atoms / cm 2 At time B, the concentration of tin is substantially higher due to contamination generated during the dry development step. For example, at time B, the concentration of tin is approximately 12E12 atoms / cm 2 ~15E12 atoms / cm 2 The tin concentration was measured by PDB and H 2 / N 2 As a result of the plasma treatment, the concentration of tin is substantially reduced between times B and C. At time C, the concentration of tin is approximately 3E10 atoms / cm 2 ~13E10 atoms / cm2 The tin concentration is further reduced between times C and D as a result of the wet backside and bevel edge cleaning operations. At time D, the tin concentration is <0.5E10 atoms / cm 2 These concentrations are comparable to and even lower than the starting concentrations at time A.

[0224] 12 depicts experimental results showing the concentration of tin contamination on the backside of a substrate after various processing steps described herein. Results are shown at five different times: (A) after photoresist deposition, (B) after A and dry development of the photoresist, (C) after B and post-development bake, (D) after C and wet cleaning of the substrate backside and beveled edge, and (E) after D and H. 2 After dry cleaning of the backside of the substrate with plasma, three different measurements were taken at each time point, including (1) the center of the substrate, (2) 1 cm from the edge of the substrate, and (3) 0.5 cm from the edge of the substrate. As an example, vertical bar A1 in FIG. 12 shows the tin concentration on the substrate at location 1 at time A.

[0225] At time A, the concentration of tin is about 0.5E10 atoms / cm 2 ~1E10 atoms / cm 2 At time B, the concentration of tin is substantially higher due to contamination generated during the dry development step. For example, at time B, the concentration of tin is approximately 12E12 atoms / cm 2 ~15E12 atoms / cm 2 The tin concentration is substantially reduced between times B and C as a result of the post-development bake. At time C, the tin concentration is approximately 6E10 atoms / cm 2 ~65E10 atoms / cm 2 The tin concentration is further reduced between times C and D as a result of the wet backside and bevel edge cleaning operations. At time D, the tin concentration is reduced to about 0.1E10 atoms / cm 2 ~0.2E10 atoms / cm 2 The tin concentration ranges from 0.01 to 0.01 on the back side of the substrate. 2Due to exposure to the plasma, the tin concentration continues to decrease between times D and E. At time E, the tin concentration is approximately 0.01E10 atoms / cm 2 ~0.05E10 atoms / cm 2 The range is as follows:

[0226] In particular, Figure 12 shows that a post-develop bake allowed for a significant reduction in the tin concentration on the backside of the substrate. Furthermore, a backside wet clean reduced the tin concentration to <1E10 atoms / cm. 2 to H for cleaning the backside of the board. 2 The addition of plasma further reduced the backside tin concentration by about four times.

[0227] 13A and 13B depict experimental results showing the benefit of adding a plasma treatment to the post-develop bake. In this example, the process flow involved (1) depositing photoresist, (2) wet cleaning the backside of the substrate, (3) dry developing the photoresist, (4) performing a post-develop bake (with and without a plasma treatment step), (5) wet cleaning the backside of the substrate again, (6) exposing the substrate to typical cue conditions for various durations, and (7) performing measurements to measure the concentration of tin on the backside of the substrate after different cue durations. The tin concentration was measured at three different times including 0, 3, and 5 days of cue time. On 0, 3, and 5 days, the tin concentration was measured at the center of the substrate and 0.5 cm from the edge of the substrate. Additionally, on 5 days, the tin concentration was measured 0.5 cm from the edge of the substrate along a crescent shape (CM). Measurements were performed on the backside of the substrate.

[0228] FIG. 13A shows the results when the post-development bake step did not include any plasma treatment. In contrast, FIG. 13B shows the results when the post-development bake step included a plasma treatment. The plasma treatment in this example was to expose the substrate to H 2 / N 2The first and second treatments involved exposure to plasma. As shown in Figures 13A and 13B, both treatment processes resulted in similar backside tin concentrations when the queue time was 0 or 3 days. When the queue time was increased to 5 days, the substrates exposed to plasma treatment during the post-development bake step exhibited substantially lower backside tin concentrations compared to substrates that were not exposed to plasma during this step. These results indicate that plasma treatment during the post-development bake step does not adversely affect the available queue time (e.g., the time available before the backside tin concentration rises to an unacceptably high level as a result of the problems described herein). In fact, such plasma treatments may in many cases increase the available queue time.

[0229] FIG. 14 shows experimental results that demonstrate the effectiveness of adding a plasma treatment to a post-develop bake. These results are consistent with those shown in FIG. 13A and FIG. 13B. In the example of FIG. 14, the process flow is: (1) depositing photoresist, (2) wet cleaning the backside of the substrate, (3) dry developing the photoresist, (4) performing a post-develop bake (with and without a plasma treatment step), (5) again wet cleaning the backside of the substrate, (6) exposing the substrate to typical queue conditions for a duration of about 2 days, and (7) dry developing the photoresist. Duration The plasma treatment during the post-development bake involved performing measurements to measure the concentration of tin on the backside of the substrate after development. 2 / N 2 As shown in FIG. 14, if no plasma treatment was used during the post-develop bake, the resulting backside tin concentration after 2 days of queue time was about 38E10 atoms / cm 2 When a plasma treatment was added to the post-develop bake, the resulting backside tin concentration after a queue time of 2 days was only about 4.2E10 atoms / cm 2 This represents nearly an order of magnitude reduction in backside tin concentration.

[0230] FIG. 15 depicts a substrate divided into three different analysis zones (Z1-Z3) and a table reporting the backside tin concentration within each zone. The first zone (Z1) corresponds to the central circular portion of the substrate down to a radius of about 75 mm. The second zone (Z1) corresponds to the middle annular portion of the substrate from a radius of about 75 mm to a radius of about 135 mm. The third zone (Z3) corresponds to the outer annular portion of the substrate from a radius of about 135 mm to a radius of about 148 mm. In this example, the process flow includes (1) depositing photoresist, (2) wet cleaning the backside of the substrate, (3) dry developing the photoresist, (4) performing a post-develop bake with a plasma treatment step, (5) wet cleaning the backside of the substrate again, (6) exposing the substrate to typical queue conditions for a duration of about 4.5 days, and (7) dry developing the photoresist. Duration The post-development bake step involved performing measurements to measure the concentration of tin on the backside of the substrate after development. 2 / N 2 The results in Figure 15 show that after this sequence, most of the tin contamination remaining on the backside of the substrate is located in the third zone, e.g., near the edge of the substrate.

[0231] 16A and 16B show the substrate H 2 / N 2 FIG. 16 depicts experimental results showing improvements in line critical diameter (FIG. 16A) and line width roughness (FIG. 16B) across a range of typical EUV doses as a result of a post-develop bake step that was accompanied by exposure to plasma treatment. These figures show measurements taken at two times, including before the post-develop bake step and after the post-develop bake step. FIG. 16A shows that the post-develop bake and plasma treatment steps resulted in a reduction in line critical diameter of about 0.4-0.5 nm across the EUV dose range. This represents a reduction of about 2-4% at each dose. Similarly, FIG. 16B shows that the post-develop bake and plasma treatment steps resulted in a reduction in line width roughness across the EUV dose range.

[0232] 17A and 17B depict experimental results showing the concentration of residual bromine on the front side of the substrate (FIG. 17A) and the concentration of tin contamination on the backside of the substrate (FIG. 17B) after processing in a post-development bake performed at various temperatures. In this example, the development process was a dry development process, and no wet cleaning (or other cleaning process) was performed between the post-development bake process and the measurement. FIG. 17A shows that exposing the substrate to a post-development bake process dramatically reduces the concentration of bromine in the substrate. As the temperature of the post-development bake increases, the residual bromine concentration decreases substantially. At higher temperatures (e.g., above about 250° C.), this benefit becomes less and less. FIG. 17B shows that as the post-development bake temperature increases, the concentration of tin contamination on the backside of the substrate decreases. The tin concentration decreased both at the center and edge of the substrate, with the decrease being especially large near the center of the substrate.

[0233] 18A and 18B depict experimental results showing the benefit of periodically cleaning the processing chamber used to perform the post-develop bake process. The first series of substrates shown in FIG. 18A were processed using a post-develop bake step, with no chamber cleaning performed between substrates. The second series of substrates shown in FIG. 18B were processed using a post-develop bake step, with the chamber being cleaned after each substrate was baked. In both cases, the tin concentration was measured after every fifth substrate was processed (e.g., after five substrates, after ten substrates, etc.). FIG. 18A shows that when the chamber is not periodically cleaned, the concentration of backside tin contamination continues to increase as additional substrates are processed. Indeed, the backside tin concentration is about two orders of magnitude higher after ten substrates have been processed, reaching 100E10 atoms / cm. 2 Such an increase is large and undesirable. In contrast, FIG. 18B shows that when the chamber is periodically cleaned, the concentration of backside tin contamination reaches 1E10 atoms / cm 2 This low and stable tin concentration is consistent with the onset concentration being orders of magnitude higher, 10E10 atoms / cm. 2This was achieved even when the

[0234] 19A and 19B show experimental results related to optimizing plasma processing according to various embodiments at lower temperatures. FIG. 19A focuses on the effect of different carrier gases on the backside tin concentration, while FIG. 19B focuses on the effect of the total flow rate on the backside tin concentration. In all of the examples related to FIG. 19A and FIG. 19B, the plasma processing was performed with hydrogen (H 2 The method involves exposing the substrate to a plasma generated from helium, nitrogen (N 2 ), or a combination of helium and nitrogen, was used as the carrier gas. Hydrogen was present at a concentration of about 5% by volume in each case. As shown in FIG. 19A, H 2 / He plasma treatment is H 2 / N 2 The results of the first plasma treatment resulted in a substantially lower backside tin concentration compared to the first plasma treatment. This suggests that helium provides better tin reduction results compared to nitrogen when acting as a carrier gas for hydrogen. Figure 19B shows the results from three different plasma treatments. The first plasma treatment was performed in which the substrate was heated to 1000 K and the second plasma treatment was performed in 1000 K. 2 The first plasma treatment involved a low flow regime where the substrate was exposed to a plasma generated from H 2 With intermediate flow conditions exposed to plasma generated from H 2 The flow of H / He was approximately double that of the first plasma treatment. The third plasma treatment was performed when the substrate was 2 / He / N 2 The high flow conditions involve exposure to plasma generated from H 2 / He / N 2 The flow of H used in the first plasma treatment 2 In this example, the flow rate of H 2 Doubling the flow rate of N / He resulted in a reduction in the concentration of backside tin contamination. 2 The addition of tin resulted in increased backside tin contamination.

[0235] Additional Embodiments 20 and 21 illustrate an example process flow according to various embodiments. In the example of FIG. 20, the substrate is processed using a wet development technique. In the example of FIG. 21, the substrate is processed using a dry development technique. The steps described in FIG. 20 and 21 may be combined with any one or more of the techniques described herein. Furthermore, any details provided herein with respect to a particular step may also apply when practicing the corresponding step in FIG. 20 and 21. For the sake of brevity, such details will not be repeated.

[0236] The wet development method 2000 of FIG. 20 begins at operation 2001, where photoresist is deposited on a substrate. The photoresist may be a metal-containing photoresist as described herein. In operation 2003, the substrate is cleaned using a wet cleaning technique, specifically targeting the backside and beveled edge regions of the substrate. In operation 2005, the substrate is exposed to a post-apply bake. In operation 2007, the substrate is exposed to EUV radiation to begin patterning the photoresist. In operation 2009, the substrate is exposed to a post-exposure bake. In operation 2011, the photoresist is developed using a wet development technique. In operation 2013, the substrate may be exposed to metrology or further processing. The further processing may involve one or more of the techniques described herein.

[0237] The dry development method 2050 of FIG. 21 begins in a similar manner to the method of FIG. 20. For example, operations 2001, 2003, 2005, 2007, and 2009 are the same as those of FIG. 20. After operation 2009, the method of FIG. 21 continues with operation 2021, where the photoresist is developed using a dry development technique. Then, in operation 2023, the substrate is exposed to a post-development bake. In operation 2025, the substrate is exposed to a chemical treatment. In various examples, the chemical treatment in operation 2025 may occur simultaneously with the photoresist dry development in operation 2021 and / or the post-development bake in operation 2023. In other examples, the chemical treatment in operation 2025 may occur separately, for example, between operations 2021 and 2023, or between operations 2023 and 2027. In operation 2027, the substrate is exposed to a wet cleaning operation to clean the backside of the substrate. In operation 2029, the substrate may be exposed to metrology or further processing.

[0238] 20 and 21 present some specific operations, it should be understood that one or more of these steps may be omitted in various embodiments. Any subset of the steps shown in FIG. 20 or 21 may be used in various embodiments.

[0239] conclusion A process and apparatus for controlling metal contamination on semiconductor substrates is disclosed. In many embodiments, the process and apparatus may be used in conjunction with the deposition, development, and / or processing of metal-containing photoresists, such as EUV photoresists. Other applications, such as in-situ cleaning, mandrel pull-out, smoothing, and photoresist descum applications, may also benefit from the disclosed embodiments.

[0240] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes therein will be suggested to those skilled in the art. Various details have been omitted for the sake of brevity, but various design alternatives may be implemented. Thus, the examples shall be considered illustrative rather than restrictive, and the present disclosure shall not be limited to the details provided herein, but may be modified within the scope of the present disclosure. The present invention can be realized, for example, in the following manner. Application example 1: 1. A method for controlling contamination on a substrate, comprising: (a) either (i) treating a front side of the substrate, thereby causing the formation of contamination comprising a metal on a back side of the substrate, or (ii) receiving the substrate with contamination on the back side of the substrate; (b) after (a), heating the substrate in a post-treatment bake process, where heating the substrate reduces a concentration of the metal on the backside of the substrate; and A method comprising: Application example 2: 13. The method of claim 1, wherein treating the front side of the substrate comprises at least one process selected from the group consisting of developing a layer of photoresist, in-situ cleaning the substrate, withdrawing mandrels in a patterning application, smoothing features on a substrate, and descumming a layer of photoresist. Application example 3: 3. The method of claim 2, (a) includes either (i) developing a layer of photoresist on the substrate, or (ii) receiving the substrate having a layer of photoresist developed on the front side of the substrate and contamination on the back side of the substrate; the metal in the contamination originates from the layer of photoresist on the front side of the substrate; The method, wherein the post-treatment bake process of (b) is a post-development bake process that occurs when the layer of photoresist is at least partially developed. Application example 4: 4. The method of claim 3, wherein during the post-development bake process of (b), the substrate is baked at a temperature of about 160-300° C. for a duration of about 1-10 minutes. Application example 5: 4. The method of claim 3, further comprising exposing the substrate to a process gas, the process gas comprising N 2 、H 2 , Ar, He, Xe, and combinations thereof. Application example 6: 4. The method of claim 3, further comprising exposing the substrate to a reactive process gas to increase the volatility of a metal-containing material on the substrate, the metal-containing material comprising the metal. Example 7: 4. The method of claim 3, further comprising exposing the substrate to a reactive process gas to increase stability of a metal-containing material on the substrate, the metal-containing material comprising the metal. Application example 8: The method of claim 3, further comprising the step of: 3 ), hydrogen iodide (HI), diatomic iodine (I 2 ), and combinations thereof. Example 9: 9. The method of claim 8, wherein the substrate is exposed to the chlorine-containing gas, the chlorine-containing gas being BCl 3 、Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 and combinations thereof. Example 10: 9. The method of claim 8, wherein the substrate is exposed to an oxygen-containing gas, the oxygen-containing gas comprising O 2 、O 3 、H 2 O, SO 2 , CO2, CO, COS, H 2 O 2 , NO x and combinations thereof. Example 11: 9. The method of claim 8, wherein the substrate is exposed to a fluorine-containing gas, the fluorine-containing gas being HF, C x F y H z , N.F. 3 ,SCIENCE FICTION 6 、F 2 and combinations thereof. Example 12: 4. The method of claim 3, further comprising exposing the substrate to a plasma to increase volatility of a metal-containing material on the substrate, the metal-containing material comprising the metal. Application example 13: 4. The method of claim 3, further comprising exposing the substrate to a plasma to increase stability of a metal-containing material on the substrate, the metal-containing material comprising the metal. Example 14: 4. The method of claim 3, further comprising: 2 ), diatomic nitrogen (N 2 ), argon, helium, krypton, methane (CH 4 ), an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a hydrogen halide, and combinations thereof. Example 15: 15. The method of claim 14, wherein the plasma generating gas comprises an oxygen-containing gas, the oxygen-containing gas being O 2 、O 3 , CO, CO 2 , COS, SO 2 , NOx, H 2 at least one gas selected from the group consisting of O, NH, NH3, NH4, NH5, NH6, NH7, NH8, NH9, NH10, NH11, NH12, NH3, NH4, NH5, NH6, NH7, NH8, NH9, NH12, NH13, NH14, NH15, NH16, NH17, NH18, NH19, NH20, NH21, NH22, NH30, NH41, NH42, NH50, NH51, NH52, NH63, NH74, NH85, NH96, NH97, NH106, NH118, NH128, NH14, NH15, NH16, NH17, NH18, NH19, NH22, NH30, Application example 16: 15. The method of claim 14, wherein the plasma generating gas comprises a fluorine-containing gas, the fluorine-containing gas being NF3 , C.F. 4 , C.H. 3 F 3 , C.H. 2 F 2 , CHF 3 、F 2 ,SCIENCE FICTION 6 and combinations thereof. Example 17: 15. The method of claim 14, wherein the plasma generating gas comprises the chlorine-containing gas, the chlorine-containing gas being BCl 3 、Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 and combinations thereof. Application example 18: 15. The method of claim 14, wherein the plasma generating gas is: (i) the diatomic hydrogen (H 2 ), and (ii) diatomic nitrogen (N 2 ) or a noble gas. Example 19: 4. The method of claim 3, wherein heating the substrate in the post-develop bake process reduces the concentration of the metal on the backside of the substrate by at least an order of magnitude. Example 20: 4. The method of claim 3, further comprising exposing the substrate to a plasma, wherein heating the substrate in a post-development bake process, and exposing the substrate to a plasma reduces the concentration of the metal on the backside of the substrate by at least two orders of magnitude. Example 21: 4. The method of claim 3, further comprising exposing the substrate to light to reduce a concentration of the metal on the backside of the substrate. Example 22: 22. The method of claim 21, wherein the light comprises at least one of a UV wavelength, a visible wavelength, or an IR wavelength. Example 23: 23. The method of claim 22, wherein the light is provided by an IR lamp or a plurality of LEDs, and the substrate is heated to a temperature of about 250-400°C for a duration of about 60 seconds or less while the substrate is exposed to the light. Application 24: 4. The method of claim 3, wherein heating the substrate in the post-develop bake process begins while the layer of photoresist is still being developed onto the substrate. Example 25: 4. The method of claim 3, further comprising transferring the substrate from the first processing chamber to the second processing chamber after (a), such that (a) occurs in the first processing chamber and (b) occurs in the second processing chamber. Example 26: 4. The method of claim 3, wherein (a) occurs in a processing chamber, the method further comprising heating the processing chamber to a temperature of about 40° C. or greater while the layer of photoresist is developed in (a). Example 27: 4. The method of claim 3, wherein (a) occurs within a processing chamber, the method further comprising purging the processing chamber while maintaining the processing chamber at a temperature of about 100° C. or greater, the purging occurring after (a). Example 28: 30. The method of claim 27, further comprising sweeping the processing chamber with an inert gas, the purging and the sweep being part of a pump-purge sequence. Example 29: 4. The method of claim 3, further comprising performing a wet clean on the backside of the substrate after (a) and (b). Example 30: 30. The method of claim 29, wherein performing the wet clean on the backside of the substrate further reduces the concentration of the metal on the backside of the substrate by at least an order of magnitude. Example 31: 30. The method of claim 29, wherein the wet cleaning also cleans a beveled edge region of the front side of the substrate. Example 32: 30. The method of claim 29, wherein performing the wet clean on the backside of the substrate comprises exposing the backside of the substrate to dilute HF. Application 33: 33. The method of claim 32, wherein performing the wet cleaning on the backside of the substrate comprises: wet cleaning the backside of the substrate in dilute HCl or NH 4 OH, H 2 O 2 , and H 2 The method further comprises exposing the mixture to a standard wash 1 solution containing O. Example 34: 4. The method of claim 3, wherein the layer of photoresist is formed using dry deposition. Example 35: 4. The method of claim 3, wherein the layer of photoresist is formed using wet deposition. Example 36: 4. The method of claim 3, wherein the layer of photoresist is developed using a dry process. Example 37: 37. The method of claim 36, wherein the layer of photoresist is developed using a halogen-containing chemistry. Application 38: 4. The method of claim 3, wherein the layer of photoresist is developed using a wet process. Example 39: 4. The method of claim 3, wherein the post-development bake process of (b) occurs in a processing chamber and is performed under the following conditions: (i) the pressure in the processing chamber is maintained at about 0.01 to 1 Torr; (ii) a chlorine-containing gas is provided to the processing chamber at a rate of about 200-10,000 sccm for a duration of about 1-10 minutes; (iii) the temperature of one or more components of the processing chamber is maintained at about 20-150° C.; and (iv) the substrate is not exposed to a plasma during (b). is used during the post-development bake process of (b). Example 40: 4. The method of claim 3, wherein the layer of photoresist is developed in (a) in a process chamber and (b) occurs in the same process chamber as (a), the method comprising: (i) the pressure in the processing chamber is about 0.01 to 1 Torr; (ii) a flow of purge gas is provided to the process chamber at a rate of about 200 to 10,000 sccm, the purge gas being diatomic nitrogen (N 2 ), a noble gas, and combinations thereof, wherein the purge gas is provided to the processing chamber for a duration of about 1 to 10 minutes; and (iii) one or more components of the processing chamber are maintained at about 100-300° C. and a substrate support within the processing chamber is maintained at about 120-300° C.; The method further comprises purging the processing chamber using Example 41: 4. The method of claim 3, wherein (a) occurs in a first processing chamber and (b) occurs in a second processing chamber, the method comprising the steps of: (i) the pressure in the second processing chamber is between about 0.1 and 760 Torr; (ii) a flow of gas is provided to the second process chamber at a rate of about 200-10,000 sccm for a duration of about 1-10 minutes, the substrate is exposed to the flow of gas, the flow of gas being selected from the group consisting of air, diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), water (H 2 O), a noble gas, or a combination thereof; and (iii) The substrate is baked at a temperature of about 140 to 300° C. is used during the post-development bake process of (b). Example 42: The method of claim 3, wherein the following conditions are met: (i) the pressure in the processing chamber is about 0.1 to 1 Torr; (ii) a plasma generating gas is provided at a rate of about 50-5,000 sccm for a duration of about 3-30 seconds, the plasma generating gas being: (a) H 2 , (b) H 2 and N 2 , (c) H 2 and noble gases, (d) H 2 N for None 2 , (e) H 2 (f) an oxygen-containing gas; (g) a fluorine-containing gas; and (h) combinations thereof; and (iii) a plasma is generated from the plasma generating gas and the substrate is exposed to the plasma. The method further comprising exposing the substrate to a plasma in a processing chamber under a Example 43: 4. The method of claim 3, wherein at least one of (a) and (b) occurs within a processing chamber, the method further comprising cleaning the processing chamber to remove the metal from an interior surface of the processing chamber. Example 44: 44. The method of claim 43, wherein the processing chamber is operated under the following conditions: (i) the pressure in the processing chamber is about 0.1 to 10 Torr; (ii) a plasma containing H radicals is exposed to the processing chamber, and the H radicals react with the metal on the interior surface of the processing chamber to form a metal hydride. (iii) the plasma is generated using an RF power of about 300 to 4,000 watts; and (iv) the processing chamber is maintained at about 25 to 250° C.; The method is carried out using Example 45: 44. The method of claim 43, wherein the processing chamber is operated under the following conditions: (i) the pressure in the processing chamber is about 0.1 to 10 Torr and is cycled between lower and higher pressures as part of a pumping and purging process; (ii) the processing chamber is not exposed to plasma during cleaning; (iii) a gas flow is provided to the process chamber during cleaning, the gas flow comprising diatomic nitrogen (N 2 ), diatomic oxygen (O 2), a noble gas, and combinations thereof; and (iv) the processing chamber is maintained at about 25 to 250° C.; The method is carried out using Example 46: The method of claim 3, wherein the following conditions are met: (i) in a first step, the substrate is exposed to a first cleaning solution provided at a rate of about 1-3 L / min, the first cleaning solution comprising dilute HF; (ii) in a second step, the substrate is exposed to a second cleaning solution provided at a rate of about 1-3 L / min, the second cleaning solution comprising a solution selected from the group consisting of dilute HCl, standard cleaning 1, and combinations thereof; (iii) the first step and the second step together have a duration of about 20 to 300 seconds; and (iv) the substrate is maintained at about 15 to 60° C.; performing a wet cleaning on the backside of the substrate using. Example 47: 4. The method of claim 3, wherein the concentration of the metal in at least one of the backside or beveled edge regions of the substrate is about 1E11 atoms / cm 2 wherein the compound is reduced by at least an order of magnitude to Example 48: 48. The method of claim 47, wherein the concentration of the metal in at least one of the backside or beveled edge regions of the substrate is about 1E10 atoms / cm 2 wherein the compound is reduced by at least an order of magnitude to Example 49: 4. The method of claim 3, wherein the metal is tin. Application example 50: 1. A system for processing a substrate, comprising: a processing chamber; an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber; an outlet into the processing chamber for removing material from the processing chamber; A heater; A substrate support; a controller configured to cause any one or more of the methods of claims 1 to 49 or otherwise described herein; A system comprising: Example 51: 1. A system for processing a substrate, comprising: a processing chamber; an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber; an outlet into the processing chamber for removing material from the processing chamber; A heater; A substrate support; A controller, (a) either (i) treating a front side of the substrate, thereby causing the formation of metal-containing contamination on a back side of the substrate, or (ii) receiving the substrate with contamination on the back side of the substrate; and (b) after (a), heating the substrate in a post-treatment bake process, where heating the substrate reduces a concentration of the metal on the backside of the substrate. a controller configured to cause A system comprising: Application example 52: 52. The system of claim 51 , wherein treating the front side of the substrate comprises at least one process selected from the group consisting of developing a layer of photoresist, in situ cleaning the substrate, withdrawing mandrels in a patterning application, smoothing features on a substrate, and descumming a layer of photoresist. Application example 53: 53. The system of claim 52, wherein the controller is configured to cause (a) by causing either (i) developing the layer of photoresist on a substrate, or (ii) receiving the substrate having a layer of photoresist developed on the front side of the substrate and contamination on the back side of the substrate; the metal in the contamination originates from the layer of photoresist on the front side of the substrate; The post-treatment bake process of (b) is a post-development bake process that occurs when the layer of photoresist is at least partially developed. Application example 54: 54. The system of claim 53, wherein both (a) and (b) occur within the same processing chamber. Application example 55: 54. The system of claim 53, wherein (a) occurs within the processing chamber and (b) occurs within a second processing chamber, the second processing chamber being a different processing chamber than the processing chamber. Application example 56: 54. The system of claim 53, further comprising a plasma generator configured to provide a plasma in the processing chamber. Example 57: 57. The system of claim 56, wherein the plasma generator is a remote plasma generator such that the plasma is generated at a first location outside the processing chamber and delivered to a second location inside the processing chamber.

Claims

1. 1. A method for controlling contamination on a substrate, comprising: (a) either (i) treating a front side of the substrate, thereby causing the formation of contamination comprising a metal on a back side of the substrate, or (ii) receiving the substrate with contamination on the back side of the substrate; (b) after (a), heating the substrate in a post-treatment bake process, the post-treatment bake process including a post-development bake process that occurs when a layer of photoresist is at least partially developed, the post-development bake process of (b) being performed under conditions that reduce a concentration of the metal on the backside of the substrate, and further including exposing the substrate to a treatment gas, the treatment gas being H. 2 , Ar, He, Xe, and combinations thereof; (b) heating the substrate, during which the substrate is baked at a temperature of about 160-300° C.; and A method comprising:

2. 10. The method of claim 1, wherein treating the front side of the substrate comprises at least one process selected from the group consisting of developing the layer of photoresist, in-situ cleaning the substrate, withdrawing mandrels in a patterning application, smoothing features on a substrate, and descumming the layer of photoresist.

3. 3. The method of claim 2, (a) includes either (i) developing a layer of photoresist on the substrate, or (ii) receiving the substrate having a layer of photoresist developed on the front side of the substrate and contamination on the back side of the substrate; The method, wherein the metal in the contamination originates from the layer of photoresist on the front side of the substrate.

4. 2. The method of claim 1, wherein during the post-development bake process of (b), the substrate is baked for a duration of about 1 to 10 minutes.

5. 10. The method of claim 1, further comprising exposing the substrate to a reactive process gas to increase the volatility of a metal-containing material on the substrate, the metal-containing material comprising the metal.

6. 10. The method of claim 1, further comprising exposing the substrate to a reactive process gas to increase stability of a metal-containing material on the substrate, the metal-containing material comprising the metal.

7. 2. The method of claim 1, further comprising the step of: 3 ), hydrogen iodide (HI), diatomic iodine (I 2 ), and combinations thereof.

8. 8. The method of claim 7, wherein the substrate is exposed to a chlorine-containing gas, the chlorine-containing gas being BCl 3 , Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 and combinations thereof.

9. 8. The method of claim 7, wherein the substrate is exposed to an oxygen-containing gas, the oxygen-containing gas comprising O 2 , O 3 , H 2 O, S.O. 2 , CO2, CO, COS, H 2 O 2 , NO x and combinations thereof.

10. 8. The method of claim 7, wherein the substrate is exposed to a fluorine-containing gas, the fluorine-containing gas being selected from the group consisting of HF, C x F y H z , N.F. 3 , S.F. 6 , F 2 and combinations thereof.

11. 10. The method of claim 1, further comprising exposing the substrate to a plasma to increase volatility of a metal-containing material on the substrate, the metal-containing material comprising the metal.

12. 10. The method of claim 1, further comprising exposing the substrate to a plasma to increase stability of a metal-containing material on the substrate, the metal-containing material comprising the metal.

13. 2. The method of claim 1, wherein the diatomic hydrogen (H 2 ), diatomic nitrogen (N 2 ), argon, helium, krypton, methane (CH 4 ), exposing the substrate to a plasma generated from a plasma generating gas comprising at least one gas selected from the group consisting of an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a hydrogen halide, and combinations thereof.

14. 14. The method of claim 13, wherein the plasma generating gas comprises an oxygen-containing gas, the oxygen-containing gas being O 2 , O 3 , CO, CO 2 , COS, SO 2 , NOx, H 2 , O, and combinations thereof.

15. 14. The method of claim 13, wherein the plasma generating gas comprises a fluorine-containing gas, the fluorine-containing gas being NF 3 , C.F. 4 , C.H. 3 F 3 , C.H. 2 F 2 , C.H.F. 3 , F 2 , S.F. 6 and combinations thereof.

16. 14. The method of claim 13, wherein the plasma generating gas comprises the chlorine-containing gas, the chlorine-containing gas being BCl 3 , Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 and combinations thereof.

17. 14. The method of claim 13, wherein the plasma generating gas is: (i) the diatomic hydrogen (H 2 ), and (ii) diatomic nitrogen (N 2 ) or a noble gas.

18. 10. The method of claim 1, wherein heating the substrate in the post-develop bake process reduces the concentration of the metal on the backside of the substrate by at least an order of magnitude.

19. 10. The method of claim 1, further comprising exposing the substrate to a plasma, wherein heating the substrate in the post-development bake process, and exposing the substrate to a plasma reduces the concentration of the metal on the backside of the substrate by at least two orders of magnitude.

20. 10. The method of claim 1, further comprising exposing the substrate to light to reduce a concentration of the metal on the backside of the substrate.

21. 21. The method of claim 20, wherein the light comprises at least one of a UV wavelength, a visible wavelength, or an IR wavelength.

22. 22. The method of claim 21, wherein the light is provided by an IR lamp or a plurality of LEDs, and the substrate is heated to a temperature of about 250-400° C. for a duration of about 60 seconds or less while the substrate is exposed to the light.

23. 2. The method of claim 1, wherein heating the substrate in the post-development bake process begins while the layer of photoresist is still being developed onto the substrate.

24. 10. The method of claim 1, further comprising transferring the substrate from the first processing chamber to the second processing chamber after (a), such that (a) occurs in the first processing chamber and (b) occurs in the second processing chamber.

25. 10. The method of claim 1 , wherein (a) occurs in a process chamber, the method further comprising heating the process chamber to a temperature of about 40° C. or greater while the layer of photoresist is developed in (a).

26. 10. The method of claim 1 , wherein (a) occurs within a processing chamber, the method further comprising purging the processing chamber while maintaining the processing chamber at a temperature of about 100° C. or greater, the purging occurring after (a).

27. 27. The method of claim 26, further comprising sweeping the processing chamber with an inert gas, the purging and the sweeping being part of a pump-purge sequence.

28. 10. The method of claim 1, further comprising, after (a) and (b), performing a wet clean on the backside of the substrate.

29. 30. The method of claim 28, wherein performing the wet clean at the backside of the substrate further reduces the concentration of the metal at the backside of the substrate by at least an order of magnitude.

30. 30. The method of claim 28, wherein the wet cleaning also cleans a beveled edge region of the front side of the substrate.

31. 30. The method of claim 28, wherein performing the wet clean on the backside of the substrate comprises exposing the backside of the substrate to dilute HF.

32. 32. The method of claim 31, wherein performing the wet cleaning on the backside of the substrate comprises: wet cleaning the backside of the substrate in dilute HCl or NH 4 O.H. 2 O 2 , and H 2 The method further comprises exposing the cells to a standard wash 1 solution containing O.

33. The method of claim 3 , wherein the layer of photoresist is formed using dry deposition.

34. The method of claim 3 , wherein the layer of photoresist is formed using wet deposition.

35. 4. The method of claim 3, wherein the layer of photoresist is developed using a dry process.

36. 36. The method of claim 35, wherein the layer of photoresist is developed using a halogen-containing chemistry.

37. 4. The method of claim 3, wherein the layer of photoresist is developed using a wet process.

38. 4. The method of claim 3, wherein the post-development bake process of (b) occurs in a processing chamber and is performed under the following conditions: (i) the pressure in the processing chamber is maintained at about 0.01 to 1 Torr; (ii) a chlorine-containing gas is provided to the processing chamber at a rate of about 200-10,000 sccm for a duration of about 1-10 minutes; (iii) the temperature of one or more components of the processing chamber is maintained at about 20-150° C.; and (iv) the substrate is not exposed to a plasma during (b). is used during the post-development bake process of (b).

39. 4. The method of claim 3, wherein the layer of photoresist is developed in (a) in a process chamber and (b) occurs in the same process chamber as (a), the method comprising the steps of: (i) the pressure in the processing chamber is about 0.01 to 1 Torr; (ii) a flow of purge gas is provided to the processing chamber at a rate of about 200 to 10,000 sccm, the purge gas being diatomic nitrogen (N 2 ), a noble gas, and combinations thereof, wherein the purge gas is provided to the processing chamber for a duration of about 1 to 10 minutes; and (iii) one or more components of the processing chamber are maintained at about 100-300° C. and a substrate support within the processing chamber is maintained at about 120-300° C.; The method further comprises purging the processing chamber using

40. 4. The method of claim 3, wherein (a) occurs in a first processing chamber and (b) occurs in a second processing chamber, the method comprising the steps of: (i) the pressure in the second processing chamber is between about 0.1 and 760 Torr; (ii) a flow of gas is provided to the second processing chamber at a rate of about 200-10,000 sccm for a duration of about 1-10 minutes, the substrate is exposed to the flow of gas, the flow of gas being selected from the group consisting of air, diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), water (H 2 O), a noble gas, or a combination thereof; and (iii) the substrate is baked at a temperature of about 140-300° C. is used during the post-development bake process of (b).

41. 4. The method of claim 3, wherein the method is performed under the following conditions: (i) the pressure in the processing chamber is about 0.1 to 1 Torr; (ii) a plasma generating gas is provided at a rate of about 50-5,000 sccm for a duration of about 3-30 seconds, said plasma generating gas comprising: (a) H 2 , (b) H 2 and N 2 , (c) H 2 and noble gases, (d) H 2 No N 2 , (e) H 2 (f) an oxygen-containing gas; (g) a fluorine-containing gas; and (h) combinations thereof; and (iii) a plasma is generated from the plasma generating gas and the substrate is exposed to the plasma. The method further comprising exposing the substrate to a plasma in a processing chamber under a

42. 4. The method of claim 3, wherein at least one of (a) and (b) occurs in a processing chamber, the method further comprising cleaning the processing chamber to remove the metal from an interior surface of the processing chamber.

43. 43. The method of claim 42, wherein the processing chamber is operated under the following conditions: (i) the pressure in the processing chamber is about 0.1 to 10 Torr; (ii) a plasma containing H radicals is exposed to the processing chamber, and the H radicals react with the metal on the interior surface of the processing chamber to form a metal hydride. (iii) the plasma is generated using an RF power of about 300 to 4,000 watts; and (iv) the processing chamber is maintained at about 25-250° C.; The method is carried out using

44. 43. The method of claim 42, wherein the processing chamber is operated under the following conditions: (i) the pressure in the processing chamber is about 0.1 to 10 Torr and is cycled between lower and higher pressures as part of a pumping and purging process; (ii) the processing chamber is not exposed to plasma during cleaning; (iii) a gas flow is provided to the process chamber during cleaning, the gas flow comprising diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), a noble gas, and combinations thereof; and (iv) the processing chamber is maintained at about 25-250° C.; The method is carried out using

45. 4. The method of claim 3, wherein the method is performed under the following conditions: (i) in a first step, the substrate is exposed to a first cleaning solution provided at a rate of about 1-3 L / min, the first cleaning solution comprising dilute HF; (ii) in a second step, the substrate is exposed to a second cleaning solution provided at a rate of about 1-3 L / min, the second cleaning solution comprising a solution selected from the group consisting of dilute HCl, standard cleaning 1, and combinations thereof; (iii) the first and second steps together have a duration of about 20 to 300 seconds; and (iv) the substrate is maintained at about 15-60° C.; performing a wet cleaning on the backside of the substrate using.

46. 4. The method of claim 3, wherein the concentration of the metal in at least one of the backside or bevel regions of the substrate is about 1E11 atoms / cm 2 wherein the compound is reduced by at least an order of magnitude to

47. 47. The method of claim 46, wherein the concentration of the metal in at least one of the backside or beveled edge regions of the substrate is about 1E10 atoms / cm 2 wherein the compound is reduced by at least an order of magnitude to

48. The method of claim 3 , wherein the metal is tin.

49. 1. A system for processing a substrate, comprising: a processing chamber; an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber; an outlet into the processing chamber for removing material from the processing chamber; A heater; A substrate support; A controller, (a) either (i) treating a front side of the substrate, thereby causing the formation of metal-containing contamination on a back side of the substrate, or (ii) receiving the substrate with contamination on the back side of the substrate; and (b) after (a), heating the substrate in a post-treatment bake process, the post-treatment bake process including a post-development bake process that occurs when a layer of photoresist is at least partially developed, the post-development bake process of (b) being performed under conditions that reduce a concentration of the metal on the backside of the substrate, and further including exposing the substrate to a treatment gas, the treatment gas being H. 2 , Ar, He, Xe, and combinations thereof; During the post-development bake process of (b), the substrate is baked at a temperature of about 160 to 300° C. Heating the substrate a controller configured to cause A system comprising:

50. 50. The system of claim 49, wherein treating the front side of the substrate comprises at least one process selected from the group consisting of developing the layer of photoresist, in-situ cleaning the substrate, withdrawing mandrels in a patterning application, smoothing features on a substrate, and descumming the layer of photoresist.

51. 51. The system of claim 50, wherein the controller is configured to cause (a) by causing either (i) developing a layer of photoresist on a substrate, or (ii) receiving the substrate having the layer of photoresist developed on the front side of the substrate and having contamination on the back side of the substrate; The system, wherein the metal in the contamination originates from the layer of photoresist on the front side of the substrate.

52. 51. The system of claim 50, wherein both (a) and (b) occur in the same processing chamber.

53. 51. The system of claim 50, wherein (a) occurs within the processing chamber and (b) occurs within a second processing chamber, the second processing chamber being a different processing chamber than the processing chamber.

54. 51. The system of claim 50, further comprising a plasma generator configured to provide a plasma in the processing chamber.

55. 55. The system of claim 54, wherein the plasma generator is a remote plasma generator such that the plasma is generated at a first location outside the processing chamber and delivered to a second location inside the processing chamber.

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