Conformally doped amorphous silicon as a nucleation layer for metal deposition.

Abstract

A method is disclosed for depositing a metal layer onto a doped amorphous silicon layer as a nucleation layer and / or adhesion layer on a substrate, and some embodiments further include incorporating an adhesion layer to enhance the ability of the doped amorphous silicon layer and the metal layer to adhere to the substrate. [Selected Figure] Figure 2B

Description

[Technical field]

[0001]

[0001] The present disclosure relates generally to methods for depositing thin films, and in particular to processes for the deposition of films including doped amorphous silicon. [Background technology]

[0002]

[0002] Amorphous silicon is widely used in semiconductor devices, flat panel displays, and solar cells. Significant technical challenges remain in developing amorphous silicon deposition processes with conformality (i.e., good step coverage) or gap-filling performance in high aspect ratio features. Conventional LPCVD processes are limited to high temperatures (>550 degrees Celsius) and low pressures, and therefore exhibit poor step coverage and / or gap-filling performance, and PECVD processes also do not provide good step coverage and / or gap-filling performance.

[0003]

[0003] Atomic layer deposition (ALD) of tungsten thin films exhibits very long incubation delays due to poor nucleation performance in the service of silicon, silicon dioxide, and titanium nitride. Nucleation layers are typically used to alleviate this challenge. Conventionally, ALD WSi x Or WB x are deposited by WF6 / Si2H6 and WF6 / B2H6, respectively. However, WF6 is directly exposed to the substrate surface (e.g., Si, SiO2), which will damage the substrate.

[0004]

[0004] Therefore, there is a need in the art for a method of depositing metal films with high conformality at lower temperatures. Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a processing method that includes exposing a substrate surface to a silicon precursor and a dopant to form a doped amorphous silicon layer having a thickness. A metal layer is formed on the doped amorphous silicon layer.

[0006]

[0006] A further embodiment of the present disclosure is directed to a stack comprising a substrate having an oxide surface. An adhesive layer is on the oxide surface, the adhesive layer comprising TiN. A doped amorphous silicon layer is on the adhesive layer and comprises one or more of boron, phosphorus, arsenic, or germanium. A metal layer is on the doped amorphous silicon layer and comprises one or more of tungsten or molybdenum.

[0007]

[0007] A further embodiment of the present disclosure is directed to a process comprising providing a silicon substrate having a silicon oxide surface. An adhesive layer is formed on the silicon substrate. The adhesive layer comprises TiN and has a thickness within a range of about 1 Å to about 30 Å. A doped amorphous silicon layer is formed on the adhesive layer by exposing the adhesive layer to a silicon precursor comprising disilane and a dopant comprising diborane. The substrate is maintained at a temperature of about 100 degrees Celsius or less. A metal layer is formed on the amorphous silicon layer.

[0008]

[0008] In order to allow the above-mentioned features of the present disclosure to be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief description of the drawings]

[0009] [Figure 1] 1 shows a schematic of a membrane stack according to one or more embodiments of the present disclosure. [Figure 2A]

[0010] 1 shows a process scheme according to one or more embodiments of the present disclosure. [Figure 2B]

[0011] 2B shows a schematic of a film stack according to the process scheme of FIG. 2A. [Diagram 3]

[0012] 1 shows a process scheme according to one or more embodiments of the present disclosure. [Figure 4A]

[0013] 1 shows a process scheme according to one or more embodiments of the present disclosure. [Figure 4B]

[0014] 4B shows a schematic of a film stack according to the process scheme of FIG. 4A. [Diagram 5]

[0015] 1 illustrates an exemplary system for processing a substrate in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0016] Before certain exemplary embodiments of the present disclosure are described, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0011]

[0017] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on an underlayer formed on the substrate as disclosed in more detail below. The term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0012]

[0018] As used herein and in the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0013]

[0019] One or more embodiments of the present disclosure are directed to methods of depositing conformally doped amorphous silicon thin films as one or more of an adhesion layer, a fluorine diffusion barrier, and / or a nucleation layer for metal deposition (e.g., ALD tungsten deposition). Although tungsten deposition is referenced in many embodiments, one of ordinary skill in the art will appreciate that other metals (e.g., Mo) may be deposited by the processes of the present disclosure. The present disclosure is not limited to ALD tungsten deposition, ALD deposition, or tungsten deposition.

[0014]

[0020] Embodiments of the present disclosure include a process integration scheme for a metal ALD process. For example, tungsten is deposited on a silicon substrate by atomic layer deposition. Referring to FIG. 1, a stack 10 includes an adhesion layer 14 (e.g., TiN), a nucleation layer 16 (e.g., WSi x and W.B. x ), and metal 18 (e.g., W). In one or more embodiments of the process scheme, the nucleation layer is replaced by a doped amorphous silicon layer. In some embodiments, the nucleation layer is replaced by a doped amorphous silicon layer and the TiN glue layer is made thinner. In one or more embodiments, both the nucleation layer and the glue layer are replaced by a doped amorphous silicon layer.

[0015]

[0021] 2A and 2B, one or more embodiments of the present disclosure are directed to a processing method 100 and a film stack 200. A substrate 220 having a substrate surface 222 is provided in step 110. In step 120, the substrate 220 is exposed to a silicon precursor and a dopant to form a doped amorphous silicon layer 240 on the substrate surface 222.

[0016]

[0022] Some embodiments of the present disclosure advantageously provide a method of lowering the deposition temperature of the nucleation layer by incorporating dopants. In some embodiments, the morphology of the nucleation layer is modified by adding dopants during the deposition of the conformal amorphous silicon layer. In some embodiments, the deposition temperature of the amorphous silicon can be reduced from about 400 degrees Celsius or higher to about 100 degrees Celsius or lower. In some embodiments, the properties of the tungsten film can be advantageously modified by changing the dopant concentration due to the different film properties / morphology of the doped silicon film compared to the undoped amorphous silicon film.

[0017]

[0023] In some embodiments, the formation of doped amorphous silicon (doped a-Si) can be achieved by maximizing the partial pressure of the silicon precursor while minimizing the wafer temperature. In some embodiments, the doped amorphous silicon is deposited using a CVD deposition process, where the silicon precursor and the dopant are exposed to the substrate simultaneously.

[0018]

[0024] Suitable silicon precursors are polysilanes (Si x H y ) and halosilane (Si x H y X a For example, polysilanes include, but are not limited to, silane, disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), isotetrasilane, neopentasilane (Si5H 12 ), cyclopentasilane (Si5H 10 ), Hexasilane (C6H 14 ), cyclohexasilane (Si6H 12 ), or generally, Si x H y where x=1 or more x H y For example, disilane, which has a moderate processing temperature and high vapor pressure, may be used as a silicon precursor, either alone or in combination with other species.

[0019]

[0025] For example, the halosilane may be a dihalosilane (SiH2X2), a trihalosilane (SiHX3), a tetrahalosilane (SiX4), or a hexahalodisilane (Si2X6), or generally, Si x H y X a where x=1 or more, X is a halogen, and a=1 or more. x H y X aand combinations thereof. In some embodiments, the halogens present in the halosilane are individually selected from fluorine, chlorine, bromine, or iodine. In some embodiments, the halogens consist essentially of chlorine.

[0020]

[0026] In some embodiments, the silicon precursor comprises substantially only disilane. In some embodiments, the silicon precursor comprises substantially only dichlorosilane. As used in this specification and the accompanying claims, the term "substantially only" means that at least 95% of the active species are the described species. Other gases, such as carrier gases and inert gases, may also be included in any amount.

[0021]

[0027] The dopant may be any material suitable for doping the amorphous silicon layer being deposited. In some embodiments, the doped amorphous silicon layer comprises one or more of boron, phosphorus, arsenic, or germanium. In some embodiments, the dopant comprises one or more of borane, diborane, phosphine, diphosphine, arsine, diarsine, germane, or digermane. In some embodiments, the dopant comprises substantially only diborane. In some embodiments, the dopant comprises substantially only diphosphine. In some embodiments, the dopant comprises substantially only diarsine. In some embodiments, the dopant comprises substantially only digermane.

[0022]

[0028] The thickness of the doped amorphous silicon layer 240 can vary depending on, for example, the substrate surface and subsequent films and processes. In some embodiments, the doped amorphous silicon layer 240 has a thickness of about 20 Å or more. In one or more embodiments, the doped amorphous silicon layer 240 has a thickness in the range of about 1 Å to about 200 Å, or in the range of about 10 Å to about 150 Å, or in the range of about 20 Å to about 100 Å, or in the range of about 40 Å to about 100 Å. In some embodiments, the doped amorphous silicon layer 240 has a thickness in the range of about 10 Å to about 50 Å. In some embodiments, the doped amorphous silicon layer 240 has a thickness above 0 Å and less than or equal to about 100 Å, 75 Å, 50 Å, 45 Å, or 40 Å. In some embodiments, the doped amorphous silicon layer 240 has a minimum thickness sufficient to form a continuous layer. As used herein, the term "continuous" refers to covering the entire exposed surface with no gaps or bare spots exposing the underlying material of the deposited layer. A continuous layer may have gaps or bare spots with a surface area of ​​less than about 1% of the total surface area of ​​the film.

[0023]

[0029] In an embodiment, the doped amorphous silicon layer 240 is formed conformally on the substrate 220. As used herein, the terms "conformal" or "conformally" refer to a layer that adheres to and uniformly covers an exposed surface with a thickness that has less than 1% variation relative to the average thickness of the film. For example, a 100 Å thick film will have less than 1 Å variation in thickness. This thickness and variation includes edges, corners, sides, and bottoms of recesses. For example, the conformal layer deposited in various embodiments of the present disclosure will provide essentially uniform thickness coverage of the deposition area over a complex surface.

[0024]

[0030] In step 130, a metal layer 280 is formed on the doped amorphous silicon layer 240. The metal layer 280 may be formed by any suitable technique, including, but not limited to, atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PE-ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PE-CVD), and physical vapor deposition (PVD).

[0025]

[0031] Metal layer 280 may include any suitable metal. In some embodiments, metal layer 280 includes one or more of tungsten or molybdenum. In some embodiments, metal layer 280 consists essentially of tungsten. In some embodiments, metal layer 280 consists essentially of molybdenum. As used in this context, "consisting essentially of" means that metal layer 280 comprises greater than or equal to about 80, 85, 90, or 95 atomic % of the specified element. For example, metal layer 280 consisting essentially of tungsten has a composition that is, for example, greater than or equal to about 90 atomic % tungsten.

[0026]

[0032] In one embodiment, the metal layer 280 is deposited by CVD. Metal precursors and reactants may be co-flowed into a process chamber to deposit a layer on the substrate. The precursors and reactants may react in the gas phase.

[0027]

[0033] In an embodiment, the metal layer 280 is deposited by ALD. In a time-domain ALD process, a metal precursor is flowed into a processing chamber to react with the surface. The chamber is purged of excess precursor and by-products, and reactants are flowed into the chamber. The precursor and reactants are not present in the processing chamber at the same time such that there is minimal or no gas-phase reaction. In a spatial ALD process, a metal precursor is flowed into a first section of the processing chamber, and a reactant is simultaneously flowed into a second section of the processing chamber. The first and second sections are separated by a gas curtain to prevent gas-phase reaction between the precursor and reactant. The substrate is moved between the first and second sections to sequentially expose the surface to the precursor and reactant. In an embodiment, the metal layer 280 is deposited by sequentially exposing the doped amorphous silicon layer 240 to the metal precursor and reactant.

[0028]

[0034] The metal precursor may be any suitable precursor that can be used to deposit a metal film. In some embodiments, the metal precursor includes a metal selected from tungsten, molybdenum, and combinations thereof. In one or more embodiments, the metal precursor includes one or more of WF6 and MoF6. In some embodiments, the metal precursor is a fluorine-containing precursor. It is known that fluorine can etch silicon surfaces. Some embodiments of the present disclosure advantageously allow for the use of a fluorine precursor because the doped amorphous silicon layer 240 can be formed to a sufficient thickness to ensure that the precursor does not remove all of the doped amorphous silicon film.

[0029]

[0035] The reactant may be any suitable reactant capable of reacting with the species formed on the surface. For example, in an ALD process, when WF is used as a precursor, WF is formed on the surface. x The reactants are WF x The W film can be produced by reacting with the species.

[0030]

[0036] 3 illustrates a process flow for another embodiment of the present disclosure that includes a degassing process 125 after the formation of the doped amorphous silicon layer 240. In one embodiment, the doped amorphous silicon layer 240 is exposed to a degassing environment to remove outgassed species prior to forming the metal layer 280.

[0031]

[0037] The deposited doped amorphous silicon layer 240 may release or outgas species (e.g., hydrogen). The degassing environment provides an opportunity for gas species to be released to minimize bubbles in the finished film. The degassing environment may include any condition that allows or promotes degassing of the film. For example, the degassing environment may consist essentially of an inert gas. As used in this context, "consists essentially of" means that there are no gas species that would interfere with outgassing of the deposited film. While still consisting essentially of an inert gas, other reactive species may also be present without inhibiting degassing of the film.

[0032]

[0038] Suitable inert gases include, but are not limited to, one or more of argon, helium, nitrogen, and / or mixtures thereof.

[0033]

[0039] In one or more embodiments, the outgassed species include hydrogen, SiH2, SiH3, SiH4, and / or other lower silanes.

[0034]

[0040] The pressure in the process chamber or regions of the process chamber may be controlled separately for the precursor exposure and the degassing environment. In some embodiments, the exposure to each of the silicon precursor, dopant, and degassing environment is performed at a pressure in the range of about 100 mTorr to about 600 Torr. In some embodiments, the silicon precursor and / or dopant is exposed to the substrate at a pressure of about 500 mTorr or more, or about 1 Torr or more, or about 5 Torr or more, or about 10 Torr or more, or about 20 Torr or more, or about 30 Torr or more.

[0035]

[0041] The temperature at which the substrate surface is exposed to the silicon precursor, dopant, and / or degassing environment may vary depending, for example, on the thermal balance between the device being formed and the silicon precursor and / or dopant. In some embodiments, the exposure to each of the silicon precursor, dopant, and / or degassing environment occurs at a temperature in the range of about 25 degrees Celsius to about 700 degrees Celsius. In one or more embodiments, the doped amorphous silicon layer 240 is formed at a temperature in the range of about 25 degrees Celsius to about 700 degrees Celsius, or in the range of about 50 degrees Celsius to about 600 degrees Celsius, or in the range of about 100 degrees Celsius to about 550 degrees Celsius. In some embodiments, the doped amorphous silicon layer 240 is formed at a temperature of about 25 degrees Celsius or more and about 550 degrees Celsius or less, about 400 degrees Celsius or less, about 250 degrees Celsius or less, about 200 degrees Celsius or less, or about 100 degrees Celsius or less.

[0036]

[0042] The thickness of the doped amorphous silicon layer 240 formed using the silicon precursor and dopant prior to exposure to the degassing environment can be modified, in some embodiments, each exposure to the silicon precursor, dopant, and degassing environment grows a film having a thickness within a range of about 5 Å to about 20 Å, or about 20 Å to about 100 Å, or about 40 Å to 100 Å.

[0037]

[0043] The precursor, dopant, and degassing environments are repeatedly and sequentially exposed to the substrate surface to form a film having a predetermined thickness, hi one embodiment, the amorphous silicon film has a total thickness within a range of about 20 Å to about 1 μm.

[0038]

[0044] 4A and 4B, certain embodiments of the present disclosure further include step 160, in which an adhesive layer 260 is deposited on the substrate prior to forming the doped amorphous silicon layer 240. The adhesive layer 260 is a layer to which the doped amorphous silicon adheres, making peeling less likely than if the doped amorphous silicon layer were deposited directly on the substrate 220. In certain embodiments, the adhesive layer comprises TiN. In one or more embodiments, the substrate 220 has a silicon oxide surface and the adhesive layer comprises TiN.

[0039]

[0045] The thickness of adhesive layer 260 can vary depending on the substrate and the thickness of the doped amorphous silicon to be deposited. In some embodiments, adhesive layer 260 has a thickness in the range of about 1 Å to about 30 Å, or in the range of about 5 Å to about 30 Å. In some embodiments, adhesive layer 260 has a thickness of about 20 Å or less, or about 15 Å or less, or 10 Å or less, or about 5 Å or less.

[0040]

[0046] 4B, one or more embodiments of the present disclosure are directed to a stack 200 including a substrate 220 having an oxide surface 222. On the oxide surface 222 is an adhesive layer 260. The adhesive layer in one embodiment comprises TiN and has a thickness in a range of about 5 Å to about 30 Å. On top of the adhesive layer 260 is a doped amorphous silicon layer 240 and has a thickness in a range of about 5 Å to about 50 Å. On top of the doped amorphous silicon layer 240 is a metal layer 280 and includes one or more of tungsten and molybdenum.

[0041]

[0047] According to one or more embodiments, the substrate undergoes processing before and / or after forming the layer. This processing may be performed in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is transferred from the first chamber to a separate, second chamber for further processing. The substrate may be moved directly from the first chamber to another processing chamber, or from the first chamber to one or more transfer chambers and then to another processing chamber. Thus, the processing apparatus may comprise multiple chambers in communication with a transfer station. This type of apparatus may be referred to as a "cluster tool" or a "cluster system", etc.

[0042]

[0048] A cluster tool is generally a modular system with multiple chambers that perform various functions including center detection and orientation of the substrate, degassing, annealing, deposition, and / or etching. According to one or more embodiments, the cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber may house a robot that can transfer substrates back and forth between the processing chambers and the load lock chambers. The transfer chamber is typically maintained at reduced pressure and provides an intermediate stage for transferring substrates back and forth from one chamber to another chamber and / or to the load lock chamber located at the front end of the cluster tool. Two well-known cluster tools that may be adapted for the present disclosure are the Centura® and Endura®, both available from Applied Materials, Inc., Santa Clara, Calif. However, the exact arrangement and combination of chambers may be altered for the purposes of performing specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal processing such as RTP, plasma nitridation, degassing, alignment, hydroxylation, and other substrate processing. By performing processing in a chamber on a cluster tool, surface contamination of the substrate from airborne impurities can be avoided without oxidation prior to depositing a subsequent film.

[0043]

[0049] According to one or more embodiments, the substrate is continuously under reduced pressure or "load-lock" conditions and is not exposed to ambient air when it is transferred from one chamber to the next. The transfer chamber is therefore under reduced pressure and is "pumped down" under reduced pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants. According to one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent the transfer of reactants from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, a flow of inert gas forms a curtain at the outlet of the chamber.

[0044]

[0050] Referring to FIG. 5, further embodiments of the present disclosure are directed to a processing system 900 for performing the methods described herein. FIG. 5 illustrates a system 900 that may be used to process substrates according to one or more embodiments of the present disclosure. The system 900 may be referred to as a cluster tool. The system 900 includes a central transfer station 910 having a robot 912 therein. The robot 912 is shown as a single blade robot, but one of ordinary skill in the art will recognize that other robot 912 configurations are within the scope of the present disclosure. The robot 912 is configured to move one or more substrates between chambers coupled to the central transfer station 910.

[0045]

[0051] At least one pre-clean / buffer chamber 920 is coupled to the central transfer station 910. The pre-clean / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-clean / buffer chamber 920 may be used as a holding area for individual semiconductor substrates or for a cassette of wafers for processing. The pre-clean / buffer chamber 920 may perform a pre-clean process or may pre-heat the substrate for processing, or may simply be a staging area for a processing sequence. In an embodiment, there are two pre-clean / buffer chambers 920 coupled to the central transfer station 910.

[0046]

[0052] 5, a pre-clean chamber 920 may act as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robots 906 for moving substrates from a cassette to the pre-clean / buffer chamber 920. A robot 912 may then move the substrate from the pre-clean / buffer chamber 920 to other chambers in the system 900.

[0047]

[0053] A first processing chamber 930 may be coupled to the central transfer station 910. The first processing chamber 930 may be configured as a silicon layer deposition chamber and may be in fluid communication with one or more reactive gas sources to provide one or more flows of reactive gas to the first processing chamber 930. Substrates may be moved to and from the processing chamber 930 by a robot 912 through a shut-off valve 914.

[0048]

[0054] Processing chambers 940 may also be coupled to the central transfer station 910. In an embodiment, the processing chambers 940 comprise metal deposition chambers and are in fluid communication with one or more reactive gas sources to provide a flow of reactive gas to the processing chambers 940 to perform an isotropic etch process. Substrates may be moved to and from the processing chambers 940 by a robot 912 through a shut-off valve 914.

[0049]

[0055] A processing chamber 945 may also be coupled to the central transfer station 910. In some embodiments, processing chamber 945 is of the same type as processing chamber 940, configured to perform the same process as processing chamber 940. This arrangement may be useful when the process performed in processing chamber 940 takes significantly longer than the process in processing chamber 930.

[0050]

[0056] In an embodiment, a processing chamber 960 is coupled to the central transfer station 910 and configured to serve as a silicon layer deposition chamber. The processing chamber 960 may be configured to perform one or more different epitaxial growth processes.

[0051]

[0057] In one embodiment, processing chamber 930 and processing chamber 960 may be configured to perform a silicon deposition process on two substrates simultaneously, and processing chamber 940 and processing chamber 945 may be configured to perform a metal deposition process.

[0052]

[0058] In an embodiment, each of the processing chambers 930, 940, 945, and 960 is configured to perform various portions of a processing method. For example, processing chamber 930 may be configured to perform a doped silicon layer formation process, processing chamber 940 may be configured to perform a metal layer formation process, processing chamber 945 may be configured as a metrology station or to perform a silicon layer formation process, and processing chamber 960 may be configured to perform a metal layer formation process. One skilled in the art will recognize that the number and arrangement of individual processing chambers on a tool can vary, and the embodiment shown in FIG. 5 represents just one possible configuration.

[0053]

[0059] In some implementations, the processing system 900 includes one or more metrology stations. For example, a metrology station may be located in the pre-clean / buffer chamber 920, in the central transfer station 910, or within any of the individual processing chambers. The metrology station may be any location in the system 900 that is capable of measuring the recessed distance without exposing the substrate to an oxidizing environment.

[0054]

[0060] At least one controller 950 is connected to one or more of the central transfer station 910, the pre-clean / buffer chamber 920, the processing chambers 930, 940, 945, or 960. In an embodiment, there are two or more controllers 950 connected to individual chambers or stations, and a main control processor is connected to each of the individual processors to control the system 900. The controller 950 may be one of any form of general purpose computer processor, microcontroller, microprocessor, etc. that may be used in an industrial environment to control various chambers and sub-processors.

[0055]

[0061] At least one controller 950 may include a processor 952, a memory 954 coupled to the processor 952, input / output devices 956 coupled to the processor 952, and support circuits 958 for communicating between various electronic components. The memory 954 may include one or more of a transient memory (e.g., random access memory) and a non-transient memory (e.g., a storage device).

[0056]

[0062] The processor's memory 954 or computer readable medium may be one or more of readily available memory, such as random access memory (RAM), read only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. The memory 954 may hold a set of instructions executable by the processor 952 to control parameters and components of the system 900. The support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. For example, the circuits may include cache, power supplies, clock circuits, input / output circuits, subsystems, and the like.

[0057]

[0063] The process may generally be stored in memory as a software routine. When executed by a processor, the software routine causes the processing chamber to perform the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the process may be implemented in software and executed using a computer system in hardware, for example, as an application specific integrated circuit or other type of hardware implementation or a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into a special-purpose computer (controller) that controls the chamber operation to perform the process.

[0058]

[0064] In some embodiments, controller 950 has one or more configurations for executing individual processes or sub-processes to perform the method. Controller 950 may be connected or configured to operate intermediate components to perform the functions of the method. For example, controller 950 may be connected and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum controls, etc.

[0059]

[0065] The controller 950 in one embodiment has one or more configurations selected from a configuration for moving a substrate on a robot between multiple processing chambers and a metrology station, a configuration for loading and / or unloading a substrate into the system, a configuration for forming a doped amorphous silicon layer, a configuration for forming a metal layer, and a configuration for depositing an adhesive layer on a substrate.

[0060]

[0066] Substrates may be processed in a single substrate deposition chamber where a single substrate is loaded, processed, and unloaded before another substrate is processed. Substrates may also be processed in a continuous manner similar to a conveyor system where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The geometry of the chamber and associated conveyor system may form a linear or curved path. Additionally, the processing chamber may be a carousel where multiple substrates move around a central axis and undergo processing such as deposition, etching, annealing, cleaning, etc. throughout the carousel path.

[0061]

[0067] During processing, the substrate may be heated or cooled. Such heating or cooling may be accomplished by any suitable means, including but not limited to, varying the temperature of the substrate support and flowing heated or cooled gas to the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to conductively vary the substrate temperature. In one or more embodiments, the gas used (either reactive or inert) is heated or cooled to locally vary the substrate temperature. In some embodiments, a heater / cooler is positioned inside the chamber adjacent to the substrate surface to vary the substrate temperature by convection.

[0062]

[0068] The substrate can also be stationary or rotated during processing. A rotating substrate can be rotated continuously or in non-continuous steps. For example, the substrate can be rotated throughout the entire process, or the substrate can be rotated in small increments between exposures to various reactive or purge gases. Rotating the substrate (continuously or in steps) during processing can, for example, minimize the effects of local variability in gas flow profiles, helping to produce a more uniform deposition or etching.

[0063]

[0069] In an atomic layer deposition chamber, a substrate can be exposed to a first and a second precursor in a spatially or temporally separated process. Temporal ALD is a traditional process in which a first precursor flows into the chamber and reacts with the surface. Before flowing the second precursor, the first precursor is purged from the chamber. In spatial ALD, both the first and second precursors are flowed into the chamber at the same time, but are spatially separated such that there is a region between the flows that prevents the precursors from mixing. In spatial ALD, the substrate moves relative to the gas distribution plate or vice versa.

[0064]

[0070] In embodiments where one or more parts of the method are carried out in one chamber, the process may be a spatial ALD process. Although one or more of the above chemical properties may be incompatible (i.e., resulting in reaction other than on the substrate surface and / or deposition on the chamber), the spatial separation ensures that the reagents in the gas phase are not exposed to each other. For example, temporal ALD involves purging of the deposition chamber. However, in practice, it may sometimes be impossible to purge excess reagents out of the chamber before flowing in additional reagents. Thus, any remaining reagents in the chamber may react. With spatial separation, there is no need to purge excess reagents, limiting cross-contamination. Furthermore, it may take a lot of time to purge a chamber, and therefore, eliminating the purge step may increase throughput.

[0065]

[0071] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0066]

[0072] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. depositing an adhesive layer comprising TiN having a thickness within the range of 1 Å to 30 Å on the substrate surface; exposing the adhesive layer to a silicon precursor and a dopant at a temperature of 100° C. or less to form a doped amorphous silicon layer on the adhesive layer having a thickness in the range of 20 Å to 100 Å; and forming a metal layer on said doped amorphous silicon layer.

2. The method of claim 1 , wherein the silicon precursor comprises a silane, a polysilane, or a halosilane.

3. The method of claim 2 , wherein the polysilane comprises one or more of disilane, trisilane, tetrasilane, isotetrasilane, neopentasilane, cyclopentasilane, hexasilane, or cyclohexasilane.

4. The method of claim 2 , wherein the halosilane comprises one or more of a dihalosilane, a trihalosilane, a tetrahalosilane, or a hexahalodisilane.

5. 5. The method of claim 4, wherein the halogen of the halosilane comprises chlorine.

6. The method of claim 1 , wherein the doped amorphous silicon layer comprises one or more of boron, phosphorus, arsenic, or germanium.

7. The method of claim 6 , wherein the dopant comprises one or more of borane, diborane, phosphine, germane, or digermane.

8. The method of claim 6 , wherein the doped amorphous silicon layer comprises one or more of phosphorous, arsenic, or germanium.

9. The method of claim 1 , wherein the metal layer is deposited by atomic layer deposition.

10. The metal layer is formed by exposing the doped amorphous silicon layer to a metal precursor and a reactant, the metal precursor being WF 6 and MoF 6 and wherein the reactants include hydrogen.

11. The method of claim 1 , wherein the metal layer comprises one or more of tungsten and molybdenum.

12. Providing a silicon substrate having a silicon oxide surface; forming an adhesive layer comprising TiN on the silicon substrate, the adhesive layer having a thickness within a range of 1 Å to 30 Å; forming a doped amorphous silicon layer having a thickness in a range of 20 Å to 100 Å on the adhesive layer by exposing the adhesive layer to a silicon precursor comprising disilane and a dopant comprising diborane, wherein the silicon substrate is maintained at a temperature of 100° C. or less; forming a metal layer on said doped amorphous silicon layer.

13. The method of claim 12 , wherein the metal layer is formed by atomic layer deposition.

14. The method of claim 13 , wherein the metal layer comprises one or more of tungsten and molybdenum.

15. The metal layer is deposited by exposing the doped amorphous silicon layer to a metal precursor and a reactant, the metal precursor being WF 6 and MoF 6 and wherein the reactants include hydrogen.

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