In-situ drift mitigating liner for pillar cell PCM

Abstract

A method for forming an in-situ drift mitigation liner on a sidewall of a phase-change material (PCM) device stack includes providing an intermediate device having a substrate including a bottom wiring portion, a bottom electrode metal layer, a drift mitigation liner layer, an active area layer, a carbon layer, and a top electrode metal layer; patterning the top electrode metal layer to form a top electrode; performing a first medium-angle ion beam etch (IBE) to etch the carbon layer and the active area layer formed on the drift mitigation liner to form a carbon portion and an active area portion of the PCM device stack; and performing a low-angle IBE to etch the drift mitigation liner and redeposit material etched from the drift mitigation liner as a conductive liner material on a sidewall of the PCM device stack having the exposed portion of the carbon portion, the active area portion, and the top electrode.

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to a method for forming an in-situ drift mitigating liner on the sidewalls of Phase-Change Memory (PCM) devices during ion beam etching.

[0002] Phase change memory (PCM) is based on chalcogenide glass materials that change phase from crystalline to amorphous and back again when an appropriate electric current is applied. GST alloy (germanium antimony tellurium or Ge2Sb2Te5) is one such chalcogenide glass material. Each phase has a different resistance level, which is stable until the phase is changed. The maximum and minimum resistance levels in a PCM device are the basis for the binary 1 or 0 value.

[0003] During electrical programming of the PCM device, at least a portion (or possibly all) of the phase change material undergoes a phase transformation, thereby changing the electrical resistance of the PCM device.

[0004] Phase change materials, notably in the amorphous phase where the resistance rises with time according to a power law, suffer from resistance drift that needs to be mitigated for analog computing applications where multiple states are required for computation.

[0005] One way to do this is by using a conductive liner that can separate the write and read paths of the PCM cell by acting as a parallel variable resistor. For PVD-based pillar cells, this involves deposition of a conductive liner around the GST fill. However, post-RIE air exposure and oxidation of the GST is a challenge. Summary of the Invention

[0006] According to one embodiment of the present invention, a method for forming an in-situ drift mitigating liner on the sidewalls of a phase change material (PCM) device stack includes the steps of: providing an intermediate device (201) having, in sequence, a substrate including a bottom interconnect, a bottom electrode metal layer, a drift mitigating liner layer, an active area layer, a carbon layer, a top electrode metal layer, a dielectric hardmask layer, an OPL, a silicon-based anti-reflective coating layer, and a patterned resist; patterning the dielectric hardmask and the top electrode metal layer with the patterned resist to form a top electrode (202); performing a first intermediate angle ion beam etch (203); performing a low angle etch (IBE) to etch the carbon layer and the active area layer formed on the drift mitigating liner to form a carbon portion and an active area portion of the PCM device stack (203); and performing a low angle IBE to etch the drift mitigating liner and redeposit material etched from the drift mitigating liner as a conductive liner material on sidewalls of the PCM device stack having the carbon portion, the active area portion, and the exposed portion of the top electrode (204).

[0007] According to some embodiments, a phase change memory (PCM) device comprises a substrate (101) having a bottom interconnect (102), a bottom electrode (103) disposed on the bottom interconnect, a drift mitigating liner (104) disposed on the bottom electrode, an active area layer (105) disposed on the drift mitigating liner, a carbon layer (106) disposed on the active area layer, and a top electrode (107) disposed on the carbon layer, and comprises a PCM device stack (110) including a sidewall, and a conductive liner material (108) in contact with exposed portions of the carbon layer, the active area layer, and the top electrode that form a portion of the sidewall of the PCM device stack.

[0008] As used herein, "facilitating" an action includes performing an action, making an action easier, assisting in the performance of an action, or having an action performed. Thus, by way of example and not limitation, instructions executing on one processor may facilitate an action performed by instructions executing on a remote processor by sending appropriate data or commands that cause or assist in the performance of the action. For the avoidance of doubt, an action is performed by some entity or combination of entities even if an actor facilitates an action by other than performing the action.

[0009] One or more embodiments of the present invention or elements thereof may be implemented in the form of a computer program product including a computer-readable storage medium with computer usable program code for performing the illustrated method steps. Furthermore, one or more embodiments of the present invention or elements thereof may be implemented in the form of a system (or apparatus) including a memory and at least one processor coupled to the memory and operable to perform the illustrated method steps. Still further, in another aspect, one or more embodiments of the present invention or elements thereof may be implemented in the form of a means for performing one or more of the method steps described herein, which may include (i) a hardware module, (ii) a software module stored in a computer-readable storage medium (or multiple such media) and implemented in a hardware processor, or (iii) a combination of (i) and (ii), any of (i)-(iii) implementing the specific techniques described herein.

[0010] The techniques of the present invention can provide significant beneficial technical advantages. For example, one or more embodiments may: A method for forming an in-situ drift mitigation liner on a sidewall of a PCM device; A method for forming an in-situ drift mitigation liner on the sidewalls of a PCM device that avoids post-RIE atmospheric exposure; and Method for forming in-situ drift mitigation liner on sidewalls of PCM devices that avoids oxidation of GST This can be achieved.

[0011] These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings. [Brief description of the drawings]

[0012] Preferred embodiments of the invention are described in more detail below with reference to the accompanying drawings.

[0013] [Figure 1] FIG. 1 illustrates a PCM device in accordance with at least one embodiment of the present invention.

[0014] [Diagram 2] 1A-1C illustrate a method of forming an in-situ drift mitigation liner on the sidewalls of a PCM device in accordance with at least one embodiment of the present invention.

[0015] [Diagram 3] 1A-1C illustrate a method of forming an in-situ drift mitigation liner on the sidewalls of a PCM device in accordance with at least one embodiment of the present invention. [Figure 4] 1A-1C illustrate a method of forming an in-situ drift mitigation liner on the sidewalls of a PCM device in accordance with at least one embodiment of the present invention. [Diagram 5] 1A-1C illustrate a method of forming an in-situ drift mitigation liner on the sidewalls of a PCM device in accordance with at least one embodiment of the present invention. [Figure 6] 1A-1C illustrate a method of forming an in-situ drift mitigation liner on the sidewalls of a PCM device in accordance with at least one embodiment of the present invention. [Figure 7]1A-1C illustrate a method of forming an in-situ drift mitigation liner on the sidewalls of a PCM device in accordance with at least one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is directed to a method for forming an in-situ drift mitigating liner on the sidewalls of a PCM device during ion beam etching (IBE).

[0017] In accordance with at least one embodiment of the present invention, the PCM device 100 comprises a substrate 101 (interlayer dielectric (ILD)) and a bottom wiring level 102. A stack 110 disposed on the bottom wiring level 102 comprises a bottom electrode 103, a drift mitigation liner 104, a GST 105, a carbon layer 106, and a top electrode 107. A sidewall conductive liner 108 is disposed on a sidewall of the stack 110. The sidewall conductive liner 108 has a thickness of about 2-10 nanometers (nm). The stack 110 and the sidewall conductive liner 108 are encapsulated in a layer of SiN (encapsulation layer 109).

[0018] According to some embodiments, IBE is used to pattern the active area of ​​the device GST. A (usually) low angle IBE is used to encapsulate the PCM device in-situ by redepositing a portion of the drift mitigation liner from underneath the GST onto the sidewalls of the device. Optional surface treatments can then be applied to modify the microstructure or composition of this conductive liner (without oxidizing or modifying the GST / liner interface).

[0019] 2 illustrates a method 200 for forming an in-situ drift mitigating liner on the sidewall of a PCM device stack according to at least one embodiment of the present invention. According to FIG. 2, the method includes step 201 of providing an intermediate device having, in sequence, a substrate including a bottom interconnect, a bottom electrode metal layer, a drift mitigating liner layer, an active area layer, a carbon layer, a top electrode metal layer, a dielectric hard mask layer, an OPL, a silicon-based anti-reflective coating layer, and a patterned resist, and step 202 of patterning the dielectric hard mask and the top electrode metal layer with the patterned resist to form a top electrode. The method further includes step 203 of performing intermediate angle (e.g., between about 40°-60° from normal) IBE to etch the carbon layer and the GST layer formed on the drift mitigating liner. In block 204, a low angle (e.g., between about 5°-20° from normal) IBE etches the drift mitigating liner and redeposits the etched material (from the drift mitigating liner) in-situ on the sidewalls of the PCM device stack, which now includes the GST 105, the carbon layer 106, and the top electrode 107, as a conductive liner material. In block 205, a second medium angle IBE is performed to etch the remaining portions of the drift mitigating liner and the bottom electrode material to complete the PCM device stack. In block 206, an ex-situ surface treatment (e.g., plasma-based treatment and / or thermal anneal) is performed to modify the composition or microstructure of the conductive liner material abutting the sidewalls of the PCM device stack.

[0020] According to at least one embodiment, the IBE process performed in blocks 203 and 204 can include performing an etch at a voltage greater than 1. For example, the intermediate angle IBE process 203 can include performing a first etch at a first relatively high voltage followed by a second etch at a second relatively low voltage.

[0021] 3 shows a device stack 300 of layers deposited on a substrate 101 (interlayer dielectric (ILD)) and a bottom wiring level 102. The device stack 300 includes a bottom electrode metal layer 301, a drift mitigation liner layer 302, a GST layer 303, a carbon layer 304, a top electrode metal layer 305, a dielectric hard mask 306, an organic planarization layer (OPL) 307, a Silicon-Containing Anti-Reflective Coating (SiARC) layer 308, and a resist 309.

[0022] According to some embodiments, resist 309, SiARC 308, and OPL 307 are removed by reactive ion etch (RIE), which is an etch selective to these layers.

[0023] 4, a pattern transfer of resist 309 into the dielectric hard mask 306 and the top electrode metal layer 305 is performed, stopping on the carbon layer 304. Thus, the top electrode 107 is formed with a dielectric hard mask cap 401. According to some embodiments, the pattern transfer can include a halide chemistry based RIE.

[0024] 5, a mid-angle (e.g., between about 40°-60° from normal) IBE (e.g., Ar (argon), or Ar / H2 (hydrogen), or Ar / N2 (nitrogen) chemistry) removes the carbon layer 304 and the portions of the GST film 303 that are not protected by the dielectric hardmask cap 401. The remaining stack comprises the GST 303, the carbon layer 304, the top electrode 107, and the dielectric hardmask cap 401.

[0025] 6, a low angle (e.g., between about 5°-20° from vertical) IBE (e.g., Ar, or Ar / H2, or Ar / N2 chemistry) is performed to redeposit some of the material of the drift mitigation liner layer 302 onto the sidewalls to form a conductive liner 108 on the sidewalls of the stack. According to some embodiments, the low angle IBE is configured to form a conductive liner 108 having a thickness of about 2-10 nm.

[0026] According to one or more embodiments, a conductive liner 108 is disposed in contact with the GST 105, the carbon layer 106, and the top electrode 107. According to some embodiments, the conductive liner 108 may be formed from a nitride, carbide, or oxide of titanium (Ti), tungsten (W), tantalum (Ta), hafnium (Hf), vanadium (V), or ruthenium (Ru). For example, the conductive liner 108 can be formed from, for example, titanium nitride (TiN), titanium carbide (TiC), tungsten carbide (WC), tungsten nitride (WN), carbon (C), hafnium nitride (HfN), hafnium carbide (HfC), vanadium nitride (VN), vanadium carbide (VC), tantalum nitride (TaN), tantalum carbide (TaC), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), other transition or refractory metal carbides or nitrides, etc. According to some embodiments, the conductive liner 108 is made from carbon or a carbon-containing material (e.g., SiC).

[0027] As shown in FIG. 7, a second intermediate angle (between approximately 40° and 60°) IBE removes the remaining drift mitigating liner layer 302 and patterns the bottom electrode metal layer 301 to form a completed stack 110 comprising the bottom electrode 301 and the drift mitigating liner 104.

[0028] According to some embodiments, an optional surface treatment of the conductive liner 108 is performed. For example, due to damage caused by Ar-based removal of N from TiN or WN or other metal nitride films, the stoichiometry of the drift mitigation layer can be modified during the IBE redeposition process 204. Thus, a surface treatment (e.g., plasma nitridation or carbonation for metal carbides) can restore the stoichiometry of the drift mitigation layer. According to some embodiments, the surface treatment can include applying a H2-based plasma to remove oxygen from the conductive liner 108, followed by applying a N2 / NH3 plasma to incorporate nitrogen into the conductive liner 108. For example, an oxidized layer can be reduced to a metallic state using a H2-based plasma, which can then be nitridized or carbonated to adjust the stoichiometry and film properties.

[0029] According to some embodiments, one or more thermal anneals in H2, H2 / N2 ambient are performed.

[0030] According to some embodiments, the method further includes dielectric encapsulation of the stack with a film of SiN 109, resulting in the device shown in FIG.

[0031] According to some embodiments, the substrate 101 is formed from silicon nitride (SiN). According to at least one embodiment, the top and bottom electrodes 107 and 103 can be formed from, for example, TiN, W, WN, or TaN.

[0032] According to some embodiments, in blocks 203 and 204, the Ar-based gas used for IBE can be replaced with another noble gas with a heavier atomic mass, such as xenon (Xe).

[0033] [Summary]

[0034] According to some embodiments of the present invention, a method for forming an in-situ drift mitigating liner on the sidewalls of a phase change material (PCM) device stack includes the steps of: providing an intermediate device having, in sequence, a substrate including a bottom interconnect, a bottom electrode metal layer, a drift mitigating liner layer, an active area layer, a carbon layer, a top electrode metal layer, a dielectric hardmask layer, an OPL, a silicon-based anti-reflective coating layer, and a patterned resist (201); patterning the dielectric hardmask and the top electrode metal layer using the patterned resist to form a top electrode (202); 2), performing a first medium angle ion beam etch (IBE) to etch the carbon layer and the active area layer formed on the drift mitigating liner to form a carbon portion and an active area portion of the PCM device stack (203); and performing a low angle IBE to etch the drift mitigating liner and redeposit material etched from the drift mitigating liner as a conductive liner material on sidewalls of the PCM device stack having the carbon portion, the active area portion, and the exposed portion of the top electrode (204).

[0035] According to some embodiments, a phase change memory (PCM) device comprises a substrate (101) having a bottom interconnect (102), a bottom electrode (103) disposed on the bottom interconnect, a drift mitigating liner (104) disposed on the bottom electrode, an active area layer (105) disposed on the drift mitigating liner, a carbon layer (106) disposed on the active area layer, and a top electrode (107) disposed on the carbon layer, and comprises a PCM device stack (110) including a sidewall, and a conductive liner material (108) in contact with exposed portions of the carbon layer, the active area layer, and the top electrode that form a portion of the sidewall of the PCM device stack.

[0036] References in the specification to "one embodiment" or "one embodiment" of the present principles, as well as other variations thereof, mean that the particular features, structures, characteristics, and the like described in connection with the embodiment are included in at least one embodiment of the present principles. Thus, appearances of the phrases "in one embodiment" or "in an embodiment," as well as any other variations thereof, in various places throughout the specification are not necessarily all referring to the same embodiment.

[0037] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may be performed in a different order than that noted in the drawings. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or such blocks may possibly be executed in reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that executes the specified functions or operations, or executes a combination of dedicated hardware and computer instructions.

[0038] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprise" and / or "comprising", as used herein, specify the presence of stated features, integers, steps, operations, elements, or components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups or combinations thereof.

[0039] In the following claims, the corresponding structure, material, acts, and equivalents of any means-plus-function or step-plus-function elements are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed. The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations that do not depart from the scope and spirit of the described embodiments will be apparent to those skilled in the art. The terminology used in this specification has been selected to best explain the principles of the embodiments, practical applications or technical improvements to the technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for forming an in-situ drift mitigation liner on a sidewall of a phase change material (PCM) device stack, comprising: providing an intermediate device having, in sequence, a substrate including a bottom interconnect, a bottom electrode metal layer, a drift mitigating liner layer, an active area layer, a carbon layer, a top electrode metal layer, a dielectric hardmask layer, an OPL, a silicon-based anti-reflective coating layer, and a patterned resist; patterning the dielectric hard mask layer and the top electrode metal layer using the patterned resist to form a top electrode; performing a first medium angle ion beam etch (IBE) to etch the carbon layer and the active area layer formed on the drift mitigating liner layer to form a carbon portion and an active area portion of the PCM device stack; and performing low angle IBE to etch the drift mitigating liner layer and redepositing material etched from the drift mitigating liner layer in-situ as a conductive liner material on sidewalls of the PCM device stack including the carbon portion, the active area portion, and the exposed portion of the top electrode. A method for providing the above.

2. 10. The method of claim 1, further comprising performing a second medium angle IBE to etch remaining portions of the drift mitigating liner layer and bottom electrode metal layer to form a drift mitigation portion and a bottom electrode of the PCM device stack, the bottom electrode overlying and in electrical contact with the bottom wiring portion of the substrate.

3. The method of claim 1 or 2, further comprising performing a surface treatment on the conductive liner material on a sidewall of the PCM device stack.

4. The method of claim 3 , wherein the surface treatment is a plasma-based treatment.

5. The method of claim 3 , wherein the surface treatment is a thermal anneal.

6. The method of claim 3 , wherein the surface treatment removes oxygen from the conductive liner material.

7. The method of claim 3 , wherein the surface treatment incorporates nitrogen into the conductive liner material.

8. The method of claim 2 further comprising encapsulating the PCM device stack.

9. The method of claim 8 , wherein the PCM device stack is encapsulated in a silicon nitride film.

10. 10. The method of claim 1, wherein the PCM device stack is not exposed to air prior to depositing the conductive liner material on the sidewalls of the PCM device stack.

11. 11. The method of claim 1, wherein the active area portion of the PCM device stack is not exposed to air prior to depositing the conductive liner material on sidewalls of the PCM device stack.

12. 1. A phase change memory (PCM) device comprising: A substrate having a bottom interconnect; a bottom electrode disposed on the bottom interconnect; a drift mitigation liner disposed on the bottom electrode; an active area layer disposed on the drift mitigation liner; a carbon layer disposed on the active area layer; and An upper electrode disposed on the carbon layer a PCM device stack having a sidewall; and a conductive liner material in contact with the carbon layer, the active area layer, and an exposed portion of the top electrode that forms a portion of the sidewall of the PCM device stack; Equipped with the conductive liner material comprises a portion of the drift mitigation liner material; the conductive liner material contacts the carbon layer, the active area layer, and the top electrode. PCM device.

13. The PCM device of claim 12 further comprising a film encapsulating the PCM device laminate.

14. The PCM device of claim 13 , wherein the film is disposed on an exposed portion of the substrate.

15. The PCM device of any one of claims 12 to 14, wherein the conductive liner material has a thickness of between about 2 to 10 nanometers.

16. 16. The PCM device of claim 12, wherein the conductive liner material is not formed on sidewalls of the bottom electrode and the drift mitigation liner.

Images