Test and measurement system and method for analyzing a device under test

Abstract

To design a new device under test in a shorter period of time.SOLUTION: A server 212 accepts, from a plurality of test measurement devices 202 on a network 204, data such as results of electrical margin tests of a device under test (DUT) 222 and information about components of a test system 224, and constructs a database in a storage device thereof. When a user tests a new DUT 222, the server 212 accepts the test result thereof, compares the same with data of a similar DUT 222 in the past, for analyzing, and answers a soundness score of the new DUT 222.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The disclosed technology relates to systems and methods related to test and measurement systems, and more particularly to test and measurement systems that can effectively analyze new devices under test (DUTs) based on data associated with previous tests performed on the test and measurement system. [Background technology]

[0002] Designers and manufacturers of electrical and electronic devices require test and measurement equipment and appropriate test procedures to ensure that their electrical and electronic devices function properly. Such testing is performed during the engineering characterization stage of designing a new device, for example, to compare the actual electrical performance of the device with simulated performance to ensure that the device is operating as designed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0250368 [Patent Document 2] US Patent Application Publication No. 2020 / 0249275 [Patent Document 3] International Publication No. 2020 / 160477 [Non-patent literature]

[0004] [Non-Patent Document 1] "BERTScope BSA Series" introduction site, Tektronix, [online], [searched June 22, 2021], Internet<https: / / jp.tek.com / bit-error-rate-tester / bertscope> [Non-Patent Document 2] "Plugtest" article (English version), [Online], [Retrieved June 27, 2021], Internet<https: / / en.wikipedia.org / wiki / Plugtest> [Non-Patent Document 3] "Semiconductor intellectual property core" article (English version), "Vendors" section mentions "Silicon Intellectual Property (SIP, Silicon IP)", [online], [retrieved June 27, 2021], Internet<https: / / en.wikipedia.org / wiki / Semiconductor_intellectual_property_core> Summary of the Invention [Problem to be solved by the invention]

[0005] Users often test the actual electrical performance of the device by connecting it to a Bit Error Rate Tester (BERT) or Vector Network Analyzer (VNA) to test whether it meets certain standards (compliance). However, setting up such tests can be very expensive and require a significant amount of manual effort. If the new device does not pass the compliance test, the device needs to be redesigned and the test repeated. The real device may not pass the test even though the simulated performance passes the test, and users need to spend time debugging the newly designed device to find out why the real device tests differently from the simulation.

[0006] The presently disclosed technology addresses these and other deficiencies of the prior art. [Means for solving the problem]

[0007] In the following, examples useful for understanding the technology disclosed in the present application are presented. The embodiment of the technology may include one or more of the examples described below and any combination thereof.

[0008] Example 1 is a test and measurement system comprising a memory configured to store a database of test results relating to tests previously performed on one or more devices under test, an input unit configured to receive new test results relating to a new device under test, a data analysis unit configured to analyze the new test results based on the stored test results, and a health score generation unit configured to generate a health score for the new device under test based on the analysis from the data analysis unit.

[0009] A second embodiment is the test and measurement system of the first embodiment, wherein the new test results include test results from a test and measurement instrument for the new device under test.

[0010] A third embodiment is the test and measurement system of the second embodiment, in which the test and measurement device is a margin tester.

[0011] Example 4 is the test and measurement system of any of examples 1 to 3, wherein the new test results include information of the individual end user's test system.

[0012] Example 5 is the test and measurement system of any of Examples 1 to 4, wherein the new test results include simulation data.

[0013] Example 6 is the test and measurement system of any of Examples 1 to 5, wherein the health score generator is further configured to generate a result of the compliance test.

[0014] Example 7 is the test and measurement system of any of Examples 1 to 6, wherein the stored test results include data of at least one past revision of the device under test.

[0015] Example 8 is the test and measurement system of Example 7, wherein the data analysis unit is further configured to determine improvement suggestions for the new device under test based on the analysis, and the health score generation unit is further configured to output the improvement suggestions together with the health score.

[0016] Example 9 is a method for analyzing a new device under test, comprising steps of storing test results associated with tests previously performed on one or more devices under test, receiving new test results for the new device under test, analyzing the new test results based on the stored test results, and generating a health score for the new device under test based on the analysis.

[0017] Example 10 is the method of example 9, wherein the new test results include test results from a test and measurement instrument on the new device under test.

[0018] Example 11 is the method of example 10, wherein the test and measurement device is a margin tester.

[0019] Example 12 is the method of any of examples 9-11, wherein the new test results include information about an individual end user's test system.

[0020] Example 13 is the method of any of Examples 9 to 12, wherein the new test results include simulation data.

[0021] Example 14 is the method of any of examples 9 to 13, further comprising generating a compliance test result based on the analysis.

[0022] Example 15 is the method of claim 9, wherein the stored test results include revision data of at least one previous device under test.

[0023] Example 16 is the method of example 15, further comprising: determining improvement suggestions for the new device under test based on the analysis; and outputting the improvement suggestions together with the health score.

[0024] Example 17 is a computer program including instructions that, when executed by one or more processors of a test and measurement system, cause the test and measurement system to receive new test results for a new device under test, analyze the new test results based on stored past test results for one or more devices under test, and generate a health score for the new device under test based on the analysis.

[0025] Example 18 is the computer program of example 17, wherein the new test results include test results from a test and measurement instrument for the new device under test.

[0026] Example 19 is the computer program of Example 18, in which the test and measurement device in the test and measurement system is a margin tester.

[0027] Example 20 is the computer program of any of Examples 17 to 19, wherein the new test results include simulation data.

[0028] Aspects, features and advantages of embodiments of the present invention will become apparent from the following description of the embodiments, taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0029] [Figure 1] FIG. 1 is a block diagram of a margin tester in accordance with an example of the disclosed technique. [Diagram 2] FIG. 2 is a block diagram of a test and measurement system in accordance with an example of the disclosed technique. [Diagram 3] FIG. 3 is a flow chart for analyzing a device under test according to an example of the disclosed technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] A margin tester (or margin test measurement system) is a test and measurement instrument that can perform electrical margin testing of high-speed electrical signals on a device under test (DUT). A margin tester can establish a single lane or multiple lanes of high-speed I / O links for the DUT and evaluate the electrical margin of each lane of the single or multiple lanes of the high-speed I / O links in either or both the transmit or receive directions.

[0031] Applicant's US Pat. Nos. 5,993,333 and 5,343,633 disclose systems and methods for performing electrical margin testing of high speed electrical signals in a DUT. The contents of US Pat. Nos. 5,993,333 and 5,343,633 are incorporated herein by reference. Such margin testers may be particularly useful for testing DUTs that employ multi-lane communication protocols such as PCI Express.

[0032] 1 is a block diagram illustrating a margin tester 100 having multiple interfaces 102 in accordance with an example of the disclosed technique. The multiple interfaces 102 are configured to be connected to at least one test fixture, for example, via one or more cables. The margin tester 100 evaluates the electrical margin of a multi-lane high speed I / O link of a DUT in one or both of the transmit and receive directions.

[0033] Margin tester 100 includes a controller 104 and associated memory 106. Memory 106 may store instructions and other data that may be read, used or executed by controller 104 to perform the functions described herein. Margin tester 100 includes a number of lanes that may be connected to standard test fixtures, cables or adapters via interface 102 under the control of controller 104 to perform margin testing. Margin tester 100 includes a transmitter and receiver (not shown) connected to interface 102.

[0034] The controller 104 may be configured to evaluate the electrical margin of a single-lane or multi-lane high-speed input / output (I / O) link after performing some processing to reduce the opening of the eye width of the eye pattern, such as injecting jitter into a signal to be transmitted, in the transmitter of the margin tester 100. In this case, the jitter injection may be performed simultaneously for all lanes of the single-lane or multi-lane high-speed input / output (I / O) link, or may be performed independently for each of the lanes, or may be selectively performed. The controller 104 may be configured to evaluate the electrical margin of a single-lane or multi-lane high-speed input / output (I / O) link after performing some processing to reduce the opening of the eye height of the eye pattern, such as injecting noise into a signal to be transmitted, in the transmitter of the margin tester 100. In this case, the noise injection may be performed simultaneously for all lanes of the single-lane or multi-lane high-speed input / output (I / O) link, or may be performed independently for each of the lanes, or may be selectively performed.

[0035] The margin tester 100 can support multiple protocols, and the configuration of the margin tester's 100 controller 104 includes options to configure different protocol lanes and host / device roles. The margin tester 100 can also be used to test add-in cards by cabling it to a test fixture, such as a standard PCI Express Compliance Base Board (CBB) for testing add-in cards.

[0036] During electrical margin evaluation, the controller 104 can compare the measured electrical margin of the DUT to the expected electrical margin. A certain margin must be exceeded for the DUT to be considered minimally compliant. However, the margin that must be exceeded varies depending on the effects of the margin tester and any adapters or accessories (cables, connectors, etc.) installed between the margin tester and the DUT.

[0037] The controller 104 may also be coupled to a memory 106, which may store instructions and other data that the controller 104 may read, use, or execute to perform the functions described herein. For example, the memory 106 may store an identifier 108 for the margin tester 100. The identifier 108 may be any unique identifier, such as, but not limited to, a serial number for the margin tester 100. The memory 106 may also store an expected margin for the DUT.

[0038] The interface 102 of the margin tester 100 may include standard coaxial connectors and cables for each high-speed differential signal, or in various other embodiments, may include specially designed (customized) high-density connectors and fixtures to minimize the number of cables and to more efficiently switch from one DUT to another. To connect the margin tester 100 to the DUT, for example, a high-density connector adapter may be used to connect to a specific mechanical form factor (typically a motherboard standard, or more broadly, physical specifications and standards such as the shape and dimensions of the case or components, and the arrangement of terminals) of the DUT. An example of a specific mechanical form factor is a specific type of PCI Express motherboard slot. That is, the adapter may have one end that is used to connect to the interface 102 of the margin tester 100 and the other end that is used to connect to a specific type of PCI Express motherboard slot. The high-density adapter may be any adapter with eight or more connection points.

[0039] Although the margin tester 100 illustrated in FIG. 1 is used to illustrate various examples of the disclosed techniques, one skilled in the art will appreciate that examples of the disclosed techniques are not limited to margin tester 100 and may be applied to any test and measurement instrument, such as, but not limited to, an oscilloscope, a bit error rate tester, or a vector network analyzer.

[0040] 2 illustrates a block diagram of an example test and measurement system 200 in accordance with an example of the disclosed technique. In the example test and measurement system 200 of FIG. 2, one or more test and measurement instruments 202 can be connected through a network 204 by communication links 206 and 208, respectively. The communication links 206 and 208 may be connected to the test and measurement instruments 202 through a port 210. The communication links 206 and 208 may be wired or wireless connections.

[0041] The test and measurement instruments 202 can be connected to a server 212. The server 212 can be a proprietary server owned by the entity that owns the test and measurement instruments 202, or can be a cloud server to which the entity has an account or is otherwise authorized to access. The server 212 can have memory (mass storage) that stores a database or can have access to a memory that has a database of stored data. The server 212 can be connected to other test and measurement instruments 202 through the network 204 by communication lines 214. The server 212 can have a data analyzer, which can be implemented with any known processor or any combination of hardware and software, that analyzes newly received data based on the data stored in the database in the memory of the server 212. The server 212 can also have a health score generator, which can be implemented with any known processor or any combination of hardware and software, as described in more detail below. The analysis results and health score information from the server 212 may be sent to each test and measurement device 202 via the network 204 and displayed to the user on the display thereof.

[0042] In addition to the processor 216 and memory 218, the test and measurement instrument 202 may include other hardware components such as a display, an analog-to-digital converter, etc. The test and measurement instrument 202 may include a user interface 220 for receiving commands, selections, or other inputs from a user. As shown, the test and measurement instrument 202 may be connected to a device under test (DUT) 222. The test and measurement instrument 202, the device under test (DUT) 222, and the connectors, cables, and other accessories (fixtures, etc., as necessary) that connect them together constitute an individual end user's test system 224. Although the test system 224 can be connected to the network 204 to allow a user to test the DUT 222 even if it is not connected to the network 204, the test system 224 can be connected to the network 204 to obtain significant benefits of the present invention. 2 shows only two test and measurement instruments 202 (or individual test systems 224), this is merely an example, and a large number of test and measurement instruments 202 distributed around the world may be present on network 204. As a result, server 212 may receive data from a large number of test and measurement instruments 202 and form a database containing big data consisting of a huge amount of data.

[0043] The database accessible to the server 212 contains test results from hundreds, thousands, or even millions of different combinations of semiconductor products (including those without hardware, such as intellectual property cores (IP cores)), motherboards, and add-in cards available from many different vendors, and various test and measurement equipment, such as margin testers 100, bit error rate testers, oscilloscopes, and vector network analyzers, available from many different vendors. The test results may include simulated or predicted data, such as those disclosed in U.S. Provisional Patent Application No. 63 / 081,265, filed September 21, 2020 (which is incorporated herein by reference). In some examples, the database may be opt-in or open source, such that when tests are performed on DUTs 222 by test and measurement equipment 202, the test results as well as individual end user test system 224 information relevant to the tests, such as the type of DUT 222, the specific test and measurement equipment 202 information, and information about accessories (connectors, cables, etc.) used, may be sent to server 212 and stored in a memory (mass storage) database. The memory database may also include, among other things, design revision data for the DUTs tested and a timeline of changes made in each revision of the design.

[0044] 3 shows a flow chart according to an example of the disclosed technique. In step 300, information about the DUT as well as information about the individual test system 224 may be sought or collected. For example, such test system 224 information may include the type and identification of the test and measurement equipment 202, accessories used (cables, connectors, etc.), information related to the DUT 222 (e.g., product information, IP cores (semiconductor circuit information) used, motherboard, add-in cards used in the DUT 222, etc.), etc.

[0045] Such information can be collected in a number of ways, including by user input via the user interface 220, or based on a photographic image of the DUT 222. Additionally or alternatively, information can be collected using electrical signals from the DUT 222.

[0046] At step 302, tests may be performed on the DUT 222 to obtain test results. The test results and the individual test system 224 information at step 300 may be sent to the server 212 for analysis. The test results and the test system 224 information may be sent over the network 204 or directly to the server 212 via a wired or wireless connection. In some examples, the test results may not be from the test and measurement equipment 202 but may be the result of a simulation program. In such cases, the test system 224 information includes only information related to the simulation.

[0047] In step 304, the server 212 may analyze the test system 224 information from step 300 and the test results from step 302. In step 306, the server 212 may then generate a health score based on the analysis from step 304. The analysis of the data from step 304 may include determining how the test system 224 information and test results relate to data stored in the memory database. For example, the server 212 may identify similar product families built using a certain IP core (silicon IP) and compare the test results of these product families to data of semiconductor products using the IP core. The analysis from step 304 may also include selecting a specific test item of the DUT, such as eye height and eye width of an eye pattern. The server 212 may identify similar semiconductor products or similar product families from the accessed memory database and generate a trend plot of the results of these products for the same specific test item based on a specific time period.

[0048] A health score can be generated, for example, by comparing a particular test item to a compliance test specification. A health score can be generated based on how closely the particular test item meets the compliance test specification. For example, a particular compliance test specification may require an eye height or eye width to meet a particular height or width. If the particular test item does not meet the compliance test specification, a low health score is generated, and if the particular test item exceeds the compliance test specification, a high health score is generated. A trend plot of the DUT and similar semiconductor products or product families along with the health score can be displayed to the user, allowing the user to evaluate the design of the DUT in comparison to other similar products. That is, the health score can indicate whether the DUT fell short of, met, or exceeded the compliance test specification.

[0049] The health score may include a confidence score for the health of the DUT, pass / fail data for specific parameters associated with the DUT, and compliance test results. Additionally or alternatively, the analysis may include determining whether changes made to similar product families stored in the database have resulted in improved confidence, pass / fail, or compliance scores. Once revision data has been stored in the memory database for similar product types, the server 212 may suggest design changes or other troubleshooting tips for the DUT 222. For example, the server 212 may determine that a particular accessory, such as a cable, is worn out and needs to be replaced, and may alert the user to replace the cable and rerun the test. Additionally or alternatively, the server 212 may determine that changing a particular component on the board (e.g., a resistor to a different size) would improve the score for the DUT 222, and may output that information to the test and measurement instrument 202.

[0050] For example, a designer may select certain semiconductor products or IP cores to design a new video card. The designer may test an early version of the new video card using the margin tester 100 described above. Electrical margin data collected during testing may be sent to the server 212.

[0051] The server 212 can identify data in the memory database for similar video cards built based on a given (or similar) IP core or semiconductor product (e.g., IC chip) and analyze the designer's data based on the existing data. The data for the similar video card may include timing data, electrical data, two-dimensional eye data, etc. The server 212 can output a health score for the health of the design based on both the test results of the new video card and the test results of another similar video card built based on the similar IP core. For example, the server 212 can compare the design of the new video card to those of known video cards in the memory database to determine (i.e., determine) what differences exist and what the test results are. Based on this data, the server 212 can determine whether the current video card is performing as well or better than other video cards stored in the memory database. Based on this information, the server 212 can generate a confidence score for the health of the designed board. The server 212 can also output pass / fail data for particular parameters, as well as the results of various compliance tests.

[0052] Additionally or alternatively, server 212 can call up and classify similar video card design revisions that improved the scores and results of these similar video cards. Based on these design revisions, server 212 can recommend design changes to the designer. For example, if server 212 discovers that in the past, a video card designed by another designer had issues with lane 4, but a solution was discovered that fixed the issue, server 212 can recognize that the current video card may have the same issue, so server 212 may output (e.g., display) the following: "Design failed to pass PCIe gen 4 compliance on the transmit side due to lane 4. We recommend adding another resistor family to the line."

[0053] By combining time series data from testing multiple revisions of a protoboard on the test and measurement equipment 202 and user input data on actions / benefits taken during each revision, a neural network in the server 212 is trained (machine learning, see below) to classify different board layouts of each protoboard into different risk levels. This can then be fed back to a physical simulation tool, allowing designers to predict defects at an early design stage. This further allows the newly simulated design to be compared to existing optional reference data in a database in memory.

[0054] For example, a simulated design may be sent to server 212, which can search a memory database for designs of similar type and may be able to provide information regarding the health of the design without performing any testing on the DUT. The combination of correlated data, human input, and life cycle data in a memory database accessed by server 212 may dramatically increase the value of the simulation data beyond the current single-use model.

[0055] Examples of the disclosed technology also provide a universal compliance tool that could be adopted by those with a specific need for faster and cheaper compliance testing (e.g., special interest groups that write specifications). Currently, DUTs are taken to a plug fest (also called a plug test, see Non-Patent Document 2), power-on, or other compliance event to get a stamp of compliance.

[0056] However, the in-memory database accessed by server 212 can be a multi-vendor database. By collecting electrical margin information (data) from actual testing of multiple boards and multiple accessories (connectors, cables, etc.) in a wide variety of combinations, server 212 may be able to function as a virtual compliance checker. To build a virtual compliance checker using an example of the disclosed technology, a memory database is first built from test results from a margin tester 100 or the like that follows current guidelines. Once there is enough data in the memory database, a majority of the variables of DUT 222 can be captured, and the test results of DUT 222 can be referenced to the data in the database to provide a stamp of compliance.

[0057] Additionally, as new generations of device protocols are developed, examples of the disclosed technology can be used to assist special interest groups (SIGs) in developing specifications by highlighting common problem areas related to device design.

[0058] Specifically for margin testing, many companies that manufacture semiconductor products provide on-die electrical margin checkers in the package with their semiconductor products, which are then given to designers in downstream companies who deploy the semiconductor products in various ways, such as motherboards, graphic cards, etc., along with standard test documentation.

[0059] Designers often test the electrical integrity of their own products using IP cores (silicon IP), and the results can be significantly different from the results provided by the silicon IP provider. It is not uncommon for the silicon IP provider to say that a semiconductor product using the IP core should pass with a healthy electrical margin, while the board designer says that the product has failed and cannot be used. This discrepancy can cause problems between silicon IP providers and designers.

[0060] Both silicon IP providers (including semiconductor manufacturers) and designers can upload their design information and test-related information, such as test methods and test results, to a database in memory that is accessed by the server 212. The server 212 can review information from both silicon IP providers and designers, and can also access other information in the database. By analyzing this data, the server 212 can identify design issues with either the silicon IP (IP core, semiconductor circuit information) or the designed board, and in some instances can provide information about which changes made by the designer are causing the problem and information about possible fixes. For example, in high-speed serial data analysis, eye diagrams (eye patterns) may be used to quickly check the integrity of a signal, and most standards define ranges for eye diagrams in terms of eye height and eye width. The channel loss of the DUT board can affect the eye height. Thus, if the server 212 notices or determines that there is a problem with the eye height, the server 212 can determine that there is a design problem with the channel loss of the DUT board. Alternatively, the server 212 may provide information regarding problems that exist in the IP core or semiconductor circuit information and what changes can be made to fix the problems.

[0061] In some examples, the server 212 may have a machine learning capability that utilizes neural networks, allowing the server 212 to design new layouts based on machine learning through computational processing. As described above, the server 212 may also use big data based on data from a large number of test and measurement instruments 202 to perform the necessary training for machine learning. Success definitions such as power requirements, size, etc. can be uploaded to the server 212, and the server 212 can use this information to organically design new board layouts for the user when troubleshooting issues with the DUT 222.

[0062] In step 304 above, the individual test system 224 information may include component manufacturing information. The server 212 can then compare data across all vendors and identify faulty components or batches of components. The server 212 can then output (e.g., display) a warning or recommendation to the designer to replace the component or components that are causing problems in other DUTs 222.

[0063] Additionally or alternatively, in some examples, the server 212 may determine whether certain portions of the DUT 222 are over-engineered. For example, the server 212 may discover that certain portions of the DUT 222 have never failed, and thus may flag those portions of the DUT 222 as potentially over-engineered. The server 212 may provide (e.g., display) this information in step 306 and provide (e.g., display on a display) suggestions for alternative parts that are cheaper, smaller, use less power, etc. In some examples, using the example above, the server 212 may simulate a redesigned board before providing suggestions. The results of the simulation may also be included in providing the suggestions. In the above description, it is assumed that the server 212 exists separately and independently from the test and measurement instrument 202, but this is merely an example, and the test and measurement instrument 202 itself may function as the server 212.

[0064] Examples of the disclosed technology can reduce the amount of time and manual effort required to design a new product. Examples of the disclosed technology can provide previously unavailable information about a device under test by analyzing the device under test with reference to data from tests performed on previous devices under test. This can help guide a designer to designs that have worked well for other designers who have worked on similar products in the past, thereby reducing the amount of rework or redesign of the device under test by the designer.

[0065] Aspects of the disclosed technology can operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The term "controller" or "processor" in this application contemplates microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology can be implemented in computer-available data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, and the like, which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data formats. The computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, and the like. As will be appreciated by those skilled in the art, the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more effectively implement one or more aspects of the disclosed techniques, and such data structures are considered to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0066] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media that may be read and executed by one or more processors. Such instructions may be referred to as computer program products. A computer-readable medium as described herein means any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.

[0067] Computer storage media means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and transitory forms of signal transmission.

[0068] A communication medium refers to any medium capable of communicating computer readable information. By way of example, and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for communicating electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0069] The above-described versions of the disclosed subject matter have many advantages that have been described or that will be apparent to those of skill in the art. Nevertheless, not all of these advantages or features are required in every version of a disclosed device, system or method.

[0070] In addition, the description of this application refers to specific features. All features disclosed in the specification, claims, abstract and drawings, and all steps in any method or process disclosed, may be combined in any combination, unless they are at least partially exclusive of one another. Each feature disclosed in the specification, claims, abstract and drawings may be replaced by an alternative feature serving the same, equivalent or similar purpose, unless otherwise specified.

[0071] Furthermore, when the application refers to a method having two or more defined steps or processes, those defined steps or processes may be performed in any order or simultaneously, unless the context precludes such a possibility.

[0072] For convenience of illustration, specific embodiments of the invention have been illustrated and described, but it will be understood that various modifications can be made therein without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited, except as by the appended claims. [Explanation of symbols]

[0073] 100 Margin Tester 102 Interface 104 Controller 106 Memory 108 Identifier 200 Test and Measurement Systems 202 Test and measurement equipment 204 Network 206 Communication Links 208 Communication Links 210 Port 212 Server 214 Communication Line 216 processors 218 Memory 220 User Interface 222 Device Under Test (DUT) 224 Individual Test Systems

Claims

1. a memory configured to store a database of test results relating to tests previously performed on one or more devices under test; an input configured to receive new test results relating to a new device under test; a data analysis unit configured to analyze the new test results based on the stored test results; a health score generator configured to generate a health score for the new device under test based on the analysis by the data analyzer; A test and measurement system comprising:

2. 2. The test and measurement system of claim 1, wherein the new test results include test system information or simulation data.

3. 3. The test and measurement system of claim 1 or 2, wherein the health score generator is further configured to generate a result of a compliance test.

4. 4. The test and measurement system of claim 1, wherein the stored test results include revision data for at least one previous device under test.

5. the data analysis unit is further configured to determine improvement suggestions for the new device under test based on the analysis; 5. The test and measurement system of claim 1, wherein the health score generator is further configured to output the improvement suggestions together with the health score.

6. storing test results relating to tests previously performed on one or more devices under test; receiving new test results for the new device under test; analyzing the new test results based on the stored test results; generating a health score for said new device under test based on the analysis; A method for analyzing a new device under test comprising:

7. 7. The method of analyzing a new device under test of claim 6, wherein the new test results include test system information or simulation data.

8. 8. The method of analyzing a new device under test according to claim 6 or 7, further comprising generating a compliance test result based on the analysis.

9. 9. A method for analysing a new device under test according to any of claims 6 to 8, wherein the stored test results include revision data of at least one previous device under test.

10. determining improvement suggestions for the new device under test based on the analysis; A process of outputting the improvement proposal together with the health score; 10. The method of analyzing a new device under test of claim 9, further comprising:

11. The process of storing test results relating to the tests previously performed on one or more of the devices under test includes storing information about a past test system used to test the devices under test; receiving the new test results for the new device under test includes receiving, along with the new test results, information about a new test system used to test the new device under test; 7. The method of analyzing a new device under test of claim 6, wherein the process of generating a health score for the new device under test based on the analysis includes a process of identifying a test system similar to the new test system from among stored information of the past test systems, and a process of generating the health score based on a comparison of test results of the similar test system with the new test results.

12. A computer program comprising instructions which, when executed by one or more processors of a test and measurement system, cause the test and measurement system to carry out a method according to any one of claims 6 to 11.

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