Bidirectional Redriver for Half-Duplex Interfaces

Abstract

The circuit (102) includes a first port (152) coupled to a first device (108), a second port (154) coupled to a second device (110), a first channel (137) having an input (138) coupled to the first port and an output (142) coupled to the second port, redriving a signal and outputting the redriven signal, a second channel (143) having an input (144) coupled to the second port and an output (148) coupled to the first port, redriving a signal and outputting the redriven signal, and a controller (150). The controller is configured to enable the first channel and disable the second channel in response to detecting a signal edge at the first port, enable the second channel and disable the first channel in response to detecting a signal edge at the second port, sample an impedance at the first port when a signal received at the first port is deasserted while the first channel is enabled, and sample an impedance at the second port when a signal received at the second port is deasserted while the second channel is enabled.

Description

Summary of the Invention

[0001] In some examples, a redriver circuit includes a first port configured to couple to a first device by a first bus and a second port configured to couple to a second device by a second bus, and includes a first communication channel having an input coupled to the first port and an output coupled to the second port and configured to redrive an input signal and output a redriven input signal, a second communication channel having an input coupled to the second port and an output coupled to the first port and configured to redrive the input signal and output a redriven input signal, and a controller. The controller is configured to enable the first communication channel and disable the second communication channel in response to detecting a first signal edge at the first port, enable the second communication channel and disable the first communication channel in response to detecting a first signal edge at the second port, sample an impedance at the first port in response to an input signal received at the first port being deasserted while the first communication channel is enabled, and sample an impedance at the second port in response to an input signal received at the second port being deasserted while the second communication channel is enabled.

[0002] In another example, a redriver circuit includes a first port configured to couple to a first device by a first clock bus, a second port configured to couple to a second device by a second clock bus, a third port configured to couple to the first device by a first data bus, a fourth port configured to couple to the second device by a second data bus, a first communication channel configured to redrive an input clock signal received from the first port as an output clock signal to the second port, a second communication channel configured to redrive an input clock signal received from the second port as an output clock signal to the first port, a third communication channel configured to redrive an input data signal received from the third port as an output data signal to the fourth port, a fourth communication channel configured to redrive an input data signal received from the fourth port as an output data signal to the third port, and a controller.The controller enables a first communication channel and disables a second communication channel in response to detecting a start of a clock signal edge at the first port, enables the second communication channel and disables the first communication channel in response to detecting a start of a clock signal edge at the second port, enables a third communication channel and disables a fourth communication channel in response to detecting a start of a data signal edge at the third port, enables the fourth communication channel and disables the third communication channel in response to detecting a start of a data signal edge at the fourth port, and controls an input clock received at the first port while the first communication channel is enabled. the first port in response to the clock signal being deasserted, the second port in response to the input clock signal received at the second port being deasserted while the second communication channel is enabled, the third port in response to the input data signal received at the third port being deasserted while the third communication channel is enabled, and the fourth port in response to the input data signal received at the fourth port being deasserted while the fourth communication channel is enabled.

[0003] In yet another example, a method includes detecting a first signal edge at a first port configured to couple to a first device by a first bus or detecting a first signal edge at a second port configured to couple to a second device by a second bus. The method also includes, in response to detecting the first signal edge at the first port, enabling a first communication channel configured to redrive an input signal received from the first port as an output signal to the second port and disabling a second communication channel configured to redrive an input signal received from the second port as an output signal to the first port. The method also includes, in response to detecting the first signal edge at the second port, enabling the second communication channel and disabling the first communication channel. The method also includes sampling an impedance at the first port in response to an input signal received at the first port being deasserted while the first communication channel is enabled, and sampling an impedance at the second port in response to an input signal received at the second port being deasserted while the second communication channel is enabled. [Brief description of the drawings]

[0004] Reference will now be made to the accompanying drawings for a detailed description of various examples.

[0005] [Figure 1] 1 illustrates a block diagram of a system in accordance with various examples.

[0006] [Diagram 2] 1A-1C show schematic diagrams of redriver circuits in various examples.

[0007] [Diagram 3] 3 illustrates a state diagram for the redriver circuit of FIG. 2 in various examples.

[0008] [Figure 4] 3A-3C show timing diagrams illustrating the operation of the redriver circuit of FIG. 2 in various examples.

[0009] [Diagram 5] 3 illustrates another state diagram for the redriver circuit of FIG. 2 in accordance with various examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Communication interfaces are prevalent in modern electronic devices. Some communication interfaces are unidirectional (e.g., data flows in only one direction), while other communication interfaces are bidirectional (e.g., data flows in both directions). Half-duplex communication systems use bidirectional communication interfaces. In half-duplex communication systems, devices can communicate with each other, but not simultaneously. For example, communication occurs in only one direction at a time.

[0011] Computers and other electronic devices commonly use serial communication interfaces to provide for the transfer of data between connected devices. The Universal Serial Bus (USB) interface is one of various serial buses used to interface electronic devices. The System Power Management Interface (SPMI) is another serial bus used to interface electronic devices. SMPI is a bidirectional, two-wire serial bus interface for controlling, for example, the voltage supplied to the processor and the power management of auxiliary components coupled to the processor. Other serial interfaces are within the scope of this disclosure. Regardless of the particular type of interface, electronic devices that communicate using such interfaces include, for example, computers, smartphones, video game consoles, and other computing devices. Peripheral devices also communicate using such interfaces and include, for example, flash drives, printers, keyboards, smartphones, cameras, tablets, and a variety of other devices.

[0012] Regardless of the particular type of device that communicates using the bidirectional, half-duplex serial communication interface, in some examples, the input / output (I / O) voltage levels vary by device type. For example, as process technology gets smaller for processors (e.g., systems on chips (SoCs)), the I / O voltage limits for the processors also decrease. As an example, a processor using a 5 nm process technology may have an I / O voltage limit of about 1.2 V, while a processor using a 3 nm process technology may have an I / O voltage limit of about 1.0 V. Also, in some examples, the processor interfaces with a higher voltage interface, such as SPMI (e.g., 1.8 V I / O voltage limit) or USB (e.g., 3.3 V I / O voltage limit). For a device in a first voltage domain (e.g., a processor with an I / O voltage limit of about 1.2V) to communicate with a device in a second voltage domain (e.g., an SPMI device with an I / O voltage limit of 1.8V), level shifting is used to shift the voltage level of the signal from one voltage domain to the other. Also, the communication signal benefits from being redriven or received and retransmitted by a redriver circuit. For example, redriving the signal by a redriver circuit between devices increases the tolerance between the devices while isolating the two sides of the communication bus, which prevents the bus capacitance from one side of the redriver circuit from loading the bus on the other side of the redriver circuit. In some examples, a dedicated hub or bridge device accomplishes such level shifting and redriving of the signal, but a dedicated hub is space consuming and costly to implement. For example, a dedicated hub or bridge device may actively participate in the bus arbitration process and emulate both a slave-facing master device and a master-facing slave device. Active participation in bus arbitration and such master / slave emulation involves more complex de-packetization and re-packetization of the payload, which increases overall device complexity.

[0013] Some examples include a redriver circuit between the two voltage domains that functions to level-shift signal voltages to facilitate communication between devices in different voltage domains and / or to redrive these communication signals between the devices. In particular, the redriver circuit facilitates half-duplex communication, and in some examples, the level shifting occurs in both directions regardless of the direction of the communication traffic. Preferably, the redriver circuit is configured to detect a first signal edge (e.g., a rising edge of a signal carried by a clock and / or data bus) from a device in one of the voltage domains that indicates the start of a signal transmission. However, the redriver circuit may use other techniques to indicate the start of a signal transmission. When a first signal edge is detected from a first one of the two voltage domains (e.g., on a first bus coupled to a first port of the redriver circuit), the redriver circuit is configured to enable a first communication channel from the first voltage domain to a second one of the two voltage domains. When a first signal edge is detected from the second voltage domain (e.g., on a second bus coupled to a second port of the redriver circuit), the redriver circuit is configured to enable a second communication channel from the second voltage domain to the first voltage domain. As described further below, the communication channel facilitates level-shifting the signal voltage and / or redriving the signal from one voltage domain to the other. For example, in some cases, the I / O voltage limits for each voltage domain are approximately the same, and thus the redriver circuit functions to drive signals (e.g., clock and / or data signals) between the voltage domains, but does not necessarily level-shift the signals between the voltage domains.

[0014] The redriver circuit is also configured to sample the impedance of a bus coupled to a device that is providing a communication signal to the redriver circuit (e.g., the communication signal that the redriver circuit level-shifts and / or redrives to a device in the other voltage domain). The redriver circuit samples the impedance of the bus to determine whether the device is still providing the communication signal or whether the device has ceased providing the communication signal. If so, the bus coupled to the device is in a high impedance state. In one example, the redriver circuit samples the impedance of the bus by injecting a current into the bus (e.g., by controlling a current source) and monitoring the voltage on the bus in response to the injected current - e.g., when a clock and / or data signal on the bus transitions to a low state. In some examples, a pull-down resistor is coupled to the bus. If the bus is still driven, the injected current has a relatively small effect on the voltage of the bus. However, when the bus is not driven (e.g., in a high impedance state), the injected current has a greater effect on the bus voltage due to the pull-down resistor, which the redriver circuit detects (e.g., using a comparator). The pull-down resistor value and the amount of current injected are selected so that the pull-down resistor voltage is detected when the bus is in a high impedance state, but such voltage is not high enough to be interpreted as a high or asserted signal on the bus. When a high impedance state is detected on a bus, the communication channel that was level-shifting and / or redriving signals from that bus is disabled, and the redriver circuit again monitors for the first signal edge, as described above. In this manner, the redriver circuit monitors both sides of the bus and detects the direction of the communication signal in order to level-shift and / or redrive the communication signal in the direction of data transmission.

[0015] 1 illustrates a block diagram of a system 100 in some examples. The system 100 illustrates a redriver circuit 102, a first voltage domain 104, and a second voltage domain 106. Each voltage domain 104, 106 includes one or more devices 108, 110, respectively, that communicate with devices in the other voltage domain. Thus, the redriver circuit 102 couples to one or more devices 108 in the first voltage domain 104 by a first bus 107a and to one or more devices 110 in the second voltage domain 106 by a second bus 107b, facilitating communication between the devices 108, 110 in the first and second voltage domains 104, 106. Although the buses 107a, 107b are referred to separately, in some examples, the buses 107a, 107b are parts of the same bus, such as a clock bus or a data bus, that couples the devices 108 in the first voltage domain 104 to the devices 110 in the second voltage domain 106. In other examples, the redriver circuit 102 is coupled to the devices 108, 110 in each voltage domain 104, 106 by two or more buses. In the particular example of an SPMI interface using a two-wire bus (e.g., a clock signal bus and a data signal bus), the redriver circuit 102 is coupled to the devices 108, 110 in each voltage domain 104, 106 by two buses. As described above, the redriver circuit 102 allows for bidirectional communication while facilitating half-duplex communication by detecting the start of a signal transmission from the first voltage domain 104 or the second voltage domain 106 (preferably by detecting a first signal edge of an input signal).

[0016] As discussed above, in some examples, the devices 108 in the first voltage domain 104 operate at a first I / O voltage level, while the devices 110 in the second voltage domain 106 operate at a second I / O voltage level that is different from the first I / O voltage level. In these examples, the redriver circuit 102 both level-shifts and redrives the signal originating from the voltage domain 104, 106 in which the first signal edge was first detected. In other examples, the devices 108, 110 in the first and second voltage domains 104, 106 operate near the same I / O voltage level, and therefore the redriver circuit 102 redrives the signal from the voltage domain 104, 106 in which the first signal edge was first detected, but does not necessarily level-shift the signal between the voltage domains 104, 106. In some examples, even in the absence of a voltage shift, redriving the signal allows it to drive a larger capacitive load than if the redriver circuit 102 were not present between the devices 108, 110.

[0017] As will be described in more detail below, the redriver circuit 102 is also configured to sample the impedance of the buses 107a, 107b coupled to the devices providing the communication signals to the redriver circuit 102. The redriver circuit 102 samples the impedance of the buses 107a, 107b to determine whether the devices 108, 110 are still providing the communication signals or whether the devices 108, 110 have ceased providing the communication signals. If so, the buses 107a, 107b coupled to the devices 108, 110 are in a high impedance state (e.g., an idle state). When a high impedance state is detected on the buses 107a, 107b, the redriver circuit 102 disables the communication channels that were level shifting and / or redriving signals from the buses 107a, 107b, and the redriver circuit 102 again monitors for a first signal edge as described above. In this manner, the redriver circuitry monitors both sides of the buses 107a, 107b and detects the direction of the communication signals in order to level shift and / or redrive the communication signals in the direction of data transmission.

[0018] FIG. 2 illustrates the system 100 described above with respect to FIG. 1, including a schematic diagram of the redriver circuit 102 in further detail. In the example of FIG. 2, the redriver circuit 102 is shown as being used in an exemplary SPMI interface and coupled to multiple devices 108a-108n in a first voltage domain 104 and multiple devices 110a-110n in a second voltage domain 106. In other examples, there is only a single device 108 in the first voltage domain 104 and / or a single device 110 in the second voltage domain 106. In some examples, the devices 108, 110 are configured to function as either a master or a slave to implement a communication protocol between the devices 108, 110. Also in the example of FIG. 2, the redriver circuit 102 is coupled to the devices 108a-108n by a first clock bus 112 and a first data bus 114 (e.g., of a two-wire SPMI interface). Similarly, the redriver circuit 102 is coupled to the devices 110a-110n by a second clock bus 116 and a second data bus 118. Pull-down resistors 120, 122, 124, and 126 are coupled to the buses 112, 114, 116, and 118, respectively. The pull-down resistors 120, 122, 124, and 126 are also coupled to ground nodes.

[0019] The redriver circuit 102 includes a controller 150 configured to perform various functions described herein. In some examples, the controller 150 is an integrated circuit or a processing device. The scope of the present disclosure is not limited by the particular form of the controller 150. The functionality of the controller 150 is described more fully below.

[0020] The redriver circuit 102 includes a first port 152 configured to couple to the first clock bus 112, a second port 154 configured to couple to the second clock bus 116, a third port 156 configured to couple to the first data bus 114, and a fourth port 158 ​​configured to couple to the second data bus 118. Through the ports 152, 154, 156, 158, the redriver circuit 102 may send and receive communication signals to and from the various devices 108, 110 in the first and second voltage domains 104, 106, respectively. A controller 150 is coupled to each of the ports 152, 154, 156, 158, and to various other elements of the redriver circuit 102, as will be described further below.

[0021] The redriver circuit 102 includes a first communication channel 137 that includes a receiver 138, a delay element 140, and a driver 142. The first communication channel 137 is configured to redrive an input signal received from a first port 152 as an output signal to a second port 154. In the particular example of FIG. 2, the input signal to and the output signal from the first communication channel 137 are clock signals. Also, in some examples, the first communication channel 137 redrives the input clock signal received from the first port 152 to a first I / O voltage limit (V IOA ) from a first voltage domain 104 having a second I / O voltage limit (V IOB ) to a second voltage domain 106 having a first input voltage

[0022] The redriver circuit 102 includes a second communication channel 143 that includes a receiver 144, a delay element 146, and a driver 148. The second communication channel 143 is configured to redrive an input signal received from a second port 154 as an output signal to the first port 152. In the particular example of FIG. 2, the input signal to the second communication channel 143 and the output signal from the second communication channel 143 are clock signals. Also, in some examples, the second communication channel 143 redrives the input clock signal received from the second port 154 to a second voltage domain 106 (V IOB ) to the first voltage domain 104 (V IOA )

[0023] The redriver circuit 102 also includes a third communication channel 167 (including a receiver 168, a delay element 170, and a driver 172) and a fourth communication channel 173 (including a receiver 174, a delay element 176, and a driver 178), which are similar in function to the first and second communication channels 137, 143 described above, except that they are coupled to the third port 156 and the fourth port 158 ​​rather than the first port 152 and the second port 154. In the particular example of FIG. 2, the input signals to and output signals from the third and fourth communication channels 167, 173 are data signals. Also, in some examples, the third communication channel 167 couples an input data signal received from the third port 156 to the first voltage domain 104 (V IOA ) to a second voltage domain 106 (V IOB ) to the second voltage domain 106 (V IOB ) to the first voltage domain 104 (V IOA ) for level shifting.

[0024] Each of the receivers 138, 144, 168, 174 functions in a similar manner. In particular, the receiver 138 is configured to receive an input signal from a first port 152. Similarly, the receiver 144 is configured to receive an input signal from a second port 154, the receiver 168 is configured to receive an input signal from a third port 156, and the receiver 174 is configured to receive an input signal from a fourth port 158. The receivers 138, 144, 168, 174 generate signals based on the received input signals and provide the generated signals to the respective delay elements 140, 146, 170, 176. In one example, the receivers 138, 144, 168, 174 are comparators that meet certain threshold levels defined by the SPMI standard.

[0025] The delay elements 140, 146, 170, 176 introduce delays into each of the communication channels 137, 143, 167, 173 to ensure that the control path (e.g., functions performed by the controller 150) is faster than the data path (e.g., via the communication channels 137, 143, 167, 173) so that the controller 150 can enable the appropriate one of the communication channels 137, 143, 167, 173 while avoiding loss of signal data between the devices 108, 110 in the voltage domains 104, 106. The purpose of introducing delays is explained in more detail below. Each delay element 140, 146, 170, 176 provides its delayed signal to a respective driver 142, 148, 172, 178. In one example, the delay elements 140, 146, 170, 176 are inverter chains and may be programmable by adjusting the number of inverter stages and the RC loads of the inverter stages.

[0026] Drivers 142, 148, 172, 178 each drive an output signal to their associated port 154, 152, 158, 156, respectively, and in some cases perform level shifting on the signal received from its respective delay element 140, 146, 170, 176. For example, drivers 142, 172 level shift the signal from delay element 140, 170 from the first voltage domain 104 to the second voltage domain 106. Similarly, drivers 148, 178 level shift the signal from delay element 146, 176 from the second voltage domain 106 to the first voltage domain 104. In some examples, an enable signal may be provided to one or more of drivers 142 (ENCLKB), 148 (ENCLKA), 172 (ENDATB), 178 (ENDATA). When an enable signal is provided, the enable signal enables the corresponding driver 142, 148, 172, 178 (and therefore the respective communication channel 137, 143, 167, 173). In this manner, each of the communication channels 137, 143, 167, 173 is configured to redrive signals from one voltage domain 104, 106 to the other, and to level shift these signals from the first voltage domain 104 to the second voltage domain 106 or vice versa, facilitating bidirectional communication between the devices 108, 110. Also, as described in more detail below, only one of the first communication channel 137 and the second communication channel 143 is enabled at a time. Similarly, only one of the third communication channel 167 and the fourth communication channel 173 is enabled at a time. In this manner, the redriver circuit 102 also facilitates half-duplex communication between the devices 108, 110.

[0027] The controller 150 is configured to receive several signals from other portions of the redriver circuit 102 and, based at least in part on these received signals, to control various aspects of the redriver circuit 102. For example, the controller receives an indication of whether a signal received at one of the ports 152, 154, 156, 158 is asserted (e.g., from one comparator coupled to the port, described further below), an indication of whether a signal received at one of the ports 152, 154, 156, 158 is deasserted (e.g., from another comparator coupled to the port, described further below), and / or an indication of whether a bus 112, 116, 114, 118 coupled to one of the ports 152, 154, 156, 158 is in a high impedance state (e.g., from one of the comparators 134, 136, 164, 166, described further below). Based on the signals received by the controller 150, the controller 150 is configured to enable or disable the various communication channels 137, 143, 167, 173, and to control the various current sources 130, 132, 160, 162, which are also described further below.

[0028] The controller 150 of the redriver circuit 102 is configured to detect a first signal edge indicating the start of a signal transmission on the buses 112, 114, 116, 118. Although not shown for simplicity, in one example, a comparator is coupled to each of the ports 152, 154, 156, 158. These comparators are configured to compare the voltage at the ports 152, 154, 156, 158 to a reference voltage. In one example, the reference voltage is set above a level that indicates a signal is asserted for the particular voltage domain 104, 106. For example, the reference voltage is a value that is slightly less (e.g., within 10 percent) than the I / O voltage limit for the voltage domain 104, 106 to which the ports 152, 154, 156, 158 are configured to couple.

[0029] For example, comparators coupled to the first or third ports 152, 156 compare their voltages to a reference voltage (VBIASA) that is slightly less than the I / O voltage limit for the first voltage domain 104 such that an output of the comparator coupled to the first or third port 152, 156 is asserted when the received signal voltage indicates an asserted signal for the first voltage domain 104 (e.g., which corresponds to a rising edge). In a particular example where one voltage domain 104 corresponds to an SPMI interface having an I / O voltage limit of 1.8V, the comparator compares the voltage of the signal received at the port 152, 156 to a reference voltage of approximately 1.62V (e.g., 10 percent less than 1.8V). Similarly, comparators coupled to the second or fourth ports 154, 158 compare their voltages to a reference voltage (VBIASB) that is slightly less than the I / O voltage limit for the second voltage domain 106 such that the output of the comparator coupled to the second or fourth port 154, 158 is asserted when the received signal voltage indicates an asserted signal for the second voltage domain 106 (e.g., which corresponds to a rising edge). In an example where the other voltage domain 106 corresponds to a processor / SoC interface having an I / O voltage limit of 1.2V, the comparator compares the voltage of the signal received at the port 154, 158 to a reference voltage of approximately 1.08V (e.g., 10 percent less than 1.2V). In some examples, the clock and data signals may be asserted at different voltages and therefore their reference voltages may be different as well. However, for simplicity of explanation, it will be assumed that both the clock and data signals from one of the voltage domains 104, 106 are asserted at approximately the same voltage.

[0030] The controller 150 of the redriver circuit 102 is also configured to detect when the signals received from the buses 112, 114, 116, 118 are deasserted. Again, not shown for simplicity, in one example, additional comparators are coupled to each of the ports 152, 154, 156, 158. These comparators are configured to compare the voltages at the ports 152, 154, 156, 158 to a reference voltage that is set below a level that indicates the signal is deasserted. For example, the reference voltage is a value that is slightly (e.g., 0.1V) higher than the ground node voltage. The outputs of these comparators are asserted when the received signal voltage indicates a deasserted signal, while the outputs of these comparators are deasserted when the received signal voltage indicates an asserted signal.

[0031] In addition to detecting asserted (or rising edges) and deasserted (or falling edges) signals at the ports 152, 154, 156, 158, the controller 150 is also configured to sample impedances at the various ports 152, 154, 156, 158. In particular, as described in more detail below, the controller 150 is configured to sample impedances at the various ports 152, 154, 156, 158 in response to a signal at one of the ports 152, 154, 156, 158 being deasserted while the corresponding channel of that port is enabled. For example, when the first communication channel 137 is enabled, the controller 150 is configured to sample impedances at the first port 152 in response to detecting that an input signal (e.g., a clock signal) to the first port 152 is deasserted. The controller 150 functions similarly for the other ports 154, 156, 158 and their corresponding communication channels 143, 167, 173, respectively.

[0032] The controller 150 is configured to sample the impedance at the first port 152, as described above, to detect, for example, a high impedance state of the first clock bus 112 coupled to the first port 152. This high impedance state indicates that the device 108 coupled to the first clock bus 112 is no longer driving the first clock bus 112. In one example, a current source 130 is coupled to the first port 152. The controller 150 is configured to control the current source 130, for example, to inject a current into the first port 152. Also, in another example, the amount of current injected is controllable by the controller 150. A comparator 134 includes a non-inverting terminal coupled to the first port 152 and an inverting terminal coupled to a reference voltage source (whose value is given by VBIASA).

[0033] For example, when device 108 coupled to first clock bus 112 is driving first clock bus 112, the impedance seen at first port 152 is the impedance of the driver of device 108 and is relatively low (e.g., about 50 ohms). However, when device 108 is not driving first clock bus 112, the driver of device 108 is in a high impedance state and therefore the impedance seen at first port 152 is approximately the resistance of pull-down resistor 120 and may have a minimum value of, for example, about 125 k ohms. Therefore, if controller 150 causes current source 130 to inject current (e.g., about 2 uA) into first port 152 when device 108 is driving first clock bus 112, the voltage dropped across pull-down resistor 120 is relatively small (e.g., below VBIASA) because the impedance of the driver of device 108 is lower than the impedance of pull-down resistor 120. As a result, the comparator 134 output is not asserted. However, if the controller 150 causes the current source 130 to inject current into the first port 152 when the device 108 is not driving the first clock bus 112, the voltage dropped across the pull-down resistor will be larger (e.g., greater than VBIASA) because the driver of the device 108 itself is now in a high-impedance state. As a result, the output of the comparator 134 is asserted, indicating that the first clock bus 112 is in a high-impedance state (e.g., idle state). The particular values ​​of the resistance of the pull-down resistor 120, the current injected by the current source 130, and the voltage VBIASA are exemplary and may be different from those described above, so long as they still achieve the functionality described for detecting a high-impedance bus state.

[0034] Also, in one example, the controller 150 is configured to control the value of VBIASA. As mentioned above, the pull-down resistor 120 is coupled to the first clock bus 112 and to a ground node. Thus, when the first clock bus 112 is not being driven by the device 108 (e.g., in a high impedance state) and a current is injected by the current source 130 into the first port 152, a voltage is dropped across the pull-down resistor 120. However, when the first clock bus 112 is being driven by the device 108, the injection of current into the first port 152 has relatively no effect on the voltage of the first clock bus 112. As mentioned above, the value of the pull-down resistor 120 and the amount of current injected by the current source 130 are selected such that the voltage of the pull-down resistor 120 is detected when the first clock bus 112 is in a high impedance state, but such voltage is not high enough to be interpreted as a high signal or an asserted signal on the first clock bus 112. In one example, controller 150 sets the value of VBIASA such that the voltage across resistor 120 in response to current injection by current source 130 when first clock bus 112 is in a high impedance state causes comparator 134 to assert its output. However, the value of VBIASA is also set such that a voltage increase on first clock bus 112 in response to current injection by current source 130 when first clock bus 112 is driven by device 108 does not cause comparator 134 to assert its output. Current sources 132, 160, 162 and comparators 136, 164, 166 function for ports 154, 156, 158 in the same manner as current source 130 and comparator 134 described above with respect to first port 152.

[0035] The functionality of the controller 150 and the redriver circuit 102 is generally described further with respect to Figures 3-5. In one example, as described above, the redriver circuit 102 is used in an SPMI interface, where the buses 112, 116 and the buses 114, 118 comprise the two-wire buses of the SPMI interface. Figure 3 shows a state diagram 300 illustrating the functionality of the controller 150 and the redriver circuit 102 with respect to facilitating level shifting and / or redriving of a clock signal (e.g., on the buses 112, 116) between the device 108 in the first voltage domain 104 and the device 110 in the second voltage domain 106. In one example, the device 108, 110 that is the master provides the clock signal used to communicate to and from the corresponding slave device. For example, when a device 108, 110 provides a clock signal to the redriver circuit 102 (detected as the first signal edge by the redriver circuit 102), that device 108, 110 is assumed to be the master until the driven clock bus 112, 116 transitions to a high impedance state. Thus, the redriver circuit 102 continues to drive the first detected clock signal from one voltage domain 104, 106 to the other until the driven clock bus 112, 116 transitions to a high impedance state. Figure 4 shows a timing diagram 400 corresponding to this functionality. Timing diagram 400 includes waveforms representing signals on first clock bus 112 (SCLKA) and second clock bus 116 (SCLKB), control signals for current injected by current source 130 (ICC_ENCLKA) and current injected by current source 132 (ICC_ENCLKB), and an enable signal for first communication channel 137 (ENCLKB, which enables driver 142 of first communication channel 137) and an enable signal for second communication channel 143 (ENCLKA, which enables driver 148 of second communication channel 143).

[0036] Initially, upon a power-on or reset event of the devices including the voltage domains 104, 106 and the redriver circuit 102, for example as shown in portion 402 of Figure 4, the state diagram 300 begins in state 302. In state 302, both of the clock buses 112, 116 are in a high impedance state (e.g., not driven by either device 108, 110). Because the devices 108, 110 are not driving the clock buses 112, 116, neither the first communication channel 137 nor the second communication channel 143 of the redriver circuit 102 are enabled, and therefore the controller 150 does not assert ENCLKA or ENCLKB. Also, in state 302, it has been determined that both clock buses 112, 116 are in a high impedance state (e.g., due to a power-on or reset event), and therefore the controller 150 does not cause current sources 130 or 132 to inject current, and therefore ICC_ENCLKA and ICC_ENCLKB are also deasserted.

[0037] Thereafter, during time domain 408, controller 150 detects a first signal edge on clock bus 112, therefore state diagram 300 continues to state 304. For purposes of illustration, it is assumed that a first signal edge is first detected on first clock bus 112 when SCLKA goes high or is asserted before SCLKB, therefore state diagram 300 continues to state 306. In state 306, controller 150 enables first communication channel 137 by asserting ENCLKB (also in time domain 408), which enables driver 142 of first communication channel 137. When enabled, driver 142 level shifts and / or redrives the clock signal received from first clock bus 112 onto second clock bus 116. This is illustrated in portion 402 of FIG. 4 as redrive signal. The second communication channel 143 remains disabled (e.g., ENCLKA is deasserted). As discussed above, the delay element 140 in the first communication channel 137 provides the controller 150 with enough time to assert ENCLKB before the signal from the first port 152 that causes a state change (e.g., a first signal edge) reaches the driver 142. This is reflected in the timing diagram 400, where SCLKB is delayed from SCLKA.

[0038] State diagram 300 then proceeds to state 308. In state 308, the first clock bus 112 (SCLKA) is monitored by controller 150 to detect if SCLKA has been deasserted. As mentioned above, in one example, controller 150 monitors a comparator output that is asserted when the signal on first clock bus 112 goes low or is deasserted. As long as SCLKA is high or remains asserted, state diagram 300 remains in states 306 and 308. However, when SCLKA goes low or is deasserted, state diagram 300 continues to state 310.

[0039] In state 310, the controller 150 samples the impedance at the first port 152 coupled to the first clock bus 112, as described above. In particular, the controller 150 asserts ICC_ENCLKA to cause the current source 130 to inject current into the first port 152. This is reflected in the timing diagram 400, where ICC_ENCLKA is asserted (e.g., as two pulses 410, 412) while SCLKA is deasserted. The state diagram 300 continues in state 312, where the controller 150 determines whether the first clock bus 112 is in a high impedance state, for example, by monitoring the output of the comparator 134, as described above. For example, when the first clock bus 112 is being driven by the device 108, the injection of current into the first port 152 does not raise the voltage of the first clock bus 112 above the reference voltage VBIASA for the comparator 134. This is reflected in the timing diagram 400, where the first assertion of ICC_ENCLKA does not raise the voltage of SCLKA above VBIASA because the device 108 is driving SCLKA low. If, in state 312, the controller 150 determines that the first clock bus 112 is not in a high impedance state (e.g., the controller 150 determines that HIZCLKA is not a high value), the state diagram 300 returns to state 308 and then returns to one of the states 306, 310 described above depending on whether SCLKA is low or deasserted.

[0040] However, when the first clock bus 112 is not being driven by the device 108, the injection of current into the first port 152 causes a voltage (reflected at 406) greater than the reference voltage VBIASA for the comparator 134 to drop across the pull-down resistor 120, which causes the output of the comparator 134 to assert. Therefore, the controller 150 determines that the first clock bus 112 is in a high-impedance state in response to the output of the comparator 134 being asserted. This is reflected in the timing diagram 400, where a second assertion 412 of ICC_ENCLKA (after SCLKA transitions to a high-impedance state, shown by the dashed line) results in the voltage of SCLKA exceeding VBIASA at 406. If, in state 312, the controller 150 determines that the first clock bus 112 is in a high impedance state, the state diagram 300 returns to state 302, where the controller 150 disables the first communication channel 137 and waits to receive a first signal edge from the devices 108, 110 in the first or second voltage domains 104, 106, respectively.

[0041] Referring back to state 304, in another example, the controller 150 detects a first signal edge from the second clock bus 116 when SCLKB goes high or is asserted before SCLKA. This is reflected during time domain 413 of portion 404 of timing diagram 400. In this case, state diagram 300 continues to state 314. States 314, 316, 318, and 320 are generally similar to states 306, 308, 310, 312 described above, but the direction of communication proceeds in the opposite direction. For example, in state 314, the controller 150 enables the second communication channel 143 by asserting ENCLKA (also during time domain 413), which enables the driver 148 of the second communication channel 143. When enabled, the driver 148 level shifts and / or redrives the clock signal received from the second clock bus 116 onto the first clock bus 112. Example portion 404 of timing diagram 400 illustrates a level shift of a clock signal from a higher voltage level to a lower voltage level. The first communication channel 137 remains disabled (e.g., ENCLKB is deasserted). As discussed above, the delay element 146 in the second communication channel 143 provides the controller 150 with sufficient time to assert ENCLKA before a signal from the second port 154 causing a state change (e.g., a first signal edge) reaches the driver 148. This is reflected in portion 404 of timing diagram 400, where SCLKA is delayed from SCLKB.

[0042] The state diagram 300 then proceeds to state 316. In state 316, the second clock bus 116 (SCLKB) is monitored by the controller 150 to detect if SCLKB has been deasserted. As mentioned above, in one example, the controller 150 monitors a comparator output that is asserted when the signal on the second clock bus 116 goes low or is deasserted. As long as SCLKB is high or remains asserted, the state diagram 300 remains in states 314 and 316. However, when SCLKB goes low or is deasserted, the state diagram 300 continues to state 318.

[0043] In state 318, the controller 150 samples the impedance at the second port 154 coupled to the second clock bus 116, as described above. In particular, the controller 150 asserts ICC_ENCLKB to cause the current source 132 to inject current into the second port 154. This is reflected in the timing diagram 400, where ICC_ENCLKB is asserted (e.g., as two pulses 414, 416) while SCLKB is deasserted. The state diagram 300 continues in state 320, where the controller 150 determines whether the second clock bus 116 is in a high impedance state, for example, by monitoring the output of the comparator 136, as described above. For example, when the second clock bus 116 is being driven by the device 110, the injection of current into the second port 154 does not raise the voltage of the second clock bus 116 above the reference voltage VBIASB for the comparator 136. This is reflected at 418 in the timing diagram 400, where the assertion 414 of ICC_ENCLKB does not raise the voltage of SCLKB above VBIASB because the device 110 is driving SCLKB low. If, in state 320, the controller 150 determines that the second clock bus 116 is not in a high impedance state, the state diagram 300 returns to state 316 and then returns to one of the states 314, 318 described above depending on whether SCLKB is low or deasserted.

[0044] However, when the second clock bus 116 is not being driven by the device 110, the injection of current into the second port 154 causes a voltage greater than the reference voltage VBIASB for the comparator 136 to drop across the pull-down resistor 124, which causes the output of the comparator 136 to assert. Therefore, the controller 150 determines that the second clock bus 116 is in a high impedance state in response to the output of the comparator 136 being asserted. This is reflected at point 420 of the timing diagram 400. If, in state 320, the controller 150 determines that the second clock bus 116 is in a high impedance state, the state diagram 300 returns to state 302, where the controller 150 disables the second communication channel 143 and waits to receive a first signal edge from the device 108, 110 in the first or second voltage domain 104, 106, respectively.

[0045] As described above, the redriver circuit 102 detects the direction of a received communication signal by monitoring both sides of a clock bus (e.g., first clock bus 112 and second clock bus 116) and detecting a first signal edge arriving from devices 108, 110 in the first or second voltage domains 104, 106, respectively. The redriver circuit 102 level shifts and / or redrives the communication signal in the direction of data transmission. At the same time, the redriver circuit 102 prevents data transmission in the opposite direction by enabling only one of the first communication channel 137 and second communication channel 143 at a time, allowing bidirectional half-duplex communication between the devices 108, 110 in the first and second voltage domains 104, 106, respectively.

[0046] 5 shows a state diagram 500 illustrating the functionality of the controller 150 and the redriver circuit 102 with respect to facilitating level shifting and / or redriving of data signals (e.g., on the data buses 114, 118) between the devices 108 in the first voltage domain 104 and the devices 110 in the second voltage domain 106. In one example, the master device 108, 110 provides a clock signal (as described above) along with the data signals, which are used for communication to and from the corresponding slave devices. However, unlike a clock signal always provided by the master, in a bidirectional communication interface, the master also expects to receive data from one or more slaves. Also, while the redriver circuit 102 itself does not perform bus arbitration functions, the redriver circuit 102 is configured to enable the devices 108, 110 to perform such bus arbitration while still facilitating bidirectional half-duplex communication between the devices 108, 110 in the different voltage domains 104, 106.

[0047] 3, upon a power-on or reset event of the devices including the voltage domains 104, 106 and the redriver circuit 102, the state diagram 500 begins at state 502. In state 502, both data buses 114, 118 are in a high impedance state (e.g., not driven by either device 108, 110). Since the devices 108, 110 are not driving the data buses 114, 118, and therefore neither the third communication channel 167 nor the fourth communication channel 173 of the redriver circuit 102 are enabled, the controller 150 does not assert ENDATA or ENDATB. Also, in state 502, it has been determined that both data buses 114, 118 are in a high impedance state (e.g., due to a power-on or reset event), and therefore the controller 150 does not cause the current sources 160 or 162 to inject current, and therefore ICC_ENDATA and ICC_ENDATB are also deasserted.

[0048] The controller 150 then detects a first signal edge on one of the data buses 114, 118, and therefore the state diagram 500 continues to state 504. For purposes of illustration, it is assumed that the first signal edge is first detected on the first data bus 114 when SDATA goes high or is asserted before SDATB, and therefore the state diagram 500 continues to state 506. In state 506, the controller 150 enables the third communication channel 167 by asserting ENDATB, which enables the driver 172 of the third communication channel 167. When enabled, the driver 172 level shifts and / or redrives the data signal received from the first data bus 114 onto the second data bus 118. The fourth communication channel 173 remains disabled (e.g., EDATA is deasserted). As described above, the delay element 170 in the third communication channel 167 provides the controller 150 with sufficient time to assert ENDATB before the signal from the third port 156 that causes a state change (e.g., a first signal edge) reaches the driver 172. The effect of the delay element 170 is similar to that shown in FIG.

[0049] The state diagram 500 then proceeds to state 508. In state 508, the controller 150 determines whether a bus arbitration entry condition has occurred. As mentioned above, the redriver circuit 102 does not itself perform bus arbitration functions, but is configured to enable the devices 108, 110 to perform such bus arbitration. In an example in which the redriver circuit 102 is used in an SPMI interface, a bus arbitration entry condition occurs when a data signal (e.g., received from the first data bus 114) remains asserted while a clock signal (e.g., received from the first clock bus 112) increases for at least the bus turnaround time (T BT ) is indicated by remaining deasserted for T BTThe value of q is determined by the SPMI standard. The occurrence of this bus arbitration start condition indicates to the controller 150 that bus arbitration is occurring between the devices 108, 110, and therefore, the state diagram 500 proceeds to block 510.

[0050] The controller 150 may be configured to facilitate various bus arbitration schemes, such as those defined in one or more standards for the interface through which the redriver circuit 102 facilitates communication. In one example, the bus arbitration scheme occurring in state 510 continues for a predetermined duration (e.g., a number of clock cycles). Thus, in state 510, the controller 150 facilitates the bus arbitration scheme (e.g., by enabling and disabling the third and fourth communication channels 167, 173 depending on the scheme) and when the predetermined duration has elapsed, bus arbitration is complete and the state diagram proceeds to state 502 described above.

[0051] If, at state 508, the controller 150 determines that a bus arbitration entry condition has not occurred, the state diagram 500 continues to block 512. For example, if SDATA is deasserted, if SCLKA is asserted, or if SCLKA is at 0.5 V, then the state diagram 500 continues to block 512. BTIf it is deasserted for a shorter period of time, no bus arbitration entry condition occurs. In state 512, the controller 150 continues to enable the third communication channel 167 by asserting ENDATB while disabling the fourth communication channel 173 by deasserting ENDATA. From state 512, the state diagram 500 proceeds to state 514. In state 514, the first data bus 114 (SDATA) and the first clock bus 112 (SCLKA) are monitored by the controller 150 to detect whether SDATA and SCLKA are both deasserted. As discussed above, in the example where the controller 150 monitors the comparator outputs, one of the outputs is asserted when the signal on the first clock bus 112 goes low or is deasserted, and another of the outputs is asserted when the signal on the first data bus 114 goes low or is deasserted. While SDATA and / or SCLKA remain high or asserted, state diagram 500 remains in states 512 and 514. However, when SDATA and SCLKA go low or are deasserted, state diagram 500 continues to state 516.

[0052] In state 516, the controller 150 samples the impedance at the third port 156 coupled to the first data bus 114, as described above. In particular, the comparator 164 asserts ICC_ENDATA to cause the current source 160 to inject current into the third port 156. The state diagram 500 continues at state 518. In state 518, the controller 150 determines whether the first data bus 114 is in a high impedance state, for example, by monitoring the output (HIZDATA) of the comparator 164, as described above. For example, when the first data bus 114 is driven by the device 108, the injection of current into the third port 156 does not raise the voltage of the first data bus 114 above the reference voltage VBIASA for the comparator 164. In state 518, the controller 150 determines that the first data bus 114 is not in a high impedance state. State diagram 500 returns to state 514 and then back to one of states 512, 516 described above depending on whether SDATA and SCLKA are low or deasserted.

[0053] However, when the first data bus 114 is not being driven by the device 108, the injection of current into the third port 156 causes a voltage greater than the reference voltage VBIASA for the comparator 164 to drop across the pull-down resistor 122, which causes the output of the comparator 164 to assert. Thus, the controller 150 determines that the first data bus 114 is in a high impedance state in response to the output of the comparator 164 being asserted. If, in state 518, the controller 150 determines that the first data bus 114 is in a high impedance state, the state diagram 500 returns to state 502, where the controller 150 disables the third communication channel 167 and waits to receive a first signal edge from the device 108, 110 in the first or second voltage domain 104, 106, respectively.

[0054] Referring back to state 504, in another example, the controller 150 detects a first signal edge from the second data bus 118 when SDATB goes high or is asserted before SDATA. In this case, the state diagram 500 continues to state 520. States 520, 522, 524, 526, 528, 530, and 532 are generally similar to states 506, 508, 510, 512, 514, 516, and 518 described above, but the direction of communication proceeds in the opposite direction. For example, in state 520, the controller 150 enables the fourth communication channel 173 by asserting ENDATA, which enables the driver 178 of the fourth communication channel 173. When enabled, the driver 178 level shifts and / or redrives the data signal received from the second data bus 118 onto the first data bus 114. The third communication channel 167 remains disabled (e.g., ENDATB is deasserted). As described above, the delay element 176 in the fourth communication channel 173 provides the controller 150 with sufficient time to assert ENDATA before the signal from the fourth port 158 ​​that causes a state change (e.g., a first signal edge) reaches the driver 178.

[0055] The state diagram 500 then proceeds to state 522. In state 522, the controller 150 determines whether a bus arbitration entry condition has occurred. As mentioned above, in one example, a bus arbitration entry condition occurs when a data signal (e.g., received from the second data bus 118) remains asserted while a clock signal (e.g., received from the second clock bus 116) increases to at least T BT5. The occurrence of this bus arbitration start condition indicates to the controller 150 that bus arbitration is occurring between the devices 108, 110, and therefore the state diagram 500 proceeds to block 524. As discussed above, in state 524, the controller 150 facilitates a bus arbitration scheme (e.g., by enabling and disabling the third and fourth communication channels 167, 173 accordingly), and when a predetermined duration has elapsed, bus arbitration is complete and the state diagram proceeds to state 502, discussed above.

[0056] If, at state 522, the controller 150 determines that a bus arbitration entry condition has not occurred, the state diagram 500 continues to block 526. For example, if SDATB is deasserted, if SCLKB is asserted, or if SCLKB is at 0.5 V, the state diagram 500 continues to block 526. BT If it is deasserted for a shorter period of time, no bus arbitration entry condition occurs. In state 526, the controller 150 continues to enable the fourth communication channel 173 by asserting ENDATA while disabling the third communication channel 167 by deasserting ENDATB. From state 526, the state diagram 500 proceeds to state 528. In state 528, the second data bus 118 (SDATB) and the second clock bus 116 (SCLKB) are monitored by the controller 150 to detect whether SDATB and SCLKB are both deasserted. As discussed above, in the example where the controller 150 monitors the comparator outputs, one of the outputs is asserted when the signal on the second clock bus 116 goes low or is deasserted, and another of the outputs is asserted when the signal on the second data bus 118 goes low or is deasserted. While SDATB and / or SCLKB remain high or asserted, state diagram 500 remains in states 526 and 528. However, when SDATB and SCLKB go low or are deasserted, state diagram 500 continues to state 530.

[0057] In state 530, the controller 150 samples the impedance at the fourth port 158 ​​coupled to the second data bus 118, as described above. In particular, the controller 150 asserts ICC_ENDATB to cause the current source 162 to inject current into the fourth port 158. The state diagram 500 continues at state 532. In state 532, the controller 150 determines whether the second data bus 118 is in a high impedance state, for example, by monitoring the output (HIZDATB) of the comparator 166, as described above. For example, when the second data bus 118 is being driven by the device 110, the injection of current into the fourth port 158 ​​does not raise the voltage of the second data bus 118 above the reference voltage VBIASB for the comparator 166. If, in state 532, the controller 150 determines that the second data bus 118 is not in a high impedance state (HIZDATB is not high), the state diagram 500 returns to state 528 and then returns to one of states 526, 530 described above depending on whether SDATB and SCLKB are low or deasserted.

[0058] However, when the second data bus 118 is not being driven by the device 110, the injection of current into the fourth port 158 ​​causes a voltage greater than the reference voltage VBIASB for the comparator 166 to drop across the pull-down resistor 126, which causes the output of the comparator 166 to assert. Therefore, the controller 150 determines that the second data bus 118 is in a high impedance state in response to the output of the comparator 166 being asserted. If, in state 532, the controller 150 determines that the second data bus 118 is in a high impedance state (HIZDATB is high), the state diagram 500 returns to state 502, where the controller 150 disables the fourth communication channel 173 and waits to receive a first signal edge from the device 108, 110 in the first or second voltage domain 104, 106, respectively.

[0059] As described above, the redriver circuit 102 thus detects the direction of a received communication signal by monitoring both sides of the data bus (e.g., the first data bus 114 and the second data bus 118) and detecting the first signal edge arriving from the devices 108, 110 in the first or second voltage domains 104, 106, respectively. The redriver circuit 102 level shifts and / or redrives the communication signal in the direction of data transmission. The redriver circuit 102 also facilitates a bus arbitration scheme between the devices 108, 110 by detecting a bus arbitration start condition, allowing bus arbitration to occur, and when completed, continuing to facilitate data transmission between the devices 108, 110. While facilitating data transmission in one direction, the redriver circuit 102 also prevents data transmission in the opposite direction by enabling only one of the third communication channel 167 and the fourth communication channel 173 at a time. In this manner, the redriver circuit 102 also enables bidirectional, half-duplex data communication between the devices 108, 110 in the first and second voltage domains 104, 106, respectively.

[0060] In this description and claims, the term "including" is open-ended and therefore means "including, but not limited to." Also, the term "couple" means indirect or direct connection. Thus, when a first device couples to a second device, such connection may be through a direct connection or through an indirect connection via other devices and connections. Similarly, a device coupled between a first component or location and a second component or location may be through a direct connection or through an indirect connection via other devices and connections. An element or feature that is "configured to" perform a task or function may be configured (e.g., programmed or structurally designed) to perform such function at the time of manufacture by a manufacturer and / or may be configurable (or reconfigurable) by a user after manufacture to perform such function and / or other additional or alternative functions. Such configuration may be achieved through firmware and / or software programming of the device, through the configuration and / or layout of the hardware components and the interconnections of the device, or through a combination thereof. Additionally, "ground" or similar expressions include chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. Unless otherwise stated, "about" preceding a value means + / - 10 percent of the stated value.

[0061] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. 1. A redriver circuit, comprising: a first port configured to couple to a first device by a first bus; a second port configured to couple to a second device by a second bus; a first communication channel having an input coupled to the first port and an output coupled to the second port, the first communication channel configured to redrive an input signal and to output the redriven input signal; a second communication channel having an input coupled to the second port and an output coupled to the first port, the second communication channel configured to redrive an input signal and to output the redriven input signal; a first current source coupled to the first port; a second current source coupled to the second port; a first comparator having a non-inverting input coupled to the first port and an inverting input coupled to a first reference voltage source; a second comparator having a non-inverting input coupled to the second port and an inverting input coupled to a second reference voltage source; A controller, enabling the first communication channel and disabling the second communication channel in response to detecting a first signal edge at the first port; enabling the second communication channel and disabling the first communication channel in response to detecting a first signal edge at the second port; sampling an impedance at the first port in response to an input signal received at the first port being deasserted while the first communication channel is enabled; sampling an impedance at the second port in response to an input signal received at the second port being deasserted while the second communication channel is enabled; The controller configured to: Including, the first bus has an impedance and is coupled to a first pull-down resistor, the first pull-down resistor being coupled to a ground node; The second bus has an impedance and is coupled to a second pull-down resistor, the second pull-down resistor being coupled to the ground node.

2. 2. The redriver circuit of claim 1, the first device is in a first voltage domain and the second device is in a second voltage domain; the first communication channel is further configured to level shift an input signal received from the first port from the first voltage domain to the second voltage domain; The redriver circuit, wherein the second communication channel is further configured to level shift an input signal received from the second port from the second voltage domain to the first voltage domain.

3. 2. The redriver circuit of claim 1, The first communication channel: a first receiver having an input coupled to the first port and an output; a first delay element having an input coupled to the output of the first receiver and an output; a first driver having an input coupled to the output of the first delay element and an output coupled to the second port; Including, The second communication channel: a second receiver having an input coupled to the second port and an output; a second delay element having an input coupled to the output of the second receiver and an output; a second driver having an input coupled to the output of the second delay element and an output coupled to the first port; a redriver circuit comprising:

4. 2. The redriver circuit of claim 1, the controller is further configured to cause the first current source to inject current into the first port and monitor an output of the first comparator when sampling an impedance at the first port; the controller is further configured to cause the second current source to inject current into the second port and monitor an output of the second comparator when sampling an impedance at the second port; the assertion of the output of the first comparator indicates a high impedance state at the first port, and in response the controller is further configured to disable the first communication channel; The redriver circuit, further configured such that the assertion of the output of the second comparator indicates a high impedance state at the second port, and in response, the controller disables the second communication channel.

5. 1. A redriver circuit, comprising: a first port configured to couple to a first device by a first bus; a second port configured to couple to a second device by a second bus; a first communication channel having an input coupled to the first port and an output coupled to the second port, the first communication channel configured to redrive an input signal and to output the redriven input signal; a second communication channel having an input coupled to the second port and an output coupled to the first port, the second communication channel configured to redrive an input signal and to output the redriven input signal; A controller, enabling the first communication channel and disabling the second communication channel in response to detecting a first signal edge at the first port; enabling the second communication channel and disabling the first communication channel in response to detecting a first signal edge at the second port; sampling an impedance at the first port in response to an input signal received at the first port being deasserted while the first communication channel is enabled; sampling an impedance at the second port in response to an input signal received at the second port being deasserted while the second communication channel is enabled; facilitating bus arbitration between the first device and the second device in response to a bus arbitration start condition being detected at the first port while the first communications channel is enabled or in response to a bus arbitration start condition being detected at the second port while the second communications channel is enabled; disabling the first and second communication channels in response to the bus arbitration being completed; The controller configured to: a redriver circuit comprising:

6. 1. A redriver circuit, comprising: a first port configured to couple to a first device by a first clock bus; a second port configured to couple to a second device by a second clock bus; a third port configured to be coupled to the first device by a first data bus; a fourth port configured to be coupled to the second device by a second data bus; a first communications channel configured to redrive an input clock signal received from the first port to the second port as an output clock signal; a second communications channel configured to redrive an input clock signal received from the second port to the first port as an output clock signal; a third communication channel configured to redrive input data signals received from the third port to the fourth port as output data signals; a fourth communications channel configured to redrive input data signals received from the fourth port to the third port as output data signals; a first current source coupled to the first port; a second current source coupled to the second port; a third current source coupled to the third port; a fourth current source coupled to the fourth port; a first comparator having a non-inverting input coupled to the first port and an inverting input coupled to a first reference voltage source; a second comparator having a non-inverting input coupled to the second port and an inverting input coupled to a second reference voltage source; a third comparator having a non-inverting input coupled to the third port and an inverting input coupled to a third reference voltage source; a fourth comparator having a non-inverting input coupled to the fourth port and an inverting input coupled to a fourth reference voltage source; A controller, enabling the first communication channel and disabling the second communication channel in response to detecting a beginning of a clock signal edge at the first port; enabling the second communication channel and disabling the first communication channel in response to detecting a beginning of a clock signal edge at the second port; enabling the third communication channel and disabling the fourth communication channel in response to detecting a beginning of a data signal edge at the third port; enabling the fourth communication channel and disabling the third communication channel in response to detecting a beginning of a data signal edge at the fourth port; sampling an impedance at the first port in response to an input clock signal received at the first port being deasserted while the first communication channel is enabled; sampling an impedance at the second port in response to an input clock signal received at the second port being deasserted while the second communication channel is enabled; sampling an impedance at the third port in response to an input data signal received at the third port being deasserted while the third communication channel is enabled; sampling an impedance at the fourth port in response to an input data signal received at the fourth port being deasserted while the fourth communication channel is enabled; The controller configured to: Including, the first clock bus is coupled to a first pull-down resistor, the first pull-down resistor being coupled to a ground node; the second clock bus is coupled to a second pull-down resistor, the second pull-down resistor being coupled to the ground node; the first data bus is coupled to a third pull-down resistor, the third pull-down resistor being coupled to the ground node; A redriver circuit, wherein the second data bus is coupled to a fourth pulldown resistor, the fourth pulldown resistor being coupled to the ground node.

7. 7. A redriver circuit according to claim 6, comprising: the first device is in a first voltage domain and the second device is in a second voltage domain; the first communications channel is further configured to level-shift an input clock signal received from the first port from the first voltage domain to the second voltage domain; the second communications channel is further configured to level-shift an input clock signal received from the second port from the second voltage domain to the first voltage domain; the third communication channel is further configured to level shift an input data signal received from the third port from the first voltage domain to the second voltage domain; The redriver circuit, wherein the fourth communication channel is further configured to level shift an input data signal received from the fourth port from the second voltage domain to the first voltage domain.

8. 7. A redriver circuit according to claim 6, comprising: the first communications channel includes a first receiver for receiving the input clock signal from the first port, a first delay element for receiving a signal from the first receiver, and a first driver for receiving a signal from the first delay element and driving the output clock signal to the second port; the second communications channel includes a second receiver for receiving the input clock signal from the second port, a second delay element for receiving a signal from the second receiver, and a second driver for receiving a signal from the second delay element and driving the output clock signal to the first port; the third communication channel includes a third receiver for receiving the input data signal from the third port, a third delay element for receiving a signal from the third receiver, and a third driver for receiving a signal from the third delay element and driving the output data signal to the fourth port; a fourth communication channel including a fourth receiver for receiving the input data signal from the fourth port, a fourth delay element for receiving a signal from the fourth receiver, and a fourth driver for receiving a signal from the fourth delay element and driving the output data signal to the third port.

9. 7. A redriver circuit according to claim 6, comprising: the controller is further configured to cause the first current source to inject current into the first port and monitor an output of the first comparator when sampling an impedance at the first port; the controller is further configured to cause the second current source to inject current into the second port and monitor an output of the second comparator when sampling an impedance at the second port; the controller is further configured to cause the third current source to inject current into the third port and monitor an output of the third comparator when sampling an impedance at the third port; the controller is further configured to cause the fourth current source to inject current into the fourth port and monitor an output of the fourth comparator when sampling an impedance at the fourth port; the assertion of the output of the first comparator indicates a high impedance state at the first port, and in response the controller is further configured to disable the first communication channel; the assertion of the output of the second comparator indicates a high impedance state at the second port, and in response the controller is further configured to disable the second communication channel; the assertion of the output of the third comparator indicates a high impedance state at the third port, and in response the controller is further configured to disable the third communication channel; The redriver circuit, further configured such that the assertion of the output of the fourth comparator indicates a high impedance state at the fourth port, and in response, the controller disables the fourth communication channel.

10. 1. A redriver circuit, comprising: a first port configured to couple to a first device by a first clock bus; a second port configured to couple to a second device by a second clock bus; a third port configured to be coupled to the first device by a first data bus; a fourth port configured to be coupled to the second device by a second data bus; a first communications channel configured to redrive an input clock signal received from the first port to the second port as an output clock signal; a second communications channel configured to redrive an input clock signal received from the second port to the first port as an output clock signal; a third communication channel configured to redrive input data signals received from the third port to the fourth port as output data signals; a fourth communications channel configured to redrive input data signals received from the fourth port to the third port as output data signals; A controller, enabling the first communication channel and disabling the second communication channel in response to detecting a beginning of a clock signal edge at the first port; enabling the second communication channel and disabling the first communication channel in response to detecting a beginning of a clock signal edge at the second port; enabling the third communication channel and disabling the fourth communication channel in response to detecting a beginning of a data signal edge at the third port; enabling the fourth communication channel and disabling the third communication channel in response to detecting a beginning of a data signal edge at the fourth port; sampling an impedance at the first port in response to an input clock signal received at the first port being deasserted while the first communication channel is enabled; sampling an impedance at the second port in response to an input clock signal received at the second port being deasserted while the second communication channel is enabled; sampling an impedance at the third port in response to an input data signal received at the third port being deasserted while the third communication channel is enabled; sampling an impedance at the fourth port in response to an input data signal received at the fourth port being deasserted while the fourth communication channel is enabled; facilitating bus arbitration between the first device and the second device in response to a bus arbitration start condition being detected at the first port and the third port while the first and third communications channels are enabled, or in response to a bus arbitration start condition being detected at the second port and the fourth port while the second and fourth communications channels are enabled; disabling the third and fourth communication channels in response to the bus arbitration being completed; The controller configured to: a redriver circuit comprising:

11. 11. A redriver circuit as claimed in claim 10, comprising: the bus arbitration initiation condition detected at the first port and the third port includes an input clock signal received at the first port being deasserted while an input data signal received at the third port is asserted during at least a bus turnaround time; a redriver circuit, wherein the bus arbitration initiation condition detected at the second port and the fourth port includes an input data signal received at the fourth port being asserted while an input clock signal received at the second port is deasserted during at least the bus turnaround time.

12. 1. A method in a redriver circuit including a first port, a second port, a first communication channel, a second communication channel, a first current source coupled to the first port, a second current source coupled to the second port, a first comparator having a non-inverting input coupled to the first port and an inverting input coupled to a first reference voltage, and a second comparator having a non-inverting input coupled to the second port and an inverting input coupled to a second reference voltage, detecting a first signal edge at the first port configured to couple to a first device by a first bus or detecting a first signal edge at the second port configured to couple to a second device by a second bus; in response to detecting the first signal edge at the first port, enabling the first communication channel configured to redrive an input signal received from the first port as an output signal to a second port and disabling a second communication channel configured to redrive an input signal received from the second port as an output signal to the first port; in response to detecting the first signal edge at the second port, enabling the second communications channel and disabling the first communications channel; sampling an impedance at the first port in response to an input signal received at the first port being deasserted while the first communication channel is enabled; sampling an impedance at the second port in response to an input signal received at the second port being deasserted while the second communication channel is enabled; Including, The method of claim 1, wherein the first bus is coupled to a ground node through a first pull-down resistor and the second bus is coupled to the ground node through a second pull-down resistor.

13. 13. The method of claim 12, the first device is in a first voltage domain and the second device is in a second voltage domain; The method further comprising: level shifting an input signal received from the first port from the first voltage domain to the second voltage domain when the first communication channel is enabled; level shifting an input signal received from the second port from the second voltage domain to the first voltage domain when the second communication channel is enabled; The method further comprises:

14. 13. The method of claim 12, Sampling the impedance at the first port further comprises causing the first current source to inject a current into the first port and monitoring an output of the first comparator; Sampling the impedance at the second port further comprises causing the second current source to inject current into the second port and monitoring an output of the second comparator; The method further comprising: disabling the first communications channel in response to the output of the first comparator being asserted indicating a high impedance state at the first port; disabling the second communications channel in response to the output of the second comparator being asserted indicating a high impedance state at the second port; The method further comprises:

15. 1. A method comprising: detecting a first signal edge at a first port configured to couple to a first device by a first bus or detecting a first signal edge at a second port configured to couple to a second device by a second bus; in response to detecting a first signal edge at the first port, enabling a first communication channel configured to redrive an input signal received from the first port as an output signal to a second port and disabling a second communication channel configured to redrive an input signal received from the second port as an output signal to the first port; in response to detecting a first signal edge at the second port, enabling the second communication channel and disabling the first communication channel; sampling an impedance at the first port in response to an input signal received at the first port being deasserted while the first communication channel is enabled; sampling an impedance at the second port in response to an input signal received at the second port being deasserted while the second communication channel is enabled; facilitating bus arbitration between the first device and the second device in response to detecting a bus arbitration start condition at the first port while the first communication channel is enabled or in response to detecting a bus arbitration start condition at the second port while the second communication channel is enabled; disabling the first and second communication channels in response to the bus arbitration being completed; A method comprising:

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