MEMORY CONTROLLER AND FLASH MEMORY SYSTEM - Patent application

Abstract

A memory controller according to one embodiment of the present invention is equipped with: a layout setting unit for setting the data arrangement to be applied to a plurality of channels when performing parallel data forwarding using the plurality of channels between the memory controller and a flash memory; and an access processing unit which, when subjecting the flash memory to data access processing, performs parallel data forwarding to the flash memory by using the data arrangement in the plurality of channels which was set by the layout setting unit. When arranging the parity data and the user data included in the data, the layout setting unit sets the data arrangement in the plurality of channels in a manner such that a second arrangement region in which the parity data is arranged is positioned all to the front or all to the rear in the order of access when performing parallel data forwarding, with a first arrangement region in which the user data is arranged in each of the plurality of channels as a reference.

Description

[Technical field]

[0001] The present invention relates to a memory controller and a flash memory system. [Background technology]

[0002] 2. Description of the Related Art There have been proposals of a memory controller that controls a nonvolatile memory such as a flash memory, and a memory system (such as a flash memory system) that includes such a memory controller and a nonvolatile memory (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2021-520021 Summary of the Invention

[0004] However, in such memory controllers and the like, there is generally a demand for an improved data transfer rate with a simple configuration. It is desirable to provide a memory controller and a flash memory system that are capable of improving the data transfer rate with a simple configuration.

[0005] A memory controller according to an embodiment of the present invention is a memory controller for controlling a flash memory, and includes: a layout setting unit that sets data arrangements to be applied to multiple channels when parallel data transfer is performed between the memory controller and the flash memory using the multiple channels; and an access processing unit that performs parallel data transfer between the memory controller and the flash memory using the data arrangements in the multiple channels set by the layout setting unit when accessing data to the flash memory. When arranging user data and parity data included in data, the layout setting unit sets data arrangements in the multiple channels so that, in each of the multiple channels, a second arrangement area in which parity data is arranged is collectively arranged forward or backward in accordance with the access order during parallel data transfer, based on a first arrangement area in which user data is arranged.

[0006] A flash memory system according to an embodiment of the present invention includes the memory controller according to the embodiment of the present invention described above, and the flash memory described above.

[0007] According to the memory controller and flash memory system according to an embodiment of the present invention, it is possible to improve the data transfer speed with a simple configuration. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram illustrating an example of a schematic configuration of a flash memory system according to an embodiment of the present invention. [Diagram 2] 2 is a block diagram illustrating an example of a detailed configuration of a control circuit illustrated in FIG. 1. [Diagram 3] 4 is a schematic diagram illustrating an example of a data arrangement configuration in each channel according to the embodiment. FIG. [Figure 4] 11 is a schematic diagram illustrating a configuration example of data arrangement in each channel according to Comparative Example 1. FIG. [Diagram 5]FIG. 11 is a schematic diagram illustrating a configuration example of data arrangement in each channel according to Comparative Example 2. [Figure 6] 11 is a schematic diagram illustrating an example of an operation of parallel data transfer during a read process (sequential read) according to Comparative Example 1. FIG. [Figure 7] FIG. 11 is a schematic diagram illustrating an example of an operation of parallel data transfer during a read process (sequential read) according to Comparative Example 2. [Figure 8] 11 is a schematic diagram illustrating an example of an operation of parallel data transfer during a read process (at the time of random read) according to Comparative Example 1. FIG. [Figure 9] FIG. 11 is a schematic diagram illustrating an example of an operation of parallel data transfer during a read process (at the time of random read) according to Comparative Example 2. [Figure 10] 11 is a schematic diagram illustrating an example of an operation of parallel data transfer during a write process according to Comparative Example 1. FIG. [Figure 11] FIG. 11 is a schematic diagram illustrating an example of an operation of parallel data transfer during a write process according to Comparative Example 2. [Figure 12] 11 is a schematic diagram illustrating an example of parallel data transfer during a read process (sequential read) according to the embodiment. FIG. [Figure 13] 11 is a schematic diagram illustrating an example of parallel data transfer during a read process (at the time of random read) according to the embodiment. FIG. [Figure 14] 11 is a schematic diagram illustrating an example of a parallel data transfer operation during a write process in the embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The description will be given in the following order. 1. Embodiment (Example of Arrangement of User Data and Parity Data During Parallel Data Transfer) 2. Variations

[0010] <1. Preferred embodiment> [Schematic configuration] 1 is a block diagram showing an example of a schematic configuration of a flash memory system (flash memory system 3) according to an embodiment of the present invention, together with an external host system 4. This flash memory system 3 is a system equivalent to, for example, an SSD (Solid State Drive) or an eMMC (embedded Multi Media Card).

[0011] 1, the flash memory system 3 includes a flash memory 1 and a memory controller 2. The host system 4 and the memory controller 2 (host interface 25 described later) are connected to each other via an external bus 82, and the memory controller 2 (memory interface 21 described later) and the flash memory 1 are connected to each other via an internal bus 81.

[0012] (A. Host System 4) The host system 4 is a host system that uses the flash memory system 3 as a secondary storage device. The host system 4 includes a CPU (Central Processing Unit) for controlling the overall operation of the host system 4, a companion chip for transmitting and receiving various information to and from the flash memory system 3, and the like. Such a host system 4 is, for example, an information processing device such as a personal computer (PC) or a digital still camera.

[0013] The host system 4 also instructs the flash memory system 3 to execute various processes by supplying predetermined commands to the flash memory system 3. Specifically, these commands are commands that the memory controller 2 in the flash memory system 3 uses to instruct the flash memory 1 to execute various processes. In other words, the flash memory 1 performs various operations in accordance with the commands provided by the memory controller 2.

[0014] (B. Flash Memory 1) The flash memory 1 is a non-volatile memory and is configured using one or more flash memory chips. The flash memory 1 is, for example, a NAND type flash memory. In this NAND type flash memory, data access processing (write processing or read processing) is performed in page units, and data erasure processing (all-at-once erasure) is performed in block units consisting of multiple pages.

[0015] Incidentally, the pages and blocks in the flash memory 1 are also generally called physical pages and physical blocks, respectively, in order to distinguish them from logical pages and logical blocks, which are the units in which the host system 4 handles data.

[0016] Specifically, each physical block includes, for example, 64, 128, or 256 physical pages. Each physical page includes, for example, 4, 8, or 16 sectors (physical sectors). Each physical sector is an area allocated to store 512 bytes of data (one sector of data).

[0017] Such a flash memory 1 includes a register and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word lines are used to select a specific memory cell from the memory cell group. A write process (a write process) of data from the register to the selected memory cell or a read process (a read process) of data from the selected memory cell to the register is performed between the selected memory cell and the register via the word line.

[0018] (C. Memory Controller 2) The memory controller 2 controls the flash memory 1 in accordance with instructions (the commands described above) from the host system 4. Specifically, for example, when there is a write request from the host system 4, the memory controller 2 writes data received from the host system 4 to the flash memory 1. Also, for example, when there is a read request from the host system 4, the memory controller 2 reads data from the flash memory 1 and transmits it to the host system 4.

[0019] In addition, in this embodiment, as will be described in detail later, parallel data transfer is performed using multiple channels between the memory controller 2 and the flash memory 1, and between the memory controller 2 and the host system 4.

[0020] Such a memory controller 2 includes a memory interface 21, a control circuit 22, a RAM (Random Access Memory) 23, a ROM (Read Only Memory) 24, and a host interface 25, as shown in FIG.

[0021] The memory interface 21 is an interface for communicating with the flash memory 1. The memory interface 21 is, for example, a memory interface that complies with the ONFI (Open NAND Flash Interface) standard.

[0022] The control circuit 22 is a circuit that transmits and receives data to and from the host system 4 via the host interface 25, and controls the flash memory 1 via the memory interface 21. The control circuit 22 includes a CPU (Central Processing Unit) and peripheral circuits. The CPU reads and executes a control program stored in the ROM 24, thereby realizing the functions of each functional unit described below.

[0023] The RAM 23 is a section for temporarily storing working data necessary for the CPU to execute the above-mentioned control programs, data received from the host system 4, data read from the flash memory 1, etc. In other words, the RAM 23 functions as a buffer memory. The RAM 23 is a volatile memory that can be accessed at high speed, such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0024] The ROM 24 is a section for storing the above-mentioned control programs, and is a non-volatile memory such as a PROM (Programmable Read-Only Memory) or an EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0025] The host interface 25 is an interface for communicating with the host system 4. The host interface 25 is, for example, an interface conforming to the SATA (Serial Advanced Technology Attachment) standard, or an interface conforming to the NVMe (Non-Volatile Memory Express) standard.

[0026] [Detailed configuration of control circuit 22] Next, a detailed configuration example of the above-mentioned control circuit 22 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing a detailed configuration example of the control circuit 22. Specifically, Fig. 2 shows, as functional blocks, each functional unit of the control circuit 22 that is realized by the CPU of the control circuit 22 reading and executing a control program stored in the ROM 24.

[0027] As shown in FIG. 2, the control circuit 22 includes, as such functional components, a data preparation unit 221, a layout setting unit 222, a parity data generation unit 223, an access processing unit 224, a read check unit 225, and a recovery unit 226.

[0028] The data preparation unit 221 prepares data to be saved in each block described above in units of pages. Data in units of pages is written sequentially to each page in a block by the access processing unit 224 described later. The data preparation unit 221 prepares data to be saved in units of pages, for example, by dividing data requested to be written from the host system 4 (data received from the host system 4) in units of pages and storing the data in the RAM 23. Furthermore, when new data to be written to the flash memory 1 for management purposes, not data from the host system 4, is generated, the data preparation unit 221 prepares the data in units of pages.

[0029] The layout setting unit 222 sets a predetermined layout for each data during the above-mentioned parallel data transfer (parallel data transfer using multiple channels between the memory controller 2 and the flash memory 1 or the host system 4). Specifically, the layout setting unit 222 sets data arrangements to be applied to multiple channels during such parallel data transfer. Details of the data arrangement configurations in each channel set by the layout setting unit 222 will be described later (FIG. 3).

[0030] The parity data generating unit 223 obtains parity across data (user data) written to pages in each block, and generates parity data that is redundant data. That is, the parity data generating unit 223 generates parity data based on such user data. Specifically, the parity data generating unit 223 generates horizontal parity as parity data, which is obtained by calculating an exclusive OR of user data written to pages in each block. Alternatively, the parity data generating unit 223 may generate, for example, Galois parity obtained by using Galois arithmetic, or parity using other arithmetic, as parity data. Details of the method of generating parity data by the parity data generating unit 223 will be described later (FIGS. 3 and 14).

[0031] The access processing unit 224 performs access processing (the above-mentioned write processing or read processing) of data to the flash memory 1. This access processing unit 224 also performs parallel data transfer between the flash memory 1, using the data arrangement in the multiple channels set by the above-mentioned layout setting unit 222. Details of the write processing (read processing) and read processing (write processing) performed by the access processing unit 224 will be described later (FIGS. 12 to 14).

[0032] The read check unit 225 judges whether the data (user data) read by the access processing unit 224 has been read normally. Specifically, the read check unit 225 first reads the data and the corresponding error correction code from the block on a page-by-page basis. Then, the read check unit 225 judges that the data has been read normally, for example, when there is no error in the data for all pages, or when there is an error in the data but the error can be corrected by the error correction code. On the other hand, the read check unit 225 judges that the data has not been read normally, for example, when there is an error in the data and the error cannot be corrected by the error correction code.

[0033] The recovery unit 226 performs data recovery processing based on the data (user data) read by the access processing unit 224 and the parity data further read. Specifically, the recovery unit 226 recovers data (user data) that has not been read normally in units managed by RAID (Redundant Arrays of Inexpensive Disks).

[0034] [Data placement configuration] Next, a detailed description will be given of an example of the data arrangement in each channel, which is set by the layout setting unit 222, with reference to Fig. 3. Fig. 3 is a schematic diagram showing an example of the data arrangement in each channel according to an embodiment of the present invention.

[0035] In the example of Fig. 3, four channels CH0 to CH3 are provided as the above-mentioned multiple channels. In the example of Fig. 3, data (user data or parity data) equivalent to one page is arranged in each of the channels CH0 to CH3 according to the access order dac of each data during the above-mentioned parallel data transfer. These points are also the same in the comparative examples (Comparative Examples 1 and 2) described later (Figs. 4 and 5).

[0036] First, in the embodiment shown in Fig. 3, the layout setting unit 222 sets the following data allocation Ld when arranging the user data (user data d0 to d11) and parity data (parity data Pa to Pd) included in the data. That is, the layout setting unit 222 sets the following data allocation Ld for the data allocation area Ad in which the user data d0 to d11 are arranged and the parity allocation area Ap in which the parity data Pa to Pd are arranged in each of the channels CH0 to CH3. Specifically, the layout setting unit 222 sets the data allocation Ld in each of the channels CH0 to CH3 so that the parity allocation area Ap is collectively (concentrated) arranged forward or backward according to the above-mentioned access order dac based on such a data allocation area Ad.

[0037] In particular, in the example of Fig. 3, the layout setting unit 222 sets the data allocation Ld in each channel CH0 to CH3 so that the parity allocation area Ap is collectively arranged behind the data allocation area Ad along the access order dac in each channel CH0 to CH3. That is, in the data allocation Ld in Fig. 3, the data allocation area Ad is arranged in front and the parity allocation area Ap is arranged behind along the access order dac in each channel CH0 to CH3.

[0038] Specifically, as shown in Fig. 3, in channel CH0, the data are arranged in the order of user data d0, d4, d8, and parity data Pa along the access order dac (from front to back). In channel CH1, the data are arranged in the order of user data d1, d5, d9, and parity data Pb along the access order dac. In channel CH2, the data are arranged in the order of user data d2, d6, d10, and parity data Pc along the access order dac. In channel CH3, the data are arranged in the order of user data d3, d7, d11, and parity data Pd along the access order dac.

[0039] 3, the parity data generating unit 223 generates each of the parity data Pa to Pd based on the user data d0 to d11, for example, by the following generation formulas. Note that the symbol "+" shown below may be, for example, the exclusive OR or a Galois operation or other operation as described above. This point is also the same in the comparative examples (Comparative Examples 1 and 2) described later (FIGS. 4 and 5).

[0040] Pa=d9+d10+d11 Pb=d6+d7+d8 Pc=d3+d4+d5 Pd=d0+d1+d2

[0041] Here, the above-mentioned data allocation area Ad corresponds to a specific example of the "first allocation area" in the present invention. Also, the above-mentioned parity allocation area Ap corresponds to a specific example of the "second allocation area" in the present invention.

[0042] [Operation and Effects] Next, an operation example (an operation example during read processing and write processing as the above-mentioned data access processing) in the flash memory system 3 of this embodiment will be described in detail while comparing it with comparative examples (Comparative Examples 1 and 2). Note that Comparative Examples 1 and 2 described below correspond to examples in which so-called "RAID4, RAID5" are applied, respectively.

[0043] (A. Data arrangement configurations of comparative examples 1 and 2) Fig. 4 is a schematic diagram showing an example of data allocation in each channel according to Comparative Example 1 (the above-mentioned "RAID4"), and Fig. 5 is a schematic diagram showing an example of data allocation in each channel according to Comparative Example 2 (the above-mentioned "RAID5").

[0044] First, the data allocation Ld101 of Comparative Example 1 shown in Fig. 4 is set as follows, unlike the data allocation Ld of the embodiment shown in Fig. 3. That is, in this data allocation Ld101, only user data d0-d11 are arranged in each of the channels CH0-CH2, while only parity data Pa-Pd are arranged in the channel CH3.

[0045] Specifically, as shown in Fig. 4, in channel CH0, the user data are arranged in the order of d0, d3, d6, d9 along the access order dac (from front to back). In channel CH1, the user data are arranged in the order of d1, d4, d7, d10 along the access order dac. In channel CH2, the user data are arranged in the order of d2, d5, d8, d11 along the access order dac. In channel CH3, the parity data are arranged in the order of Pa, Pb, Pc, Pd along the access order dac.

[0046] On the other hand, the data allocation Ld201 of Comparative Example 2 shown in Fig. 5 is set as follows, unlike the data allocation Ld of the embodiment shown in Fig. 3. That is, in this data allocation Ld201, in each of the channels CH0 to CH2, the allocation areas of the user data d0 to d11 and the allocation areas of the parity data Pa to Pd are mixed along the access order dac, and are not collectively (concentrated) arranged in the front or back.

[0047] Specifically, as shown in Fig. 5, in channel CH0, the data are arranged in the order of user data d0, d3, d6, and parity data Pd along the access order dac (from front to back). In channel CH1, the data are arranged in the order of user data d1, d4, parity data Pc, and user data d9 along the access order dac. In channel CH2, the data are arranged in the order of user data d2, parity data Pb, and user data d7 and d10 along the access order dac. In channel CH3, the data are arranged in the order of parity data Pa, and user data d5, d8, and d11 along the access order dac.

[0048] Furthermore, in both comparison examples 1 and 2 shown in Figures 4 and 5, unlike the embodiment of Figure 3 described above, the parity data Pa to Pd are generated based on the user data d0 to d11, for example, using the following generation formulas.

[0049] ·Pa=d0+d1+d2 Pb=d3+d4+d5 Pc=d6+d7+d8 Pd=d9+d10+d11

[0050] (B. Lead Treatment in Comparative Examples 1 and 2) Here, Fig. 6 is a schematic diagram showing an example of parallel data transfer during read processing (sequential read) according to Comparative Example 1. Fig. 7 is a schematic diagram showing an example of parallel data transfer during read processing (sequential read) according to Comparative Example 2. In these sequential read examples, the user data d0 to d11 are read out sequentially according to the access order dac described above. This point is the same in the case of the embodiment described later (Fig. 12).

[0051] On the other hand, Fig. 8 is a schematic diagram showing an example of parallel data transfer during a read process (at random read) according to Comparative Example 1. Fig. 9 is a schematic diagram showing an example of parallel data transfer during a read process (at random read) according to Comparative Example 2. In these examples of random read, only the user data d0 to d3 among the user data d0 to d11 are read out in sequence according to the access order dac described above. This point is the same in the case of the embodiment described later (Fig. 13).

[0052] In these Figures 6 to 9, the horizontal axis indicates time t, and the unit period during the read process is indicated as Δt1. Also, "Read Busy" shown in these Figures 6 to 9 means a read preparation period in the flash memory 1 during the read process. Furthermore, during the read process shown in these Figures 6 to 9, the parity data generation unit (the parity data generation unit 103 in Comparative Example 1 and the parity data generation unit 203 in Comparative Example 2) shown in each figure does not generate parity data. These points are also the same in the case of the embodiment described later (Figures 12 and 13).

[0053] First, when the data arrangement Ld101 of Comparative Example 1 shown in FIG. 4 is taken into consideration, during sequential reading in Comparative Example 1 shown in FIG. 6, the channel CH3 out of the four channels CH0 to CH3 is occupied by the parity data Pa to Pd, so that the following occurs. That is, in Comparative Example 1, the data transfer speed during the read process is slowed down because the three channels CH0 to CH2 are used for parallel data transfer (triple parallel data transfer) in practical terms. Specifically, in the case of Comparative Example 1 shown in FIG. 6, the data transfer time during the read process (excluding the above-mentioned preparation period) is expressed as (4×Δt1) using the unit period Δt1 during the read process described above.

[0054] On the other hand, when the data arrangement Ld201 of Comparative Example 2 shown in FIG. 5 is taken into consideration during sequential reading in Comparative Example 2 shown in FIG. 7, the parity data Pa to Pd are distributed to the four channels CH0 to CH3, as in the data arrangement Ld of the embodiment shown in FIG. 3, so that the following is obtained. That is, in Comparative Example 2, as in the case of the embodiment described later (FIG. 12), parallel data transfer (four-parallel data transfer) is performed using the four channels CH0 to CH3, so the data transfer speed during read processing is faster than that of Comparative Example 1. Specifically, in the case of Comparative Example 2 shown in FIG. 7, the data transfer time during read processing (excluding the preparation period described above) is expressed as (3×Δt1).

[0055] However, in the case of random read shown in Fig. 8 and Fig. 9, in the case of comparative example 2 as well as comparative example 1, when only user data d0 to d3 are read, channel CH3 is occupied by parity data Pa, taking into consideration data arrangements Ld101 and Ld201. Therefore, in the case of random read, in both comparative examples 1 and 2, the data transfer speed during read processing is slowed down because the data transfer is performed in three parallel ways as described above. Specifically, in the case of comparative examples 1 and 2 shown in Fig. 8 and Fig. 9, the data transfer time during read processing (excluding the preparation period described above) is expressed as (2 x Δt1).

[0056] In the data allocation Ld201 of Comparative Example 2, as described above, the allocation areas of the user data d0 to d11 and the allocation areas of the parity data Pa to Pd are mixed along the access order dac (see FIG. 5). Therefore, in this Comparative Example 2, the data transfer control during the read process becomes a complicated method.

[0057] (C. Write processing of comparative examples 1 and 2) Next, Fig. 10 is a schematic diagram showing an example of parallel data transfer during a write process according to Comparative Example 1. Fig. 11 is a schematic diagram showing an example of parallel data transfer during a write process according to Comparative Example 2.

[0058] In these examples of write processing, the user data d0 to d11 are written sequentially according to the access order dac described above. In addition, in these Figs. 10 and 11, the horizontal axis indicates time t, and the unit period during the write processing is indicated as Δt2. Furthermore, "Program Busy" shown in these Figs. 10 and 11 means the program processing period in the flash memory 1 during the write processing. These points are the same in the case of the embodiment described later (Fig. 14).

[0059] First, in the write process of Comparative Example 1 shown in Fig. 10, taking into consideration the data arrangement Ld101 of Comparative Example 1 shown in Fig. 4, the parallel data transfers in each channel CH0 to CH3 are sequentially performed in the following manner according to the access order dac described above. That is, in channel CH0, the user data are transferred in the order of d0, d3, d6, d9, in channel CH1, the user data are transferred in the order of d1, d4, d7, d10, in channel CH2, the user data are transferred in the order of d2, d5, d8, d11. In addition, in channel CH3, the parity data are transferred in the order of Pa, Pb, Pc, Pd.

[0060] However, during the write process of Comparative Example 1, unlike the read process described above, the parity data generating unit 103 according to Comparative Example 1 performs a generation process of each of the parity data Pa to Pd. Therefore, as shown by the dashed arrows in FIG. 10, for example, after each of the parity data Pa to Pd is generated, each of the parity data Pa to Pd is transferred sequentially. As a result, during the write process of Comparative Example 1, a waiting period Δt102 (see the dashed period shown in FIG. 10) occurs in the channel CH3 before the transfer period of each of the parity data Pa to Pd.

[0061] On the other hand, in the write process of Comparative Example 2 shown in FIG. 11, taking into consideration the data arrangement Ld201 of Comparative Example 2 shown in FIG. 5, the parallel data transfers in each of the channels CH0 to CH3 are sequentially performed in the following manner according to the access order dac described above. That is, in channel CH0, data is transferred in the order of user data d0, d3, d6, and parity data Pd, and in channel CH1, data is transferred in the order of user data d1, d4, parity data Pc, and user data d9. In addition, in channel CH2, data is transferred in the order of user data d2, parity data Pb, and user data d7 and d10, and in channel CH3, data is transferred in the order of parity data Pa, and user data d5, d8, and d11.

[0062] However, in the write process of Comparative Example 2, unlike the read process described above, the parity data generating unit 203 according to Comparative Example 2 generates each of the parity data Pa to Pd. Therefore, as shown by the dashed arrow in FIG. 11, after each of the parity data Pa to Pd is generated, each of the parity data Pa to Pd is transferred in sequence. As a result, in the write process of Comparative Example 2, a waiting period Δt202 (see the dashed period shown in FIG. 11) occurs before the transfer period of each of the parity data Pa to Pc in the channels CH1 to CH3. Specifically, in the channel CH1, such a waiting period Δt202 occurs between the transfer period of the user data d4 and the transfer period of the parity data Pc. In addition, in the channel CH2, a waiting period Δt202 occurs between the transfer period of the user data d2 and the transfer period of the parity data Pb, and in the channel CH3, a waiting period Δt202 occurs before the transfer period of the parity data Pa.

[0063] For these reasons, in the write processing of Comparative Examples 1 and 2, a decrease in the data transfer rate occurs due to the period during which the parity data is generated.

[0064] In this way, it can be said that with the methods of Comparative Examples 1 and 2, it is difficult to improve the data transfer speed with a simple configuration during data read and write processing.

[0065] (D. Operation Example of This Embodiment) Therefore, in the flash memory system 3 of this embodiment, the memory controller 2 performs data read and write processes using, for example, the data arrangement Ld shown in FIG.

[0066] Specifically, first, when arranging the user data and parity data included in the data, the layout setting unit 222 sets the data arrangement Ld as follows for each of the multiple channels. That is, the layout setting unit 222 sets the data arrangement Ld for each channel so that the parity arrangement area Ap is collectively arranged in front or behind the data arrangement area Ad based on the access order dac during parallel data transfer (see FIG. 3, for example). In particular, in the example of FIG. 3, the layout setting unit 222 sets the data arrangement Ld for each of the channels CH0 to CH3 so that the parity arrangement area Ap is collectively arranged behind the data arrangement area Ad in the access order dac.

[0067] Furthermore, when performing data read processing or write processing, the access processing unit 224 performs parallel data transfer according to the access order dac for each of the user data in the data placement area Ad and the parity data in the parity placement area Ap in accordance with the data placement Ld set in this way. The read processing and write processing of this embodiment will be described in detail below using the data placement Ld of the embodiment shown in FIG. 3 described above.

[0068] (D-1. Lead Processing in the Example) Fig. 12 is a schematic diagram showing an example of parallel data transfer during a read process (sequential read) according to an embodiment. Fig. 13 is a schematic diagram showing an example of parallel data transfer during a read process (random read) according to an embodiment.

[0069] First, when the data arrangement Ld of the embodiment shown in FIG. 12 is taken into consideration, the parity data Pa to Pd are distributed to the four channels CH0 to CH3 in the same manner as the data arrangement Ld201 (FIG. 5) of the comparative example 2 described above, so that the following is obtained. That is, in this embodiment, parallel data transfer (four-parallel data transfer) is performed using the four channels CH0 to CH3 in the same manner as the comparative example 2 (FIG. 7). Therefore, the data transfer speed during the read process is faster than that in the comparative example 1 described above (FIG. 6: three-parallel data transfer). Specifically, in the comparative example 1 shown in FIG. 6, the data transfer time during the read process (excluding the preparation period described above) is expressed as (4×Δt1) using the unit period Δt1 during the read process described above. On the other hand, in the embodiment shown in FIG. 12, the data transfer time during the read process (excluding the preparation period described above) is (3×Δt1) in the same manner as the comparative example 2 described above (FIG. 7).

[0070] Also, in the case of random read in the embodiment shown in FIG. 13, when considering the data arrangement Ld of the embodiment, even when only user data d0 to d3 are to be read, it becomes as follows, unlike the above-mentioned comparative examples 1 and 2 (FIGS. 8 and 9). That is, in this embodiment, unlike the comparative examples 1 and 2, even in such a random read, each channel CH0 to CH3 is not occupied by parity data. Therefore, even in such a random read, in this embodiment, unlike the comparative examples 1 and 2 (data transfer in three parallels), data is transferred in four parallels, so the data transfer speed in the read process is faster than in the comparative examples 1 and 2. Specifically, in the comparative examples 1 and 2 shown in FIG. 8 and FIG. 9, the data transfer time in the read process (excluding the preparation period described above) is expressed as (2×Δt1). On the other hand, in the case of the embodiment shown in FIG. 13, the data transfer time in the read process (excluding the preparation period described above) is (1×Δt1).

[0071] In addition, in the data arrangement Ld of this embodiment, the arrangement areas of the user data d0 to d11 and the arrangement areas of the parity data Pa to Pd are not mixed along the access order dac, as in the data arrangement Ld201 of the comparative example 2. That is, in the data arrangement Ld of this embodiment, as described above, the parity arrangement area Ap is collectively arranged in front of or behind the data arrangement area Ad along the access order dac. Therefore, unlike the comparative example 2, in this embodiment, the data transfer control during the read process is a simple method (simpler than the method of the comparative example 2).

[0072] (D-2. Write processing in the embodiment) On the other hand, FIG. 14 is a schematic diagram showing an example of parallel data transfer operations during write processing according to the embodiment.

[0073] In the write process of the embodiment shown in Fig. 14, taking into consideration the data arrangement Ld of the embodiment, the parallel data transfer in each channel CH0 to CH3 is performed in sequence according to the access order dac described above as follows. That is, in channel CH0, data is transferred in the order of user data d0, d4, d8, and parity data Pa, and in channel CH1, data is transferred in the order of user data d1, d5, d9, and parity data Pb. In addition, in channel CH2, data is transferred in the order of user data d2, d6, d10, and parity data Pc, and in channel CH3, data is transferred in the order of user data d3, d7, d11, and parity data Pd.

[0074] During the write process of the embodiment shown in Fig. 14, the parity data generation unit 223 generates the parity data Pa to Pd belonging to each channel CH0 to CH3 as follows. That is, the parity data generation unit 223 generates each parity data Pa to Pd in ​​parallel with the period of parallel data transfer for each user data d0 to d11, which is set to precede the period of parallel data transfer for each parity data Pa to Pd. That is, during the data transfer period for each user data d0 to d11 collectively arranged in front of the data arrangement area Ad, the generation process for each parity data Pa to Pd is also performed in parallel.

[0075] Therefore, during the write process of this embodiment, unlike the write processes of the comparative examples 1 and 2 described above (FIGS. 10 and 11), no waiting period occurs in each of the channels CH0 to CH3. That is, for example, as shown in FIG. 14, the user data d0 to d11 and the parity data Pa to Pd are seamlessly transferred in each of the channels CH0 to CH3. As a result, unlike the comparative examples 1 and 2, this embodiment avoids a decrease in the data transfer rate due to the generation period of the parity data described above. In other words, in this embodiment, the data transfer rate during the write process is improved compared to the comparative examples 1 and 2.

[0076] (E. Actions and Effects) In this manner, in this embodiment, when the user data and parity data included in the data are respectively arranged, the following data arrangement is set in each of the multiple channels. That is, the data arrangement is set in each channel so that the parity arrangement area Ap described above is arranged collectively in front or behind the data arrangement area Ad described above according to the access order dac during parallel data transfer.

[0077] As a result, in this embodiment, when data access processing (the above-mentioned read processing and write processing) is performed, for example, it is as follows. That is, as described above, according to the data arrangement set in each of the multiple channels, parallel data transfer is performed along the access order dac for each of the user data in the data arrangement area Ad and the parity data in the parity arrangement area Ap. As a result, unlike the above-mentioned comparative examples 1 and 2, this embodiment can avoid a decrease in data transfer speed during read processing and write processing by a simple method. For these reasons, this embodiment can improve the data transfer speed with a simple configuration compared to comparative examples 1 and 2.

[0078] In addition, in this embodiment, in each of the multiple channels, the parity allocation area Ap is arranged collectively behind the data allocation area Ad along the access order dac, so that the following is obtained. That is, unlike the above-mentioned comparative examples 1 and 2, for example, it is possible to avoid a decrease in data transfer speed caused by the generation period of parity data during data write processing. As a result, in this embodiment, it is possible to more easily improve the data transfer speed during write processing compared to comparative examples 1 and 2, etc.

[0079] Specifically, as described above, in this embodiment, when a write process is performed, parity data belonging to a plurality of channels is generated in parallel with the period of parallel data transfer for user data, which is set to precede the period of parallel data transfer for parity data. This makes it easier to avoid the decrease in data transfer speed caused by the generation period of parity data as described above. As a result, in this embodiment, it becomes easier to further improve the data transfer speed during write process compared to Comparative Examples 1 and 2.

[0080] <2. Modifications> Although the present invention has been described above by way of the embodiment, the present invention is not limited to this embodiment and various modifications are possible.

[0081] For example, in the above embodiment, the configurations of the host system, the flash memory, and the memory controller, and the configuration of the control circuit are specifically described, but these configurations are not limited to those described in the above embodiment. Specifically, for example, in the above embodiment, the flash memory 1 is a NAND type flash memory, but the present invention is not limited to this example, and for example, a NOR type flash memory may be used as the flash memory 1.

[0082] In the above embodiment, an example in which the parity allocation area Ap is collectively arranged behind the data allocation area Ad along the access order dac in each of the multiple channels has been described. However, the data arrangement setting example in each channel is not limited to this example, and for example, conversely, in each of the multiple channels, the parity allocation area Ap may be collectively arranged ahead of the data allocation area Ad along the access order dac. In addition, the configurations of the number of channels, the number and amount of data in each channel, and the arrangement order when arranging data in each channel are not limited to the examples described in the above embodiment, and may be other configurations.

[0083] Furthermore, in the above embodiment, specific examples of setting data arrangement in each channel by the layout setting unit 222, examples of data access processing (read processing and write processing) by the access processing unit 224, and examples of a method for generating parity data by the parity data generating unit 223 have been given and explained. However, these various processing examples are not limited to those explained in the above embodiment, and these various processing examples may be performed using other methods.

[0084] In addition, the configuration examples and operation examples described so far may be applied in any combination.

Claims

1. A memory controller for controlling a flash memory, a layout setting unit that sets a data arrangement to be applied to a plurality of channels when parallel data transfer is performed between the memory controller and the flash memory using the plurality of channels; an access processing unit that performs the parallel data transfer between the flash memory and the flash memory by using the data arrangement in the plurality of channels set by the layout setting unit when performing data access processing for the flash memory; Equipped with The layout setting unit includes: When arranging the user data and the parity data included in the data, In each of the plurality of channels, With respect to a first allocation area in which the user data is allocated, a second allocation area in which the parity data is allocated is allocated collectively in front or behind the first allocation area in accordance with an access order during the parallel data transfer. Setting the data arrangement in the plurality of channels Memory controller.

2. The layout setting unit includes: In each of the plurality of channels, The second placement area is placed collectively behind the first placement area in the access order, Setting the data arrangement in the plurality of channels The memory controller of claim 1 .

3. a parity data generating unit configured to generate the parity data based on the user data; The parity data generation unit When the data write process is performed as the access process, In parallel with a period of the parallel data transfer for the user data, the period of the parallel data transfer for the parity data being set to precede the period of the parallel data transfer for the user data, generating the parity data belonging to each of the plurality of channels; The memory controller of claim 2 .

4. The access processing unit includes: When performing the data read process or the data write process as the access process, According to the data arrangement set in each of the plurality of channels, The parallel data transfer is performed in accordance with the access order for each of the user data in the first allocation area and the parity data in the second allocation area.

4. The memory controller according to claim 1.

5. A memory controller according to any one of claims 1 to 4, The flash memory; A flash memory system comprising:

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