Logic Circuit

Abstract

To provide a logic circuit that achieves a higher speed of operation and reduces malfunctions.SOLUTION: A logic circuit has a first circuit including a static type D flip-flop and a second circuit including a dynamic type D flip-flop. A clock signal and a first reset signal are inputted into the first circuit. The first circuit outputs a second reset signal generated by synchronizing the first reset signal with the clock signal. Into a second circuit, the clock signal and a signal based on the second reset signal are inputted.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to logic circuits. [Background technology]

[0002] D flip-flops are applied to various logic circuits. Patent Document 1 discloses a clock signal generating circuit including a ring counter. The ring counter includes three D flip-flops connected in cascade. The output signal of the third stage is input to the input terminal of the first stage D flip-flop, and the three D flip-flops form a ring shape. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-12944 A Summary of the Invention [Problem to be solved by the invention]

[0004] In logic circuits including D flip-flops such as the ring counter described in Patent Document 1, there is a demand for faster operation and reduced malfunction.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a logic circuit which realizes faster operation and reduced malfunctions. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor device having a first circuit including a static D flip-flop and a second circuit including a dynamic D flip-flop, wherein a clock signal and a first reset signal are input to the first circuit, the first circuit outputs a second reset signal generated by synchronizing the first reset signal with the clock signal, and the clock signal and a signal based on the second reset signal are input to the second circuit. The time when the initial state of the first circuit is released based on the first reset signal is before the time when the potential of the clock signal starts to change. A logic circuit is provided. Effect of the Invention

[0007] According to the present invention, a logic circuit is provided that realizes faster operation and fewer malfunctions. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a PLL including a frequency divider circuit according to a first embodiment. [Diagram 2] 2 is a circuit diagram showing a configuration of a frequency divider circuit according to the first embodiment. FIG. [Diagram 3] 1 is a circuit diagram of a dynamic D flip-flop according to a first embodiment. [Figure 4] FIG. 1 is a circuit diagram of a static D flip-flop according to a first embodiment. [Diagram 5] 4A to 4C are schematic diagrams illustrating the operation of the static D flip-flop according to the first embodiment. [Figure 6] 4 is a timing chart showing the operation of the frequency divider circuit according to the first embodiment. [Figure 7] FIG. 11 is a circuit diagram showing a configuration of a frequency divider circuit according to a comparative example. [Figure 8] 6 is a timing chart showing an operation of a frequency divider circuit according to a comparative example. [Figure 9] 11 is a timing chart illustrating a malfunction in a frequency divider circuit according to a comparative example. [Figure 10] FIG. 11 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a second embodiment. [Figure 11]FIG. 11 is a block diagram of a device according to a third embodiment. [Figure 12] FIG. 13 is a block diagram of an apparatus according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The same elements or corresponding elements in multiple drawings are denoted by the same reference numerals, and the description thereof may be omitted or simplified.

[0010] [First embodiment] In this embodiment, a frequency divider circuit, which is an example of a logic circuit to which the present invention can be applied, and a PLL (Phase Locked Loop) including the frequency divider circuit will be described. Fig. 1 is a block diagram showing a schematic configuration of a PLL including a frequency divider circuit according to this embodiment. The PLL includes a phase frequency detector PFD, a charge pump CP, a low-pass filter LPF, a voltage controlled oscillator VCO, and a frequency divider circuit DIV.

[0011] The phase frequency detector PFD receives the external reference clock signal REF_CLK and the feedback clock signal FB_CLK from the frequency divider circuit DIV, and detects the phase and frequency differences between the reference clock signal REF_CLK and the feedback clock signal FB_CLK.

[0012] The charge pump CP outputs a control voltage VCNT corresponding to the detected phase difference to the voltage controlled oscillator VCO via a low pass filter LPF. Here, the low pass filter LPF performs operations such as reducing the AC component of the voltage signal output from the charge pump CP. The voltage controlled oscillator VCO oscillates at a frequency corresponding to the control voltage VCNT and outputs a clock signal CLK having a frequency corresponding to the control voltage VCNT.

[0013] The clock signal CLK is input to the frequency divider circuit DIV. The frequency divider circuit DIV divides the frequency of the input clock signal CLK by 1 / N (N is a positive integer) to generate a feedback clock signal FB_CLK. The feedback clock signal FB_CLK is fed back to the phase frequency detector PFD. A reset signal RST for resetting the frequency divider circuit DIV is input from the outside to the frequency divider circuit DIV.

[0014] The PLL performs feedback control so that the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK, which is the divided output of the voltage-controlled oscillator VCO, is constant. As a result, the PLL outputs a clock signal CLK synchronized with the reference clock signal REF_CLK. In addition, the frequency divider circuit DIV divides the frequency of the clock signal CLK by 1 / N during feedback, so the frequency of the clock signal CLK is N times that of the reference clock signal REF_CLK.

[0015] Next, an example of the configuration of the above-mentioned frequency divider circuit DIV will be described in more detail. Fig. 2 is a circuit diagram showing the configuration of the frequency divider circuit DIV according to this embodiment. The frequency divider circuit DIV has a reset synchronization unit 10, a frequency divider unit 20, and an inverter INV2. A clock signal CLK is input to the reset synchronization unit 10 and the frequency divider unit 20 from a voltage controlled oscillator VCO. A reset signal RST is input to the reset synchronization unit 10 from the outside.

[0016] The reset synchronization unit 10 (first circuit) is a circuit that generates and outputs a reset synchronization signal RSTB_SYNC (second reset signal) by synchronizing an externally input reset signal RST (first reset signal) with a clock signal. The reset synchronization unit 10 has three cascaded static type D flip-flops 11, 12, and 13 and an inverter INV1. In the following, the static type D flip-flop may also be referred to as ST_DFF. Each of the ST_DFFs 11, 12, and 13 has an input terminal D, an output terminal Q, a clock terminal CK, and a reset terminal RB.

[0017] A clock signal CLK is input to the clock terminal CK of ST_DFF11, 12, and 13. The input terminal D of ST_DFF11 is connected to the power supply line VDD having a high-level power supply potential. The output terminal Q of ST_DFF11 is connected to the input terminal D of ST_DFF12. The output terminal Q of ST_DFF12 is connected to the input terminal D of ST_DFF13. The output terminal Q of ST_DFF13 is the output terminal of the reset synchronization section 10, and is connected to the input terminal of the inverter INV2. Note that the output signals from the output terminals Q of ST_DFF11 and 12 may be referred to as Q11 and Q12, respectively.

[0018] A reset signal RST is input to the input terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the reset terminals RB of ST_DFF11, 12, and 13. When the reset signal RST is at a high level, it is inverted by the inverter INV1, and a low-level signal is input to the reset terminals RB of ST_DFF11, 12, and 13. At this time, the level of the output terminals Q of ST_DFF11, 12, and 13 is reset to a low level.

[0019] The frequency dividing unit 20 (second circuit) is a circuit that divides the frequency of the clock signal CLK by 1 / 5 by receiving a signal based on the clock signal CLK and the reset synchronization signal RSTB_SYNC. The frequency dividing unit 20 has five dynamic D flip-flops 21, 22, 23, 24, 25 connected in cascade and an inverter INV3. Note that, hereinafter, the dynamic D flip-flops may also be referred to as D_DFFs. Each of the D_DFFs 21 and 22 has an input terminal D, an output terminal Q, a clock terminal CK, and a set terminal S. Each of the D_DFFs 23, 24, 25 has an input terminal D, an output terminal Q, a clock terminal CK, and a reset terminal RB.

[0020] A clock signal CLK is input to the clock terminal CK of D_DFF21, 22, 23, 24, and 25. The output terminal Q of D_DFF21 is connected to the input terminal D of D_DFF22, which is connected to the input terminal D of D_DFF23. The output terminal Q of D_DFF23 is connected to the input terminal D of D_DFF24, which is connected to the input terminal D of D_DFF25. The output terminal Q of D_DFF25 is connected to the input terminal D of D_DFF21. In this way, D_DFF21, 22, 23, 24, and 25 configure a ring counter. Note that the output signals from the output terminal Q of D_DFF21, 22, 23, 24, and 25 may be referred to as Q0, Q1, Q2, Q3, and Q4, respectively.

[0021] The inverter INV2 outputs an inverted signal of the reset synchronization signal RSTB_SYNC to the frequency division unit 20. The inverted signal of the reset synchronization signal RSTB_SYNC is input to the set terminals S of D_DFF21 and 22. A signal obtained by further inverting the inverted signal of the reset synchronization signal RSTB_SYNC by the inverter INV3, i.e., a signal at the same level as the reset synchronization signal RSTB_SYNC, is input to the reset terminals RB of D_DFF23, 24, and 25.

[0022] In the initial state, the reset synchronization signal RSTB_SYNC is at a low level. At this time, a high-level signal is input to the set terminals S of D_DFF21 and 22, and a low-level signal is input to the reset terminals RB of D_DFF23, 24, and 25. As a result, the levels of the output terminals Q of D_DFF21 and 22 are set to a high level, and the levels of the output terminals Q of D_DFF23, 24, and 25 are reset to a low level. When the reset synchronization signal RSTB_SYNC becomes a high level and the initial state is released (reset is released), the frequency division unit 20 starts a frequency division operation in synchronization with the clock signal CLK. The frequency division number at this time is determined according to the number of dynamic D flip-flops. In this embodiment, the number of dynamic D flip-flops is five, and therefore the frequency division number is five. The output terminal of the frequency division circuit DIV may be any one of the output terminals Q of D_DFF21, 22, 23, 24, and 25. That is, the frequency divider circuit DIV outputs any one of the output signals Q0, Q1, Q2, Q3, and Q4 as the feedback clock signal FB_CLK.

[0023] Next, an example of the configuration of the above-mentioned D flip-flop will be described in more detail. Fig. 3(a) and Fig. 3(b) are circuit diagrams of dynamic D flip-flops according to this embodiment. Fig. 3(a) is an example of a circuit diagram of D_DFF21, 22 which are dynamic D flip-flops having a set terminal S. Fig. 3(b) is an example of a circuit diagram of D_DFF23, 24, 25 which are dynamic D flip-flops having a reset terminal RB.

[0024] First, a configuration example of D_DFF21, 22 will be described with reference to Fig. 3(a). Each of D_DFF21, 22 includes switches SW1, SW2, a NOR circuit NO1, an NMOS transistor NM, and an inverter INV4. D, S, Q, and CK in Fig. 3(a) correspond to the terminals of D_DFF21, 22 shown in Fig. 2. A clock terminal CKB in Fig. 3(a) indicates a terminal to which an inverted signal of a clock signal CLK input to the clock terminal CK is input, although this is not shown in Fig. 2. The switches SW1, SW2 are turned on when the signals input to the clock terminals CKB, CK, respectively, are at high levels.

[0025] The input terminal D is connected to a first terminal of the switch SW1. The second terminal of the switch SW1 is connected to a first input terminal of the NOR circuit NO1. The set terminal S is connected to a second input terminal of the NOR circuit NO1 and the gate of the NMOS transistor NM. The output terminal of the NOR circuit NO1 is connected to a first terminal of the switch SW2. The second terminal of the switch SW2 is connected to the drain of the NMOS transistor NM and the input terminal of the inverter INV4. The source of the NMOS transistor NM is connected to a ground line GND having a ground potential. The output terminal of the inverter INV4 is connected to the output terminal Q.

[0026] C1 in Fig. 3(a) indicates a parasitic capacitance including a gate capacitance of the first input terminal of the NOR circuit NO1. C2 in Fig. 3(a) indicates a parasitic capacitance including a gate capacitance of the input terminal of the inverter INV4. Although these parasitic capacitances may exist between various nodes, in Fig. 3(a) these parasitic capacitances are illustrated as ground capacitances between the corresponding nodes and the ground line GND for the sake of simplicity.

[0027] In the initial state where the reset synchronization signal RSTB_SYNC is at a low level, the potential of the set terminal S is at a high level, and the NMOS transistor NM is turned on. At this time, the potential of the input node QB of the inverter INV4 is at a low level, and a high-level signal is output to the output terminal Q.

[0028] When the initial state is released, the potential of the node of the set terminal S becomes low level. After that, the PLL starts operating, and as the clock signal CLK repeatedly transitions between high and low levels, the switches SW1 and SW2 alternately turn on and off. When the switch SW1 changes from off to on, the parasitic capacitance C1 is charged or discharged depending on the level of the input terminal D. When the switch SW2 changes from off to on, the parasitic capacitance C2 is charged or discharged depending on the level of the output terminal of the NOR circuit NO1.

[0029] Next, a configuration example of D_DFF23, 24, and 25 will be described with reference to Fig. 3(b). Each of D_DFF23, 24, and 25 includes switches SW3 and SW4, a NAND circuit NA1, a PMOS transistor PM, and an inverter INV5. D, RB, Q, and CK in Fig. 3(b) correspond to the terminals of D_DFF23, 24, and 25 shown in Fig. 2. The clock terminal CKB denotes a terminal to which an inverted signal of the clock signal CLK is input, as in Fig. 3(a). The switches SW3 and SW4 are turned on when the signals input to the clock terminals CKB and CK, respectively, are at high level.

[0030] The input terminal D is connected to a first terminal of the switch SW3. The second terminal of the switch SW3 is connected to a first input terminal of the NAND circuit NA1. The reset terminal RB is connected to a second input terminal of the NAND circuit NA1 and the gate of the PMOS transistor PM. The output terminal of the NAND circuit NA1 is connected to a first terminal of the switch SW4. The second terminal of the switch SW4 is connected to the drain of the PMOS transistor PM and the input terminal of the inverter INV5. The source of the PMOS transistor PM is connected to a power supply line VDD having a power supply potential. The output terminal of the inverter INV5 is connected to the output terminal Q.

[0031] C3 in Fig. 3(b) indicates a parasitic capacitance including the gate capacitance of the first input terminal of the NAND circuit NA1. C4 in Fig. 3(b) indicates a parasitic capacitance including the gate capacitance of the input terminal of the inverter INV5. As in Fig. 3(a), these parasitic capacitances are also illustrated as ground capacitances between the corresponding nodes and the ground line GND.

[0032] In the initial state where the reset synchronization signal RSTB_SYNC is at a low level, the potential of the reset terminal RB is at a low level, and the PMOS transistor PM is turned on. At this time, the potential of the input node QB of the inverter INV5 is at a high level, and a low-level signal is output to the output terminal Q.

[0033] When the initial state is released, the potential of the node of the reset terminal RB becomes high level. After that, the PLL starts operating, and the clock signal CLK repeatedly transitions between high level and low level, causing the switches SW3 and SW4 to alternately turn on and off. When the switch SW3 changes from off to on, the parasitic capacitance C3 is charged or discharged according to the level of the input terminal D. When the switch SW4 changes from off to on, the parasitic capacitance C4 is charged or discharged according to the level of the output terminal of the NAND circuit NA1.

[0034] As described above, the dynamic D flip-flops D_DFF21, 22, 23, 24, and 25 all have a circuit configuration that uses charging and discharging of parasitic capacitance to hold data. The charging and discharging are performed by the clock signal CLK repeatedly transitioning between high and low levels.

[0035] Fig. 4 is a circuit diagram of a static D flip-flop according to this embodiment. Fig. 4 is an example of a circuit diagram of ST_DFF11, 12, and 13, which are static D flip-flops having a reset terminal RB.

[0036] Each of ST_DFF11, 12, and 13 has switches SW5, SW6, SW7, and SW8, inverters INV6, INV7, INV8, and INV9, and NAND circuits NA2 and NA3. D, RB, Q, and CK in Fig. 4 correspond to the terminals of ST_DFF11, 12, and 13 shown in Fig. 2. The clock terminal CKB indicates a terminal to which an inverted signal of the clock signal CLK is input, as in Fig. 3(a). The switches SW6 and SW7 are turned on when the signal input to the clock terminal CK is at a high level. The switches SW5 and SW8 are turned on when the signal input to the clock terminal CKB is at a high level.

[0037] The input terminal D is connected to the input terminal of the inverter INV6. The output terminal of the inverter INV6 is connected to the first terminal of the switch SW5. The second terminal of the switch SW5 is connected to the input terminal of the inverter INV7 and the first terminal of the switch SW6. The output terminal of the inverter INV7 is connected to the first terminal of the switch SW7 and the first input terminal of the NAND circuit NA2. The output terminal of the NAND circuit NA2 is connected to the second terminal of the switch SW6. The second terminal of the switch SW7 is connected to the first input terminal of the NAND circuit NA3 and the first input terminal of the switch SW8. The reset terminal RB is connected to the second input terminal of the NAND circuit NA2 and the second input terminal of the NAND circuit NA3. The output terminal of the NAND circuit NA3 is connected to the input terminal of the inverter INV8 and the input terminal of the inverter INV9. The output terminal of the inverter INV8 is connected to the second terminal of the switch SW8. The output terminal of the inverter INV9 is connected to the output terminal Q.

[0038] 5(a) and 5(b) are schematic diagrams showing the operation of the static D flip-flop according to this embodiment. The operation of the static D flip-flop will be described with reference to Fig. 5(a) and 5(b) together with Fig. 4.

[0039] In the initial state where the reset signal RST is at a high level, the potential of the reset terminal RB is at a low level. At this point, the clock signal CLK is at a low level. Therefore, the switches SW6 and SW7 are off, and the switches SW5 and SW8 are on. At this time, the output of the NAND circuit NA3 is at a high level, and the output of the inverter INV8 is at a low level. A low-level signal is output to the output terminal Q, which is the output node of the inverter INV9. Figure 5(b) shows a schematic diagram of this state. As shown in Figure 5(b), in the initial state, the NAND circuit NA3 and the inverter INV8 form a loop L2.

[0040] When the initial state is released, the reset signal RST goes low, and the potential of the reset terminal RB goes high. At this point, a low-level potential is supplied from the inverter INV8 to the first input terminal of the NAND circuit NA3, so the output of the NAND circuit NA3 remains high without changing. In this way, even after the initial state is released, the data of the initial state is held by the loop L2.

[0041] After that, when the clock signal CLK becomes high level, the switches SW5 and SW8 are turned off, and the switches SW6 and SW7 are turned on. At this time, the potential of the input terminal of the inverter INV7 is the inverted potential of the input terminal D immediately before the clock signal CLK becomes high level. If the potential of the input terminal D is high level immediately before the clock signal CLK becomes high level, the potential of the input terminal of the inverter INV7 is low level. At this time, the potential of the first input terminal of the NAND circuit NA3 is high level, the output of the NAND circuit NA3 is low level, and a high level signal is output to the output terminal Q which is the output node of the inverter INV9. FIG. 5(a) shows the state at this time. As shown in FIG. 5(a), when the clock signal CLK is high level, the NAND circuit NA2 and the inverter INV7 form a loop L1.

[0042] Thereafter, when the PLL starts operating and the clock signal CLK repeatedly transitions between high and low levels, the state in which the loop L1 holds data (Fig. 5(a)) and the state in which the loop L2 holds data (Fig. 5(b)) are repeated. In this way, the static D flip-flop has a configuration in which the loops in the circuit hold data.

[0043] Next, the operation of the frequency divider circuit DIV of this embodiment will be described. Fig. 6 is a timing chart showing the operation of the frequency divider circuit DIV of this embodiment. Fig. 6 shows a reset signal RST, a clock signal CLK, a reset synchronization signal RSTB_SYNC, output signals Q11 and Q12 of ST_DFF11 and 12, and output signals Q0, Q1, Q2, Q3, and Q4 of D_DFF21, 22, 23, 24, and 25. It is assumed that the frequency divider circuit DIV is disposed in the PLL shown in Fig. 1, and the operation of the PLL may also be mentioned in the description of the operation of the frequency divider circuit DIV.

[0044] In the period before time T11, the frequency divider circuit DIV is in the initial state, and the reset signal RST is at a high level. At this time, the clock signal CLK is at a low level. That is, the reset signal RST and the clock signal CLK are asynchronous when input to the reset synchronization unit 10. In addition, in the initial state, ST_DFF11 and 12 are reset to their initial values, and the output signals Q11 and Q12 are at a low level. D_DFF21 and 22 are set to their initial values, and the output signals Q0 and Q1 are at a high level. D_DFF23, 24, and 25 are reset to their initial values, and the output signals Q2, Q3, and Q4 are at a low level. It is to be noted that in this initial state, the voltage-controlled oscillator VCO is also reset and is not operating.

[0045] At time T11, the reset signal RST goes from high to low, and the initial state is released. This causes a high-level signal to be input to the reset terminals RB of ST_DFF11, 12, and 13, and the initial state of the reset synchronization unit 10 is released. At this time, the initial state of the PLL is also released, and it starts operating. As a result, after time T11, the control voltage VCNT input to the voltage-controlled oscillator VCO gradually increases.

[0046] Time T12 is the time when the control voltage VCNT rises to a level at which the voltage-controlled oscillator VCO can oscillate. From time T12, the voltage-controlled oscillator VCO starts oscillating, and pulses of the clock signal CLK generated by the voltage-controlled oscillator VCO start to be input to the frequency divider circuit DIV. At time T12, the clock signal CLK goes from low to high. In synchronization with this, the output signal Q11 of ST_DFF11 goes from low to high.

[0047] At time T13, the clock signal CLK changes from low to high. In synchronization with this, the output signal Q12 of ST_DFF12 changes from low to high.

[0048] At time T14, the clock signal CLK goes from low to high. In sync with this, the reset synchronization signal RSTB_SYNC output from ST_DFF13 goes from low to high. At this time, the signal input to the set terminals S of D_DFF21 and 22 in the frequency dividing unit 20 goes from high to low. Also, the signal input to the reset terminals RB of D_DFF23, 24, and 25 in the frequency dividing unit 20 goes from low to high. As a result, at time T14, the initial state of the frequency dividing unit 20 is released. After time T14, the frequency dividing unit 20 starts frequency division operation in sync with the clock signal CLK.

[0049] At time T15, the clock signal CLK goes from low to high. In synchronization with this, D_DFFs 21, 22, 23, 24, and 25 output signals of the same level as the output signal of the preceding D_DFF. That is, the output signal Q0 goes from high to low, and the output signal Q2 goes from low to high. The output signals Q1, Q3, and Q4 maintain their previous states.

[0050] At time T16, the clock signal CLK goes from low to high. In synchronization with this, D_DFF21, 22, 23, 24, and 25 output signals of the same level as the output signal of the preceding D_DFF. That is, the output signal Q1 goes from high to low, and the output signal Q3 goes from low to high. The output signals Q0, Q2, and Q4 maintain their previous states. Thereafter, similarly, D_DFF21, 22, 23, 24, and 25 perform an operation of outputting signals of the same level as the output signal of the preceding D_DFF in synchronization with the rising edge of the clock signal CLK. By repeating such an operation, D_DFF21, 22, 23, 24, and 25 function as a ring counter that counts the clock signal CLK. Then, as shown in FIG. 6, the frequency dividing unit 20 divides the clock signal CLK and outputs it as a feedback clock signal FB_CLK (one of the output signals Q0, Q1, Q2, Q3, and Q4).

[0051] After time T14, the frequency of the clock signal CLK output from the voltage controlled oscillator VCO gradually increases over time until it reaches the desired frequency. Therefore, the period of the clock signal CLK gradually decreases as shown in Figure 6. In this way, the PLL can generate a clock signal CLK of a desired frequency that is synchronized with the reference clock signal REF_CLK.

[0052] In reality, the output signals Q0, Q1, Q2, Q3, and Q4 rise with a certain delay from the rising edge of the clock signal CLK due to gate delays, but for simplicity, this delay is not shown in FIG.

[0053] The frequency divider circuit DIV of this embodiment has a reset synchronization section 10 including a static type D flip-flop. The effect of the reset synchronization section 10 will be described below in comparison with a comparative example.

[0054] Fig. 7 is a circuit diagram showing the configuration of a frequency divider circuit DIV according to a comparative example. The frequency divider circuit DIV shown in Fig. 7 differs from the frequency divider circuit DIV in Fig. 2 in that the reset synchronization unit 10 and the inverter INV2 are not provided. As shown in Fig. 7, the reset signal RST is directly input to the frequency divider unit 20. The other configurations are the same as those of the frequency divider circuit DIV in Fig. 2, and therefore will not be described.

[0055] The operation of the frequency divider circuit DIV of the comparative example will be described. Fig. 8 is a timing chart showing the operation of the frequency divider circuit DIV according to the comparative example. Fig. 8 shows a reset signal RST, a clock signal CLK, and output signals Q0, Q1, Q2, Q3, and Q4 of D_DFFs 21, 22, 23, 24, and 25. Note that the frequency divider circuit DIV is assumed to be disposed in the PLL shown in Fig. 1, and the operation of the PLL may also be mentioned in the description of the operation of the frequency divider circuit DIV.

[0056] In the period before time T31, the frequency divider circuit DIV is in the initial state, and the reset signal RST is at a high level. At this time, the clock signal CLK is at a low level. In the initial state, D_DFF21 and 22 are set to their initial values, and the output signals Q0 and Q1 are at a high level. D_DFF23, 24, and 25 are reset to their initial values, and the output signals Q2, Q3, and Q4 are at a low level. In this initial state, the voltage-controlled oscillator VCO is also reset and is not operating.

[0057] At time T31, the reset signal RST goes from high to low, and the initial state is released. At this time, the signal input to the set terminals S of D_DFF21 and 22 in the frequency dividing unit 20 goes from high to low. The signal input to the reset terminals RB of D_DFF23, 24, and 25 in the frequency dividing unit 20 goes from low to high. As a result, at time T31, the initial state of the frequency dividing unit 20 is released. At this time, the initial state of the PLL is also released and starts operating. After time T31, the control voltage VCNT input to the voltage controlled oscillator VCO gradually increases.

[0058] At time T32, the control voltage VCNT rises to a level at which the voltage-controlled oscillator VCO can oscillate. From time T32, the voltage-controlled oscillator VCO starts oscillating, and pulses of the clock signal CLK generated by the voltage-controlled oscillator VCO start to be input to the frequency divider circuit DIV. After time T32, the frequency divider 20 starts a frequency division operation in synchronization with the clock signal CLK.

[0059] At time T32, the clock signal CLK goes from low to high. In synchronization with this, D_DFFs 21, 22, 23, 24, and 25 output signals of the same level as the output signal of the preceding D_DFF. That is, the output signal Q0 goes from high to low, and the output signal Q2 goes from low to high. The output signals Q1, Q3, and Q4 maintain their previous states. After this, the frequency divider circuit DIV of the comparative example performs the operation of dividing the clock signal CLK in the same manner as in FIG. 6.

[0060] As described above, if the frequency divider circuit DIV of the comparative example operates normally as shown in Fig. 8, it can perform frequency division in the same manner as in Fig. 6. However, the frequency divider circuit DIV of the comparative example may malfunction. This malfunction will be described.

[0061] A dynamic D flip-flop is used in the frequency division unit 20 of the frequency division circuit DIV of the comparative example. As shown in FIG. 3(a) and FIG. 3(b), the dynamic D flip-flop holds data using a parasitic capacitance. Therefore, the potential may fluctuate due to the influence of charge leakage. If the level of the clock signal CLK alternates between high and low levels, charging and discharging are performed periodically, so that the influence of such potential does not cause malfunction. However, if the level of the clock signal CLK is fixed at a high or low level for a long period of time, a data error may occur due to charge leakage.

[0062] Fig. 9 is a timing chart for explaining a malfunction in the frequency divider circuit DIV according to the comparative example. Fig. 9 shows a case where a malfunction occurs due to charge leakage in the frequency divider circuit DIV shown in Fig. 7. Fig. 9 shows a reset signal RST, a clock signal CLK, output signals Q0, Q1, Q2, Q3, Q4 of D_DFF21, 22, 23, 24, 25, and internal signals Q2B, Q3B, Q4B of D_DFF23, 24, 25. The internal signals Q2B, Q3B, Q4B correspond to the levels of the input QB of the inverter INV5 in D_DFF23, 24, 25 shown in Fig. 3(b), respectively. Therefore, the internal signals Q2B, Q3B, Q4B are inverted signals of the output signals Q2, Q3, Q4.

[0063] Time T51 corresponds to time T31 in Fig. 8. Just before time T51, the output signals Q0 and Q1 are at high level, and the output signals Q2, Q3, and Q4 are at low level, similar to Fig. 8. At this time, the internal signals Q2B, Q3B, and Q4B are at high level.

[0064] At time T51, after the initial state is released, the charge stored in the parasitic capacitance C4 shown in Fig. 3(b) is gradually discharged over time. Therefore, as shown in Fig. 9, the potentials of the internal signals Q2B, Q3B, and Q4B gradually decrease over time. Note that in D_DFF21 and 22, the level of the input QB of the inverter INV4 shown in Fig. 3(a) is low, so there is no effect due to charge leakage, and this is not shown in Fig. 9.

[0065] At time T52, the potentials of the internal signals Q2B, Q3B, and Q4B become lower than the threshold potential TH of the inverter INV5, causing the output level of the inverter INV5 to invert, and the output signals Q2, Q3, and Q4 change from low level to high level.

[0066] Time T53 corresponds to time T32 in FIG. 8. At time T53, the voltage-controlled oscillator VCO starts oscillating, and the pulses of the clock signal CLK generated by the voltage-controlled oscillator VCO start to be input to the frequency divider circuit DIV. However, since the output signals Q0, Q1, Q2, Q3, and Q4 are all at a high level, the output signals Q0, Q1, Q2, Q3, and Q4 continue to maintain a high level even when the pulses of the clock signal CLK are input. Therefore, the frequency divider circuit DIV cannot perform a frequency division operation. In this way, the frequency divider circuit DIV according to the comparative example may malfunction due to charge leakage.

[0067] The operation of the PLL when the divider circuit DIV malfunctions as described above will be described. The feedback clock signal FB_CLK output from the divider circuit DIV remains at a high level. At this time, the phase frequency detector PFD cannot detect the edge of the feedback clock signal FB_CLK, so it controls the charge pump CP to increase the control voltage VCNT. As the control voltage VCNT increases, the oscillation frequency of the voltage-controlled oscillator VCO also continues to increase, so the PLL does not lock and cannot oscillate at the desired frequency.

[0068] As described above, when the frequency divider circuit DIV is configured solely by the frequency divider unit 20 configured by the dynamic D flip-flop as in the comparative example, a malfunction may occur if the period from the release of the initial state to the input of the clock signal CLK is long. Also, a PLL equipped with such a frequency divider circuit DIV may not be able to oscillate at a desired frequency.

[0069] In contrast, in this embodiment, the frequency division circuit DIV has a reset synchronization unit 10 including a static type D flip-flop. The reset synchronization signal RSTB_SYNC output from the reset synchronization unit 10 becomes high level in synchronization with the pulse of the clock signal CLK. Therefore, the initial state in the frequency division unit 20 is released after the pulse of the clock signal CLK starts to be input. Therefore, the period from the release of the initial state in the frequency division unit 20 to the input of the clock signal CLK is short, so that the possibility of malfunction caused by leakage of electric charge is reduced. In addition, the reset synchronization unit 10 uses a static type D flip-flop, and the static type D flip-flop has a configuration in which data is held in a loop rather than a parasitic capacitance. Therefore, in the reset synchronization unit 10, even if the period from the release of the initial state to the input of the clock signal CLK is long, the possibility of malfunction is low. Therefore, the frequency division circuit DIV of this embodiment realizes a reduction in malfunction.

[0070] Furthermore, when charge leakage occurs in a dynamic D flip-flop, the node may become an intermediate potential. When an intermediate potential is input to a logic gate or the like, a through current may flow, increasing power consumption. Furthermore, when the input to a logic gate or the like becomes an intermediate potential, the circuit operation may become unstable. According to this embodiment, the effects of the increase in power consumption or the instability of the circuit operation as described above may also be reduced.

[0071] The reduction of malfunctions can also be achieved by using a static D flip-flop in the frequency division unit 20. However, since a dynamic D flip-flop can generally operate at a higher speed than a static D flip-flop, it is desirable to use a dynamic D flip-flop in the frequency division unit 20 from the viewpoint of increasing the speed of operation. For example, referring to the inverter INV7 of the static D flip-flop shown in FIG. 4, the output terminal of the inverter INV7 is connected to two, the switch SW7 and the NAND circuit NA2. In contrast, referring to the NAND circuit NA1 of the dynamic D flip-flop shown in FIG. 3(b), the output terminal of the NAND circuit NA1 is connected only to the switch SW4. Thus, in the static D flip-flop, each logic gate circuit is connected to many elements to form a loop, and the parasitic capacitance driven by each logic gate circuit is also large. In contrast, in the dynamic D flip-flop, since no loop is formed, the parasitic capacitance driven by each logic gate circuit is small. Therefore, in general, a dynamic D flip-flop can operate faster than a static D flip-flop. In this manner, in this embodiment, the dynamic D flip-flop is used in the frequency division unit 20, thereby realizing high-speed operation.

[0072] From the above viewpoints, the frequency divider circuit DIV of this embodiment has a reset synchronization unit 10 including a static type D flip-flop and a frequency divider unit 20 including a dynamic type D flip-flop. This allows both high-speed operation and reduced malfunctions. As described above, according to this embodiment, a logic circuit that achieves high-speed operation and reduced malfunctions is provided.

[0073] In this embodiment, the reset synchronization unit 10 includes three stages of static D flip-flops, but is not limited to this and may include, for example, one stage. However, it is preferable that the reset synchronization unit 10 includes multiple stages of static D flip-flops. The reason for this will be explained.

[0074] In the PLL of this embodiment, the frequency of the clock signal CLK immediately after the voltage-controlled oscillator VCO starts oscillating is indefinite. Therefore, the interval between pulses of the clock signal CLK immediately after the voltage-controlled oscillator VCO starts oscillating in FIG. 6, that is, the length of the period from time T12 to time T13, is also indefinite. Here, if the static type D flip-flop included in the reset synchronization unit 10 is one stage, the initial state of the frequency division unit 20 is released at time T12 in FIG. 6. However, since the frequency of the clock signal CLK is indefinite, there is a possibility that the period from time T12 to time T13 (the period of the clock signal CLK) is longer than the period during which the dynamic type D flip-flop of the frequency division unit 20 can hold the initial value. In such a case, there is a possibility that a malfunction occurs in the frequency division unit 20.

[0075] In contrast, in this embodiment, since the reset synchronization unit 10 includes multiple stages of static D flip-flops, the timing at which the initial state of the frequency division unit 20 is released is delayed according to the number of stages of the static D flip-flops. For example, in the example of FIG. 2 and FIG. 6, since the reset synchronization unit 10 includes three stages of static D flip-flops, the initial state of the frequency division unit 20 is released at time T14 when the third pulse is input. As a result, the oscillation frequency of the voltage controlled oscillator VCO at the time when the initial state of the frequency division unit 20 is released becomes higher than when there is one stage of static D flip-flops, and the period of the clock signal CLK can be shortened. This reduces the possibility of malfunction occurring in the frequency division unit 20.

[0076] Furthermore, the possibility of metastable state occurring is reduced by cascading a plurality of static D flip-flops in the reset synchronization unit 10. This also reduces the possibility of malfunction occurring in the reset synchronization unit 10. As described above, the reset synchronization unit 10 includes a plurality of static D flip-flops, which can further reduce the possibility of malfunction occurring in the frequency division circuit DIV.

[0077] In this embodiment, the configuration of the frequency division unit 20 is not limited to the one described above. For example, it may be a circuit other than a ring counter. In addition, the number of dynamic type D flip-flops is not limited to five, and may be changed appropriately according to a desired frequency division number. The circuit configurations of the D flip-flops shown in Figures 3(a), 3(b) and 4 are examples, and other circuit configurations may be adopted. In addition, the circuit configuration of the PLL is not limited to that shown in Figure 1.

[0078] [Second embodiment] The frequency divider circuit of the first embodiment and a PLL including the frequency divider circuit are applicable to, for example, a photoelectric conversion device. In this embodiment, an example in which a PLL including the frequency divider circuit of the first embodiment is applied to a photoelectric conversion device will be described.

[0079] 10 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. The photoelectric conversion device includes a pixel array 101, a column analog-to-digital conversion circuit (hereinafter, column ADC circuit) 102, a column memory 103, a digital readout circuit 104, a PLL 105, a calculation unit 106, a serializer 107, and a transmitter TX. These circuits are formed on a semiconductor substrate. Note that the photoelectric conversion device of this embodiment is an imaging device that acquires an image, but is not limited to this. For example, the photoelectric conversion device may be a focus detection device, a distance measurement device, a TOF (Time-Of-Flight) camera, or the like.

[0080] The pixel array 101 includes a plurality of pixels 100 arranged in a plurality of rows and a plurality of columns, and outputting pixel signals in response to incident light. Each of the pixels 100 includes a photoelectric conversion unit that generates and accumulates a signal charge based on the incident light. The photoelectric conversion unit may be a photodiode. A microlens and a color filter may be disposed in each of the pixels 100. The pixels 100 are controlled row by row by a vertical scanning circuit including a shift register, a gate circuit, a buffer circuit, and the like.

[0081] The column ADC circuits 102 are arranged corresponding to each column of the pixels 100, and convert analog signals output from the pixels 100 into digital data. The converted digital data is stored in the corresponding column memory 103.

[0082] The digital readout circuit 104 may include a horizontal scanning circuit, a signal line for reading out digital data, etc. The horizontal scanning circuit includes a shift register, a gate circuit, a buffer circuit, etc. The horizontal scanning circuit sequentially selects the column memories 103 of each column and outputs the digital data to the calculation unit 106 via the signal line.

[0083] The calculation unit 106 is a signal processing circuit equipped with a digital signal processor. The calculation unit 106 performs digital calculation processes such as digital gain, digital correlated double sampling, digital offset, and linearity correction on the input digital data, and outputs the result to the serializer 107. The serializer 107 performs parallel-to-serial conversion on the input digital data, and outputs the result to the transmitter TX. The transmitter TX outputs the digital data to the outside of the photoelectric conversion device based on a Low Voltage Differential Signaling (LVDS) method or the like.

[0084] The PLL 105 is a PLL including the frequency divider circuit DIV described in the first embodiment. The PLL 105 outputs a clock signal CLK to the serializer 107. The serializer 107 performs parallel-to-serial conversion in synchronization with the clock signal CLK.

[0085] The photoelectric conversion device of this embodiment performs parallel-serial conversion based on the clock signal CLK output from the PLL including the frequency divider circuit DIV described in embodiment 1. As a result, this embodiment provides a photoelectric conversion device that achieves faster operation and reduced malfunctions.

[0086] [Third embodiment] The photoelectric conversion device in the above-described embodiment can be applied to various devices, such as digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, surveillance cameras, etc. Fig. 11 shows a block diagram of a digital still camera as an example of the device.

[0087] The device 7 shown in FIG. 11 includes a barrier 706, a lens 702, an aperture 704, and an imaging device 70 (an example of a photoelectric conversion device). The device 7 further includes a signal processing unit (processing device) 708, a timing generating unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the imaging device 70. The aperture 704 makes the amount of light passing through the lens 702 variable. The imaging device 70 is configured as in the above-mentioned embodiment, and converts the optical image formed by the lens 702 into image data (image signal). Here, it is assumed that an AD (analog-digital) conversion unit is formed on a semiconductor substrate of the imaging device 70. The signal processing unit 708 performs various corrections, data compression, etc. on the imaging data output from the imaging device 70. The timing generating unit 720 outputs various timing signals to the imaging device 70 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to the recording medium 714, and the recording medium 714 is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer, etc. Timing signals, etc. may be input from outside the device. Furthermore, the device 7 may further include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device includes at least a photoelectric conversion device. Furthermore, the device 7 includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (for example, a robot arm) that operates in response to a signal from the photoelectric conversion device.

[0088] In this embodiment, the imaging device 70 and the AD conversion unit are provided on different semiconductor substrates, but the imaging device 70 and the AD conversion unit may be formed on the same semiconductor substrate. Also, the imaging device 70 and the signal processing unit 708 may be formed on the same semiconductor substrate.

[0089] Furthermore, each pixel may include a plurality of photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and to acquire distance information from the imaging device 70 to the subject.

[0090] [Fourth embodiment] FIG. 12(a) and FIG. 12(b) are block diagrams of devices related to the vehicle-mounted camera in this embodiment. The device 8 has an imaging device 80 (an example of a photoelectric conversion device) and a signal processing device (processing device) that processes a signal from the imaging device 80. The device 8 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 80, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the device 8. The device 8 also has a distance measurement unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0091] The device 8 is connected to a vehicle information acquisition device 810, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. In addition, the device 8 is connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. In addition, the device 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, when the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm such as a sound, displaying alarm information on the screen of a car navigation system, etc., and applying vibrations to a seat belt or steering wheel. The device 8 functions as a control means that controls the operation of controlling the vehicle as described above.

[0092] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are captured by the device 8. Fig. 12(b) shows the device when capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810, which serves as an imaging control means, sends an instruction to the device 8 or the imaging device 80 to perform an imaging operation. This configuration can further improve the accuracy of distance measurement.

[0093] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the device is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, in addition to moving bodies.

[0094] [Modified embodiment] The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment of the present invention.

[0095] In the first embodiment, the divider circuit DIV and the PLL including the divider circuit DIV are shown as an example of a logic circuit, but the present invention is applicable to various logic circuits including dynamic D flip-flops. For example, the present invention is also applicable to a serializer and a deserializer, that is, a data conversion circuit that converts one of serial data and parallel data into the other. In this case, the present invention can be applied by configuring the shift register used in the serializer and the deserializer with a dynamic D flip-flop and supplying a reset signal to the shift register from a circuit having a similar configuration to the reset synchronization unit 10.

[0096] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) for implementing one or more of the functions.

[0097] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0098] 10 Reset Synchronization Section 11-13 Static D Flip-Flop (ST_DFF) 20 frequency divider 21-25 Dynamic D Flip-Flop (D_DFF) CLK Clock signal DIV frequency divider circuit RST Reset signal RSTB_SYNC Reset sync signal

Claims

1. a first circuit including a static D flip-flop; a second circuit including a dynamic D flip-flop; having a clock signal and a first reset signal are input to the first circuit; the first circuit outputs a second reset signal generated by synchronizing the first reset signal with the clock signal; the second circuit receives the clock signal and a signal based on the second reset signal; The time when the initial state of the first circuit is released based on the first reset signal is before the time when the potential of the clock signal starts to change.

1. A logic circuit comprising:

2. The first reset signal is asynchronous to the clock signal when input to the first circuit.

2. The logic circuit according to claim 1 .

3. The second circuit includes a ring counter having the dynamic D flip-flop.

3. The logic circuit according to claim 1 or 2.

4. The second circuit is a frequency divider circuit.

4. The logic circuit according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

5. the second circuit includes n dynamic D flip-flops (n is a number equal to or greater than 1); The second circuit performs frequency division by a frequency division number corresponding to the number n.

5. The logic circuit according to claim 4.

6. the second circuit includes, as the dynamic D flip-flop, a dynamic D flip-flop having a set terminal; The second circuit further includes a dynamic D flip-flop having a reset terminal.

6. The logic circuit according to claim 1,

7. The first circuit includes a plurality of the static D flip-flops connected in cascade.

7. The logic circuit according to claim 1,

8. The time when the initial state of the second circuit is released based on the second reset signal is later than the time when the potential of the clock signal starts to vary.

8. The logic circuit according to claim 1, wherein the first and second inputs are connected to the first and second inputs.

9. A logic circuit according to any one of claims 1 to 8. A PLL (Phase Locked Loop) characterized in that:

10. A logic circuit according to any one of claims 1 to 8, Converts serial data to parallel data and vice versa A data conversion circuit comprising:

11. A logic circuit according to any one of claims 1 to 8. A photoelectric conversion device comprising:

12. The photoelectric conversion device according to claim 11 ; an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; A storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. An apparatus characterized by:

13. The processing device processes the image signals generated by the plurality of photoelectric conversion units, and obtains distance information from the photoelectric conversion devices to a subject.

13. The device of claim 12.

Images