Multilayer circuit boards having traces thicker than the circuit board layers

Abstract

Multilayer circuit boards are formed from multiple layers of catalyst layers, each catalyst layer having an exclusion depth below the surface, and catalyst particles of sufficient density to achieve electroless deposition in channels formed in the surface. A first catalyst layer has channels formed that are plated with electroless copper. Each subsequent catalyst layer is bonded or laminated to the underlying catalyst layer, forming channels that extend through the catalyst layer to the underlying electroless copper traces, and electroless copper is deposited in the channels to electrically connect with the underlying electroless copper traces. In this manner, traces having thicknesses greater than the thickness of a single catalyst layer can be formed.

Description

[Technical field]

[0001] The present invention relates to a multilayer printed circuit board formed of at least two catalyst layers having traces having a depth formed continuously across at least two catalyst layers using electroless deposition in channels formed in adjacent catalyst layers to form traces having a dimensional thickness spanning more than one catalyst layer. [Background technology]

[0002] Prior art printed circuit boards (PCBs) are formed using a subtractive process by etching sheets of copper laminated to a substrate using a patterned resist to form conductive metal interconnects (known as "traces") on the dielectric substrate, where each conductor-carrying side is known as a "layer." Each dielectric core has traces formed on one or both sides, and a multilayer printed circuit can be formed by stacking several such dielectric cores with traces formed on one or more sides and laminating them together under temperature and pressure by inserting a bare dielectric layer. The dielectric substrate comprises an epoxy resin embedded in a fibrous matrix, such as glass fibers woven into a cloth. In one prior art manufacturing method, copper is laminated onto the outer surface of a dielectric layer, and the copper surface is patterned with a photoresist or photosensitive film, or the like, to create masked and unmasked areas, and then etched to form a conductive trace layer on one or both sides of the core dielectric. The stack of dielectric cores with conductive traces can then be laminated together to form a multi-layer circuit board and any interlayer trace interconnections made of vias, which are drilled holes that are plated with copper to form annular rings that provide connectivity from one layer to another.

[0003] Printed circuit boards (PCBs) are typically used to implement conductive traces between various electronic components that are mounted on the PCB. The dimension of the trace parallel to the plane of the laminate is considered the trace width, and the dimension of the trace perpendicular to the plane of the laminate is considered the trace thickness. One type of electronic component is a through-hole device that is mounted on the PCB by positioning leads through one or more holes in the PCB, where the PCB holes include conductive annular ring pads on each trace connection layer, and the component leads are soldered to the annular ring pads of the PCB holes. Although through-hole components have leads that tend to be difficult to align with the associated PCB mounting holes, surface mount technology (SMT) provides a preferred mounting system, where the component leads are simply placed and soldered onto the surface of a PCB pad or land, and is preferred in PCB assembly due to the smaller size and high density of SMT components, and the ease of mechanized assembly compared to through-hole components. Surface mount components require only surface mount pads, which provide surface solder terminals on the externally finished PCB layers. In a two-layer or multi-layer PCB, the interconnection of conductive traces from one layer to another is accomplished using through-hole vias, where conductive traces on one trace layer are typically drilled through one or more dielectric layers of the PCB to holes that are plated with copper or other conductive metal to complete the trace layer connection. Holes that are drilled through all dielectric layers are known as through-vias, holes that are drilled only through the outer layers (typically as part of the manufacture of individual layers) are known as microvias, and holes that are drilled through one or more inner layers are known as blind vias. In either of these via types, the vias are patterned to include annular ring conductive areas on opposing trace layers of the PCB, and the drilled holes are aligned with conductive material connecting the annular ring conductors on either side of the stack or PCB.

[0004] The thickness of pre-patterned or post-patterned copper on a printed circuit board laminate can be increased using electroplating, where a PCB or dielectric layer with traces is placed in an electrolytic bath and a DC power source is connected between a sacrificial anode conductor electrode (such as a copper rod) that forms two electrodes between which a DC current can be applied, and an electrode that is clamped or attached to an existing conductive layer of the PCB. If there is no existing conductive copper layer on the PCB to facilitate electroplating, such as in the case of a bare dielectric layer or drilled via holes, a seed layer of copper must first be deposited. This is done using an electroless process aided by a "seed" catalytic material (which enhances the deposition of certain conductive materials) that is deposited on the surface of the dielectric, and then the board is placed in the electroless bath. In an electroless bath with a catalyst such as palladium and copper, copper ions in solution deposit on the palladium until the surface is sufficiently covered to achieve homogenous electrical conductivity, and then the copper deposited using the electroless process provides a conductive scaffold for the subsequent addition of material using an electroplating process. Electroplating is preferred for completing the plating operation because it has a faster deposition rate than electroless plating processes.

[0005] As electronic assemblies become more complex, there is a desire to increase component density on PCB assemblies, such as by using narrower trace widths (known as fine pitch traces) in combination with increasingly dense integrated circuit (IC) lead patterns. One problem with prior art surface mount PCB manufacturing and assembly methods is that because the traces are formed on the surface of the dielectric, the adhesion between the copper traces and the underlying laminate for the narrower conductor line widths (known as fine pitch traces) is reduced, and during component replacement operations, the fine pitch traces and component pads separate (lift up), ruining the entire circuit board assembly and the expensive components thereon. Another problem with fine pitch surface traces is that when manufacturing multilayer circuit boards, the individual trace layers are laminated together under the pressure of an elevated temperature environment. During lamination, the fine pitch traces have a tendency to move laterally across the surface of the dielectric. High speed circuit board layout and design, especially in (edge-coupled) differential pair transmission lines, require maintaining a fixed impedance between the traces. This lateral movement of the traces during lamination causes the transmission line impedance of the finished PCB differential pair to vary over the length of the trace, which results in reflections and losses in the transmission line compared to having a fixed impedance characteristic resulting from constant spacing.

[0006] When traces are formed using subtractive methods, such as etching a copper foil surface layer to form the traces, lower resistance traces can be formed using electroplating to increase the thickness of the trace on the outer surface to lower the trace resistance, or by widening the trace on the top surface to lower the current density in the trace. However, copper spill into the surrounding areas and increasing the width of the traces makes it difficult to electroplate more than 3 ounces of copper, limiting the thickness of copper that can be electroplated. Typically, during circuit board design, the traces are made wider, which consumes available mounting area on the board. Alternatively, the traces can be duplicated on a lower trace layer to form parallel traces on separate inner trace layers separated by a dielectric, where the inner layer is typically formed from a thinner base copper, such as 1 / 2 ounce copper (about 0.5 mils thick). Alternatively, the traces can be formed in the channel using Applicant's additive processes such as those described in U.S. Patent Nos. 9,706,650, 9,380,700, 9,674,967, and 9,631,279. It is also possible to increase the width of the traces of these additive processes formed in the channel to reduce the trace resistance, subject to the same limitations to increasing the width of the traces to support higher current densities. It would be desirable to provide traces with lower resistance than achieved by prior art processes, without increasing the width of the traces. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent No. 9,706,650 [Patent Document 2] U.S. Patent No. 9,380,700 [Patent Document 3] U.S. Pat. No. 9,674,967 [Patent Document 4] U.S. Pat. No. 9,631,279 Summary of the Invention [Problem to be solved by the invention]

[0008] A first object of the present invention is to provide a circuit board having a first catalyst layer formed from either a catalyst stack or a catalyst adhesive having traces having a width and a depth, the traces being formed into channels that are filled with a conductive metal using electroless deposition, the first catalyst layer being laminated to a second catalyst layer formed from either a catalyst stack or a catalyst adhesive, the second catalyst layer having channels formed through the thickness of the second catalyst layer to the traces of the first catalyst layer, the channels being filled with a conductive metal such as from electroless deposition to form a circuit board having elongated traces having a depth greater than the thickness of a single layer of the circuit board and having elongated trace spans, the electroless deposition of the first catalyst layer being in electrical contact with the electroless deposition of the second catalyst layer.

[0009] A second object of the present invention is a process for forming a circuit board, the process comprising: forming a channel having a width and a depth in a first catalyst layer formed from either a catalyst stack or a catalyst adhesive; electrolessly plating a conductive trace into the first catalytic layer; laminating a second catalyst layer formed from either a catalyst stack or a catalyst adhesive to the first catalyst layer; forming a channel in the second catalyst layer having a width and a depth, the channel depth reaching the conductive trace of the first catalyst layer; electrolessly plating conductive traces into a second catalyst layer in electrical contact with the conductive traces of the first catalyst layer; Includes.

[0010] A third object of the present invention is a multilayer circuit board having at least one trace formed in a first catalyst layer formed from either a catalyst laminate or a catalyst adhesive, the first catalyst layer having a channel filled with electroless deposition of a conductive metal, the first catalyst layer adjacent to a subsequent adjacent catalyst layer, each adjacent catalyst layer formed from a catalyst adhesive or catalyst laminate and adhered or laminated to the previous catalyst layer, having a channel formed and deposited with electroless metal into the channel, the metal deposition extending into the electroless metal deposition of the previous adjacent layer, thereby forming a homogenous trace having a trace depth spanning at least two catalyst layers. [Means for solving the problem]

[0011] In a first embodiment of the invention, a first catalyst layer formed from either a catalyst stack or a catalyst adhesive has catalyst particles with an exclusion depth below at least one surface of the catalyst layer, and the catalyst layer has channels formed to at least one surface of the catalyst layer with a depth of at least the exclusion depth, thereby exposing the catalyst particles. The channels of the first catalyst layer are exposed to electroplating of a conductive metal, such as copper, for a time sufficient for deposition of the metal having a thickness from the bottom of the channel to a depth near the surface of the first catalyst layer. The first catalyst layer is bonded or laminated to a second catalyst layer, at least one channel is formed in the second catalyst layer that extends through the thickness of the second catalyst layer to the metal deposit on the first catalyst layer, and then the second catalyst layer channel is electrolessly plated to a depth from the metal deposit of the first catalyst layer to the surface of the second catalyst layer, thereby forming a trace having a depth deeper than a single catalyst layer. Additional catalyst layers can be adhered or laminated to previous catalyst layers, each having a channel of sufficient depth formed in the metal deposit underlying the adjacent catalyst layer, and electroless deposition plating to form a trace having a trace depth that extends through each additional catalyst layer, forming a trace having a depth that extends through several catalyst layers, each catalyst layer providing a channel of sufficient depth.

[0012] In a second embodiment of the invention, the catalyst layer is formed as either a catalyst stack or a catalyst adhesive. The catalyst stack is formed by curing a mixture of resin, catalyst particles, and fiber mesh, the catalyst particles having an exclusion depth below the surface of the catalyst stack. The catalyst adhesive is formed as a mixture of resin and catalyst particles that is cured on an underlying surface, the surface of the cured catalyst adhesive having an exclusion depth of the catalyst particles below the surface of the cured catalyst adhesive. In this embodiment, the trace is formed with a depth of multiple catalyst layers, with a channel formed with a first catalyst layer, the channel being deposited with metal using electroless plating to fill the channel substantially to the surface layer. The first catalyst layer is then bonded or laminated to one or more subsequent catalyst layers, each subsequent catalyst layer having a channel formed with electrolessly plated metal through the catalyst layer to the level of the first catalyst layer, and then electroless copper is deposited on the face of each subsequent layer into the channel, thereby achieving a trace of continuous depth across the multiple catalyst layers, with the resulting trace having a thickness greater than that of a single catalyst layer and spanning the depth of the multiple catalyst layers forming the trace. Lamination of the subsequent catalyst stack to the formed channel and underlying catalyst stack layer can be performed with electroless deposition after each lamination and channel formation step, or the channel can be formed and electrolessly plated through the multiple catalyst stack layers in a single step. In one example of the invention, the steps of performing successive lamination of catalyst stacks, forming a channel in the catalyst stack after each lamination, and electrolessly plating each channel are performed in a repeating sequence until the desired trace depth is formed.

[0013] In a third embodiment of the present invention, a process for forming traces in a catalyst layer formed from either a catalyst stack or a catalyst adhesive has at least one trace formed continuously in a channel, the resulting trace having a thickness greater than the depth of a single catalyst layer, the process comprising: forming channels in one or more faces of the first catalyst layer below the exclusion depth, thereby exposing catalyst particles; electrolessly plating the channel with a conductive metal to approximately the depth of the channel; laminating or adhering one or more additional catalyst layers to the first catalyst layer; forming a channel having a width and depth that extends through the thickness of the additional catalytic layer to the electroless metal deposit of the previous catalytic layer; performing an electroless deposition of a conductive metal in the channels of each additional catalytic layer in electrical contact with the previously deposited electroless plating of an adjacent catalytic layer; Includes. [Brief description of the drawings]

[0014] [Figure 1] 4 is a cross-sectional view and a corresponding plot of catalyst particle distribution in a catalyst bed associated with the cross-sectional view of the catalyst bed. [Figure 2A] FIG. 1 is a schematic diagram showing a switching power supply circuit having pulsating currents among certain components. [Figure 2B] 2B is a waveform plot for the switching power supply circuit of FIG. 2A. [Figure 2C] FIG. 2B is a plan view showing a printed circuit board layout for a portion of the power supply circuit of FIG. 2A. [Figure 3A] FIG. 2 is a cross-sectional view showing a catalyst prepreg laminate layer. [Figure 3B] FIG. 3B shows FIG. 3A after forming channels in the surface layer. [Figure 3C] FIG. 3B after deposition of metal traces, such as by electroless deposition. [Figure 3D] FIG. 3D shows FIG. 3C after a second catalyst prepreg layer has been adhered or laminated to the previous catalyst prepreg layer. [Figure 3E] FIG. 3D shows the result after forming channels having a depth through the thickness of the prepreg reaching the electroless deposition of the first layer added to FIG. 3C. [Figure 3F] FIG. 3E shows after electroless deposition of metal in contact with the electrolessly deposited traces of FIG. 3C. [Figure 3G]FIG. 3C illustrates an optional additional step of adding a catalyst layer to the stack of FIG. 3F. [Figure 3H] FIG. 3G after forming channels for a catalyst layer added to FIG. 3G. [Figure 3I] FIG. 3G shows after electroless deposition of metal in contact with the electrolessly deposited traces of FIGS. 3C and 3H. [Figure 4] FIG. 1 illustrates process steps for forming trace layers of various thicknesses using a catalyst layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] FIG. 1 shows an exemplary catalyst prepreg for use in one embodiment of the invention. The catalyst prepreg consists of a matrix of pre-impregnated fibers that are bonded in a resin containing catalyst particles. Many different materials can be used for the fibers of the prepreg, including woven fiberglass cloth, carbon fiber, or other fibers, and a variety of different materials can be used for the resin, including epoxy resin, polyimide resin, cyanate ester resin, PTFE (Teflon) mixed resin, or other resin. While one embodiment of the invention is described for a printed circuit board laminate capable of supporting fine pitch conductive traces on the order of 1 mil (25 u), and for the formation of copper traces using a catalyst in electroless copper formation, it is understood that the scope of the invention can be extended to other materials suitable for electroless and electroplating. For electroless deposition of copper (Cu) channels, elemental palladium (Pd) is preferred as a catalyst, but other metals, including selected transition metal elements of the periodic table, such as groups 9 to 11, platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or other compounds thereof, iron (Fe), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tin (Sn), or mixtures or salts of the above, any of which may be used as the catalyst particle. This candidate list is intended to be exemplary rather than comprehensive, and it is known in the art that other catalysts for attracting copper ions may also be used. In one example of the present invention, the catalyst particle is a homogeneous catalyst particle. In another example of the invention, the catalyst particles are inorganic particles or high temperature resistant plastic particles that are coated with a catalytic metal to a thickness of a few angstroms, thereby forming heterogeneous catalyst particles with a thin catalytic outer surface that encapsulates a non-catalytic inner particle. This formulation may be desirable for larger catalyst particles, such as those on the order of 25 u in maximum dimension.The heterogeneous catalyst particles of this formulation can include inorganic, organic, or inert fillers, such as silicon dioxide (SiO2), inorganic clays such as kaolin, or high temperature plastic fillers, coated on the surface with a catalyst such as palladium absorbed onto the surface of the filler, such as by vapor deposition or chemical deposition. Only a few atomic layers of catalyst are required for the catalyst particles to have the desired properties to be conductive for electroless plating.

[0016] In another example of a catalyst layer formed using a catalyst adhesive, the catalyst adhesive formulation is the same as for the catalyst stack, except that no fibers are introduced into the resin and catalyst particle mixture, and the resin and catalyst particle mixture is applied to the underlying surface and cured, so that the catalyst particles are at an exclusion depth below the surface of the cured catalyst adhesive, similar to the catalyst particle distribution of the catalyst stack layer, thereby allowing electroless plating only in the channels formed and extending below the exclusion depth for the catalyst particles.

[0017] In one example of forming heterogeneous catalyst particles, a bath of (organic or inorganic) filler is sorted by size to include particles with a size of less than 25 u. These sorted inorganic particles are mixed and stirred into an aqueous bath in a tank. A palladium salt such as PdCl (or any other catalyst, such as a silver salt of another catalyst) is then introduced together with an acid such as HCl and a reducing agent such as hydrazine hydrate, whereby the mixture reduces the metallic Pd that coats the inorganic particles, resulting in a coating of Pd several angstroms thick on the filler, thereby creating heterogeneous catalyst particles with the catalytic properties of homogeneous Pd particles with a greatly reduced volume requirement of Pd compared to using homogeneous Pd metal particles. However, for extremely small catalyst particles, on the order of a few nm, homogeneous catalyst particles (such as pure Pd) may be preferred.

[0018] Exemplary inorganic fillers include clay minerals, such as hydrous aluminum phyllosilicates, which may contain varying amounts of iron, magnesium, alkali metal, alkaline earth, and other cations. Exemplary inorganic fillers in this family include silicon dioxide, aluminum silicate, kaolinite (Al2Si2O5(OH)4), polysilicates, or other clay minerals belonging to the kaolin or china clay families. Exemplary organic fillers include PTFE (Teflon) and other polymers with high temperature resistance.

[0019] Examples of palladium salts are BrPd, Cl2Pd, Pd(CN)2, I2Pd, Pd(NO3)2*2H2O, Pd(NO3)2, PdSO4, Pd(NH3)4Br2, Pd(NH3)4Cl2H2O. The catalyst powders of the present invention can also contain a mixture of heterogeneous catalyst particles (e.g., catalytic material coated over inorganic filler particles), homogeneous catalyst particles (such as elemental palladium), and non-catalytic particles (selected from the inorganic filler family).

[0020] Among the catalysts, palladium is the preferred catalyst due to its considerable economics, availability, and mechanical properties, although other catalysts can be used.

[0021] In one method of forming a catalyst laminate, woven glass fibers are fed as a set of rollers injects epoxy resin, mixed with catalyst particles and mixed with a volatile liquid to reduce viscosity, into the fabric, thereby forming an A-stage (liquid) prepreg.

[0022] The resin may be a polyimide resin, a mixture of epoxy and cyanate ester (which results in curing at high temperatures), or any other suitable resin formulation with selectable viscosity during coating and heat-setting properties after cooling. For example, flame retardants can be added to comply with flammability standards or to be compatible with one of the FR series standards for prepregs, such as FR-4 or FR-10. An additional requirement for high speed electrical circuits is the relative permittivity ε (dielectric constant), which is often around 4, governing the characteristic impedance of the transmission line formed on the dielectric, and the loss tangent δ, which is a measure of frequency-dependent energy absorption over distance. The loss tangent is thereby a measure of how the dielectric interacts with high frequency electric fields, unfavorably reducing the signal amplitude by a calculable amount in dB per cm of transmission line length. The resin is mixed with size-sorted catalyst particles. In one example formulation, the catalyst particles include at least one of homogeneous catalyst particles (palladium metal) or heterogeneous catalyst particles (palladium coated over inorganic particles or high temperature plastics), and in both formulations, the catalyst particles are preferably less than 25u, with 50% of the number of particles sized between 12u and 25u, or with a maximum range of 1-25u or less. These are example catalyst particle size embodiments and are not intended to limit the scope of the invention. In one example embodiment, the catalyst particles (either homogeneous or heterogeneous) are in the size range of 1u to 25u. In another example of the invention, the homogeneous catalyst particles are formed by grinding the palladium metal into particles and passing the resulting particles through a sieve with a mesh having a rectangular opening of 25u. In another example, the catalyst resin mixture is formed by mixing the homogeneous or heterogeneous catalyst particles into the prepreg resin by weight ratio, such as a ratio of approximately 12% catalyst particles to resin by weight. The weight ratio of catalyst particles in the resin mixture may alternatively range from 8 to 16% by weight of catalyst particles relative to the total resin weight. It is understood that other mixture ratios may also be used. Also, it may be preferable to use smaller particles.In one example of the present invention, the catalyst particle density is selected to achieve an average inter-catalyst particle distance of the order of 3u to 5u.

[0023] In one example of the invention, to create a resin-rich surface that excludes the catalyst particles, the prepreg sheets positioned near the exterior surface (where the surface will later be removed to expose the underlying catalyst particles) are selected to have more than 65% resin, such as glass 106 (71% resin), glass 1067, or glass 1035 (65% resin), and the interior prepreg sheets (not subject to surface removal) are selected to have less than 65% resin. In addition, to reduce the possibility of glass fibers being near the surface of the catalyst prepreg, woven glass fibers can be used with the interior prepreg layers, and flat, non-woven glass fibers can be used on the outer resin-rich prepreg layers. The combination of resin-rich prepreg and flat, non-woven glass fibers on the exterior layers results in an exclusion zone of 0.7 mils (17 u) to 0.9 mils (23 u) between the exterior surface and the encapsulated glass fibers. Glass styles 106, 1035, and 1067 are preferred for use on the exterior resin-rich surface. This is because the glass fiber thickness is less (1.3-1.4 mils / 33-35 u) than that found in typical prepreg sheets with more than 65% resin used in the center region of the laminate, such as glass style 2116 with 3.7 mil (94 u) fibers. These values ​​are given as an example, and it is expected that the smallest glass fibers commercially available will continue to decrease in diameter. During processing of the catalyst laminate used in the present invention, a temperature vs. time sequence is applied to move the catalyst particles and glass fibers from the outer surface of the laminate and are repelled by the surface tension of the epoxy during the liquid state period at the gel point temperature. After a cooling cycle, the cured C-stage prepreg sheet is offloaded. The process of forming the cured C-stage prepreg sheet can use single or multiple sheets of fiber weave to vary the finished thickness, which can vary from 2 mils (51 u) to 60 mils (1.5 mm). A complete description of the process for forming the catalyst stack, catalyst adhesive, and resin can be found in commonly assigned, US Pat. No. 9,706,650 to the present inventors, which is incorporated by reference.

[0024] FIG. 1 shows the resulting catalyst prepreg 102 formed by the prepreg process, with catalyst particles 114 homogenously distributed within the central region of the prepreg 102, but not below the boundary region 108 below the first face 104, or below the boundary region 110 below the second face 106. This boundary region 110 is a fundamental feature of the catalyst particle exclusion zone, common to both catalyst stacks and catalyst adhesive catalyst layers. In the example particle distribution of particles smaller than 25 u, the catalyst particle boundary is typically 10-12 u below the surface (on the order of half the length of the catalyst particle), and therefore more than this depth of surface material must be removed in order for the embedded catalyst particles to be available for electroless plating. The regions from face 106 to the catalyst particle in region 110 and from face 104 to the catalyst particle in region 108 are referred to in this application as catalyst particle exclusion zones. In one example of the invention, the catalyst particle exclusion zone contains an insufficient density of catalyst particles to allow electroless plating without forming channels below the exclusion depth of the catalyst particles. In another example of the invention, the density of catalyst particles in the exclusion zone is less than 1 / 100 of the catalyst particle density in the non-exclusion zone area of ​​the catalyst stack. In another example of the invention, the exclusion zone area is unable to form a continuous conductor through electroless plating for a given duration, while the area below the exclusion zone is able to form a continuous conductor for the same time interval.

[0025] Prior art catalyst stacks have active surfaces that must be masked to prevent unwanted electroless plating on the active surfaces of the catalyst stack. In contrast, the catalyst stacks and catalyst adhesives of the present invention exclude catalyst particles over the thickness range from the first surface 104 to the first boundary 108 and the second surface 106 to the second boundary 110, providing the benefit of not needing a separate mask layer to prevent contact of catalyst particles for electroless plating as exists in the prior art. Thus, removing surface material from the first surface 104 to the depth of the boundary layer 108 or more, or removing surface material from the second surface 106 to the second boundary 110, exposes catalyst material that can be used for electroless plating. Upon removal of the surface layer in a subsequent step, the resin-rich surface allows for the exclusion of not only the catalyst but also the fiber weave, which would require additional cleaning steps to expose the fibers, and therefore the surface removal is preferably resin only, to expose only the underlying catalyst particles. This is accomplished by using a combination of resin-rich outer prepreg layers and flat, non-woven fiberglass layers with smaller diameter fibers on the outer layers.An added advantage of using electroless plating to form the traces in the channels is that the traces are mechanically supported on three sides, which greatly improves adhesion of the traces to the dielectric laminate.

[0026] 2A shows a prior art buck regulator circuit. When switch 202 is closed, an inductor charging current flows from power source 204 through energy storage inductor 208 to smoothing capacitor 218, raising the voltage on smoothing capacitor 218. When switch 202 is open, an inductor discharging current continues to flow through inductor 208, through diode 212, and capacitor 218. Steady state current I3 drawn by load 214 and steady state current I4 drawn by load 216 are significantly lower than peak pulse current I1 206 through switch 202 or peak pulse current I2 210 through inductor 208, respectively.

[0027] FIG. 2B shows a plot of current waveforms, I1 230 indicating switch opening and closing, inductor current I2 232, and steady state currents I3 234, I4 236.

[0028] FIG. 2C illustrates an example of the effect on a prior art printed circuit board designed for pulse currents versus steady state currents. Inductor 208 corresponds to 208 in FIG. 2A, and capacitor 218A in FIG. 2C corresponds to 218 in FIG. 2A. Trace 237A (corresponding to bold line 237 in the schematic diagram of FIG. 2A) carries the peak pulse current and is therefore related to I2. 2 The width of traces 214A and 216A carrying steady-state currents I3 and I4 (associated with corresponding lines 214 and 216 in FIG. 2A) can be significantly narrower, while they must be relatively wide to reduce R losses. Furthermore, it is typical case that small signal traces are excluded from the power area during printed circuit design to prevent unwanted transient signal coupling from pulsed currents to the small signal traces due to magnetic induction or electrostatic displacement currents through cross-coupling of the traces.

[0029] For this reason, it is desirable to provide a conductive trace that can grow in thickness, but not in width, to form a trace that can utilize the thickness of two or more layers of a multi-layer circuit board.

[0030] The sequence of Figures 3A-3I shows example process steps for understanding the present invention. Figure 3A shows a cross-sectional view of a catalyst stack (or catalyst adhesive) 302 in the catalyst particle distribution plot of Figure 1, where catalyst particles are distributed throughout the inner region of the catalyst layer (either catalyst stack or catalyst adhesive) and catalyst particles are below the surface exclusion depths 306 and 304 of the associated outer surface, thereby achieving a density of catalyst particles 304-306 sufficient to achieve electroless deposition of a conductive metal such as copper in the region extending below the surface catalyst particle exclusion zone and to exclude electroless deposition on the original surface 303 or 307.

[0031] The catalyst particles (not shown) in the region between 304 and 306 may range in size up to 25 u, in this example from 12 u to 25 u. The catalyst particles may include heterogeneous catalyst particles (organic or inorganic particles with a catalytic surface coating) or homogeneous particles (catalytic metal particles) as previously described. The exclusion boundary 304 is approximately 25 u below the first face 303. The second face 307 and the second face exclusion boundary 306 on the opposite face are shown for reference, but it is understood that the process may be used on one or both sides of a candidate catalyst stack or catalyst adhesive.

[0032] FIG. 3B shows the laminate of FIG. 3A with a channel 310 formed by removal of the surface layer 303 below the exclusion zone 304 in the area where tracing is desired. Removal of surface material to form channels in the catalyst laminate or catalyst adhesive 302 may be done by laser cutting, where the temperature of the catalyst prepreg is momentarily increased until the catalyst prepreg evaporates while leaving the surrounding catalyst prepreg structurally unchanged and leaving the catalyst particles exposed. It may be preferable to use a laser with a wavelength that has low reflectivity and high absorption at this wavelength of light for the prepreg material to be cut, such as an ultraviolet (UV) wavelength. Examples of such UV lasers are UV excimer lasers or yttrium aluminum garnet (YAG) lasers, which are also good choices due to their narrow beam range and high available power to form channels of precise mechanical depth with well-defined sidewalls. Example lasers can remove material with diameter widths of 0.9 to 1.1 mils (23 u to 28 u) with depths governed by the laser power and travel speed across the surface. Another surface removal technique for forming the channel 210 is plasma etching, which can be done locally or by preparing the surface with a patterned mask that excludes the plasma from the surface layer 206 or 205, such as a dry film photoresist or other mask material that has a slow plasma etch rate compared to that of the catalyst prepreg. The photoresist thickness is typically selected based on the epoxy / photoresist etch selectivity (so that the plasma etch leaves enough photoresist at the end of the etch to the desired depth of removal of the hardened epoxy), or in the case of a photoresist used as an electroplating mask, the thickness is selected according to the desired deposition thickness. Typical dry film thicknesses are in the range of 0.8-2.5 mils (20-64 u). Suitable plasmas for etching resin-rich surfaces include a mixture of oxygen and CF4 plasma mixed with an inert gas such as nitrogen (N), or argon (Ar) may be added as a carrier gas for the reactive gas.The mask pattern can also be formed with a dry film mask, a metal mask, or any other type of mask with openings. If a mechanical mask is used, the etch resist can be applied using any photolithography, screen printing, stencil, squeegee, or any method of applying etch resist. Another method for removal of the surface layer of the catalyst prepreg is mechanical grinding, such as a linear or rotary cutting tool. In this example, the catalyst prepreg can be fixed to a vacuum plate chuck and a rotating cutter (or a fixed cutter with a moving vacuum plate) can run through a pattern that defines a trace, such as defined by the xy coordinate pairs of a Gerber format photo file. In another example of removing surface material, a water jet cutting tool can be used. Here, a water jet with abrasive particles entrained in the flow can strike the surface, thereby removing material below the first boundary 304. Any of these methods can be used separately or in combination to remove surface material and form a channel 310 from the catalyst prepreg 302. Preferably, the channel extends below the first boundary 304. Thus, the minimum channel depth is the depth required to expose the underlying catalyst particles, which is a characteristic of the cured prepreg. Because the catalyst material is homogeneously distributed throughout the cured prepreg below the exclusion boundary 304, the maximum channel depth may be limited by the depth of the woven fiber (such as fiberglass) fabric, which tends to make cleaning of the channels difficult, as the fibers may tear and redeposit into the channel intended for electroless plating or otherwise interfere with subsequent process steps. Typical channel depths are 1 mil (25 u) to 2 mils (70 u), but may extend deeper into the prepreg to reduce electrical resistance after electroless deposition. The final step after removing the surface material to form the channel 310 is to remove any particles of the removed material, which can be accomplished using ultrasonic cleaning, jets of water mixed with a surfactant, or any other cleaning means that does not result in the removal of the surface 304 material surrounding the channel.Alternatively, the use of a fiber-free catalyst adhesive that can be applied to an underlying catalyst layer and cured may be preferable for deep channels extending through a single layer, since there are no fibers remaining after ablation or channel formation to interfere with subsequent deposition steps.

[0033] FIG. 3C shows an electroless deposition 314 step. This is allowed to proceed until the deposition nearly reaches the top surface 303, which allows the application of a subsequent layer of catalyst layer 320 (which may be a catalyst stack or a catalyst adhesive) shown in FIG. 3D. As did the previously described catalyst layer 302, the catalyst layer 320 also has an associated surface catalyst particle exclusion depth 322 and 324. The use of a catalyst adhesive for the catalyst layer 320 is preferred to avoid interference between unremoved or remaining fibers in the channel 326 of FIG. 3E after the channel is formed. Unremoved or remaining fibers may interfere with the subsequent electroless copper deposition 329 of FIG. 3F. Subsequent layers of catalyst layer 320 may be bonded or laminated to adjacent catalyst layers 302, and electroless deposition 314 of FIG. 3D uses vacuum lamination or other processes for layer adhesion or lamination known in prior art PCB manufacturing.

[0034] 3E illustrates the removal of catalyst layer 326 through the depth of catalyst layer 320 using the methods previously described, from surface 321 of catalyst layer 320 to electroless deposition 314 underlying first layer 302. Formation of channel 326 can be accomplished using any known method for removing laminates, although laser ablation is preferred.

[0035] FIG. 3F shows electroless plating 329 of channels 326 from the underlying deposit 314 to the top level 321 of the catalyst layer 320. The resulting circuit board now has homogenous traces with a trace thickness greater than the thickness of a single catalyst layer 320 or 302. The circuit board can be used in this manner, in the finished form of FIG. 3F, after components have been added. High current trace sections, such as trace section 320 of FIG. 2C, can have their resistance reduced using this method, and additional layers can be bonded or laminated to continue the process, now catalyst layer 332, but increasing the depth of the trace section, as shown in FIG. 3G (where there can be a first exclusion plane 330 and a second exclusion plane 334, as before).

[0036] Figure 3H shows a subsequent step of forming a channel 336 in the catalyst layer 332 of Figure 3G. Figure 3I shows the final step, where electroless deposition of metal 340 makes electrical contact with the previous electroless depositions 329 and 314, thereby providing a method for forming elongated conductors of selectable thickness with low resistance, which may be narrower than previous techniques allowed for a given deposited metal resistivity (which translates to resistivity per inch for a given trace thickness and width) with a greater depth of trace than previous techniques have achieved. For ease of understanding the process steps and resulting circuit, boundaries are shown between the trace deposition layers 314, 329, and 340, however, the electroless metal deposit is homogenous across the layers and spans several dielectric layers, resulting in low resistance traces with no boundaries shown in the figures.

[0037] Electroless plating for 329 in FIG. 3F and 314 in FIG. 3C can be performed in several different ways. An example electroless copper bath formulation uses a mixture of Rochelle salt as a complexing agent, copper sulfate as a copper metal source, formaldehyde as a reducing agent, and sodium hydroxide as a reactant. In this example, a tartrate (Rochelle salt) bath is preferred for ease of waste disposal. Rochelle salt does not chelate as strongly as alternatives such as EDTA or quadrol. In this example, tartrate (Rochelle salt) is the finishing agent, copper sulfate is the metal source, formaldehyde is the reducing agent, and sodium hydroxide is the reactant. Other electroless plating formulations are possible, and this example is provided for reference. Electroless plating is initially formed on the surface of the exposed catalyst particles and proceeds until the deposit is below the original outer surface of the catalyst layer.

[0038] A key advantage of electroless plating of channels etched into a catalytic material is that electroless plating proceeds on all three sides simultaneously, compared to electroplating, which proceeds only from the bottom layer (the layer plated first).

[0039] FIG. 4 shows a sequence of process steps for using a catalyst layer (catalyst adhesive or catalyst laminate) to form a circuit board with trace layers having a thickness greater than a single laminate layer thickness. Openings (if necessary), such as for interlayer vias, are formed in step 402 (not shown, but well known in the art), followed by channels, such as channel 310 in FIG. 3B, in step 404. Electroless plating is performed in step 406, corresponding to 314 in FIG. 3C, and a sequence of steps 408, 410, and 412 is repeated for each layer of laminate / channel / electroless plating as necessary to extend the thickness of the electroless deposition in step 406. Step 408 corresponds to the bonding or laminating subsequent layer 320 in step 3D, and layers 332 to 302 in step 3G. Step 410 corresponds to the formation of channel 326 in FIG. 3E or 336 in FIG. 3H. Step 412 corresponds to the formation of electroless plating 329 in Figure 3F or 340 in Figure 3I. The process of adding additional layers to further increase the thickness of the traces can be performed by path 414 following step 412 for each iteration.

[0040] The above description is only to provide examples of the invention for understanding the underlying mechanisms and structures used, and is not intended to limit the scope of the invention to the specific methods or structures shown. For example, the sequence of Figures 3A-3I shows a one-sided structure in which the trace channels are formed over multiple catalyst layers built on a first layer 302, while the first catalyst layer 320 can have a side 307 that is subsequently removed to the level of electroless deposition 314, and additional layers are added to side 307 in the opposite direction using conventional methods for multilayer boards or the methods for extending trace thickness described above.

[0041] The trace structures in Figures 3A-3I are shown in combination as they commonly occur on a PCB, and these examples are for illustrative purposes only and are not intended to limit the invention to these structures. The results of using the present invention on the examples given in Figures 2A and 2C show that for a conventional subtractive circuit board process, if trace 237A is 0.25 inches wide and 3 mils thick, and a top catalyst layer and an underlying catalyst layer 15 mils thick (30 mils total) are used to form the trace depicted in Figures 3A-3I, trace 237 can be reduced from 250 mils to 25 mils wide.

[0042] As used herein, the term "approximately" is understood to mean less than ¼ greater than or less than a given rated value, and the term "substantially" is understood to mean less than ½ greater than or less than a given rated value. Terms such as "order of magnitude" of a value include a range from 0.1 times the rated value to 10 times the rated value.

[0043] Certain post-processing operations are common to printed circuit board manufacturing and can be performed using prior art methods on boards made according to the new process and are not shown. Such operations include tin plating to improve solder flow, gold flash plating to improve conductivity and reduce corrosion, solder mask operations, silkscreening information (part numbers, reference designations, etc.) on the board, scoring the finished board, or preparing tear-off tabs, etc. Circuit boards formed using the current process have a flat surface compared to the prior art of subtractive copper etching, which leaves raised traces on top of the lower underlying substrate. Some of these operations may improve results when performed on the coplanar trace and substrate surfaces of the present invention. For example, silkscreened lettering over traces or vias would traditionally fall apart due to the thickness of the traces and vias overlying the board surface, whereas these operations will produce superior results on a planarized surface. [Explanation of symbols]

[0044] 102 Catalyst prepreg 104 First Side 106 Second Side 108 Boundary area 110 Boundary area, second boundary 114 Catalytic particles 202 Switch 204 Power supply 205 Surface layer 206 Surface layer, peak pulse current I1 208 Energy Storage Inductor 210 Peak Pulse Current I2, Channel 212 Diode 214 Load, line 214A Trace 216 wire, load 216A Trace 218 Smoothing capacitor 218A capacitor 237 Thick line, trace 237A Trace 302 Catalyst prepreg, catalyst laminate, catalyst adhesive, first layer 303 original surface, first surface, surface layer, upper surface 304 first boundary, surface exclusion depth, exclusion boundary, exclusion zone, surface 306 Second Face Exclusion Boundary, Surface Exclusion Depth 307 Second Face, Original Face 310 Channels 314 Electroless deposition, deposits, trace deposits 320 Catalyst layer, trace section 321 faces, top level 322 Surface catalyst particle exclusion depth 324 Surface catalyst particle exclusion depth 326 Channel, catalyst layer 329 Electroless copper deposition, electroless plating, trace deposition layer 330 First Exclusion Surface 332 Catalyst layer 334 Second Exclusion Surface 336 Channels 340 Metal, trace deposition layer

Claims

1. a first layer formed from a catalyst layer having conductive traces formed by electroless deposition in channels in the first layer, the first layer having a catalyst particle exclusion zone and a catalyst particle non-exclusion zone, the catalyst particle exclusion zone having a density of catalyst particles that is 100 times less than the density of catalyst particles in the catalyst particle non-exclusion zone; a second catalyst layer applied, adhered, or laminated to the first layer, the second catalyst layer having channels formed through a thickness of the second catalyst layer and extending deep to the conductive traces of the first layer; A multi-layer circuit board, wherein the channels of the second catalyst layer are filled with an electrolessly deposited conductive metal in contact with the electrolessly deposited metal of the first layer.

2. 10. The multilayer circuit board of claim 1, wherein the first layer or the second catalyst layer is formed using heterogeneous catalyst particles.

3. The multilayer circuit board of claim 2 , wherein said heterogeneous catalyst particles comprise an inorganic material coated with a catalyst.

4. 4. The multilayer circuit board of claim 3, wherein the catalyst comprises at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or a mixture or salt of iron (Fe), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), or tin (Sn).

5. The catalyst is BrPd, Cl ２ Pd, Pd(CN) ２ , I ２ Pd, Pd(NO ３ ) ２ *2H ２ O, Pd(NO ３ ) ２ , PdSO ４ , Pd(NH ３ ) 4Br ２ , Pd(NH ３ ) 4Cl ２ H ２ 4. The multilayer circuit board of claim 3, further comprising a palladium salt comprising at least one of: O.

6. 10. The multilayer circuit board of claim 1, wherein the first layer and the second catalyst layer comprise a resin containing at least one of a polyimide resin or a mixture of an epoxy resin and a cyanate ester.

7. 10. The multilayer circuit board of claim 1, wherein at least one of the first layer or the second catalyst layer is a catalytic adhesive or a catalytic laminate.

8. a plurality of individual catalyst stack layers joined into a single stack, at least one individual catalyst stack layer including a first channel having electroless copper formed therein, each of the individual catalyst stack layers having a catalyst particle exclusion zone and a catalyst particle non-exclusion zone, the catalyst particle exclusion zone having a particle exclusion depth below a surface of the individual catalyst stack layer, the individual catalyst stack layer having a distribution of catalyst particles below the particle exclusion depth, the catalyst particles comprising inorganic filler coated with catalyst, and the catalyst particle exclusion zone having a density of catalyst particles that is less than 1 / 100th of the density of catalyst particles in the catalyst particle non-exclusion zone; a second channel extending through a thickness of more than one of the individual catalyst stack layers, whereby the second channel has catalyst particles exposed within the second channel; Equipped with a second channel of said single laminate layer being filled with a conductive metal by electroless deposition and in contact with the electroless deposition in said first channel of at least one layer.

9. 9. The multi-layer circuit board of claim 8, wherein at least one individual layer of said catalytic laminate is a catalytic adhesive.

10. 9. The multilayer circuit board of claim 8, wherein the catalyst comprises at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or a mixture or salt of iron (Fe), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), or tin (Sn).

11. 9. The multilayer circuit board of claim 8, wherein a majority of said catalyst particles are smaller than about 25 microns.

12. 9. The multilayer circuit board of claim 8, wherein the catalyst laminate comprises a resin containing at least one of a polyimide resin or a mixture of an epoxy resin and a cyanate ester.

13. 9. The multilayer circuit board of claim 8, wherein at least one layer comprises fibers bound to a resin containing catalytic particles.

14. The multilayer circuit board of claim 13 , wherein the fibers comprise a fiber mesh.

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