Multi-chip stacked device

Abstract

Examples described herein generally relate to multi-chip devices having stacked chips. In one example, the multi-chip device comprises a chip stack including chips. Adjacent chips are connected to one another. A plurality of the chips collectively include rows of broken via pillars and bridges. Each chip of the plurality of chips has a broken via pillar in each row. The broken via pillar has first and second continuous via pillar portions aligned in a direction perpendicular to the plane of the semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected to the second continuous via pillar portion within the broken via pillar. Each of the plurality of chips has one or more bridges. Each bridge connects a first continuous via pillar portion in one row to a second continuous via pillar portion in another row within the respective chip.

Description

[Technical field]

[0001] Examples in this disclosure relate generally to multi-chip stacked devices that include stacked chips. [Background technology]

[0002] background Devices have been developed that include multiple integrated circuit chips, including modules and / or packages. Such devices come in a variety of forms. Such devices can be formed to incorporate multiple chips into electronic devices, where each chip can be fabricated using standard semiconductor processing and then assembled and packaged into a larger multi-function device. In some cases, having different chips allows for separation of semiconductor processing that would be difficult to integrate, such as when components of one chip require different processing than another chip.

[0003] Another aspect is that devices having chips with different functions (e.g. some Field Programmable Gate Array (FPGA) chips and some memory chips) can be made to be the same device with smaller device size, more functionality, and lower power. The semiconductor processes for the chips can be more focused on making the devices more advantageous in terms of improving chip performance, reducing costs, and increasing manufacturing yields. Other advantages can be realized by such devices. Summary of the Invention [Means for solving the problem]

[0004] overview Examples described herein relate generally to multi-chip devices having vertically stacked chips. More specifically, various chips in a chip stack may include broken via pillars aligned in rows across multiple chips, with bridges between rows forming staggered via pillars. The staggered via pillars may form communication paths between, for example, a base chip and another chip in the chip stack, with any number of intervening chips between them. Such examples may implement non-programmable, non-volatile structures and communication paths as staggered via pillars. Programming of the structures and communication paths may be eliminated. The structures may be used for high voltage operation and for power-up sequencing. The same hardware layout may be implemented for intervening and / or distal chips in a chip stack, which may reduce the number of tapeouts to implement the chip stack and may reduce the cost to develop the chip stack.

[0005] One example described herein is a multi-chip device. The multi-chip device includes a chip stack. The chip stack includes chips. Adjacent ones of the chips are connected to each other. The plurality of chips generally includes rows of broken via pillars and bridges. Each chip of the plurality of chips has a broken via pillar in each of the rows. The broken via pillar has a first continuous via pillar portion and a second continuous via pillar portion that are aligned in a direction perpendicular to a surface of the semiconductor substrate of the corresponding chip. The first continuous via pillar portion is not connected to the second continuous via pillar portion at the broken via pillar. Each chip of the plurality of chips has one or more bridges. Each bridge of the bridges connects, in the corresponding chip, a first continuous via pillar portion in one of the rows to a second continuous via pillar portion in another of the rows.

[0006] Another example described herein is a method of operating a multi-chip device. A signal is communicated between a first chip and a second chip. The first chip and the second chip are in a chip stack. One or more intervening chips are disposed between the first chip and the second chip in the chip stack. In each intervening chip of the one or more intervening chips, communicating the signal includes communicating the signal from a broken via pillar row to another broken via pillar row. Each of the broken via pillar rows extends across the one or more intervening chips. In each intervening chip of the one or more intervening chips, each of the broken via pillar rows includes a first continuous via pillar portion and a second continuous via pillar portion disposed in a corresponding chip. The first continuous via pillar portion is not connected to the second continuous via pillar portion in the corresponding broken via pillar row.

[0007] Another example described herein is a multi-chip device. The multi-chip device includes a chip stack. The chip stack includes a chip. A first chip of the chip stack includes a first continuous via pillar portion, a second continuous via pillar portion, a third continuous via pillar portion, and a bridge. The first continuous via pillar portion has a first pad at an interface between the first chip and an underlying chip of the chip stack. The first continuous via pillar portion is connected to active circuitry of the first chip through an interconnect. The second continuous via pillar portion has a second pad at an interface between the first chip and an underlying chip of the chip stack. The second pad is aligned with the first pad. The second continuous via pillar portion is not connected to the first continuous via pillar portion. The third continuous via pillar portion has a third pad at an interface between the first chip and an underlying chip. A bridge connects the third continuous via pillar portion and the second continuous via pillar portion.

[0008] These and other aspects will be understood with reference to the following detailed description. So that the above features can be more fully understood, the more particular description summarized above may make reference to example implementations, some of which are illustrated in the accompanying drawings, which should not be construed as limiting the scope thereof, however, as merely illustrating examples of typical implementations. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram of a structure of a multi-chip device having a chip stack, according to some examples. [Diagram 2] 2 is a circuit schematic block diagram illustrating an integrated circuit of a chip stack of the multi-chip device of FIG. 1 in accordance with some examples. [Diagram 3] 2 illustrates the chip stack of FIG. 1 along with a simplified structure of at least a portion of each of the Z interfaces of the chips, according to some examples. [Figure 4] FIG. 1 illustrates another stack of chips, along with a simplified structure of at least a portion of each of the Z interfaces of the chips, according to some examples. [Diagram 5] 2 is a flowchart of a method for forming the multi-chip device of FIG. 1 according to some examples. [Figure 6] FIG. 1 is a flowchart of a method of operating a multi-chip device, according to some examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] For ease of understanding, the same reference numbers have been used, wherever possible, to designate identical elements common to the figures, and it is intended that elements of one example may be beneficially incorporated in other examples.

[0011] Detailed Description Examples described herein relate generally to multi-chip devices having vertically stacked chips. More specifically, some examples described herein relate to structures within stacked chips for transmitting signals between chips. In general, a chip stack may include a base chip, one or more intervening chips, and a distal chip, where the one or more intervening chips are disposed between the base chip and the distal chip. A row of broken via pillars is formed across the one or more intervening chips, possibly up to the distal chip. Within each row in each chip of the plurality of chips through which the corresponding row extends, the corresponding row includes a first continuous via pillar portion and a second continuous via pillar portion aligned within the row (e.g., in a direction perpendicular to the front side of the semiconductor substrate of the corresponding chip). The first continuous via pillar portion and the second continuous via pillar portion are not connected to each other within the corresponding row. In each of these chips, a bridge extends between and connects the first continuous via pillar portion of one row to the second continuous via pillar portion of another row. A first continuous via pillar portion in one row and a second continuous via pillar portion in another row connected by a bridge can form a staggered via pillar through a corresponding chip.

[0012] Each of the intervening chips and the distal chips may include active circuitry. Each active circuit of each chip may be connected to a broken via pillar in the same row to transmit signals between the corresponding active circuit and the base chip. The base chip may have interfaces, e.g., bond pads, connected to broken via pillars in different rows. The base chip may have circuits configured to communicate with different active circuits of other chips. In the base chip, signals may be transmitted through different rows to target active circuits on different chips. Signals may be moved from one row to another row in each intervening chip between the base chip and the chip containing the target active circuit. This movement allows signals to be transmitted to active circuits in different chips but through the same row.

[0013] By stacking chips, for example in a three-dimensional integrated circuit (3DIC), multiple larger end products with different combinations of chips can be created. Doing so can reduce the number of tape-outs required and can reduce product development costs if chips with the same hardware layout are realized in the chip stack. Larger products, for example field gate programmable arrays (FPGAs), systems on chips (SoCs), processors, and / or application specific integrated circuits (ASICs), can be created with fewer (e.g., one) tape-outs by stacking chips with the same hardware layout. If chips used in a chip stack have the same hardware layout, research and development can be reduced for fewer tape-outs, for example, which can drive cost reduction.

[0014] A challenge in stacking chips with multiple chips having the same hardware layout is the transfer of signals between the chips. Every chip with the same hardware layout receives or transmits signals at the same physical location within the respective chip, so a signal intended for one chip is also received by each chip with the same hardware layout. Various previous solutions addressed this by programming the active circuits to control the transfer of signals between different active circuits. However, these previous solutions had challenges, for example, in that programmability could cause reliability issues and / or the controls may not be able to be programmed before power-up, which could prevent communication of some signals during a power-up sequence.

[0015] To address these challenges, in some examples described herein, staggered via pillars can be implemented in multiple chips having the same hardware layout, such that signals communicated to and from active circuits on different ones of the chips can be sent or received at the same physical location, e.g., through the same column, in each chip. Signals communicated to and from active circuits of different chips can be communicated through different columns, e.g., in the base chip. Thus, signals may be communicated to and from the base chip through different columns in the base chip, moved to other columns in any intervening chips, and communicated to active circuits of the different chips through the same column in the respective chip. Such examples, as staggered via pillars, can realize non-programmable and non-volatile structures and communication paths. Thus, programming of the structures and communication paths can be eliminated. The structures can be used in high voltage operation and can be used in power-up sequences. Additionally, the same hardware layout can be realized for the intervening chips and / or the distal chips, which can reduce the number of tapeouts to realize the chip stack and the cost to develop the chip stack.

[0016] Various features will now be described with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale and elements of similar structure or function are indicated by similar reference numerals throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. In addition, the illustrated example need not have all aspects or advantages shown. An aspect or advantage described in connection with a particular example is not necessarily limited to that example and may be implemented in any other example even if not so shown or expressly described. Furthermore, while a method may be described herein with a particular order of operations, other methods according to other examples may be implemented with more or fewer operations and in various other orders (including, for example, different serial or parallel execution of various operations). Various components described as "first", "second", etc. of the components do not mean or imply any structure or position resulting from the "first", "second", etc. "First", "second", etc. are used herein to facilitate referring to different components.

[0017] FIG. 1 is a multi-chip device structure according to some examples. The multi-chip device of FIG. 1 includes a chip stack including a base chip 102 and fabric chips 104, 106, 108. The base chip 102 and fabric chips 104-108 are described herein as examples. Although different chips are described herein as being or including various integrated circuits (ICs) or components (e.g., fabric, base, programmable logic, etc.), aspects described herein may be generally applicable to chips of a multi-chip device having any type of IC or component.

[0018] 1, the fabric chips 104-108 are arranged with their active or front sides facing downward towards the base chip 102, which is arranged with its active or front side facing upward towards the fabric chips 104-108. In other multi-chip devices, the intermediate fabric chips are arranged with their active or front sides facing away from the base chip 102, the distal fabric chips are arranged with their active or front sides facing towards the base chip 102, and the base chip 102 is arranged with its active or front side facing towards the fabric chips 104-108. Other various multi-chip devices may have different configurations, different numbers of chips, and other components.

[0019] Typically, the chips 102-108 are stacked to form a chip stack in a multi-chip device. In some examples, the chips 102-108 are stacked to form an active die-on-active die (AoA) device. Each of the chips 102-108 may include an active IC. In some examples, more or fewer chips may be included in the chip stack. For example, a multi-chip device may have two chips, such as a base chip and a fabric chip or two fabric chips. In other examples, a multi-chip device may have three chips, four chips, five chips, etc.

[0020] Each of the chips 102-108 includes a respective semiconductor substrate 112, 114, 116, 118 and a respective front side dielectric layer 122, 124, 126, 128 on the front side of the respective semiconductor substrate 112-118. The front side dielectric layers 122-128 include metallization (e.g., metal lines and / or vias) (shown but not specifically numbered) formed therein that can electrically connect various components within an IC. Each of the chips 102-106 includes a respective back side dielectric layer 132, 134, 136 on the back side of the respective semiconductor substrate 112-116. The back side dielectric layers 132-136 include metallization (e.g., metal lines and / or vias) (shown but not specifically numbered) formed therein that can electrically connect various components within an IC. As shown, the metallization of the front dielectric layers 124, 126, 128 of the fabric chips 104, 106, 108 connect to respective circuit areas 143, 145, 147 of the fabric chips 104, 106, 108 in which respective active circuitry may be formed. Such connections and example active circuitry are described in further detail below in connection with subsequent figures.

[0021] Each semiconductor substrate 112-118 of chips 102-108 includes transistors 142, 144, 146, 148, for example, formed on and / or within the front side of the respective semiconductor substrate 112-118. Transistors 142-148 and any other components may be connected to metallization within the front side dielectric layers 122-128. Transistors 144, 146, 148 are shown in circuit regions 143, 145, 147 of fabric chips 104, 106, 108, respectively. However, transistors 144, 146, 148 and / or other transistors may be outside of circuit regions 143, 145, 147. Each semiconductor substrate 112-116 of each chip 102-106 has backside through-substrate vias (TSVs) 162, 164, 166 therethrough that can electrically connect the metallization in the frontside dielectric layers 122-126 to the metallization in the backside dielectric layers 132-136 of the respective chips 102-106.

[0022] Front side bond pads 152, 154, 156, 158 (e.g., metal (e.g., Cu) bond pads) are formed in the front side dielectric layers 122-128 of the respective chips 102-108 at the distal outer surface of the respective semiconductor substrate 112-118. The front side bond pads 152-158 may be configured to form respective chip-to-chip interfaces. The front side bond pads 152-158 are connected to metallizations in the respective front side dielectric layers 122-128. Back side bond pads 174, 176 (e.g., metal (e.g., Cu) bond pads) are formed in the back side dielectric layers 134, 136 of the respective fabric chips 104, 106 at the distal outer surface of the respective semiconductor substrate 114, 116. The back side bond pads 174, 176 may be configured to form respective chip-to-chip interfaces. The backside bond pads 174,176 are connected to metallization in the respective backside dielectric layers 134,136.

[0023] External connector backside pads 172 (e.g., metal (e.g., aluminum) pads) are formed on an exterior surface of the backside dielectric layer 132 of the base chip 102, distal from the semiconductor substrate 112 of the base chip 102. The external connector backside pads 172 are connected to metallization in the backside dielectric layer 132 of the base chip 102. A passivation layer 180 is formed on the exterior surface of the base chip 102, distal from the semiconductor substrate 112, with respective openings therethrough exposing the external connector backside pads 172. External connectors 182 (e.g., controlled collapse chip connections (C4), mini-bumps, etc.) are formed on the respective external connector backside pads 172 through the openings in the passivation layer 180.

[0024] The external connector 182 may be attached to a package substrate. The package substrate may further be attached to, for example, a printed circuit board (PCB) for attaching the package substrate (and thus the multi-chip device) to the PCB. Various other components may be included in the multi-chip device. For example, an interposer, an encapsulant (e.g., molding compound (MUF)), etc. may be included in the multi-chip device. Those skilled in the art will readily recognize various modifications that may be made to the multi-chip device.

[0025] The chips 102-108 are bonded together (e.g., by hybrid bonding using metal-metal and oxide-oxide bonds) to form a chip stack. The base chip 102 is bonded on its front side to the front side of the fabric chip 104 such that the front side bond pads 152 and the outer surface of the front side dielectric layer 122 of the base chip 102 are bonded to the outer surface of the front side bond pads 154 and the front side dielectric layer 124 of the fabric chip 104. The fabric chip 104 is bonded on its back side to the front side of the fabric chip 106 such that the back side bond pads 174 and the outer surface of the back side dielectric layer 134 of the fabric chip 104 are bonded to the outer surface of the front side bond pads 156 and the front side dielectric layer 126 of the fabric chip 106. The fabric chip 106 has its backside bonded to the front side of the fabric chip 108 such that the backside bond pads 176 and the outer surface of the backside dielectric layer 136 of the fabric chip 106 are bonded to the frontside bond pads 158 and the outer surface of the frontside dielectric layer 128 of the fabric chip 108.

[0026] Other configurations of bonding can be realized. For example, the base chip 102 can be bonded on its front side to the back side of the fabric chip 104 such that the front side bond pads 152 and the outer surface of the front side dielectric layer 122 of the base chip 102 are bonded to the outer surface of the back side bond pads 174 and the back side dielectric layer 134 of the fabric chip 104. The fabric chip 104 can be bonded on its front side to the back side of the fabric chip 106 such that the front side bond pads 154 and the outer surface of the front side dielectric layer 124 of the fabric chip 104 are bonded to the outer surface of the back side bond pads 176 and the back side dielectric layer 136 of the fabric chip 106. The fabric chip 106 can be bonded on its front side to the front side of the fabric chip 108 such that the front side bond pads 156 and the outer surface of the front side dielectric layer 126 of the fabric chip 106 are bonded to the outer surface of the front side bond pads 158 and the front side dielectric layer 128 of the fabric chip 108.

[0027] In other examples, the chips 102-108 can be attached to one another using external connectors (mini-bumps, solder, etc.). In some examples, some of the chips 102-108 may be attached to one another by external connectors, and other of the chips may be bonded to one another without the use of external connectors. The bonding and use of external connectors may be arbitrarily reordered.

[0028] Any of the chips in the chip stack may include Z-interface circuitry. The Z-interface circuitry may enable the transfer of signals between chips in the chip stack. The Z-interface circuitry may include staggered via pillars. Each staggered via pillar includes a first continuous via pillar portion (e.g., including a TSV) in a first broken via pillar and a second continuous via pillar portion (e.g., not including a TSV) in a second broken via pillar, with a bridge (e.g., a metal line) extending between and connecting the first and second continuous via pillar portions.

[0029] Each broken via pillar includes metal lines / pads and vias in the respective front dielectric layers, TSVs through the respective semiconductor substrates, and metal lines / pads and / or vias in the respective back dielectric layers, where the metal lines / pads, vias, and TSVs are generally aligned in a direction perpendicular to the front surface of the respective semiconductor substrates. A continuous via pillar portion of the broken via pillar is formed by the metal lines / pads and vias in the respective back dielectric layers, the TSVs, and at least some of the metal lines / pads and vias in the respective front dielectric layers, and another continuous via pillar portion of the broken via pillar is formed by at least some of the metal lines / pads and vias in the respective front dielectric layers. Different continuous via pillar portions in the broken via pillar are not connected to each other in the broken via pillar (e.g., metal portions such as vias or metal lines / pads are omitted in the metal layers in the broken via pillar).

[0030] The rows of broken via pillars may be arranged and aligned in multiple chips in a chip stack, for example across fabric chips 104-108. Each row may include one or more broken via pillars in each of the multiple chips. Thus, a staggered via pillar in one chip may bridge across two rows in the multiple chips. In such a configuration, each chip in the multiple chips may transmit and receive signals to and from the same row. As a signal propagates through any intervening chip, the signal is transferred through the bridge of the staggered via pillars to another row in each intervening chip. Further details of the Z-interface circuitry are described below. Any of the chips 102-108 may include Z-interface circuitry, although in some examples, the distal fabric chip 108 may omit TSVs and / or metallization in the backside dielectric layer since the distal fabric chip 108 may not receive backside processing.

[0031] In some examples, each of the fabric chips 104-108 includes a processing IC. A processing IC may generally include any circuitry configured or configurable to process any data and / or signals and output data and / or signals resulting from the processing, not just memory and any circuitry associated with the memory (e.g., address decoders, memory controllers, etc.). The processing ICs of the fabric chips 104-108 are generally the same IC. The hardware topology, architecture, and layout of the fabric chips 104-108 are identical in some examples, except that the distal fabric chip 108 may omit components formed by backside processing, such as backside TSVs, backside dielectric layers, and / or metallization within the backside dielectric layers. In some examples, the processing ICs of the fabric chips 104-108 include one or more programmable logic regions (e.g., fabric of an FPGA) having the same hardware topology, architecture, and layout among the fabric chips 104-108. By having a Z-interface on fabric chips 104-108, chips that undergo the same front side processing can be integrated into a multi-chip device.

[0032] In other examples, each of the chips 102-108 may be or include different ICs, or may be optionally interchangeable with the same and / or different ICs. For example, any of the fabric chips 104-108 may be or include processing ICs or memory. In some examples, the chip 108 is an ASIC. Any of the chips 102-108 may be generally referred to as an active chip.

[0033] 2 is a block diagram of a circuit schematic showing ICs of a chip stack of the multi-chip device of FIG. 1, according to some examples. In the example shown, the multi-chip device is a multi-chip programmable device. The circuit schematic may be implemented in the multi-chip device of FIG. 1 regardless of the orientation of the fabric chips 104, 106, for example.

[0034] In the illustrated example, the base chip 102 includes a base IC on the base chip 102, which may be a SoC. The fabric chips 104, 106, 108 include respective programmable logic (PL) ICs 224, 226, 228, which in some examples are the same IC and have the same hardware layout and topology. These ICs are provided as an example of implementation. Other ICs (e.g., with other hard IP blocks) can be implemented in the chips. The fabric chips 104, 106, 108 further include respective Z interfaces 234, 236, 238.

[0035] The base IC on the base chip 102 includes a processing system 202, an input / output circuit (IO) 204, an IP core circuit 206, a network on chip (NoC) 210, and a Z interface 232. The processing system 202 may be or include any of a variety of different processor types and numbers of processor cores. For example, the processing system 202 may be implemented as an individual processor, such as a single core capable of executing program instruction code. In another example, the processing system 202 may be implemented as a multi-core processor. The processing system 202 may be implemented using any of a variety of different types of architectures. Examples of architectures that may be used to implement the processing system 202 may include an ARM processor architecture, an x86 processor architecture, a graphics processing unit (GPU) architecture, a mobile processor architecture, a reduced instruction set computer (RISC) architecture (e.g., RISC-V), or other suitable architectures capable of executing computer-readable program instruction code.

[0036] The I / O circuitry 204 may include extreme performance I / O (XPIO), multi-gigabit transceivers (MGT), high bandwidth memory (HBM) interfaces, analog-to-digital converters (ADC), digital-to-analog converters (DAC), or any other I / O blocks. The I / O circuitry 204 may be configured to send and receive signals to and from circuits external to the multi-chip device. The IP core circuitry 206 may include memory controllers (such as double data rate (DDR) memory controllers, high bandwidth memory (HBM) memory controllers), peripheral component interconnect express (PCIe) interfaces, cache coherent interconnect (CCIX) interfaces for accelerators, Ethernet cores (such as media address controllers (MAC)), forward error correction (FEC) blocks, and / or any other hardening circuits. Any of the I / O circuitry 204 and / or the IP core circuitry 206 may be programmable.

[0037] The NoC 210 includes a programmable network 212 and a NoC peripheral interconnect (NPI) 214. The programmable network 212 communicatively couples together the subsystems of the base ICs and any other circuits on the base chip 102. The programmable network 212 includes NoC packet switches and interconnect lines connecting the NoC packet switches. Each NoC packet switch switches NoC packets in the programmable network 212. The programmable network 212 has interface circuits at the edges of the programmable network 212. The interface circuits include NoC master units (NMUs) and NoC slave units (NSUs). Each NMU is an ingress circuit that connects a master circuit to the programmable network 212, and each NSU is an egress circuit that connects the programmable network 212 to a slave endpoint circuit. The NMUs are communicatively coupled to the NSUs via the NoC packet switches and interconnect lines of the programmable network 212. The NoC packet switches are connected to each other and to the NMUs and NSUs via interconnect lines to implement multiple physical channels in the programmable network 212. The NoC packet switches, NMUs, and NSUs include register blocks that determine the operation of the respective NoC packet switch, NMU, or NSU.

[0038] NPI 214 includes circuits for writing to register blocks that determine the functionality of the NMUs, NSUs, and NoC packet switches. NPI 214 includes peripheral interconnects coupled to the register blocks for programming the register blocks to set the functionality. The register blocks in the NMUs, NSUs, and NoC packet switches of programmable network 212 support interrupts, quality of service (QoS), error handling and reporting, transaction control, power management, and address mapping control. NPI 214 may include an NPI root node present on processing system 202 (e.g., a platform management controller (PMC) of processing system 202), interconnected NPI switches connected to the NPI root node, and protocol blocks connected to the interconnected NPI switches and corresponding register blocks. NPI 214 may be used to program any programmable circuit of the base IC on base chip 102. For example, NPI 214 may be used to program any programmable input / output circuit 204 and / or IP core circuit 206.

[0039] The Z-interface 232 may include active circuits such as buffers for driving signals. The Z-interface 232 provides an interface, including metal lines / pads and vias in metallization layers, to chips above the base chip 102 and / or a substrate (e.g., a package substrate) below the base chip 102 for the processing system 202, the input / output circuitry 204, the IP core circuitry 206, and the programmable network 212 of the NoC 210. In addition, the Z-interface 232 can provide a pass-through interface through the base chip 102.

[0040] The various subsystems and circuits of the base IC on the base chip 102 can be communicatively coupled. As shown, the processing system 202, the input / output circuitry 204, and the IP core circuitry 206 are connected to the NoC 210 (e.g., to the programmable network 212) and thus communicatively coupled to each other. The processing system 202 is further connected to the NPI 214 for communicating configuration data to the various programmable components on the base chip 102. The processing system 202 is further connected to the programmable network 212 of the NoC 210 for communicating configuration data to chips above the base chip 102. The programmable network 212 of the NoC 210 is connected to the Z-interface 232 so that data, such as transaction data and configuration data, can be communicated to another chip via the Z-interface 232. Each of the processing system 202, the input / output circuitry 204, and the IP core circuitry 206 is connected to the Z-interface 232 for communication with programmable logic, for example, in the PL ICs 224, 226, 228 in the overlying fabric chips 104, 106. Other communication mechanisms, such as direct connections between the various subsystems and circuits, may also be implemented.

[0041] The PL ICs 224-228 on each of the fabric chips 104-108 include one or more programmable logic regions. A programmable logic region is a logic circuit that can be programmed to perform a specified function. A programmable logic region may include any number or arrangement of programmable tiles. As an example, a programmable logic region may be implemented as the fabric of an FPGA. For example, a programmable logic region may include any number of configurable logic blocks (CLBs), look-up tables (LUTs), digital signal processing blocks (DSPs), random access memory blocks (BRAMs), etc. Each of the programmable tiles (e.g., CLBs, LUTs, DSPs, BRAMs, etc.) may include one or more programmable interconnect elements. The various respective types of programmable tiles may be arranged in rows and / or columns, and associated programmable interconnect elements may be connected to adjacent programmable logic elements, for example, in the same columns and rows. The programmable interconnect elements may form an interconnect network of the programmable logic region. Any logic and connections can be implemented in a programmable logic region by programming or configuring any of the programmable tiles of the programmable logic region.

[0042] The Z-interfaces 234-238 on each of the fabric chips 104-108 may include active circuitry, such as buffers for driving signal and / or selection circuits. The Z-interfaces 234-238 provide an interface, including through metal lines and vias in metallization layers, for the respective PL ICs 224-228 to communicate with chips above and / or below the respective fabric chips 104-108. In addition, the Z-interfaces 234-238 may provide a pass-through interface through the respective fabric chips 104-108. An example of a row of broken via pillars with staggered via pillars that may provide a pass-through interface is described in more detail below. Configuration data for the PL ICs 224-228 may be transmitted via passive connections, for example, through the Z-interfaces 234-238.

[0043] Each PL IC 224-228 may also include a configuration interconnect including a configuration frame (CFRAME) driver. The CFRAME driver may be or may include control logic for communicating configuration data (such as a bitstream) to configure the programmable logic. Each programmable logic region is configurable or programmable by configuration data received via the Z-interface 232, a corresponding Z-interface 234-238 of the respective fabric chip 104-108, and any intervening Z-interfaces 234, 236. For example, the processing system 202 (e.g., a PMC of the processing system 202) may send configuration data to the respective PL IC 224-228 via the programmable network 212 and the Z-interface 232 of the NoC 210. In some examples, the configuration interconnect (e.g., including a CFRAME driver) may direct the configuration data to the appropriate programmable tile and control the configuration of such programmable tile.

[0044] 3 illustrates the chip stack of FIG. 1 along with a simplified structure of at least a portion of each of the Z-interfaces 234, 236, 238 of the fabric chips 104, 106, 108, according to some examples. Although described with respect to the fabric chips 104, 106, 108, aspects of the Z-interfaces described may also be applicable to the Z-interface 232 of the base chip 102. FIG. 3 illustrates the fabric chips 104-108 with their front sides facing the base chip 102.

[0045] The Z-interface 234 of the fabric chip 104 includes a first broken via pillar comprising first and second continuous via pillar portions 304-11, 304-12, a second broken via pillar comprising first and second continuous via pillar portions 304-21, 304-22, a third broken via pillar comprising first and second continuous via pillar portions 304-31, 304-32, and a fourth broken via pillar comprising first and second continuous via pillar portions 304-41, 304-42. Although not specifically identified in FIG. 3, reference is made to the first broken via pillar 304-1, the second broken via pillar 304-2, the third broken via pillar 304-3, and the fourth broken via pillar 304-4.

[0046] The first continuous via pillar portion 304-11 of the first broken via pillar 304-1 includes metal lines / pads (including backside bond pad 174-1) in the backside dielectric layer 134, backside TSV 164-1 through the semiconductor substrate 114, and metal lines / pads in the frontside dielectric layer 124. The second continuous via pillar portion 304-12 of the first broken via pillar 304-1 includes metal lines / pads (including frontside bond pad 154-1) in the frontside dielectric layer 124. The first continuous via pillar portion 304-21 of the second broken via pillar 304-2 includes metal lines / pads (including backside bond pad 174-2) in the backside dielectric layer 134, backside TSV 164-2 through the semiconductor substrate 114, and metal lines / pads in the frontside dielectric layer 124. The second continuous via pillar portion 304-22 of the second broken via pillar 304-2 includes metal lines / pads (including the front-side bond pad 154-2) in the front-side dielectric layer 124. The first continuous via pillar portion 304-31 of the third broken via pillar 304-3 includes metal lines / pads (including the back-side bond pad 174-3) in the back-side dielectric layer 134, the back-side TSV 164-3 through the semiconductor substrate 114, and the metal lines / pads in the front-side dielectric layer 124. The second continuous via pillar portion 304-32 of the third broken via pillar 304-3 includes metal lines / pads (including the front-side bond pad 154-3) in the front-side dielectric layer 124. The first continuous via pillar portion 304-41 of the fourth broken via pillar 304-4 includes metal lines / pads (including backside bond pad 174-4) in the backside dielectric layer 134, the backside TSV 164-4 through the semiconductor substrate 114, and the metal lines / pads in the frontside dielectric layer 124. The second continuous via pillar portion 304-42 of the fourth broken via pillar 304-4 includes metal lines / pads (including frontside bond pad 154-4) in the frontside dielectric layer 124.

[0047] The metal lines / pads, vias, and TSVs in each broken via pillar 304-1, 304-2, 304-3, 304-4 (including the respective first continuous via pillar portion and the respective second continuous via pillar portion) are aligned within the respective broken via pillar in a direction perpendicular to the front-side surface of the semiconductor substrate 114. More generally, the first continuous via pillar portion and the second continuous via pillar portion of each broken via pillar 304-1, 304-2, 304-3, 304-4 are aligned within the respective broken via pillar in a direction perpendicular to the front-side surface of the semiconductor substrate 114. The first continuous via pillar portion in this example generally includes vertically stacked backside bond pads, metal lines and / or vias in the backside dielectric layer, TSVs, and metal lines and / or vias in the front-side dielectric layer, which are continuously connected to each other. The second continuous via pillar portion in this example generally includes vertically stacked metal lines and / or vias in a front-side dielectric layer that are continuously connected to one another, and a front-side bond pad.

[0048] The first continuous via pillar portion is not connected to the second continuous via pillar portion within each broken via pillar 304-1, 304-2, 304-3, 304-4. Generally, each of the broken via pillars 304-1, 304-2, 304-3, 304-4 is not continuously connected through the metallization of the respective front-side dielectric layer 124 of the fabric chip 104. More specifically, the first continuous via pillar portions 304-11, 304-21, 304-31, 304-41 of the broken via pillars 304-1, 304-2, 304-3, 304-4, respectively, are not connected to the second continuous via pillar portions 304-12, 304-22, 304-32, 304-42 of the broken via pillars 304-1, 304-2, 304-3, 304-4, respectively. For example, there are no metal parts, such as vias, that directly connect to and directly connect between the bridges 314-21, 314-32 in the second broken via pillar 304-2, and there are no metal parts, such as vias, that directly connect to and directly connect between the bridges 314-32, 314-43 in the third broken via pillar 304-3.

[0049] The Z-interfaces 236, 238 of the fabric chips 106, 108 include broken via pillars similar to the Z-interface 234 of the fabric chip 104. The Z-interface 236 of the fabric chip 106 includes a first broken via pillar including first and second continuous via pillar portions 306-11, 306-12, a second broken via pillar including first and second continuous via pillar portions 306-21, 306-22, a third broken via pillar including first and second continuous via pillar portions 306-31, 306-32, and a fourth broken via pillar including first and second continuous via pillar portions 306-41, 306-42. 3, reference is made to first broken via pillar 306-1, second broken via pillar 306-2, third broken via pillar 306-3, and fourth broken via pillar 306-4. Broken via pillars 306-1, 306-2, 306-3, 306-4 are configured in fabric chip 106 in the same manner that broken via pillars 304-1, 304-2, 304-3, 304-4 are configured in fabric chip 104.

[0050] The Z-interface 238 of the fabric chip 108 includes a first broken via pillar including first and second continuous via pillar portions 308-11, 308-12, a second broken via pillar including first and second continuous via pillar portions 308-21, 308-22, a third broken via pillar including first and second continuous via pillar portions 308-31, 308-32, and a fourth broken via pillar including first and second continuous via pillar portions 308-41, 308-42. Although not specifically identified in FIG. 3, reference is made to the first broken via pillar 308-1, the second broken via pillar 308-2, the third broken via pillar 308-3, and the fourth broken via pillar 308-4. Broken via pillars 308-1, 308-2, 308-3, 308-4 are configured in fabric chip 108 in the same manner that broken via pillars 304-1, 304-2, 304-3, 304-4 are configured in fabric chip 104, except that fabric chip 108 does not receive backside processing and therefore has no TSVs and metal lines / pads and vias in the backside dielectric layer. Those skilled in the art will readily understand the relationship between the above description of the components of fabric chip 104 and the components of fabric chips 106, 108 shown in FIG.

[0051] The broken via pillars are aligned in a row across the fabric chips 104-108. The first broken via pillars 304-1, 306-1, 308-1 in the fabric chips 104-108 are aligned in a first row. The second broken via pillars 304-2, 306-2, 308-2 in the fabric chips 104-108 are aligned in a second row. The third broken via pillars 304-3, 306-3, 308-3 in the fabric chips 104-108 are aligned in a third row. The fourth broken via pillars 304-4, 306-4, 308-4 in the fabric chips 104-108 are aligned in a fourth row.

[0052] This alignment allows the various continuous via pillar portions on the different chips to be connected by bond pads that are bonded to each other at the bonding interface. A first continuous via pillar portion 304-11 on the fabric chip 104 is connected to a second continuous via pillar portion 306-12 on the fabric chip 106 by bonding a backside bond pad 174-1 to a frontside bond pad 156-1. A first continuous via pillar portion 304-21 on the fabric chip 104 is connected to a second continuous via pillar portion 306-22 on the fabric chip 106 by bonding a backside bond pad 174-2 to a frontside bond pad 156-2. A first continuous via pillar portion 304-31 on the fabric chip 104 is connected to a second continuous via pillar portion 306-32 on the fabric chip 106 by bonding a backside bond pad 174-3 to a frontside bond pad 156-3. A first continuous via pillar portion 304-41 on the fabric chip 104 is connected to a second continuous via pillar portion 306-42 on the fabric chip 106 by bonding a backside bond pad 174-4 to a frontside bond pad 156-4.

[0053] A first continuous via pillar portion 306-11 on the fabric chip 106 is connected to a second continuous via pillar portion 308-12 on the fabric chip 108 by bonding a backside bond pad 176-1 to a frontside bond pad 158-1. A first continuous via pillar portion 306-21 on the fabric chip 106 is connected to a second continuous via pillar portion 308-22 on the fabric chip 108 by bonding a backside bond pad 176-2 to a frontside bond pad 158-2. A first continuous via pillar portion 306-31 on the fabric chip 106 is connected to a second continuous via pillar portion 308-32 on the fabric chip 108 by bonding a backside bond pad 176-3 to a frontside bond pad 158-3. A first continuous via pillar portion 306-41 on the fabric chip 106 is connected to a second continuous via pillar portion 308-42 on the fabric chip 108 by bonding the backside bond pad 176-4 to the frontside bond pad 158-4.

[0054] Each bridge is positioned to extend between and connect a first continuous via pillar portion of a respective broken via pillar in a row and a second continuous via pillar portion of a respective different broken via pillar in a different row in the chip. Each bridge in the illustrated example is a metal line disposed in a respective front dielectric layer. The bridge may include multiple lines / pads and / or vias and may be disposed in, for example, a back dielectric layer.

[0055] The second-to-first bridge 314-21 forms at least a portion of, extends between and connects the second continuous via pillar portion 304-22 of the second broken via pillar 304-2 and the first continuous via pillar portion 304-11 of the first broken via pillar 304-1. The third-to-second bridge 314-32 forms at least a portion of, extends between and connects the second continuous via pillar portion 304-32 of the third broken via pillar 304-3 and the first continuous via pillar portion 304-21 of the second broken via pillar 304-2. The fourth-third bridge 314-43 forms part of, extends between and connects at least the second continuous via pillar portion 304-42 of the fourth broken via pillar 304-4 and the first continuous via pillar portion 304-31 of the third broken via pillar 304-3.

[0056] The second-to-first bridge 316-21 forms at least a portion of, extends between and connects the second continuous via pillar portion 306-22 of the second broken via pillar 306-2 and the first continuous via pillar portion 306-11 of the first broken via pillar 306-1. The third-to-second bridge 316-32 forms at least a portion of, extends between and connects the second continuous via pillar portion 306-32 of the third broken via pillar 306-3 and the first continuous via pillar portion 306-21 of the second broken via pillar 306-2. The fourth-third bridge 316-43 forms part of, extends between and connects at least the second continuous via pillar portion 306-42 of the fourth broken via pillar 306-4 and the first continuous via pillar portion 306-31 of the third broken via pillar 306-3.

[0057] The second-to-first bridge 318-21 forms at least a portion of, extends between and connects the second continuous via pillar portion 308-22 of the second broken via pillar 308-2 and the first continuous via pillar portion 308-11 of the first broken via pillar 308-1. The third-to-second bridge 318-32 forms at least a portion of, extends between and connects the second continuous via pillar portion 308-32 of the third broken via pillar 308-3 and the first continuous via pillar portion 308-21 of the second broken via pillar 308-2. The fourth-third bridge 318-43 forms at least a portion of, extends between and connects the second continuous via pillar portion 308-42 of the fourth broken via pillar 308-4 and the first continuous via pillar portion 308-31 of the third broken via pillar 308-3.

[0058] Each of the first and second continuous via pillar portions connected to each other by a bridge forms a staggered via pillar in the respective chip. The first continuous via pillar portion 304-11, the second-to-first bridge 314-21, and the second continuous via pillar portion 304-22 form the staggered via pillar. The first continuous via pillar portion 304-21, the third-to-second bridge 314-32, and the second continuous via pillar portion 304-32 form the staggered via pillar. The first continuous via pillar portion 304-31, the fourth-to-third bridge 314-43, and the second continuous via pillar portion 304-42 form the staggered via pillar.

[0059] The first continuous via pillar portion 306-11, the second-to-first bridge 316-21, and the second continuous via pillar portion 306-22 form a staggered via pillar. The first continuous via pillar portion 306-21, the third-to-second bridge 316-32, and the second continuous via pillar portion 306-32 form a staggered via pillar. The first continuous via pillar portion 306-31, the fourth-to-third bridge 316-43, and the second continuous via pillar portion 306-42 form a staggered via pillar.

[0060] The first continuous via pillar portion 308-11, the second-to-first bridge 318-21, and the second continuous via pillar portion 308-22 form a staggered via pillar. The first continuous via pillar portion 308-21, the third-to-second bridge 318-32, and the second continuous via pillar portion 308-32 form a staggered via pillar. The first continuous via pillar portion 308-31, the fourth-to-third bridge 318-43, and the second continuous via pillar portion 308-42 form a staggered via pillar.

[0061] Additionally, second-first bridge 314-21, 316-21, 318-21 are connected to input or output nodes of active circuits (e.g., PL ICs 224, 226, 228) of respective fabric chips 104-108. As shown, second-first bridge 314-21 is connected to PL IC 224 through interconnect 324 (e.g., metal lines / pads and / or vias), second-first bridge 316-21 is connected to PL IC 226 through interconnect 326, and second-first bridge 318-21 is connected to PL IC 228 through interconnect 328. The nodes of the active circuits to which the second-first bridges are connected may be input nodes, output nodes, or bidirectional nodes. Thus, signals may be received by the active circuits and / or output to the second-first bridges.

[0062] The base chip 102 can transmit and / or receive signals from active circuits (e.g., PL ICs 224-228) on the fabric chips 104-108 through the front-side bond pads 152-2, 152-3, 152-4. Based on the hardware configuration of the fabric chips 104-108, the front-side bond pads 152-2, 152-3, 152-4 to which a signal is transmitted or received can determine the circuitry of the fabric chips 104-108 that receives or transmits the signal. In the illustrated example, a first signal 334 on the front-side bond pad 152-2 is communicated to or from the PL IC 224 on the fabric chip 104, a second signal 336 on the front-side bond pad 152-3 is communicated to or from the PL IC 226 on the fabric chip 106, and a third signal 338 on the front-side bond pad 152-4 is communicated to or from the PL IC 228 on the fabric chip 108.

[0063] The front-side bond pad 152-2 is connected to the front-side bond pad 154-2, which is part of the second row and is also part of the second continuous via pillar portion 304-22 of the second broken via pillar 304-2. The front-side bond pad 152-3 is connected to the front-side bond pad 154-3, which is part of the third row and is also part of the second continuous via pillar portion 304-32 of the third broken via pillar 304-3. The front-side bond pad 152-4 is connected to the front-side bond pad 154-4, which is part of the fourth row and is also part of the second continuous via pillar portion 304-42 of the fourth broken via pillar 304-4.

[0064] The circuitry of the base chip 102 can transmit or receive a first signal 334 at the front-side bond pad 152-2. The first signal 334 is communicated to the PL IC 224 through the second row (e.g., the second continuous via pillar portion 304-22 of the second broken via pillar 304-2), the second-first bridge 314-21, and the interconnect 324. The first signal 334 may also be communicated to the circuitry of the fabric chip 106 through the first row (e.g., the first continuous via pillar portion 304-11 of the first broken via pillar 304-1 and the second continuous via pillar portion 306-12 of the first broken via pillar 306-1). In some examples, the first row of the first broken via pillars 304-1, 306-1, 308-1 may be omitted. In such an example, the first signal 334 is not communicated to the fabric chip 106 through the first contiguous via pillar portion 304-11 and the second contiguous via pillar portion 306-12.

[0065] The circuitry of the base chip 102 can transmit or receive a second signal 336 at the front side bond pad 152-3. The second signal 336 is propagated through the third row (e.g., the second continuous via pillar portion 304-32 of the third broken via pillar 304-3), the third-second bridge 314-32, and the second row (e.g., the first continuous via pillar portion 304-21 of the second broken via pillar 304-2) in the fabric chip 104. Thus, the second signal 336 is propagated by the staggered via pillars in the fabric chip 104 to transition from the third row to the second row. The second signal 336 is further communicated to the PL IC 226 through the second row (e.g., the second continuous via pillar portion 306-22 of the second broken via pillar 306-2), the second-to-first bridge 316-21, and the interconnect 326. The second signal 336 may be further communicated to the circuitry of the fabric chip 108 through the first row (e.g., the first continuous via pillar portion 306-11 of the first broken via pillar 306-1 and the second continuous via pillar portion 308-12 of the first broken via pillar 308-1). In some examples, the first row of the first broken via pillars 304-1, 306-1, 308-1 may be omitted. In such an example, the second signal 336 is not communicated to the fabric chip 108 through the first contiguous via pillar portion 306-11 and the second contiguous via pillar portion 308-12.

[0066] The circuitry of the base chip 102 can transmit or receive a third signal 338 at the front side bond pad 152-4. The third signal 338 is propagated through the fourth row (e.g., the second continuous via pillar portion 304-42 of the fourth broken via pillar 304-4), the fourth-third bridge 314-43, and the third row (e.g., the first continuous via pillar portion 304-31 of the third broken via pillar 304-3) in the fabric chip 104. Thus, the third signal 338 is propagated by the staggered via pillars in the fabric chip 104 to transition from the fourth row to the third row. The third signal 338 is further transmitted through the third row (e.g., the second continuous via pillar portion 306-32 of the third broken via pillar 306-3), the third-second bridge 316-32, and the second row (e.g., the first continuous via pillar portion 306-21 of the second broken via pillar 306-2) in the fabric chip 106. Thus, the third signal 338 is transmitted by the staggered via pillars in the fabric chip 106 and moves from the third row to the second row. The third signal 338 is further transmitted through the second row (e.g., the second continuous via pillar portion 308-22 of the second broken via pillar 308-2), the second-first bridge 318-21, and the interconnect 328 to the PL IC 228.

[0067] As illustrated by the above description, each of the active circuits (e.g., PL ICs 224-228) receives or transmits signals from / to base chip 102 through the same second row of second broken via pillars 304-2, 306-2, 308-2 in the respective fabric chips 104-108. Thus, PL ICs 224-228 may have the same hardware layout, but PL ICs 224-228 communicate different signals to / from base chip 102 at the same respective locations in the respective fabric chips 104-108, without other PL ICs 224-228 receiving the signals.

[0068] Staggered via pillars can allow different chips in a chip stack to have the same ICs and hardware, thereby reducing the number of variations of chips that are designed and taped out. Additionally, programming of communication interfaces between chips can be avoided in some instances by implementing staggered via pillars.

[0069] Those skilled in the art will readily appreciate that the diagram of FIG. 3 is simplified. In some examples, each of the front dielectric layers 122-128 of each chip 102-108 is or includes a group of dielectric layers, such as 18 or more dielectric layers, depending, for example, on the technology node of the chip 102-108. Additionally, each of the front dielectric layers 122-128 may have or include 18 metal layers (e.g., M0 layers-M17 layers) in some examples, although the number of metal layers may vary, for example, depending on the technology node of the chip. Various bridges and / or metal lines may be in any of the metal layers in some examples.

[0070] 4 illustrates a chip stack with a simplified structure of at least a portion of each of the Z-interfaces 234, 236, 238 of the fabric chips 104, 106, 108, according to some examples. Although described with respect to the fabric chips 104, 106, 108, aspects of the Z-interfaces described may be applicable to the Z-interface 232 of the base chip 102. FIG. 4 illustrates the intermediate fabric chips 104, 106 with their front sides facing away from the base chip 102, and the distal fabric chip 108 with its front side facing towards the base chip 102.

[0071] Those skilled in the art will readily appreciate that the above description (with respect to FIG. 3) is applicable to the chip stack of FIG. 4. As such, a detailed description of FIG. 4 may be omitted in some aspects.

[0072] Generally, the Z-interfaces 234, 236 of the fabric chips 104, 106 include broken via pillars. The Z-interface 234 of the fabric chip 104 includes a first broken via pillar including first and second continuous via pillar portions 404-11, 404-12, a second broken via pillar including first and second continuous via pillar portions 404-21, 404-22, a third broken via pillar including first and second continuous via pillar portions 404-31, 404-32, and a fourth broken via pillar including first and second continuous via pillar portions 404-41, 404-42. Although not specifically identified in FIG. 4, reference is made to first broken via pillar 404-1, second broken via pillar 404-2, third broken via pillar 404-3, and fourth broken via pillar 404-4.

[0073] The Z-interface 236 of the fabric chip 106 includes a first broken via pillar including first and second continuous via pillar portions 406-11, 406-12, a second broken via pillar including first and second continuous via pillar portions 406-21, 406-22, a third broken via pillar including first and second continuous via pillar portions 406-31, 406-32, and a fourth broken via pillar including first and second continuous via pillar portions 406-41, 406-42. Although not specifically identified in FIG. 4, reference is made to the first broken via pillar 406-1, the second broken via pillar 406-2, the third broken via pillar 406-3, and the fourth broken via pillar 406-4.

[0074] The broken via pillars are aligned in a row across the fabric chips 104-108. The first broken via pillars 404-1, 406-1, 308-1 in the fabric chips 104-108 are aligned in a first row. The second broken via pillars 404-2, 406-2, 308-2 in the fabric chips 104-108 are aligned in a second row. The third broken via pillars 404-3, 406-3, 308-3 in the fabric chips 104-108 are aligned in a third row. The fourth broken via pillars 404-4, 406-4, 308-4 in the fabric chips 104-108 are aligned in a fourth row.

[0075] Each bridge is positioned to extend between and connect a first continuous via pillar portion of a respective broken via pillar in a row and a second continuous via pillar portion of a respective different broken via pillar in a different row in the chip. The second-first bridge 414-21 forms at least a portion of each of, extends between and connects the first continuous via pillar portion 404-21 of the second broken via pillar 404-2 and the second continuous via pillar portion 404-12 of the first broken via pillar 404-1. The third-second bridge 414-32 forms at least a portion of each of, extends between and connects the first continuous via pillar portion 404-31 of the third broken via pillar 404-3 and the second continuous via pillar portion 404-22 of the second broken via pillar 404-2. The fourth-third bridge 414-43 forms part of, extends between and connects at least the first continuous via pillar portion 404-41 of the fourth broken via pillar 404-4 and the second continuous via pillar portion 404-32 of the third broken via pillar 404-3.

[0076] The second-to-first bridge 416-21 forms at least a portion of, extends between and connects the first continuous via pillar portion 406-21 of the second broken via pillar 406-2 and the second continuous via pillar portion 406-12 of the first broken via pillar 406-1. The third-to-second bridge 416-32 forms at least a portion of, extends between and connects the first continuous via pillar portion 406-31 of the third broken via pillar 406-3 and the second continuous via pillar portion 406-22 of the second broken via pillar 406-2. The fourth-third bridge 416-43 forms part of, extends between and connects at least the first continuous via pillar portion 406-41 of the fourth broken via pillar 406-4 and the second continuous via pillar portion 406-32 of the third broken via pillar 406-3.

[0077] Each of the first and second continuous via pillar portions connected to each other by a bridge forms a staggered via pillar in each chip. The second continuous via pillar portion 404-12, the second-first bridge 414-21, and the first continuous via pillar portion 404-21 form a staggered via pillar. The second continuous via pillar portion 404-22, the third-second bridge 414-32, and the first continuous via pillar portion 404-31 form a staggered via pillar. The second continuous via pillar portion 404-32, the fourth to third bridges 414-43, and the first continuous via pillar portion 404-41 form a staggered via pillar. The second continuous via pillar portion 406-12, the second-to-first bridge 416-21, and the first continuous via pillar portion 406-21 form a staggered via pillar. The second continuous via pillar portion 406-22, the third-to-second bridge 416-32, and the first continuous via pillar portion 406-31 form a staggered via pillar. The second continuous via pillar portion 406-32, the fourth-to-third bridge 416-43, and the first continuous via pillar portion 406-41 form a staggered via pillar.

[0078] Additionally, the second-first bridge 414-21, 416-21 is connected to an input or output node of the active circuitry (e.g., PL IC 224, 226) of the respective fabric chip 104, 106. As shown, the second-first bridge 414-21 is connected to the PL IC 224 through interconnect 424 (e.g., metal lines / pads and / or vias), and the second-first bridge 416-21 is connected to the PL IC 226 through interconnect 426. The node of the active circuitry to which the second-first bridge is connected may be an input node, an output node, or a bidirectional node. Thus, signals may be received by the active circuitry and / or output to the second-first bridge.

[0079] FIG. 5 is a flow chart of a method 500 for forming the multi-chip device of FIGS. 1 and 3 according to some examples. Those skilled in the art will readily appreciate modifications to achieve other multi-chip devices such as those shown in FIG. 4. The process of the method 500 of FIG. 5 is generally described, and those skilled in the art will readily appreciate more specific processes that may be implemented. The more specific processes may be in accordance with any semiconductor process for forming ICs on a substrate that are singulated into chips. For ease of description herein, a wafer on which one or more base chips 102 are formed will be referred to as a base wafer, and a wafer on which one or more fabric chips 104, 106, 108 are formed will be referred to as a fabric wafer. Any wafer may be of any shape and / or size.

[0080] At block 502, front side processing is performed on the chips on each wafer. For example, front side processing of each semiconductor substrate 112, 114, 116, 118 (e.g., wafer) may include forming devices (e.g., transistors 142, 144, 146, 148) in and / or on the front side of the semiconductor substrate 112, 114, 116, 118, and forming front side dielectric layers 122, 124, 126, 128 along with metallization and front side bond pads 152, 154, 156, 158 on the front side of the semiconductor substrate 112, 114, 116, 118. A plurality of base chips 102 may be formed on the base wafer. A plurality of fabric chips 104, 106, or 108 may be formed on each of the plurality of fabric wafers. Front side processing may, for example, form a portion of the Z-interface break via pillars on and / or in the respective semiconductor substrate and front side dielectric layer.

[0081] At block 504, the base wafer is bonded to the first fabric wafer, such as by front side to front side bonding as shown in Figure 1. This bonding results in the front side of the base chip 102 being bonded to the surface of the fabric chip 104, as shown in Figure 1. The bonding may also be a hybrid bond, such as bonding front side bond pads 152 on the base wafer to front side bond pads 154 on the first fabric wafer and bonding the outer surface of the front side dielectric layer 122 on the base wafer to the outer surface of the front side dielectric layer 124 on the first fabric wafer.

[0082] In block 506, the semiconductor substrate of the first fabric wafer is thinned from the backside of the first fabric wafer. As shown in FIG. 1, the semiconductor substrate 114 of the fabric chip 104 is thinned from the backside. The thinning may be by chemical mechanical polishing (CMP) or other suitable process. In block 508, backside processing is performed on the fabric chip on the first fabric wafer. As shown in FIG. 1, the backside processing may include forming backside TSVs 164 through the semiconductor substrate 114 of the first fabric wafer and connecting to metallization in the frontside dielectric layer 124 on the first fabric wafer. The backside processing may further include forming a backside dielectric layer 134 with metallization and backside bond pads 174 on the backside of the semiconductor substrate 114. The metallization in the backside dielectric layer 134 may be connected to the metallization in the frontside dielectric layer 124 through the backside TSVs 164. Generally, formation of metallization in the backside TSVs and the backside dielectric layer can form Z-interface broken via pillars on and / or in the respective semiconductor substrate and backside dielectric layer.

[0083] At block 510, the first fabric wafer is bonded to the second fabric wafer, such as by backside to frontside bonding as shown in Figure 1. This bonding results in the backside of the fabric chip 104 being bonded to the frontside of the fabric chip 106, as shown in Figure 1. The bonding may also be a hybrid bond, such as bonding backside bond pads 174 on the first fabric wafer to frontside bond pads 156 on the second fabric wafer and bonding an outer surface of the backside dielectric layer 134 on the first fabric wafer to an outer surface of the frontside dielectric layer 126 on the second fabric wafer.

[0084] In block 512, the semiconductor substrate of the second fabric wafer is thinned from the backside of the second fabric wafer as described with respect to block 506. As shown in FIG. 1, the semiconductor substrate 116 of the fabric chip 106 is thinned from the backside.

[0085] At block 514, backside processing is performed on the fabric chips on the second fabric wafer as described with respect to block 508. As shown in FIG. 1, the backside processing may include forming backside TSVs 166 through the semiconductor substrate 116 of the second fabric wafer and connecting to metallization in the frontside dielectric layer 126 on the second fabric wafer. The backside processing may further include forming a backside dielectric layer 136 with metallization and backside bond pads 176 on the backside of the semiconductor substrate 116. The metallization in the backside dielectric layer 136 may be connected to the metallization in the frontside dielectric layer 126 through the backside TSVs 166.

[0086] At block 516, the second fabric wafer is bonded to the third fabric wafer, such as by backside to frontside bonding as shown in Figure 1. This bonding results in the backside of the fabric chip 106 being bonded to the frontside of the fabric chip 108, as shown in Figure 1. The bonding may also be a hybrid bond, such as bonding backside bond pads 176 on the second fabric wafer to frontside bond pads 158 on the third fabric wafer and bonding the outer surface of the backside dielectric layer 136 on the second fabric wafer to the outer surface of the frontside dielectric layer 128 on the third fabric wafer.

[0087] In block 518, the semiconductor substrate of the base wafer is thinned from the backside of the base wafer as described with respect to block 506. As shown in FIG 1, the semiconductor substrate 112 of the base chip 102 is thinned from the backside.

[0088] In block 520, backside processing is performed on the base chip on the base wafer as described with respect to block 508. As shown in FIG. 1, the backside processing may include forming backside TSVs 162 through the semiconductor substrate 112 of the base wafer and connecting to metallization in the frontside dielectric layer 122 on the base wafer. The backside processing may further include forming a backside dielectric layer 132 with metallization and external connector backside pads 172 on the backside of the semiconductor substrate 112. The metallization in the backside dielectric layer 132 may be connected to the metallization in the frontside dielectric layer 122 through the backside TSVs 162. The backside processing on the base chip 102 may further include forming a passivation layer 180 and external connectors 182. In block 522, the bonded wafer is singulated (e.g., by sawing) to separate the individual multi-chip devices formed. Each of the multi-chip devices may be as shown in FIG. 1.

[0089] Various operations of the blocks of method 500 may be repeated and / or omitted to form various multi-chip devices. Method 500 is provided as an example of how some multi-chip devices may be formed. In other examples, some operations may be performed in parallel. For example, multiple different wafer stacks may be formed in parallel (e.g., by bonding and processing respective wafers), and then the multiple different wafer stacks may be bonded together and further processed to form a multi-chip device. Those skilled in the art will readily understand how to form other multi-chip devices based on the description of method 500 above.

[0090] 6 is a flow chart of a method 600 of operating a multi-chip device, according to some examples. The multi-chip device may be, for example, as shown in FIGS. 1-4. Various operations of method 600 are described with respect to the multi-chip device of FIG. 3 for illustrative purposes. Those skilled in the art will readily appreciate that such operations may be similarly performed or replicated on other multi-chip devices, such as the multi-chip device of FIG. 4.

[0091] The method 600 describes communicating signals between the base chip 102 and the fabric chips 104-108. The method 600 is described with the direction of the signals being sent from the base chip 102 and received at the fabric chips 104-108. Those skilled in the art will readily appreciate that the method 600 can be similarly performed in the reverse order where the signals are sent from the fabric chips 104-108 and received at the base chip 102. Any staggered via pillars can be implemented for unidirectional communication from the base chip 102 to the fabric chips 104-108, unidirectional communication from the fabric chips 104-108 to the base chip 102, or bidirectional communication between the base chip 102 and the fabric chips 104-108.

[0092] In block 602, signals are sent to different columns in the base chip, the signals intended for active circuits on different fabric chips. Referring to FIG. 3, the signals 334-338 are sent to different columns of break via pillars. For example, the first signal 334 is sent to the second column of the second break via pillars 304-2, 306-2, 308-2 through the front side bond pad 152-2, the second signal 336 is sent to the third column of the third break via pillars 304-3, 306-3, 308-3 through the front side bond pad 152-3, and the third signal 338 is sent to the fourth column of the fourth break via pillars 304-4, 306-4, 308-4 through the front side bond pad 152-4. The first signal 334 is intended for active circuits (e.g., PL IC 224) on the fabric chip 104. The second signal 336 is intended for active circuitry (e.g., PL IC 226) on fabric chip 106. The third signal 338 is intended for active circuitry (e.g., PL IC 228) on fabric chip 108.

[0093] In block 604, each signal is moved to another column in each intervening fabric chip between the base chip and the fabric chip having the active circuitry of interest. Referring to Figure 3, the second signal 336 intended for the active circuitry on the fabric chip 106 is moved in the intervening fabric chip 104 from the third column of the third broken via pillars 304-3, 306-3, 308-3 to the second column of the second broken via pillars 304-2, 306-2, 308-2 through the third-second bridge 314-32. A third signal 338 intended for active circuitry on the fabric chip 108 is transferred through the fourth-to-third bridge 314-43 from the fourth row of fourth broken via pillars 304-4, 306-4, 308-4 to the third row of third broken via pillars 304-3, 306-3, 308-3 in the intervening fabric chip 104. The third signal 338 intended for active circuitry on the fabric chip 108 is further transferred through the third-to-second bridge 316-32 from the third row of third broken via pillars 304-3, 306-3, 308-3 to the second row of second broken via pillars 304-2, 306-2, 308-2 in the intervening fabric chip 106.

[0094] In block 606, in the fabric chip having the targeted active circuit, the respective signals are received at the targeted active circuit through the same row. Referring to FIG. 3, the first signal 334 is received at the active circuit (e.g., PL IC 224) of the fabric chip 104 through the second row of the second broken via pillars 304-2, 306-2, 308-2 (e.g., second continuous via pillar portion 304-22) and further through the second-first bridge 314-21 and the interconnect 324. The second signal 336 is received at the active circuit (e.g., PL IC 224) of the fabric chip 106 through the second row of the second broken via pillars 304-2, 306-2, 308-2 (e.g., second continuous via pillar portion 306-22) and further through the second-first bridge 316-21 and the interconnect 326. The third signal 338 is received at the active circuitry (e.g., PL IC 228) of the fabric chip 108 through the second row of second broken via pillars 304-2, 306-2, 308-2 (e.g., second continuous via pillar portion 308-22) and further through the second-to-first bridge 318-21 and the interconnect 328.

[0095] While the above description is directed to particular examples, other and further examples may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. A multi-chip device, comprising: a chip stack including chips, adjacent ones of the chips being connected to each other, and the chips as a whole include a row of broken via pillars, each chip of the plurality of chips having a broken via pillar in each row of the rows, the broken via pillar having a first continuous via pillar portion and a second continuous via pillar portion aligned in a direction perpendicular to a plane of a semiconductor substrate of each chip, the first continuous via pillar portion not connected within the broken via pillar to the second continuous via pillar portion, and the plurality of chips further comprising: bridges, each chip of the plurality of chips having one or more of the bridges, each bridge of the bridges connecting, within each chip, the first continuous via pillar portion in one of the rows and the second continuous via pillar portion in another of the rows; a multi-chip device, wherein each chip of the plurality of chips includes active circuitry, the active circuitry of the plurality of chips being in the same column of the columns within each chip and connected to the bridge within each chip.

2. 2. The multi-chip device of claim 1 , wherein in each of the rows of each interface between adjacent chips of the plurality of chips, the first continuous via pillar portion of each of the rows in one of the adjacent chips is connected to the second continuous via pillar portion of each of the rows in another of the adjacent chips.

3. The multi-chip device described in claim 1, wherein the active circuitry is connected to the bridge using a via pillar portion within each chip.

4. 2. The multichip device of claim 1, wherein the chips include a base chip, the base chip including a first pad at an interface with one of the plurality of chips, the one of the plurality of chips including a second pad at the interface, and each of the columns including a respective one of the second pads connected to a respective one of the first pads.

5. The multi-chip device of claim 1 , wherein each of the first continuous via pillar portions in one or more of the chips comprises a through-substrate via (TSV) through the semiconductor substrate of the respective chip.

6. 1. A method of operating a multi-chip device, the method comprising: transmitting signals between a first chip and a second chip, the first chip and the second chip being in a chip stack, one or more intervening chips being disposed between the first chip and the second chip in the chip stack; in each of the one or more intervening chips, communicating the signal includes communicating the signal from one row of broken via pillars to another row of broken via pillars, each row of broken via pillars extending across the one or more intervening chips; each of the broken via pillar rows in each of the one or more intervening chips includes a first continuous via pillar portion and a second continuous via pillar portion disposed on each of the chips, the first continuous via pillar portion not being connected to the second continuous via pillar portion within each of the broken via pillar rows; In each chip of the plurality of intervening chips, a bridge is disposed within the respective chip and connects the first continuous via pillar portion of the broken via pillar row to the second continuous via pillar portion of another of the broken via pillar rows; The method of claim 1, wherein the active circuitry of each chip of the plurality of intervening chips is in the same column of columns within the respective chip and is connected to the bridge within the respective chip.

7. The method described in claim 6, wherein the active circuitry is connected to the bridge using via pillar portions within each intervening chip.

8. 7. The method of claim 6, further comprising communicating respective signals between the first chip and each of the one or more intervening chips, wherein each of the one or more intervening chips and the second chip includes active circuitry, the active circuitry being connected to the same broken via pillar row through interconnects of each of the chips.

9. 9. The method of claim 8, wherein the first chip includes pads, each of the pads being connected to a different row of broken via pillars, and signals communicated between the first chip and the second chip and between the first chip and the one or more intervening chips are communicated through different of the pads.

10. 7. The method of claim 6, wherein each of the first continuous via pillar portions comprises a through-substrate via (TSV) that extends through a semiconductor substrate of the respective chip.

11. 1. A multi-chip device, comprising: a chip stack including a first chip of the chip stack, a first continuous via pillar portion having a first pad at an interface between the first chip and an underlying chip of the chip stack, the first continuous via pillar portion being connected to active circuitry of the first chip through an interconnect, the first chip further comprising: a second continuous via pillar portion having a second pad at an interface between the first chip and an overlying chip of the chip stack, the second pad being aligned with the first pad, the second continuous via pillar portion not connected to the first continuous via pillar portion, the first chip further comprising: a third continuous via pillar portion having a third pad at the interface between the first chip and the underlying chip, the first chip further comprising: a first bridge connecting the third continuous via pillar portion and the second continuous via pillar portion; A multi-chip device, wherein active circuitry on the first chip is connected to the first bridge in the same column as the active circuitry.

12. The first chip further comprises: a fourth continuous via pillar portion having a fourth pad at the interface between the first chip and the overlying chip, the fourth pad being aligned with a third pad, the fourth continuous via pillar portion not connected to the third continuous via pillar portion, the first chip further comprising: a fifth continuous via pillar portion, the fifth continuous via pillar portion having a fifth pad at the interface between the first chip and the underlying chip, the first chip further comprising: The multi-chip device of claim 11 further comprising a second bridge connecting the fifth continuous via pillar portion and the fourth continuous via pillar portion.

13. the first chip further includes a fourth continuous via pillar portion having a fourth pad at the interface between the first chip and the overlying chip, the fourth pad being aligned with the third pad, and the fourth continuous via pillar portion not connected to the third continuous via pillar portion; The overlying chip is a fifth continuous via pillar portion having a fifth pad at the interface between the first chip and the overlying chip, the fifth pad being connected to the second pad, the fifth continuous via pillar portion being connected to active circuitry of the overlying chip through an interconnect, the overlying chip further comprising: a sixth continuous via pillar portion aligned with the fifth continuous via pillar portion, the sixth continuous via pillar portion not connected to the fifth continuous via pillar portion, the overlying chip further comprising: a seventh continuous via pillar portion having a seventh pad at the interface between the first chip and the overlying chip, the seventh pad being connected to the fourth pad, the overlying chip further comprising: an eighth continuous via pillar portion aligned with the seventh continuous via pillar portion, the eighth continuous via pillar portion not connected to the seventh continuous via pillar portion, the overlying chip further comprising: a second bridge connecting the seventh continuous via pillar portion and the sixth continuous via pillar portion; the first continuous via pillar portion, the second continuous via pillar portion, the fifth continuous via pillar portion, and the sixth continuous via pillar portion are aligned in a first broken via pillar row; 12. The multi-chip device of claim 11, wherein the third contiguous via pillar portion, the fourth contiguous via pillar portion, the seventh contiguous via pillar portion, and the eighth contiguous via pillar portion are aligned in a second broken via pillar row.

14. 12. The multi-chip device of claim 11, wherein the underlying chip is configured to communicate signals to and from the first chip through the first pads and to communicate signals to and from the overlying chip through the third pads.

15. The multi-chip device of claim 1 or 11, wherein each chip in the stack of chips has an identical hardware layout.

Images