Semiconductor package structure and manufacturing method

Abstract

An embodiment of the present disclosure provides a semiconductor package structure and a manufacturing method thereof, the semiconductor package structure including: a first substrate having a first surface; a first chip stack located on the first substrate, the first chip stack including a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the first substrate, the first chip stack being electrically connected to the first surface of the first substrate; an intermediate layer located on the first chip stack, the intermediate layer having a first interconnection surface, the first interconnection surface having a first interconnection region and a second interconnection region, the first interconnection region being electrically connected to the first substrate; and a molding layer sealing the first chip stack, the intermediate layer and the first surface of the first substrate, the first interconnection region not being sealed by the molding layer, the second interconnection region being sealed by the molding layer, and a first material layer being formed on a sidewall between an upper surface of the molding layer on the second interconnection region and the first interconnection region.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This disclosure is filed based on and claims priority to a Chinese patent having application number 202210806439.8, filing date July 8, 2022, and title "Semiconductor Package Structure and Manufacturing Method," the entire contents of which are hereby incorporated by reference into this disclosure.

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor package structure and manufacturing method. [Background technology]

[0003] Across all sectors, industries and regions, the electronics industry continues to seek to deliver products that are lighter, faster, smaller, more versatile, more reliable and more cost-effective. To meet these ever-increasing needs from many different consumers, more circuits must be integrated to provide the necessary functionality. In almost every application, there is an ever-increasing need for reduced size, improved performance and increased functionality of integrated circuits. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of this, embodiments of the present disclosure provide a semiconductor package structure and manufacturing method. [Means for solving the problem]

[0005] According to a first aspect of the embodiment of the present disclosure, a first substrate having a first surface; a first chip stack located on the first substrate, the first chip stack including a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the first substrate, the first chip stack being electrically connected to a first surface of the first substrate; an intermediate layer located in the first chip stack, the intermediate layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, the first interconnect region electrically connected to the first substrate; A semiconductor package structure is provided, comprising: a molding layer that seals the first chip stack, the intermediate layer, and a first surface of the first substrate, wherein the first interconnect region is not sealed by the molding layer, the second interconnect region is sealed by the molding layer, and a first material layer is formed on a sidewall between an upper surface of the molding layer over the second interconnect region and the first interconnect region.

[0006] In some embodiments, the material of the first layer of material comprises a conductive material or an insulating material.

[0007] In some embodiments, a second material layer disposed on top of the mold layer; The material of the second material layer is the same as the material of the first material layer.

[0008] In some embodiments, a first conductive line, each of the first semiconductor chips being electrically connected to the first substrate via the first conductive line; The second interconnect region further includes a second conductive line, the second conductive line being electrically connected to the first substrate via the second conductive line.

[0009] In some embodiments, the first interconnect region includes a plurality of first pads and the second interconnect region includes a plurality of second pads, the number of the second pads being greater than the number of the first pads, and the area of ​​the second pads being smaller than the area of ​​the first pads.

[0010] In some embodiments, an included angle between a sidewall between a top surface of the mold layer and the first interconnect region and a direction perpendicular to the first substrate is a first included angle, the first included angle being greater than or equal to 0° and less than 90°.

[0011] In some embodiments, a second package structure including a first solder ball, the first solder ball being electrically connected to the first interconnect region; There is a preset height between an upper surface of the mold layer over the second interconnect region and the first interconnect region, and a height of the first solder ball is greater than the preset height.

[0012] According to a second aspect of the embodiment of the present disclosure, Providing a first substrate having a first surface; forming a first chip stack on the first substrate, the first chip stack including a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the first substrate, the first chip stack being electrically connected to a first surface of the first substrate; forming an intermediate layer on the first chip stack, the intermediate layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, the first interconnect region electrically connected to the first substrate; forming a mold layer, the mold layer encapsulating the first chip stack, the intermediate layer and a first surface of the first substrate, the first interconnect region being not encapsulated by the mold layer, the second interconnect region being encapsulated by the mold layer, there being a predetermined height between an upper surface of the mold layer over the second interconnect region and the first interconnect region, and a first material layer being formed on a sidewall between the upper surface of the mold layer over the second interconnect region and the first interconnect region.

[0013] In some embodiments, After the intermediate layer is formed, forming a first conductive line, wherein each of the first semiconductor chips is electrically connected to the first substrate via the first conductive line; The method further includes forming a second conductive line, the second interconnect region being electrically connected to the first substrate through the second conductive line.

[0014] In some embodiments, The method further includes forming a plurality of first pads in the first interconnect region and forming a plurality of second pads in the second interconnect region, wherein the number of the second pads is greater than the number of the first pads and the area of ​​the second pads is smaller than the area of ​​the first pads.

[0015] In some embodiments, The method further includes a step of forming a covering layer on a first interconnection region of the intermediate layer after the intermediate layer is formed, the covering layer including a first portion and a second portion located on both sides of the first portion, the first portion and the second portion being formed in an inverted U-shape to form a sealed cavity with the intermediate layer, and an included angle between the second portion and a direction perpendicular to the first substrate is a first included angle, the first included angle being greater than or equal to 0° and less than 90°.

[0016] In some embodiments, the cover layer material comprises a conductive material or an insulating material.

[0017] In some embodiments, forming a pre-mold layer that encapsulates the first chip stack, the intermediate layer, the cover layer, and a first surface of the first substrate; The method further includes removing a portion of the pre-mold layer and a first portion of the cover layer and leaving the second portion to form a first material layer.

[0018] In some embodiments, After the mold layer is formed, the method further includes forming a second material layer on an upper surface of the mold layer, where the material of the second material layer is the same as the material of the first material layer.

[0019] In some embodiments, The method further includes forming a second package structure including a bonding surface and a first solder ball located on the bonding surface, electrically connecting the first solder ball to the first interconnect region, and connecting the bonding surface to the second material layer.

[0020] In the embodiment of the present disclosure, by providing an intermediate layer, the second package structure may be connected to the first chip stack and the first substrate later through the first interconnection area on the intermediate layer, thereby realizing the interconnection between chip structures of different types or different specifications, so that the combination between different chip structures is more flexible. At the same time, it is also easier to perform testing and failure analysis, since the first chip stack and the second package structure that will be connected to the first chip stack later are packaged independently. At the same time, a first material layer can be formed on the sidewall between the top surface of the mold layer and the first interconnection area to form a protection for the contact area between the intermediate layer and the second package structure that will be connected to the intermediate layer later. [Brief description of the drawings]

[0021] [Figure 1] 1 is a structural schematic diagram of a semiconductor package structure according to an embodiment of the present disclosure; [Diagram 2] FIG. 2 is a structural schematic diagram of a first substrate according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a structural schematic diagram of an intermediate layer according to an embodiment of the present disclosure. [Figure 4a] 1 is another example of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 4b] 1 is another example of a semiconductor package structure according to an embodiment of the present disclosure. [Diagram 5] 1 is a flow chart of a method for manufacturing a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6a] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6b] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6c] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6d] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6e] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6f] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6g] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6h] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. [Figure 6i] 1A-1D are structural schematic diagrams of a device in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] In order to more clearly describe the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces drawings necessary for the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0023] The exemplary embodiments disclosed in the present disclosure will be described in more detail below with reference to the drawings. The exemplary embodiments of the present disclosure are shown in the drawings, but the present disclosure can be realized in various forms and is not limited to the specific embodiments described herein. On the contrary, these embodiments are provided for a clearer understanding of the present disclosure and can fully convey the scope of the present disclosure to those skilled in the art.

[0024] In the following description, many specific details are described to provide a more complete understanding of the present disclosure. However, it is clear to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other examples, in order to avoid obscuring the present disclosure, some technical features well known in the art are not described, that is, not all features of the actual embodiment are described in this specification, and well-known functions and structures are not described in detail.

[0025] In the drawings, the sizes of layers, regions and elements as well as their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

[0026] When an element or layer is referred to as being "located...", "adjacent to...", "connected to" or "coupled" to another element or layer, it may be directly located, adjacent to, connected to or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "located directly to...", "directly adjacent to...", "directly connected to" or "directly coupled" to another element or layer, there are no intervening elements or layers. Although terms such as first, second, third, etc. may be used to describe various elements, members, regions, layers, and / or portions, these elements, members, regions, layers, and / or portions should not be limited to these terms. These terms are only intended to distinguish one element, member, region, layer, or portion from another element, member, region, layer, or portion. Thus, a first element, member, region, layer, or portion discussed below may be referred to as a second element, member, region, layer, or portion without departing from the teachings of the present disclosure. The discussion of a second element, member, region, layer or section does not imply that the first element, member, region, layer or section is necessarily present in the present disclosure.

[0027] Spatial relationship terms such as, for example, "under...", "below...", "below", "below...", "above...", "above" are used herein to facilitate description and thereby describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that the spatial relationship terms are intended to include different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is inverted, then an element or feature would be oriented as "above" the other element or feature if described as "below" or "beneath" or "below" the other element or feature. Thus, the exemplary terms "under..." and "below..." can include two orientations: above and below. The device may be oriented in another direction (rotated 90 degrees or at other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0028] The terms used herein are only for the purpose of describing specific examples, but are not intended to limit the disclosure. As used herein, the singular forms "a", "one" and "said" are intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprise" and / or "comprise" when used herein determine the presence of said features, integers, steps, operations, elements and / or members, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, members and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0029] In order to fully understand the present disclosure, the following description provides detailed steps and detailed structures to describe the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but the present disclosure can have other embodiments in addition to these detailed descriptions.

[0030] An embodiment of the present disclosure provides a semiconductor package structure. Figure 1 is a structural schematic diagram of the package structure according to an embodiment of the present disclosure.

[0031] Referring to FIG. 1 and FIG. 2, the semiconductor package structure includes: a first substrate 10 having a first surface 101; a first chip stack 20 located on the first substrate 10, the first chip stack 20 including a plurality of first semiconductor chips 21 stacked in sequence along a direction perpendicular to the first substrate 10, the first chip stack 20 being electrically connected to a first surface 101 of the first substrate 10; an intermediate layer 30 located in the first chip stack 20, the intermediate layer 30 having a first interconnection surface 301, the first interconnection surface 301 having a first interconnection region 31 and a second interconnection region 32, the first interconnection region 31 being electrically connected to the first substrate 10; and a mold layer 40 that seals the first chip stack 20, the intermediate layer 30 and the first surface 101 of the first substrate 10, wherein the first interconnect region 31 is not sealed by the mold layer 40, the second interconnect region 32 is sealed by the mold layer 40, and a first material layer 81 is formed on a sidewall between an upper surface 401 of the mold layer 40 on the second interconnect region 32 and the first interconnect region 31.

[0032] In the embodiment of the present disclosure, by providing an intermediate layer, the second package structure may be connected to the first chip stack and the first substrate later through the first interconnection area on the intermediate layer, thereby realizing the interconnection between chip structures of different types or different specifications, so that the combination between different chip structures is more flexible. At the same time, it is also easier to perform testing and failure analysis, since the first chip stack and the second package structure that will be connected to the first chip stack later are packaged independently. At the same time, a first material layer can be formed on the sidewall between the top surface of the mold layer and the first interconnection area to form a protection for the contact area between the intermediate layer and the second package structure that will be connected to the intermediate layer later.

[0033] FIG. 2 is a structural schematic diagram of a first substrate according to an embodiment of the present disclosure.

[0034] In some embodiments, the first substrate 10 may be a Printed Circuit Board (PCB) or a rewiring board.

[0035] As shown in FIG. 2, the first substrate 10 includes a substrate base 11, a substrate upper insulating dielectric layer 12 and a substrate lower insulating dielectric layer 13 provided on the upper and lower surfaces of the substrate base 11, respectively.

[0036] The substrate base 11 may be silicon-based, germanium-based, silicon germanium-based, silicon carbide-based, SOI (Silicon On Insulator)-based or GOI (Germanium On Insulator)-based, or may be a base containing other elemental semiconductors or compound semiconductors, such as glass-based or III-V compound-based (such as gallium nitride-based or gallium arsenide-based), or may be a layered structure, such as Si / SiGe, or may be another epitaxial structure, such as SGOI (Silicon Germanium On Insulator).

[0037] The upper substrate insulating dielectric layer 12 and the lower substrate insulating dielectric layer 13 may be solder mask layers, for example, the material of the upper substrate insulating dielectric layer 12 and the lower substrate insulating dielectric layer 13 may be green paint.

[0038] In the embodiment of the present disclosure, the first surface 101 of the first substrate 10 is the upper surface of the substrate upper insulating dielectric layer 12. The first substrate 10 further includes a second surface 102 which is the lower surface of the substrate lower insulating dielectric layer 13.

[0039] The first substrate 10 further includes substrate upper connection pads 14 located in the substrate upper insulating dielectric layer 12, substrate lower connection pads 15 located in the substrate lower insulating dielectric layer 13, and substrate connection vias 16 penetrating the substrate base 11 to interconnect the substrate upper connection pads 14 and the substrate lower connection pads 15.

[0040] The material of the substrate upper connection pad 14 and the substrate lower connection pad 15 can include at least one of aluminum, copper, nickel, tungsten, platinum, and gold. The substrate connection via 16 can be a through-silicon-via (TSV).

[0041] The first substrate 10 further includes substrate connection bumps 17, which can electrically connect the semiconductor package structure to an external device, and can receive at least one of control signals, power signals, and ground signals for operating the first chip stack from the external device, or can receive data signals to be stored in the first chip stack from the external device, and can also provide data in the first chip stack to an external device.

[0042] The substrate connection bumps 17 include a conductive material. In the embodiment of the present disclosure, the substrate connection bumps 17 are solder balls, and the shapes of the substrate connection bumps provided in the embodiment of the present disclosure are merely viable specific embodiments of the embodiment of the present disclosure and do not constitute limitations to the present disclosure, and the substrate connection bumps may have other shapes and structures. The number, spacing, and location of the substrate connection bumps are not limited to any particular arrangement and may be variously modified.

[0043] 2, the first substrate 10 further includes a first signal transmission region 110 and a second signal transmission region 120 located on opposite sides of the first substrate 10. The first signal transmission region 110 is electrically connected to the first chip stack 20, and the second signal transmission region 120 is electrically connected to the intermediate layer 30.

[0044] The first substrate 10 further includes a third signal transmission region 130 located between the first signal transmission region 110 and the second signal transmission region 120, and the first chip stack 20 is located in the third signal transmission region 130.

[0045] 1, the first chip stack 20 includes a plurality of first semiconductor chips 21 stacked in sequence along a direction perpendicular to the first substrate 10. In this embodiment, by stacking the plurality of first semiconductor chips in sequence in an upward direction, it is possible to save horizontal area of ​​the semiconductor package structure.

[0046] In one embodiment of the present disclosure, the first semiconductor chip may be a DRAM chip.

[0047] FIG. 3 is a structural schematic diagram of an intermediate layer according to an embodiment of the present disclosure.

[0048] As shown in FIG. 3, the intermediate layer 30 includes a base 33, and an intermediate upper insulating dielectric layer 34 and an intermediate lower insulating dielectric layer 35 provided on the upper and lower surfaces of the base 33, respectively.

[0049] The base 33 may be silicon-based, germanium-based, silicon germanium-based, silicon carbide-based, SOI (Silicon On Insulator)-based or GOI (Germanium On Insulator)-based, or may be a base containing other elemental semiconductors or compound semiconductors, such as glass-based or III-V compound-based (such as gallium nitride-based or gallium arsenide-based), or may be a layered structure, such as Si / SiGe, or may be another epitaxial structure, such as SGOI (Silicon Germanium On Insulator).

[0050] The intermediate upper insulating dielectric layer 34 and the intermediate lower insulating dielectric layer 35 may be solder mask layers, for example, the material of the intermediate upper insulating dielectric layer 34 and the intermediate lower insulating dielectric layer 35 may be green paint.

[0051] In one embodiment, there is an electromagnetic shielding layer (not shown) in the base 33 of the intermediate layer 30. By providing an electromagnetic shielding layer in the base of the intermediate layer, information interference between the second package structure and the first chip stack can be prevented from affecting the operation of the device.

[0052] The intermediate layer 30 includes a first interconnection region 31 and a second interconnection region 32, the first interconnection region 31 includes a plurality of first pads 311, the second interconnection region 32 includes a plurality of second pads 321, the number of the second pads 321 is greater than the number of the first pads 311, and the area of ​​the second pads 321 is smaller than the area of ​​the first pads 311.

[0053] Because the first pads need to be matched and interconnected with the second package structure later, the layout design is relatively fixed, and because the second pads interconnect the second package structure and the first substrate, the layout design is more flexible, and the second pads are designed to be more numerous and smaller in area, which can improve signal transmission efficiency.

[0054] The material of the first pad 311 and the second pad 321 may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold.

[0055] In one embodiment, in a direction perpendicular to the first substrate 10, the first substrate 10 has a first thickness and the intermediate layer 30 has a second thickness, the first thickness being greater than the second thickness.

[0056] Continuing to refer to FIG. 1, the semiconductor package structure further includes a first conductive line 51, where each of the first semiconductor chips 21 is electrically connected to the first substrate 10 via the first conductive line 51, and a second conductive line 52, where the second interconnection region 32 is electrically connected to the first substrate 10 via the second conductive line 52.

[0057] Specifically, the first semiconductor chip 21 has a first connection end 201, and the first connection end 201 and the first signal transmission region 110 are located on the same side, and a first conductive line 51 is extended from the first connection end 201 to the first transmission region 110 to realize an electrical connection between the first semiconductor chip 21 and the first substrate 10.

[0058] A second pad 321 is formed in the second interconnection region 32, and a second conductive line 52 is extended from the second pad 321 to the second transmission region 120 to realize an electrical connection between the intermediate layer 30 and the first substrate 10.

[0059] In an embodiment of the present disclosure, the first chip stack and the first substrate are electrically connected by a wire bonding method, and the wire bonding method includes an overhang method and a film on wire (FOW) method.

[0060] 1, wire bonding is performed by the overhang method. Two adjacent first semiconductor chips 21 are connected by an adhesive film 60, and the adhesive film 60 does not cover the first connection terminals 201 and the first conductive lines 51 on the first semiconductor chip 21 below it, and the adhesive film 60 and the first semiconductor chip 21 below it are provided in a shifted manner.

[0061] In some other embodiments, the wire bonding is performed by a wire bonding method (not shown). The first semiconductor chips are aligned along a direction perpendicular to the first substrate, and an adhesive film between two adjacent first semiconductor chips covers the first connection ends and the first conductive lines on the first semiconductor chips below it.

[0062] It will be understood that the electrical connection by wire drawing in the embodiments of the present disclosure is used only as a specific subembodiment of a possible embodiment of the embodiments of the present disclosure and does not constitute a limitation to the present disclosure, and that electrical connection can also be made in other ways, such as hybrid bonding or bump interconnection.

[0063] In one embodiment, the included angle between the sidewall between the upper surface 401 of the mold layer 40 and the first interconnect region 31 and a direction perpendicular to the first substrate 10 is a first included angle, which is greater than 0° and less than 90°.

[0064] 1, the angle between the sidewall between the upper surface 401 of the mold layer 40 and the first interconnect region 31 and the direction perpendicular to the first substrate 10 is 0°, that is, the sidewall between the upper surface 401 of the mold layer 40 and the first interconnect region 31 is perpendicular to the first substrate 10. Providing the sidewall of the mold layer with a vertical shape makes the process simpler.

[0065] 4a, the included angle between the sidewalls of the upper surface 401 of the molding layer 40 and the first interconnect region 31 and the direction perpendicular to the first substrate 10 is a, and the included angle a is greater than 0° and less than 90°. Providing the sidewalls of the molding layer with a non-vertical shape can make subsequent interconnection with a second package structure easier.

[0066] In one embodiment, the material of the first material layer 81 includes a conductive material or an insulating material. If the material of the first material layer is a conductive material, it can play the role of electrostatic protection, and if the material of the first material layer is an insulating material, it can play the role of insulation isolation.

[0067] In one embodiment, the semiconductor package structure further includes a second material layer 82 located on the upper surface 401 of the molding layer 40, and the material of the second material layer 82 is the same as the material of the first material layer 81.

[0068] The second material layer is located between the mold layer and the second package structure, thereby realizing sealing of the first chip stack and the second package structure, and at the same time protecting the joint surface between the mold layer and the second package structure, and also preventing external moisture and electromagnetic interference.

[0069] In one embodiment, when both the first material layer 81 and the second material layer 82 are conductive materials, a thermal conduction channel can be formed from the periphery of the first interconnection region 31 on the intermediate layer to the mold layer 40 to improve the thermal performance of the product; specifically, the first material layer 81 and the second material layer 82 may be copper, tin, or a copper-tin alloy, etc.

[0070] In one embodiment, when both the first material layer 81 and the second material layer 82 are insulating materials, a sealing protection ring can be formed from the periphery of the first interconnect region 31 on the intermediate layer to the mold layer 40 to improve the structural stability of the product; specifically, the first material layer 81 and the second material layer 82 can be a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer.

[0071] In one embodiment, the first material layer 81 may be copper, tin, or a copper-tin alloy, etc., and the second material layer 82 may be silicon dioxide.

[0072] In one embodiment, the first material layer 81 may be silicon dioxide and the second material layer 82 may be copper, tin, or a copper-tin alloy, or the like.

[0073] In one embodiment, the semiconductor package structure further includes a second package structure 70, the second package structure 70 including a first solder ball 71, the first solder ball 71 being electrically connected to the first interconnection region 31, there being a preset height h between the upper surface 401 of the mold layer 40 on the second interconnection region 32 and the first interconnection region 31, and the height H of the first solder ball 71 being greater than the preset height h.

[0074] In the embodiments of the present disclosure, by setting the height of the first solder balls higher than the height between the top surface of the mold layer and the first interconnection area, the second package structure may be tightly connected to the intermediate layer, and at the same time, after the second package structure is connected to the intermediate layer, a gap may exist between the second package structure and the mold layer, which can improve the heat dissipation efficiency of the controller and reduce the thermal impact on the chip.

[0075] The second package structure 70 further includes a second substrate 72, the structure of which may be the same as or different from that of the substrate 10, and will not be described here.

[0076] In an embodiment of the present disclosure, the second package structure 70 further includes a bonding surface 701, and the first solder ball 71 is located on the bonding surface 701 and electrically connected to the second substrate 72 through the bonding surface 701.

[0077] In an embodiment of the present disclosure, as shown in FIG. 1 , the material of the bonding surface 701 may be silicon dioxide, and when the material of the bonding surface 701 is silicon dioxide, the second material layer 82 on the mold layer 40 is a silicon dioxide layer, and with such an arrangement, when the first solder ball 71 is bonded to the first pad 311, the bonding between the mold layer 40 and the second package structure 70 is realized by the second material layer 82.

[0078] In an embodiment of the present disclosure, as shown in FIG. 4b, the second material layer 82 may be a copper layer, a tin layer or a copper-tin layer. When the second material layer 82 is a copper layer, a tin layer or a copper-tin layer, a copper layer, a tin layer or a copper-tin layer is provided at a position of the bonding surface 701 corresponding to the second material layer 82, and when the first solder ball 71 is bonded to the first pad 311, the bonding between the mold layer 40 and the second package structure 70 is realized by the second material layer 82.

[0079] In one embodiment, the mold layer 40 has a first thickness in a direction perpendicular to the first substrate 10, and the second package structure 70 includes a second mold layer 73, which has a second thickness in a direction perpendicular to the first substrate 10, and the first thickness is equal to or greater than the second thickness. By setting the thickness in this manner, it is possible to effectively prevent warpage from occurring after the second package structure is bonded to an intermediate layer.

[0080] The second package structure 70 further includes a second semiconductor chip structure (not shown), which may be the same or different in type as the first chip stack 20. The second semiconductor chip structure of the second package structure 70 is electrically connected to a second substrate 72.

[0081] For example, the second semiconductor chip structure may be a Universal Flash memory chip (UFS: Universal File Store).

[0082] The semiconductor package structure provided by the embodiments of the present disclosure can be applied to a multi-chip package (UMCP: UFS multi-chip package) with a package on package (PoP) structure.

[0083] An embodiment of the present disclosure further provides a manufacturing method for a semiconductor package structure, the details of which are shown in Fig. 5. As shown in the figure, the method includes the following steps:

[0084] In step 501, a first substrate having a first surface is provided.

[0085] In step 502, a first chip stack is formed on the first substrate, the first chip stack including a plurality of first semiconductor chips stacked sequentially along a direction perpendicular to the first substrate, and the first chip stack is electrically connected to a first surface of the first substrate.

[0086] In step 503, an intermediate layer is formed on the first chip stack, the intermediate layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, and the first interconnect region is electrically connected to the first substrate.

[0087] In step 504, a mold layer is formed, the mold layer encapsulating the first chip stack, the intermediate layer and a first surface of the first substrate, the first interconnect region is not encapsulated by the mold layer, the second interconnect region is encapsulated by the mold layer, there is a preset height between an upper surface of the mold layer over the second interconnect region and the first interconnect region, and a first material layer is formed on a sidewall between the upper surface of the mold layer over the second interconnect region and the first interconnect region.

[0088] The manufacturing method of a semiconductor package structure according to the embodiment of the present disclosure will be described in more detail below with reference to specific examples.

[0089] 6a to 6i are structural schematic diagrams in a manufacturing process of a semiconductor package structure according to an embodiment of the present disclosure.

[0090] First, referring to FIG. 6a, step 501 is carried out, which is to provide a first substrate 10 having a first surface.

[0091] In some embodiments, the first substrate 10 may be a printed circuit board (PCB) or a rewiring board.

[0092] As shown in FIG. 2, the first substrate 10 includes a substrate base 11, a substrate upper insulating dielectric layer 12 and a substrate lower insulating dielectric layer 13 provided on the upper and lower surfaces of the substrate base 11, respectively.

[0093] The substrate base 11 may be silicon-based, germanium-based, silicon germanium-based, silicon carbide-based, SOI (Silicon On Insulator)-based or GOI (Germanium On Insulator)-based, or may be a base containing other elemental semiconductors or compound semiconductors, such as glass-based or III-V compound-based (such as gallium nitride-based or gallium arsenide-based), or may be a layered structure, such as Si / SiGe, or may be another epitaxial structure, such as SGOI (Silicon Germanium On Insulator).

[0094] The upper substrate insulating dielectric layer 12 and the lower substrate insulating dielectric layer 13 may be solder mask layers, for example, the material of the upper substrate insulating dielectric layer 12 and the lower substrate insulating dielectric layer 13 may be green paint.

[0095] In the embodiment of the present disclosure, the first surface 101 of the first substrate 10 is the upper surface of the substrate upper insulating dielectric layer 12. The first substrate 10 further includes a second surface 102 which is the lower surface of the substrate lower insulating dielectric layer 13.

[0096] The first substrate 10 further includes substrate upper connection pads 14 located in the substrate upper insulating dielectric layer 12, substrate lower connection pads 15 located in the substrate lower insulating dielectric layer 13, and substrate connection vias 16 penetrating the substrate base 11 to interconnect the substrate upper connection pads 14 and the substrate lower connection pads 15.

[0097] The material of the substrate top connection pad 14 and the substrate bottom connection pad 15 can include at least one of aluminum, copper, nickel, tungsten, platinum and gold. The substrate connection via 16 can be a through silicon via (TSV).

[0098] The first substrate 10 further includes a first signal transmission region 110 and a second signal transmission region 120 located on opposite sides of the first substrate 10. The first signal transmission region 110 is electrically connected to a first chip stack to be formed later, and the second signal transmission region 120 is electrically connected to an intermediate layer to be formed later.

[0099] In some embodiments, the first signal transmission region 110 is not interconnected to the second signal transmission region 120 .

[0100] The first substrate 10 further includes a third signal transmission region 130 located between the first signal transmission region 110 and the second signal transmission region 120, and later the first chip stack is located in the third signal transmission region 130.

[0101] In some embodiments, the first signal transmission region 110 is interconnected to a third signal transmission region 130 , and the third signal transmission region 130 is not interconnected to the second signal transmission region 120 .

[0102] Next, referring to FIG. 6b, step 502 is performed in which a first chip stack 20 is formed on the first substrate 10, the first chip stack 20 including a plurality of first semiconductor chips 21 stacked sequentially along a direction perpendicular to the first substrate 10, and the first chip stack 20 is electrically connected to a first surface 101 of the first substrate 10.

[0103] In the embodiment of the present disclosure, a plurality of first semiconductor chips are stacked one on top of the other, thereby saving horizontal area of ​​the semiconductor package structure.

[0104] The two adjacent chips 21 are connected by an adhesive film 60 , and the chip stack 20 and substrate 10 are also connected by an adhesive film 60 .

[0105] Next, referring to Figures 6c and 6d, step 503 is performed in which an intermediate layer 30 is formed on the first chip stack 20, the intermediate layer 30 having a first interconnection surface 301, the first interconnection surface 301 having a first interconnection region 31 and a second interconnection region 32, and the first interconnection region 31 is electrically connected to the first substrate 10.

[0106] Specifically, first, referring to FIG. 6c, a carrier tape 2 is attached to a ring 1, then an adhesive film 60 is attached to the carrier tape 2, and then an intermediate layer is attached to the adhesive film 60, in which the intermediate layer is in the shape of a whole strip, and the intermediate layer is cut to form individual units as shown in FIG. 6c.

[0107] Next, referring to FIG. 6 d , an intermediate layer 30 is formed on the first chip stack 20 .

[0108] Specifically, first, an adhesive layer 60 is formed on the first chip stack 20, and then the single intermediate layer 30 formed in FIG.

[0109] As shown in FIG. 3, the intermediate layer 30 includes a base 33, and an intermediate upper insulating dielectric layer 34 and an intermediate lower insulating dielectric layer 35 provided on the upper and lower surfaces of the base 33, respectively.

[0110] The base 33 may be a silicon base, a germanium base, a silicon germanium base, a silicon carbide base, an SOI (Silicon On Insulator) base, or a GOI (Germanium On Insulator) base, or a base containing other elemental semiconductors or compound semiconductors, such as a glass base or a III-V compound base (such as a gallium nitride base or a gallium arsenide substrate), or a layered structure, such as Si / SiGe, or another epitaxial structure, such as SGOI (Silicon Germanium On Insulator), etc.

[0111] The intermediate upper insulating dielectric layer 34 and the intermediate lower insulating dielectric layer 35 may be solder mask layers, for example, the material of the intermediate upper insulating dielectric layer 34 and the intermediate lower insulating dielectric layer 35 may be green paint.

[0112] In one embodiment, there is an electromagnetic shielding layer (not shown) in the base 33 of the intermediate layer 30. By providing an electromagnetic shielding layer in the base of the intermediate layer, information interference between the second package structure and the first chip stack can be prevented from affecting the operation of the device.

[0113] In one embodiment, the method further includes a step of forming a plurality of first pads 311 in the first interconnect region 31 and a plurality of second pads 321 in the second interconnect region 32, the number of the second pads 321 being greater than the number of the first pads 311 and the area of ​​the second pads 321 being smaller than the area of ​​the first pads 311.

[0114] Because the first pads need to be matched and interconnected with the second package structure later, the layout design is relatively fixed, and because the second pads interconnect the second package structure and the first substrate, the layout design is more flexible, and the second pads are designed to be more numerous and smaller in area, which can improve signal transmission efficiency.

[0115] The material of the first pad 311 and the second pad 321 may include at least one of aluminum, copper, nickel, tungsten, platinum, and gold.

[0116] In one embodiment, in a direction perpendicular to the first substrate 10, the first substrate 10 has a first thickness and the intermediate layer 30 has a second thickness, the first thickness being greater than the second thickness.

[0117] Next, still referring to FIG. 6d, after the intermediate layer 30 is formed, a covering layer 80 is formed on the first interconnection region 31 of the intermediate layer 30, the covering layer 80 includes a first portion 801 and a second portion 802 located on both sides of the first portion 801, the first portion 801 and the second portion 802 are formed in an inverted U-shape to form a sealed cavity with the intermediate layer 30, and the included angle between the second portion 802 and a direction perpendicular to the first substrate 10 is a first included angle, and the first included angle is greater than or equal to 0° and less than 90°.

[0118] In the embodiment shown in FIG. 6d, the angle between the second portion 802 of the coating layer 80 and the direction perpendicular to the first substrate 10 is 0°, and the structure of the mold layer formed is that shown in FIG. 1; in another embodiment, the angle between the second portion 802 of the coating layer and the direction perpendicular to the first substrate is greater than 0° and less than 90°, and the structure of the mold compound formed is that shown in FIG. 4a.

[0119] In the embodiment of the present disclosure, by forming a covering layer on the first interconnection region of the intermediate layer, there is no need to use an irregular packaging mold to expose the first interconnection region after the molding layer is formed later, and the first interconnection region can be directly exposed by removing the first portion of the covering layer, which makes the manufacturing cost of the irregular packaging mold high and the process more complicated. Thus, by forming a covering layer on the first interconnection region, the cost can be reduced and at the same time the manufacturing process is made simpler.

[0120] In one embodiment, the material of the cover layer 80 includes a conductive material or an insulating material.

[0121] After the covering layer 80 is formed, the intermediate layer attached to the ring 1 needs to be cleaned to avoid the intermediate layer being contaminated and affecting the performance of the semiconductor package structure.

[0122] Next, after the intermediate layer 30 is formed, a first conductive line 51 is formed, and each of the first semiconductor chips 21 is electrically connected to the first substrate 10 via the first conductive line 51, and a second conductive line 52 is formed, and the second interconnection region 32 is electrically connected to the first substrate 10 via the second conductive line 52.

[0123] Specifically, the first semiconductor chip 21 has a first connection end 201, and the first connection end 201 and the first signal transmission region 110 are located on the same side, and a first conductive line 51 is extended from the first connection end 201 to the first transmission region 110 to realize an electrical connection between the first semiconductor chip 21 and the first substrate 10.

[0124] A second pad 321 is formed in the second interconnection region 32, and a second conductive line 52 is extended from the second pad 321 to the second transmission region 120 to realize an electrical connection between the intermediate layer 30 and the first substrate 10.

[0125] In an embodiment of the present disclosure, the first chip stack and the first substrate are electrically connected by a wire bonding method, and the wire bonding method includes an overhang method and a film on wire (FOW) method.

[0126] In the embodiment shown in Fig. 6d, the wire bonding is performed in an overhang manner. Two adjacent first semiconductor chips 21 are connected by an adhesive film 60, which does not cover the first connection terminals 201 and the first conductive lines 51 on the first semiconductor chip 21 below it, and the adhesive film 60 and the first semiconductor chip 21 below it are offset from each other.

[0127] In some other embodiments, the wire bonding is performed by a film-on-wire method (not shown). A plurality of the first semiconductor chips are aligned along a direction perpendicular to the first substrate, and an adhesive film between two adjacent first semiconductor chips covers the first connection ends and the first conductive lines on the first semiconductor chips below it.

[0128] Next, referring to Figures 6e to 6g, a step 504 is performed, which includes forming a mold layer 40, the mold layer 40 sealing the first chip stack 20, the intermediate layer 30 and the first surface 101 of the first substrate 10, the first interconnect region 31 is not sealed by the mold layer 40, the second interconnect region 32 is sealed by the mold layer 40, there is a predetermined height h between the upper surface 401 of the mold layer 40 on the second interconnect region 32 and the first interconnect region 31, and a first material layer 81 is formed on the sidewall between the upper surface 401 of the mold layer 40 on the second interconnect region 32 and the first interconnect region 31.

[0129] Specifically, first, referring to FIG. 6e, after a covering layer 80 is formed, a first package mold 91 and a second package mold 92 are formed, and the surface of the first package mold 91 is parallel to the surface of the first substrate 10, the first package mold 91 is located above the covering layer 80 and is at a certain distance from the covering layer 80, and the second package mold 92 is located below the first substrate 10 and is parallel to the surface of the first substrate 10.

[0130] Next, referring to FIG. 6f, the method further includes a step of using the first package mold 91 and the second package mold 92 as a mask to form a mold layer pre-layer 400 that seals the first chip stack 20, the intermediate layer 30, the covering layer 80 and the first surface 101 of the first substrate 10.

[0131] In one embodiment, pre-mold layer 400 includes an EMC material.

[0132] After the pre-mold layer 400 is formed, the first package mold 91 and the second package mold 92 are removed.

[0133] Next, referring to FIG. 6g, a part of the pre-mold layer 400 and the first portion 801 of the cover layer 80 are removed, leaving the second portion 802, and a first material layer 81 is formed.

[0134] Specifically, a polishing process can be used to polish the surface of the pre-mold compound layer 400, and a part of the pre-mold compound layer 400 and the first portion 801 of the cover layer 80 can be removed.

[0135] Still referring to FIG. 6g, after the molding layer 40 is formed, substrate connection bumps 17 are formed on the second surface 102 of the first substrate 10, where the substrate connection bumps 17 include a conductive material.

[0136] Next, referring to FIG. 6h, the method further includes a step of forming a second material layer on the upper surface 401 of the mold layer 10 after the mold layer 40 is formed, wherein the material of the second material layer 82 is the same as the material of the first material layer 81.

[0137] Specifically, first, a pre-layer of a second material layer (not shown) is formed on the upper surface 401 of the mold layer 40 and the surface of the intermediate layer 30, and then the pre-layer of the second material layer on the surface of the intermediate layer 30 is removed, leaving the pre-layer of the second material layer on the upper surface 401 of the mold layer 40, thereby forming the second material layer 82.

[0138] Next, referring to FIG. 6i, the method further includes forming a second package structure 70 including a bonding surface 701 and a first solder ball 71 located on the bonding surface 701, electrically connecting the first solder ball 71 to the first interconnection region 31, and connecting the bonding surface 701 to the second material layer 82.

[0139] In one embodiment, the height H of the first solder balls 71 is greater than the height h between the top surface of the molding layer 40 and the first interconnection region 31 .

[0140] In the embodiments of the present disclosure, by setting the height of the first solder balls higher than the height between the top surface of the mold layer and the first interconnection area, the second package structure may be tightly connected to the intermediate layer, and at the same time, after the second package structure is connected to the intermediate layer, a gap may exist between the second package structure and the mold layer, which can improve the heat dissipation efficiency of the controller and reduce the thermal impact on the chip.

[0141] The second package structure 70 further includes a second substrate 72, the structure of which may be the same as or different from that of the substrate 10, and will not be described here.

[0142] In an embodiment of the present disclosure, the second package structure 70 further includes a bonding surface 701, and the first solder ball 71 is located on the bonding surface 701 and electrically connected to the second substrate 72 through the bonding surface 701.

[0143] In an embodiment of the present disclosure, as shown in FIG. 6i, the material of the bonding surface 701 may be silicon dioxide, and when the material of the bonding surface 701 is silicon dioxide, the second material layer 82 on the molding layer 40 is a silicon dioxide layer, and with such an arrangement, when the first solder ball 71 is bonded to the first pad 311, the bonding between the molding layer 40 and the second package structure 70 is realized by the second material layer 82.

[0144] In an embodiment of the present disclosure, as shown in FIG. 4b, the second material layer 82 may be a copper layer, a tin layer or a copper-tin layer. When the second material layer 82 is a copper layer, a tin layer or a copper-tin layer, a copper layer, a tin layer or a copper-tin layer is provided at a position of the bonding surface 701 corresponding to the second material layer 82, and when the first solder ball 71 is bonded to the first pad 311, the second material layer 82 realizes bonding between the mold layer 40 and the second package structure 70.

[0145] In one embodiment, the molding layer 40 has a first thickness in a direction perpendicular to the first substrate 10, and the second package structure 70 includes a second molding layer 73, the second molding layer 73 having a second thickness in a direction perpendicular to the first substrate 10, the first thickness being greater than or equal to the second thickness. In one embodiment, the second molding layer 73 includes an EMC material.

[0146] The second package structure 70 further includes a second semiconductor chip structure (not shown), which may be the same or different in type as the first chip stack 20. The second semiconductor chip structure of the second package structure 70 is electrically connected to a second substrate 72.

[0147] For example, the second semiconductor chip structure may be a Universal Flash memory chip (UFS: Universal File Store).

[0148] The above are merely preferred embodiments of the present disclosure, and are not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure. [Industrial Applicability]

[0149] In the embodiment of the present disclosure, by providing an intermediate layer, the second package structure may be connected to the first chip stack and the first substrate later through the first interconnection area on the intermediate layer, thereby realizing the interconnection between chip structures of different types or different specifications, so that the combination between different chip structures is more flexible. At the same time, it is also easier to perform testing and failure analysis because the first chip stack and the second package structure that will be connected to the first chip stack later are packaged independently. At the same time, a first material layer can be formed on the sidewall between the top surface of the mold layer and the first interconnection area to form a protection for the contact area between the intermediate layer and the second package structure that will be connected to the intermediate layer later. [Explanation of symbols]

[0150] 1 Ring 2 Carrier tape 10 First board 101 Page 1 102 Side 2 11 PCB base 12 Top insulating dielectric layer of substrate 13 Bottom insulating dielectric layer 14 Top of board connection pad 15 Bottom board connection pad 16 Substrate connection vias 17 Substrate connection bumps 110 First signal transmission area 120 Second signal transmission area 130 Third signal transmission area 20 First chip stack 21 First semiconductor chip 201 First connection end 30 Middle Class 31 First Interconnection Area 32 Second Interconnection Area 301 First interconnection surface 311 1st Pad 321 2nd Pad 33 Base 34 Middle top insulating dielectric layer 35 Middle bottom insulating dielectric layer 40 Mold Layer 401 Top surface 400 mold layer front layer 51 First conductive wire 52 Second conductive wire 60 Adhesive Film 70 Second package structure 701 Joint surface 71 First solder ball 72 Second board 73 2nd mold layer 80 Covering layer 801 Part 1 802 Part 2 81 1st material layer 82 Second material layer 91 First package mold 92 2nd Package Mold

Claims

1. A semiconductor package structure, comprising: a first substrate having a first surface; a first chip stack located on the first substrate, the first chip stack including a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the first substrate, the first chip stack being electrically connected to a first surface of the first substrate; an intermediate layer located in the first chip stack, the intermediate layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, the first interconnect region electrically connected to the first substrate; a molding layer encapsulating the first chip stack, the intermediate layer, and a first surface of the first substrate, the first interconnect region being unencapsulated by the molding layer, the second interconnect region being encapsulated by the molding layer, and a first material layer being formed on a sidewall between a top surface of the molding layer over the second interconnect region and the first interconnect region; a second material layer on top of the mold layer; a second package structure including a bonding surface and a first solder ball located on the bonding surface, the first solder ball being electrically connected to the first interconnect region, and a portion of the bonding surface corresponding to the second material layer being bonded to the second material layer.

2. the material of the first material layer includes a conductive material or an insulating material; The semiconductor package structure of claim 1 , wherein the material of the second material layer is the same as the material of the first material layer.

3. a first conductive line, each of the first semiconductor chips being electrically connected to the first substrate via the first conductive line; 2. The semiconductor package structure of claim 1, further comprising: a second conductive line, wherein the second interconnect region is electrically connected to the first substrate through the second conductive line.

4. 2. The semiconductor package structure of claim 1, wherein the first interconnect region includes a plurality of first pads, the second interconnect region includes a plurality of second pads, the number of the second pads is greater than the number of the first pads, and an area of ​​the second pads is smaller than an area of ​​the first pads.

5. 2. The semiconductor package structure of claim 1, wherein an included angle between a sidewall between the top surface of the molding layer and the first interconnect region and a direction perpendicular to the first substrate is a first included angle, the first included angle being greater than or equal to 0° and less than 90°.

6. The semiconductor package structure of claim 1, wherein there is a predetermined height between an upper surface of the mold layer on the second interconnection region and the first interconnection region, and a height of the first solder ball is greater than the predetermined height.

7. A method for manufacturing a semiconductor package structure, comprising: Providing a first substrate having a first surface; forming a first chip stack on the first substrate, the first chip stack including a plurality of first semiconductor chips stacked in sequence along a direction perpendicular to the first substrate, the first chip stack being electrically connected to a first surface of the first substrate; forming an intermediate layer on the first chip stack, the intermediate layer having a first interconnect surface, the first interconnect surface having a first interconnect region and a second interconnect region, the first interconnect region electrically connected to the first substrate; forming a mold layer, the mold layer encapsulating the first chip stack, the intermediate layer, and a first surface of the first substrate, the first interconnect region being unencapsulated by the mold layer, the second interconnect region being encapsulated by the mold layer, a predetermined height being between a top surface of the mold layer over the second interconnect region and the first interconnect region, and a first material layer being formed on a sidewall between the top surface of the mold layer over the second interconnect region and the first interconnect region; after the mold layer is formed, forming a second material layer on an upper surface of the mold layer; forming a second package structure including a bonding surface and a first solder ball located on the bonding surface, electrically connecting the first solder ball to the first interconnect region, and bonding a portion of the bonding surface corresponding to the second material layer to the second material layer.

8. After the intermediate layer is formed, forming first conductive lines, each of the first semiconductor chips being electrically connected to the first substrate via the first conductive lines; 8. The method of claim 7, further comprising: forming a second conductive line, the second interconnect region being electrically connected to the first substrate through the second conductive line.

9. 8. The method of claim 7, further comprising forming a plurality of first pads in the first interconnect region and a plurality of second pads in the second interconnect region, the number of the second pads being greater than the number of the first pads and the area of ​​the second pads being smaller than the area of ​​the first pads.

10. 8. The method of claim 7, further comprising the step of forming a cover layer on a first interconnect region of the intermediate layer after the intermediate layer is formed, the cover layer including a first portion and a second portion located on both sides of the first portion, the first portion and the second portion being formed in an inverted U-shape to form a sealed cavity with the intermediate layer, and an included angle between the second portion and a direction perpendicular to the first substrate is a first included angle, the first included angle being greater than or equal to 0° and less than 90°.

11. forming a pre-mold layer that encapsulates the first chip stack, the intermediate layer, the cover layer, and a first surface of the first substrate; The method of claim 10 , further comprising removing a portion of the pre-mold layer and a first portion of the cover layer, leaving the second portion to form a first material layer.

12. The method of claim 7, wherein the material of the second material layer is the same as the material of the first material layer.

Images