SiC substrate, method for manufacturing SiC substrate, SiC semiconductor device, and method for manufacturing SiC semiconductor device

Abstract

The present invention addresses the issue of providing: an SiC substrate having a dislocation conversion layer that can reduce resistance; and a novel technology pertaining to SiC semiconductors. This SiC substrate and SiC semiconductor device comprise a dislocation conversion layer 12 having a doping concentration of at least 1 × 1015cm–3. As a result of comprising a dislocation conversion layer 12 having this kind of doping concentration: expansion of basal plane dislocations and the occurrence of high-resistance stacking faults can be suppressed; and resistance when SiC semiconductor devices are produced can be reduced.

Description

[Technical field]

[0001] The present invention relates to a SiC substrate, a method for manufacturing a SiC substrate, a SiC semiconductor device, and a method for manufacturing a SiC semiconductor device. [Background technology]

[0002] Compared to silicon (Si), silicon carbide (SiC) has an electric breakdown field one order of magnitude larger, a band gap three times larger, and a thermal conductivity three times higher. For this reason, SiC is expected to be used in power devices, high-frequency devices, high-temperature operating devices, and other applications.

[0003] Basal plane dislocation (BPD) is known to be one of the device killer defects that cause fatal defects in SiC semiconductor devices.

[0004] Many of the BPDs in the SiC substrate are converted to threading edge dislocations (TEDs) when the epitaxial growth layer (drift layer) is formed. However, there is a problem in that some BPDs are inherited directly into the epitaxial growth layer.

[0005] When a forward current is applied to a device, if minority carriers reach a BPD, the BPD expands and becomes a high-resistance stacking fault (SF). In other words, SF occurs starting from the BPD due to the energy generated when holes (positive holes), which are minority carriers, recombine with electrons. If a high-resistance area occurs within a device, the reliability of the device decreases.

[0006] To address these problems, a technology has been proposed in which a dislocation conversion layer that performs BPD->TED conversion is provided between the base substrate and the epitaxial growth layer (see, for example, Patent Document 1). In this way, by providing a dislocation conversion layer with high dislocation conversion efficiency between the base substrate and the epitaxial growth layer, it is possible to prevent BPDs from being inherited by the epitaxial growth layer.

[0007] Also, a technique has been proposed in which a recombination promotion layer that promotes the recombination of minority carriers is provided between the dislocation conversion layer and the epitaxial growth layer (see, for example, Patent Document 2). In this way, by providing a recombination promotion layer that eliminates minority carriers between the dislocation conversion layer and the epitaxial growth layer, the energy generated by recombination is prevented from being given to the BPD and causing SF. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2009-88223 A [Patent Document 2] JP 2018-166196 A Summary of the Invention [Problem to be solved by the invention]

[0009] 17 is a cross-sectional view showing the structure of a SiC substrate that has been subjected to a conventional process for suppressing stacking faults. As shown in FIG. 17, this SiC substrate 100 includes an n+ type SiC base substrate 101, an n-type dislocation conversion layer 102, an n+ type recombination promotion layer 103, and an n-type epitaxial growth layer 104.

[0010] In order to improve the conversion rate of BPD to TED conversion (hereinafter referred to as BPD to TED conversion rate), the doping concentration of the conventional n-type dislocation conversion layer 102 had to be set low. For example, Patent Document 1 discloses a doping concentration of the dislocation conversion layer of 1×10 15 cm -3 It is stated that it is desirable for the following to be true:

[0011] However, when providing an n-type dislocation conversion layer 102 with a low doping concentration as described in Patent Document 1, there is a problem that the resistance of the SiC semiconductor device increases. In other words, there is a trade-off between the BPD→TED conversion rate and the resistance of the SiC semiconductor device, and it is difficult to achieve both at the same time.

[0012] Furthermore, in the conventional process for suppressing stacking faults, an n+ type recombination promotion layer 103 is formed to suppress the occurrence of SF. For this reason, it is necessary to grow an n-type dislocation conversion layer 102, an n+ type recombination promotion layer 103, and an n-type epitaxial growth layer 104 on an n+ type SiC base substrate 101, which causes a problem that the process of setting growth conditions and the like becomes complicated.

[0013] In view of the above problems, an object of the present invention is to provide a novel technique for a SiC substrate and a SiC semiconductor having a dislocation conversion layer capable of reducing resistance. Another object of the present invention is to provide a novel technique for manufacturing a SiC substrate and a SiC semiconductor having a dislocation conversion layer capable of reducing resistance. [Means for solving the problem]

[0014] The present invention, which solves the above-mentioned problems, is a method for manufacturing a semiconductor device having a doping concentration of 1×10 15 cm -3 The SiC substrate is provided with the above-described dislocation conversion layer. By providing the dislocation conversion layer with such a doping concentration, the resistance in the dislocation conversion layer can be reduced.

[0015] In a preferred embodiment of the invention, the doping concentration is 1×10 17 cm -3 The above-described dislocation conversion layer is provided. By providing a dislocation conversion layer with such a doping concentration, it can function as a recombination promotion layer that promotes the recombination of minority carriers, in addition to functioning as a dislocation conversion layer that performs BPD->TED conversion.

[0016] In a preferred embodiment of the present invention, the dislocation conversion layer has a thickness of 1 μm or more. In this way, by forming the dislocation conversion layer thicker than the conventional dislocation conversion layer, the conversion rate of dislocations can be improved and the recombination of minority carriers can be promoted.

[0017] In a preferred embodiment of the present invention, the dislocation conversion layer has a conversion rate of basal plane dislocations to threading edge dislocations of greater than 95%. In a preferred embodiment of the present invention, the dislocation conversion layer has a conversion rate of 100% from basal plane dislocations to threading edge dislocations. By achieving both a high conversion rate and a high doping concentration, the number of layers grown on the base substrate can be reduced compared to conventional methods, which can reduce the number of manufacturing steps and costs of the SiC substrate.

[0018] In a preferred embodiment of the present invention, the semiconductor device further comprises a base substrate and an epitaxial growth layer, the dislocation conversion layer being provided between the base substrate and the epitaxial growth layer, and the doping concentration of the dislocation conversion layer being higher than the doping concentration of the epitaxial growth layer.

[0019] The present invention also relates to a method for manufacturing a SiC substrate. 15 cm -3 This is a method for manufacturing a SiC substrate, which includes a crystal growth step of growing the above dislocation conversion layer under conditions that increase the terrace width.

[0020] In a preferred embodiment of the present invention, the crystal growth step is a step of growing the crystal in a SiC-C equilibrium vapor pressure environment.

[0021] In a preferred embodiment of the present invention, the crystal growth step is a step of growing a crystal on a surface on which no macrostep bunching is formed.

[0022] The present invention also relates to a SiC semiconductor device. 15 cm -3 The SiC semiconductor device includes the dislocation conversion layer described above.

[0023] In a preferred embodiment of the invention, the doping concentration is 1×10 17 cm -3 The above-described dislocation conversion layer is provided.

[0024] In a preferred embodiment of the present invention, the dislocation conversion layer has a thickness of 1 μm or more.

[0025] In a preferred embodiment of the present invention, the dislocation conversion layer has a conversion rate of basal plane dislocations to threading edge dislocations of greater than 95%. In a preferred embodiment of the present invention, the dislocation conversion layer has a conversion rate of 100% from basal plane dislocations to threading edge dislocations.

[0026] In a preferred embodiment of the present invention, the semiconductor device further comprises a base substrate and an epitaxial growth layer, the dislocation conversion layer being provided between the base substrate and the epitaxial growth layer, and the doping concentration of the dislocation conversion layer being higher than the doping concentration of the epitaxial growth layer.

[0027] The present invention also relates to a method for manufacturing a SiC semiconductor device. 15 cm -3 This is a method for manufacturing a SiC semiconductor device, which includes a crystal growth step for growing the dislocation conversion layer described above.

[0028] In a preferred embodiment of the present invention, the crystal growth step is a step of growing the crystal in a SiC-C equilibrium vapor pressure environment.

[0029] In a preferred embodiment of the present invention, the crystal growth step is a step of growing a crystal on a surface on which no macrostep bunching is formed. Effect of the Invention

[0030] According to the disclosed technology, it is possible to provide a novel technology relating to a SiC substrate and a SiC semiconductor having a dislocation conversion layer capable of reducing resistance. Furthermore, the disclosed technology can provide a novel technology for manufacturing a SiC substrate and a SiC semiconductor having a dislocation conversion layer capable of reducing resistance.

[0031] Other objects, features and advantages will become apparent from a reading of the following detailed description when taken in conjunction with the drawings and the claims. [Brief description of the drawings]

[0032] [Figure 1] 1 is a cross-sectional view showing a configuration of a SiC substrate according to an embodiment. [Diagram 2] FIG. 11 is a cross-sectional view showing the configuration of a SiC substrate according to another embodiment. [Diagram 3] 1A to 1C are explanatory diagrams showing a manufacturing process of a SiC substrate according to an embodiment. [Figure 4] FIG. 4 is an explanatory diagram showing a process for removing a damaged layer according to the present invention. [Diagram 5] 10A to 10C are explanatory views showing a process-damaged layer removing step according to an embodiment of the present invention. [Figure 6] FIG. 2 is an explanatory diagram showing a crystal growth process according to the present invention. [Figure 7] FIG. 2 is an explanatory diagram showing a crystal growth process according to the embodiment. [Figure 8] FIG. 2 is an explanatory diagram showing an epitaxial growth process according to the present invention. [Figure 9] FIG. 2 is an explanatory diagram showing an epitaxial growth process according to the embodiment. [Figure 10] FIG. 2 is an explanatory diagram of a manufacturing apparatus for a SiC substrate according to an embodiment. [Figure 11] FIG. 2 is an explanatory diagram of a manufacturing apparatus for a SiC substrate according to the first embodiment. [Figure 12] 1 shows the results of SIMS analysis of the SiC substrate according to Example 1. [Figure 13] FIG. 11 is an explanatory diagram showing a method for calculating a BPD→TED conversion rate. [Figure 14] 1 is a graph showing the relationship between the BPD→TED conversion rate and the terrace width increase rate. [Figure 15] 1 shows Arrhenius plots during etching and crystal growth. [Figure 16] 13 shows SEM images of the SiC substrate surface after etching and after crystal growth. [Figure 17] FIG. 1 is a cross-sectional view showing the configuration of a SiC substrate that has been subjected to a conventional treatment for suppressing stacking faults. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Hereinafter, with reference to the attached drawings, preferred embodiments of the SiC substrate, the manufacturing method of the SiC substrate, the SiC semiconductor device, and the manufacturing method of the SiC semiconductor device according to the present invention will be described in detail. The technical scope of the present invention is not limited to the embodiments shown in the attached drawings, and can be appropriately modified within the scope of the claims. In this specification and the attached drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, and does not necessarily mean that the concentrations are the same. In the following description of the embodiments and the attached drawings, the same symbols are attached to similar configurations, and duplicate explanations are omitted.

[0034] <SiC substrate> Fig. 1 is a cross-sectional view showing the configuration of a SiC substrate 10 according to the embodiment. As shown in Fig. 1, the SiC substrate 10 according to the embodiment includes an undersubstrate 11 which is an n+ type substrate, a dislocation conversion layer 12 which is an n+ type layer, and an epitaxial growth layer 13 which is an n-type layer.

[0035] In this specification, the surface of the SiC substrate 10 on which a semiconductor device is to be fabricated (specifically, the surface on which the epitaxial growth layer 13 is deposited) is referred to as the main surface, and the surface opposite to the main surface is referred to as the back surface. The main surface and the back surface are collectively referred to as the front surface.

[0036] The main surface may be, for example, a surface having an off angle of several degrees (for example, 0.4 to 8°) from the (0001) or (000-1) plane. In this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it.

[0037] Usually, a step-terrace structure is formed on the surface of single-crystal SiC that has been flattened at the atomic level. This step-terrace structure is a staircase structure in which steps 14, which are steps of one molecular layer or more, and terraces 15, which are flat areas where the {0001} plane is exposed, are arranged alternately.

[0038] The step 14 has a minimum height (minimum unit) of one molecular layer (0.25 nm), and various step heights are formed by stacking multiple monolayers. In this specification, steps 14 bunched together to become huge and having a height exceeding one unit cell of each polytype are called macro step bunching (MSB).

[0039] That is, an MSB is a step 14 that has bunched more than four molecular layers (five molecular layers or more) in the case of 4H-SiC, and a step 14 that has bunched more than six molecular layers (seven molecular layers or more) in the case of 6H-SiC.

[0040] The base substrate 11 may be formed by processing single crystal SiC into a plate shape. For example, it may be a SiC wafer sliced ​​from a SiC ingot produced by a sublimation method or the like. Any polytype may be used as the crystal polytype of single crystal SiC.

[0041] Typically, a base substrate 11 that has been subjected to mechanical processing (slicing, polishing, or grinding) has a process-affected layer 111 in which processing damage has been introduced, and a bulk layer 112 in which no such processing damage has been introduced.

[0042] The damaged layer 111 includes, for example, distortion 113, scratches 114, and latent scratches 115 (see FIG. 4). The presence or absence of the damaged layer 111 can be confirmed by SEM-EBSD, TEM, μXRD, or the like.

[0043] The base substrate 11 is, for example, a nitrogen-doped SiC single crystal substrate. The doping concentration of the base substrate 11 is 1×10 17 cm -3 More preferably, 1×10 18 cm -3 More preferably, it is 1×10 19 cm -3 That's all.

[0044] The dislocation conversion layer 12 is, for example, a nitrogen-doped SiC layer. The doping concentration of the dislocation conversion layer 12 is 1×10 15 cm -3 More preferably, 1×10 16 cm -3 More preferably, it is 1×10 17 cm -3 More preferably, it is 1×10 18 cm -3 More preferably, it is 1×10 19 cm -3 That's all.

[0045] The BPD→TED conversion rate of the dislocation conversion layer 12 is greater than 95.00%, preferably 96.00% or more, more preferably 97.00% or more, even more preferably 98.00% or more, and still more preferably 99.00% or more.

[0046] In other words, when the dislocation conversion layer 12 is grown on the main surface of the base substrate 11 having 5000 BPDs, the number of BPDs present on the main surface of the dislocation conversion layer 12 will be 250 or less. When the dislocation conversion layer 12 is grown on the main surface of the base substrate 11 having 10000 BPDs, the number of BPDs present on the main surface of the dislocation conversion layer 12 will be 500 or less. Furthermore, when the dislocation conversion layer 12 is grown on the main surface of the base substrate 11 on which 20,000 BPDs exist, the main surface of the dislocation conversion layer 12 will have 1,000 or less BPDs.

[0047] In addition, the BPD→TED conversion rate of the dislocation conversion layer 12 is greater than 99.95%, preferably 99.96% or more, more preferably 99.97% or more, even more preferably 99.98% or more, even more preferably 99.99% or more, and even more preferably 100%.

[0048] That is, it is desirable that all of the BPDs present in the underlying substrate 11 are converted to TEDs during the formation of the dislocation conversion layer 12, and that no BPDs are present on the main surface of the dislocation conversion layer 12.

[0049] The thickness of the dislocation conversion layer 12 is 1 μm or more, preferably 3 μm or more, more preferably 5 μm or more, further preferably 7 μm or more, and further preferably 10 μm or more.

[0050] The epitaxial growth layer 13 is, for example, a nitrogen-doped SiC layer. The doping concentration of the epitaxial growth layer 13 is lower than the doping concentration of the dislocation conversion layer 12. In other words, the doping concentration of the dislocation conversion layer 12 is higher than the doping concentration of the epitaxial growth layer 13, and the resistance during device operation is smaller.

[0051] It is known that in a MOSFET manufactured by forming an oxide film on the main surface of the epitaxial growth layer 13, the presence of MSBs has a fatal effect on the operating performance and reliability. For this reason, it is desirable that no MSB is formed on the main surface of the epitaxial growth layer 13. It is also desirable that steps 14 each having a height of one unit cell are arranged on the main surface of the epitaxial growth layer 13. The height of these steps 14 and the terrace width W can be confirmed by AFM or the method of evaluating the contrast of an SEM image described in JP2015-179082A.

[0052] The SiC substrate 10 according to the present invention has a doping concentration of 1×10 15 cm -3 The above-described dislocation conversion layer 12 is provided. In this manner, the dislocation conversion layer 12 that performs BPD->TED conversion is set to a doping concentration higher than that of the conventional n-type dislocation conversion layer 102, thereby making it possible to reduce the resistance of the SiC semiconductor device.

[0053] In addition, the SiC substrate 10 according to the present invention has a doping concentration of 1×10 17 cm -3 The dislocation conversion layer 12 has the above structure. That is, by setting the doping concentration higher than that of the epitaxial growth layer 13 to be formed, it is possible to promote the recombination of minority carriers. As a result, the dislocation conversion layer 12 can function as a recombination promotion layer in addition to converting dislocations. That is, it is desirable that the doping concentration of the dislocation conversion layer 12 be higher than the doping concentration of the epitaxial growth layer 13 .

[0054] Moreover, the dislocation conversion layer 12 of the SiC substrate 10 according to the present invention has a thickness of 1 μm or more. By having a thickness of at least 1 μm or more, the BPD→TED conversion rate can be improved. Furthermore, by providing a thickness of 1 μm or more in this way, the region where minority carriers recombine can be expanded, and the distance between the region where recombination occurs frequently (the main surface side of the dislocation conversion layer 12) and the region where many BPDs exist (the back surface side of the dislocation conversion layer 12) can be increased. Therefore, it is possible to suppress the energy generated by recombination from being given to the BPDs.

[0055] Moreover, the SiC substrate 10 according to this embodiment has a three-layer structure including an n+ type substrate, an n+ type dislocation conversion layer 12, and an n-type epitaxial growth layer 13. On the other hand, a conventional SiC substrate 100 has a four-layer structure including an n+ type SiC substrate 101, an n-type dislocation conversion layer 102, an n+ type recombination promotion layer 103, and an n-type epitaxial growth layer 104 (see FIG. 17). According to the SiC substrate 10 according to this embodiment, the number of layers to be grown can be reduced, and the number of steps can be reduced, compared with the conventional SiC substrate 100. This allows for simplification of growth conditions, cost reduction, and the like.

[0056] Fig. 2 is a cross-sectional view showing the configuration of a SiC substrate 10 according to another embodiment. As shown in Fig. 2, the SiC substrate 10 according to the other embodiment is an epi-ready substrate including an undersubstrate 11 which is an n+ type layer and a dislocation conversion layer 12 which is an n+ type layer. In this manner, the SiC substrate 10 before the formation of the epitaxial growth layer 13 may be manufactured.

[0057] It is known that when an epitaxial growth layer 13 is formed on a surface on which MSBs are formed, defects due to the MSBs may occur in the epitaxial growth layer 13. Therefore, it is preferable that no MSB is formed on the main surface of the dislocation conversion layer 12. In addition, it is preferable that steps 14 each having a height of one unit cell are arranged on the main surface of the dislocation conversion layer 12.

[0058] According to the present invention, the SiC substrate 100 is provided with a dislocation conversion layer 12 that is an n+ type layer having a higher doping concentration than the n-type dislocation conversion layer 102 of the SiC substrate 100 that has been subjected to a conventional treatment for suppressing stacking faults. This novel structure not only suppresses the occurrence of SF, but also provides significant effects such as reducing the resistance of the SiC semiconductor device, simplifying the structure of the SiC substrate, and simplifying the process.

[0059] <SiC substrate manufacturing method> Next, a method for manufacturing a SiC substrate according to the embodiment will be described in detail. Fig. 3 is an explanatory diagram showing a manufacturing process of a SiC substrate according to the embodiment.

[0060] The method for manufacturing a SiC substrate according to the present embodiment includes a process-damaged layer removing step S1 for removing the damaged layer 111 of the base substrate 11, and a process for increasing the doping concentration to 1×10 15 cm -3 The method includes the crystal growth step S2 of growing the dislocation conversion layer 12 and the epitaxial growth step S3 of growing the epitaxial growth layer 13.

[0061] Moreover, after the process-affected layer removal step S1, a bunching decomposition step S4 may be included in which MSBs formed on the main surface of the base substrate 11 are removed. Moreover, after the crystal growth step S2, a bunching decomposition step S4 may be included in which MSBs formed on the main surface of the dislocation conversion layer 12 are removed. Moreover, after the epitaxial growth step S3, a bunching decomposition step S4 may be included in which MSBs formed on the main surface of the epitaxial growth layer 13 are removed.

[0062] Each step will be described in detail below. In addition, the bunching decomposition step S4 can be performed in any order by using a common method. Therefore, the bunching decomposition step S4 will be described after the damaged layer removal step S1, the crystal growth step S2, and the epitaxial growth step S3.

[0063] <Process for removing damaged layers> 4 is an explanatory diagram showing the damaged layer removing step S1 according to the present invention. The damaged layer removing step S1 is a step of removing the damaged layer 111 introduced into the n+ type base substrate 11.

[0064] The process-affected layer removal step S1 can employ any method capable of removing the process-affected layer 111. Examples of such methods include a Si-Vapor Etching (SiVE) method in which single-crystal SiC is etched by heating under Si vapor pressure, a hydrogen etching method in which hydrogen gas is used as an etching gas, and chemical mechanical polishing (CMP). A preferred embodiment of this step will now be described in detail.

[0065] FIG. 5 is an explanatory diagram showing the damaged layer removing step S1 according to the embodiment. The process-affected layer removing step S1 according to the present embodiment is a step of housing the SiC substrate 10 in a semi-closed space including a Si element supply source and a C element supply source, and etching the SiC substrate 10 by heating.

[0066] In this specification, the term "semi-closed space" refers to a space in which the container can be evacuated and dopant gas can be supplied, but at least a part of the vapor generated in the container can be confined. This semi-closed space can be formed in the main container 30 or the high-melting-point container 50, which will be described later.

[0067] Specifically, the process-affected layer removal process S1 is a process of placing a SiC substrate 10 opposite a SiC material body 20 (Si element supply source and C element supply source) in a main body container 30 exposing the SiC material body 20 and heating the SiC substrate 10 (see FIG. 5(a)).

[0068] By arranging the SiC substrate 10 and the SiC material body 20, which has a lower temperature than the SiC substrate 10, facing each other, an etching space X is formed between them. In the etching space X, the temperature gradient created by the heating furnace 40 acts as a driving force to transport atoms, and as a result, the SiC substrate 10 can be etched.

[0069] In addition, by controlling the atomic ratio Si / C placed in the main container 30, it is possible to select between heat treatment in a SiC-Si equilibrium vapor pressure environment and heat treatment in a SiC-C equilibrium vapor pressure environment.

[0070] In this specification, the term "SiC-Si vapor pressure environment" refers to a vapor pressure environment in which SiC (solid) and Si (liquid phase) are in phase equilibrium via the gas phase. The SiC-Si equilibrium vapor pressure environment is formed by heat treating a quasi-closed space in which the atomic ratio Si / C exceeds 1. Specifically, when a SiC substrate 10 satisfying a stoichiometric ratio of 1:1, a SiC material body 20 satisfying a stoichiometric ratio of 1:1, and a Si vapor supply source 35 (Si pellets, etc.) are placed in a main body container 30 made of SiC and satisfying a stoichiometric ratio of 1:1, the atomic ratio Si / C in the main body container 30 exceeds 1.

[0071] In addition, in this specification, the term "SiC-C equilibrium vapor pressure environment" refers to a vapor pressure environment when SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase. The SiC-C equilibrium vapor pressure environment is formed by heat treating a semi-closed space in which the atomic ratio Si / C is 1 or less. Specifically, when a SiC substrate 10 satisfying a stoichiometric ratio of 1:1 and a SiC material body 20 satisfying a stoichiometric ratio of 1:1 are placed in a main body container 30 made of SiC and satisfying a stoichiometric ratio of 1:1, the atomic ratio Si / C in the main body container 30 becomes 1 (see FIG. 5(a)). Also, the atomic ratio Si / C may be set to 1 or less by placing a C vapor supply source (C pellets, etc.).

[0072] The process-affected layer removing step S1 is a step of placing and heating the above-mentioned main body container 30 in high-melting-point container 50 exposing Si vapor supply source 54 (see FIG. 5(a)).

[0073] In this way, by disposing and heating main body container 30 together with Si vapor supply source 54 in high-melting-point container 50 forming a quasi-closed space, it is possible to prevent gaseous species containing Si element from being exhausted from main body container 30. That is, by balancing the vapor pressure of the gaseous species containing Si element inside main body container 30 and the vapor pressure of the gaseous species containing Si element outside main body container 30, the environment inside main body container 30 can be maintained.

[0074] The SiC material body 20 is made of SiC that can receive or transfer Si and C elements between the SiC substrate 10 by heating it relative to the SiC substrate 10. For example, a container (main container 30) made of SiC or a substrate (SiC material substrate) made of SiC can be used. Note that any polytype can be used as the crystal polymorph of this SiC material body 20, and polycrystalline SiC may also be used. The SiC material body 20 may be a sintered body obtained by sintering a Si element supply source and a C element supply source.

[0075] As a driving force for transporting the Si and C elements in this etching, the temperature gradient or chemical potential difference between the SiC substrate 10 and the SiC material body 20 can be used.

[0076] In the process S1 for removing the processed altered layer according to the present embodiment, the SiC substrate 10 and the SiC material body 20 are arranged opposite each other and heated in a temperature range of 1400° C. or more and 2300° C. or less so that the SiC substrate 10 is on the high temperature side and the SiC material body 20 is on the low temperature side. It is believed that this causes the following reactions 1) to 5) to continue, resulting in the etching of the SiC substrate 10 progressing (see FIG. 5(b)).

[0077] 1) SiC(s) → Si(v) + C(s) 2) 2C(s)+Si(v)→SiC2(v) 3) C(s)+2Si(v) → Si2C(v) 4) Si(v) + SiC2(v) → 2SiC(s) 5) Si2C(v) → Si(v) + SiC(s)

[0078] Description of 1): When the SiC substrate 10 (SiC(s)) is heated, Si atoms (Si(v)) are desorbed from the surface of the SiC substrate 10 by thermal decomposition (Si atom sublimation process). Explanation of 2) and 3): As a result of the desorption of the Si atoms (Si(v)), the C atoms (C(s)) remaining on the surface of the SiC substrate 10 react with the Si vapor (Si(v)) in the semi-closed space. As a result, the C atoms (C(s)) become Si2C or SiC2, etc., and sublime from the surface of the SiC substrate 10 (C atom sublimation process). Explanation of 4) and 5): Sublimated Si2C or SiC2, etc. reaches the SiC material body 20 in the semi-closed space due to the temperature gradient, and crystals grow.

[0079] Thus, the process-affected layer removal process S1 in this embodiment includes a Si atom sublimation process in which Si atoms are thermally sublimated from the surface of the SiC substrate 10, and a C atom sublimation process in which C atoms remaining on the surface of the SiC substrate 10 are sublimated from the surface of the SiC substrate 10 by reacting them with Si vapor in the quasi-closed space.

[0080] The etching temperature in this embodiment is preferably set in the range of 1400 to 2300°C. The etching rate according to this embodiment can be controlled by the above-mentioned temperature region, and can be selected within the range of 0.001 to 2 μm / min. The etching time in this embodiment can be set to any time so as to obtain a desired etching amount. For example, when the etching rate is 1 μm / min and the etching amount is desired to be 1 μm, the etching time is 1 minute. The temperature gradient according to this embodiment is set in the range of 0.1 to 5° C. / mm, for example. It is also possible to introduce an inert gas during etching. The inert gas can be selected from Ar, He, N2, etc., and this inert gas is introduced for 10 -5By introducing a pressure in the range of 10,000 Pa or less, the degree of vacuum in the heating furnace 40 (main heating chamber 41) can be adjusted.

[0081] After the process-affected layer removing step S1, a bunching decomposition step S4 for removing MSBs formed on the surface of the base substrate 11 may be included. Furthermore, in the process-damaged layer removing step S1, if etching is performed in a SiC-Si vapor pressure environment in which no MSB is formed on the main surface of the SiC substrate 10, the bunching decomposition step S4 may not be included. In other words, the process-damaged layer removing step S1 and the bunching decomposition step S4 may be performed simultaneously.

[0082] <Crystal growth process> 6 is an explanatory diagram showing the crystal growth step S2 according to the present invention. The crystal growth step S2 is a step of growing an n+ type dislocation conversion layer 12 on an n+ type base substrate 11 under conditions that increase the terrace width W.

[0083] In this way, it is possible to achieve both a high BPD->TED conversion rate and a high doping concentration by growing the dislocation conversion layer 12 under conditions that increase the terrace width W. Examples of conditions that increase the terrace width W include a SiC-C equilibrium vapor pressure environment and a C-rich environment.

[0084] Therefore, the crystal growth step S2 can be performed by any method that can grow crystals on the SiC substrate 10 in a SiC-C equilibrium vapor pressure environment or a C-rich environment. For example, sublimation and chemical vapor deposition (CVD) can be used. A preferred embodiment of this step will now be described in detail.

[0085] FIG. 7 is an explanatory diagram showing the crystal growth step S2 according to the embodiment. The crystal growth step S2 according to the present embodiment is a step of accommodating the SiC substrate 10 in a semi-closed space including a Si element supply source and a C element supply source, and heating the substrate to cause crystal growth (see FIG. 7(a)).

[0086] Specifically, the crystal growth process S2 is a process of placing the SiC substrate 10 opposite the SiC material body 20 (Si element supply source and C element supply source) in a main body container 30 exposing the SiC material body 20 and heating the SiC substrate 10 (see FIG. 7(b)).

[0087] The above-described process-affected layer removing step S1 is a step of transporting Si elements and C elements from the SiC substrate 10 to the SiC material body 20 to etch the SiC substrate 10. Conversely, the crystal growth step S2 is a step of transporting Si and C elements from the SiC material mass 20 to the SiC substrate 10 to grow the SiC substrate 10 as a crystal.

[0088] By arranging the SiC substrate 10 and the SiC material mass 20, which has a higher temperature than the SiC substrate 10, facing each other, a crystal growth space Y is formed between them. In this crystal growth space Y, atomic transport occurs with the temperature gradient created by the heating furnace 40 as a driving force, and as a result, crystals can be grown on the SiC substrate 10.

[0089] The crystal growth step S2 is a step of growing the dislocation conversion layer 12 under a SiC-C equilibrium vapor pressure environment. Therefore, a semi-closed space having an atomic ratio Si / C of 1 or less is formed by heat treatment. That is, the crystal growth process S2 is a process in which the SiC substrate 10 and the SiC material body 20 are arranged opposite each other in a quasi-closed space in which the atomic ratio Si / C exceeds 1, and heated so that a temperature gradient is formed between the SiC substrate 10 and the SiC material body 20.

[0090] In addition, in the crystal growth process S2, similar to the processing-affected layer removal process S1, the above-mentioned main body container 30 is placed in a high-melting point container 50 with an exposed Si vapor supply source 54, and heated, thereby maintaining the environment within the main body container 30.

[0091] In the crystal growth step S2 according to the present embodiment, the SiC substrate 10 and the SiC material body 20 are arranged opposite each other and heated in a temperature range of 1400° C. to 2300° C. so that the SiC substrate 10 is on the low temperature side and the SiC material body 20 is on the high temperature side. It is believed that this causes the following reactions 1) to 5) to occur continuously, resulting in the progress of crystal growth in the SiC substrate 10 (see FIG. 7(b)).

[0092] 1) Poly-SiC(s) → Si(v) + C(s) 2) 2C(s)+Si(v)→SiC2(v) 3) C(s)+2Si(v) → Si2C(v) 4) Si(v) + SiC2(v) → 2SiC(s) 5) Si2C(v) → Si(v) + SiC(s)

[0093] Explanation of 1): When SiC material (Poly-SiC(s)) is heated, Si atoms (Si(v)) are released from the SiC through thermal decomposition. Explanation of 2) and 3): The remaining C atoms (C(s)) react with the Si vapor (Si(v)) in the semi-closed space after the Si atoms (Si(v)) are removed. As a result, the C atoms (C(s)) become Si2C or SiC2, etc., and sublime into the semi-closed space. Explanation of 4) and 5): Sublimated Si2C or SiC2, etc. reach the terraces of the SiC substrate 10 due to the temperature gradient (or chemical potential difference), diffuse, and reach the steps, and grow while inheriting the polytype of the underlying SiC substrate 10 (step-flow growth).

[0094] At this time, the dopants in the SiC material body 20 are transported together with the raw materials (Si element and C element), so that the dislocation conversion layer 12 grows while inheriting the doping concentration of the SiC material body 20 . Therefore, by selecting the type and doping concentration of the dopant in the SiC material body 20, the dopant and doping concentration in the dislocation conversion layer 12 can be controlled.

[0095] That is, the nitrogen doping concentration is 1×10 15 cm -3 In order to obtain the dislocation conversion layer 12 having a doping concentration of 1×10 15 cm -3 The above-mentioned SiC material body 20 may be used. 17 cm -3 In order to obtain the dislocation conversion layer 12 having a doping concentration of 1×10 17 cm -3 The above-mentioned SiC material body 20 may be used.

[0096] Therefore, the doping concentration of the SiC material 20 is 1×10 15 cm -3 More preferably, 1×10 16 cm -3 More preferably, it is 1×10 17 cm -3 More preferably, it is 1×10 18 cm -3 More preferably, it is 1×10 19 cm -3 That's all. Doping can also be performed by supplying a dopant gas during the heat treatment.

[0097] The growth temperature in this embodiment is preferably set in the range of 1400 to 2300°C. The growth rate according to this embodiment can be controlled by the temperature region described above, and can be selected within the range of 0.001 to 2 μm / min. The growth time in this embodiment can be set to any time so as to obtain a desired growth amount. For example, when the growth rate is 1 μm / min and the growth amount is desired to be 1 μm, the growth time is 1 minute. The temperature gradient in this embodiment is set in the range of 0.1 to 5° C. / mm. In this method, a dopant gas (such as N2) can be supplied to the heating chamber 41. -5 It can be introduced in the range of ~10,000 Pa.

[0098] In the crystal growth step S2, it is preferable to grow crystals on a surface where no MSB is formed. Therefore, in the process-affected layer removal step S1, it is preferable to perform etching in a SiC-Si vapor pressure environment where no MSB is formed on the main surface of the SiC substrate 10. Furthermore, if etching is performed under conditions that form MSBs on the main surface of the SiC substrate 10 in the process-affected layer removal step S1, it is preferable to perform a bunching decomposition step S4, which will be described later, prior to the crystal growth step S2.

[0099] After the crystal growth step S2, a bunching decomposition step S4 for removing MSBs formed on the surface of the dislocation conversion layer 12 may be included.

[0100] <Epitaxial growth process> 8 is an explanatory diagram showing the epitaxial growth step S3 according to the present invention. The epitaxial growth step S3 is a step of growing an n-type epitaxial growth layer 13 on the dislocation conversion layer 12.

[0101] The epitaxial growth step S3 can be performed by any method capable of growing the epitaxial growth layer 13. For example, chemical vapor deposition (CVD), physical vapor transport (PVT), metastable solvent epitaxy (MSE), etc. can be used. A preferred embodiment of this step will now be described in detail.

[0102] The epitaxial growth step S3 according to the present embodiment is a step of accommodating the SiC substrate 10 in a semi-closed space including a Si element supply source and a C element supply source and heating the SiC substrate 10 to grow a crystal, similar to the crystal growth step S2.

[0103] Specifically, in the crystal growth process S2, the SiC substrate 10 and the SiC material body 20 are arranged opposite each other and heated in a temperature range of 1400°C to 2300°C so that the SiC substrate 10 is on the low temperature side and the SiC material body 20 is on the high temperature side (see FIG. 7).

[0104] This epitaxial growth step S3 is a step of growing a crystal of the epitaxial growth layer 13, which is an n-type layer, having a doping concentration lower than that of the dislocation conversion layer 12, which is an n+ type layer.

[0105] Therefore, the doping concentration of the SiC material body 20 used in the epitaxial growth step S3 is 1×10 17 cm -3 or less, preferably 1×10 16 cm -3 More preferably, it is 1×10 15 cm -3 The following is the result.

[0106] The growth temperature in this embodiment is preferably set in the range of 1400 to 2300°C. The growth rate according to this embodiment can be controlled by the temperature region described above, and can be selected within the range of 0.001 to 2 μm / min. The growth time in this embodiment can be set to any time so as to obtain a desired growth amount. For example, when the growth rate is 1 μm / min and the growth amount is desired to be 1 μm, the growth time is 1 minute. The temperature gradient in this embodiment is set in the range of 0.1 to 5° C. / mm.

[0107] Moreover, the epitaxial growth step S3 is a step of growing crystals on a surface where no MSB is formed. Therefore, it is desirable to carry out a bunching decomposition step S4, which will be described later, prior to the epitaxial growth step S3.

[0108] After the epitaxial growth step S3, a bunching decomposition step S4 for removing MSBs formed on the surface of the epitaxial growth layer 13 may be included.

[0109] <Bunching decomposition process> The bunching decomposition step S4 can employ any method capable of decomposing the MSB formed on the surface of the SiC substrate 10. For example, a Si-Vapor Etching (SiVE) method in which single crystal SiC is etched by heating under Si vapor pressure can be exemplified. A preferred embodiment of this step will now be described in detail.

[0110] FIG. 9 is an explanatory diagram showing the bunching decomposition step S4 according to the embodiment. The bunching decomposition step S4 according to the present embodiment is a step of accommodating the SiC substrate 10 in a semi-closed space including a Si element supply source and a C element supply source, and etching or crystal growth is performed in a SiC-Si equilibrium vapor pressure environment.

[0111] Specifically, the bunching decomposition process S4, like the processing-affected layer removal process S1 and the crystal growth process S2, is a process in which the SiC substrate 10 and the Si vapor supply source 35 are arranged opposite the SiC material body 20 in a main body container 30 exposing the SiC material body 20 (Si element supply source and C element supply source), and heated (see FIG. 9).

[0112] Furthermore, similar to the processing-affected layer removal process S1 and the crystal growth process S2, the environment within the main body container 30 is maintained by placing and heating the above-mentioned main body container 30 within a high-melting point container 50 that exposes the Si vapor supply source 54.

[0113] FIG. 9(a) shows a state in which MSB formed on the surface of a SiC substrate 10 is decomposed by etching in a SiC-Si equilibrium vapor pressure environment. That is, in a semi-closed space in which the atomic ratio Si / C exceeds 1, the SiC substrate 10 and the SiC material body 20 are arranged facing each other, and heated so that the SiC substrate 10 is on the high temperature side and the SiC material body 20 is on the low temperature side.

[0114] On the other hand, FIG. 9(b) shows a mode in which MSB formed on the surface of the SiC substrate 10 is decomposed by crystal growth in a SiC--Si equilibrium vapor pressure environment. That is, in a semi-closed space in which the atomic ratio Si / C exceeds 1, the SiC substrate 10 and the SiC material body 20 are arranged facing each other, and heated so that the SiC substrate 10 is on the low temperature side and the SiC material body 20 is on the high temperature side.

[0115] According to the bunching decomposition step S4 of the present embodiment, the MSB formed on the surface of the SiC substrate 10 can be decomposed by heat-treating the SiC substrate 10 in a SiC-Si equilibrium vapor pressure environment. The etching conditions and growth conditions may be the same as those described in the damaged layer removal step S1 or the crystal growth step S2.

[0116] <SiC substrate manufacturing equipment> Next, a manufacturing apparatus for implementing the above-mentioned method for manufacturing a SiC substrate will be described in detail. As shown in FIG. 10, the manufacturing apparatus for a SiC substrate in this embodiment includes a main body container 30 capable of accommodating a SiC substrate 10, and a heating furnace 40 capable of heating so as to form a temperature gradient between the SiC substrate 10 and a SiC material body 20.

[0117] (Main container) The main container 30 is a fitting container that includes an upper container 31 and a lower container 32 that can fit together. A minute gap 33 is formed at the fitting portion between the upper container 31 and the lower container 32, and the main container 30 is configured to be able to be evacuated (vacuumed) through this gap 33.

[0118] The upper container 31 and the lower container 32 according to the present embodiment are made of polycrystalline SiC. Therefore, the main container 30 itself may be made of the SiC material body 20. Also, only the portion of the main container 30 facing the SiC substrate 10 may be made of the SiC material body 20. In this case, a high melting point material (the same material as the high melting point container 50 described later) can be used for the portions other than the SiC material body 20.

[0119] 5, 7 and 9, a configuration in which a substrate-shaped SiC material body 20 is separately accommodated may be adopted. In that case, a spacer (such as a substrate holder 34) may be disposed between the substrate-shaped SiC material body 20 and the SiC substrate 10 to form an etching space X or a crystal growth space Y. The substrate holder 34 is desirably made of a high-melting point material similar to that of the high-melting point container 50.

[0120] That is, main body container 30 is configured to generate an atmosphere containing Si elements and C elements in the internal space when it is heated with SiC substrate 10 accommodated therein. In this embodiment, an atmosphere containing Si elements and C elements is formed in the internal space by heating SiC material body 20 made of polycrystalline SiC.

[0121] In addition, it is preferable that the space in the heated main body container 30 is a vapor pressure environment of a mixture of gaseous species containing Si element and gaseous species containing C element. Examples of the gaseous species containing Si element include Si, Si2, Si3, Si2C, SiC2, and SiC. Examples of the gaseous species containing C element include Si2C, SiC2, SiC, and C. In other words, it is preferable that the SiC-based gas exists in a semi-closed space.

[0122] The etching space X or the crystal growth space Y is a space for transporting raw materials from the SiC substrate 10 to the SiC material body 20 using a temperature gradient provided between the SiC substrate 10 and the SiC material body 20 as a driving force, and is also a space for transporting raw materials from the SiC material body 20 to the SiC substrate 10.

[0123] For example, consider a case where the SiC substrate 10 is arranged so that the temperature of the SiC substrate 10 side is higher and the temperature of the SiC material body 20 is lower when comparing the temperature of the surface of the SiC substrate 10 with the temperature of the SiC material body 20 facing this surface (see FIG. 9(a)). In this way, when the SiC substrate 10 and the SiC material body 20 are arranged facing each other and heated so that the SiC substrate 10 is on the high temperature side and the SiC material body 20 is on the low temperature side, raw material is transported from the SiC substrate 10 to the SiC material body 20, and the SiC substrate 10 is etched. That is, an etching space X is formed between the SiC material body 20 and the SiC substrate 10.

[0124] On the other hand, consider a case where the SiC substrate 10 is arranged so that, when comparing the temperature of the surface of the SiC substrate 10 with the temperature of the SiC material body 20 facing this surface, the temperature of the SiC substrate 10 side is lower and the temperature of the SiC material body 20 is higher (see FIG. 9(b)). In this way, when the SiC substrate 10 and the SiC material body 20 are arranged facing each other and heated so that the SiC substrate 10 is on the low temperature side and the SiC material body 20 is on the high temperature side, raw material is transported from the SiC material body 20 to the SiC substrate 10, and single crystal SiC grows on the SiC substrate 10. That is, a crystal growth space Y is formed between the SiC material body 20 and the SiC substrate 10.

[0125] (heating furnace) As shown in FIG. 10, the heating furnace 40 includes a main heating chamber 41 capable of heating the workpiece (such as a SiC substrate 10) to a temperature of 1000°C or higher and 2300°C or lower, a pre-heating chamber 42 capable of pre-heating the workpiece to a temperature of 500°C or higher, a high-melting point container 50 capable of accommodating the main container 30, and a moving means 43 (moving table) capable of moving the high-melting point container 50 from the pre-heating chamber 42 to the main heating chamber 41.

[0126] The main heating chamber 41 is formed into a regular hexagon in a planar cross-sectional view, and a high-melting point container 50 is placed inside the main heating chamber 41. A heater 44 (mesh heater) is provided inside the main heating chamber 41. A multi-layer heat reflecting metal plate (not shown) is fixed to the side walls and ceiling of the main heating chamber 41. This multi-layer heat reflecting metal plate is configured to reflect heat from the heater 44 toward approximately the center of the main heating chamber 41.

[0127] As a result, within the main heating chamber 41, a heating heater 44 is arranged to surround the high-melting point container 50 in which the workpiece is housed, and a multi-layer heat-reflecting metal plate is further arranged on the outside of that, thereby making it possible to raise the temperature to a temperature of 1000°C or higher and 2300°C or lower. As the heater 44, for example, a resistance heating type heater or a high-frequency induction heating type heater can be used.

[0128] The heater 44 may be configured to form a temperature gradient in the high melting point container 50. For example, the heater 44 may be configured so that more heaters are arranged on the upper side. The heater 44 may be configured so that its width increases toward the upper side. Alternatively, the heater 44 may be configured so that the power supplied to it can be increased toward the upper side.

[0129] In addition, connected to the main heating chamber 41 are a vacuum forming valve 45 for evacuating the inside of the main heating chamber 41, an inert gas injection valve 46 for introducing an inert gas into the main heating chamber 41, and a vacuum gauge 47 for measuring the degree of vacuum within the main heating chamber 41.

[0130] The vacuum forming valve 45 is connected to a vacuum pump (not shown) that evacuates the inside of the main heating chamber 41 to create a vacuum. By using the vacuum forming valve 45 and the vacuum pump, the degree of vacuum in the main heating chamber 41 is set to, for example, 10 Pa or less, more preferably 1 Pa or less, and further preferably 10 -3 The pressure can be adjusted to be equal to or less than Pa. An example of the vacuum pump is a turbo molecular pump.

[0131] The inert gas injection valve 46 is connected to an inert gas supply source (not shown). The inert gas is injected into the main heating chamber 41 by the inert gas injection valve 46 and the inert gas supply source. -5 It can be introduced at a pressure in the range of up to 10,000 Pa. As the inert gas, Ar, He, N2, etc. can be selected.

[0132] Moreover, the inert gas injection valve 46 is a dopant gas supplying means capable of supplying a dopant gas into the main body container 30. That is, by selecting a dopant gas (e.g., N2, etc.) as the inert gas, the doping concentration of the growth layer can be adjusted.

[0133] The preheating chamber 42 is connected to the main heating chamber 41, and is configured to be able to move the high-melting point container 50 by a moving means 43. The preheating chamber 42 of this embodiment is configured to be able to be heated by the residual heat of the heater 44 of the main heating chamber 41. For example, when the main heating chamber 41 is heated to 2000°C, the preheating chamber 42 is heated to about 1000°C, and degassing of the workpiece (SiC substrate 10, main container 30, high-melting point container 50, etc.) can be performed.

[0134] The moving means 43 is configured to be capable of placing the high melting point container 50 thereon and moving it between the main heating chamber 41 and the preheating chamber 42. The transfer between the main heating chamber 41 and the preheating chamber 42 by the moving means 43 can be completed in as little as one minute, making it possible to realize a temperature increase / decrease rate of 1 to 1000° C. / min. Since the temperature can be increased and decreased rapidly in this manner, it is possible to observe the surface shape that does not have a history of low-temperature growth during the temperature increase and decrease, which was difficult to do with conventional devices. In addition, in FIG. 10, the preheating chamber 42 is disposed below the main heating chamber 41, but this is not limiting and the chamber may be disposed in any direction.

[0135] Moreover, the moving means 43 according to this embodiment is a moving stage on which the high melting point container 50 is placed. A small amount of heat is released from the contact portion between the moving stage and the high melting point container 50. This allows a temperature gradient to be formed in the high melting point container 50 (and in the main container 30). That is, in the heating furnace 40 of the present embodiment, since the bottom of the high melting point container 50 is in contact with the moving stage, a temperature gradient is provided such that the temperature decreases from the upper container 51 to the lower container 52 of the high melting point container 50. It is desirable that this temperature gradient is formed along the front-to-back direction of the SiC substrate 10. As described above, a temperature gradient may be formed by the configuration of the heater 44. The heater 44 may be configured to be capable of reversing the temperature gradient.

[0136] (High melting point container) It is preferable that the heating furnace 40 forms an atmosphere containing Si element and is capable of heating the main container 30 in this atmosphere. The atmosphere containing Si element in the heating furnace 40 according to the present embodiment is formed by using a high-melting point container 50 and a Si vapor supply source 54. Naturally, any method can be used as long as it is possible to form an atmosphere containing Si elements around main container 30.

[0137] The high-melting-point container 50 is configured to include a high-melting-point material, such as C, which is a general-purpose heat-resistant member, W, Re, Os, Ta, and Mo, which are high-melting-point metals, Ta9C8, HfC, TaC, NbC, ZrC, Ta2C, TiC, WC, and MoC, which are carbides, HfN, TaN, BN, Ta2N, ZrN, and TiN, and HfB2, TaB2, ZrB2, NB2, and TiB2, which are borides, and polycrystalline SiC.

[0138] Like the main container 30, the high melting point container 50 is a fitting container having an upper container 51 and a lower container 52 that can fit together, and is configured to be able to accommodate the main container 30. A minute gap 53 is formed at the fitting portion between the upper container 51 and the lower container 52, and it is configured so that the inside of the high melting point container 50 can be evacuated (vacuumed) through this gap 53.

[0139] The high-melting-point container 50 preferably has a Si vapor supply source 55 capable of supplying the vapor pressure of a gaseous species containing an Si element into the high-melting-point container 50. The Si vapor supply source 55 may be configured to generate Si vapor in the high-melting-point container 50 when heated, and examples of the Si vapor supply source 55 include solid Si (single crystal Si pieces, Si pellets such as Si powder, etc.) and a Si compound.

[0140] The manufacturing apparatus for a SiC substrate according to this embodiment employs TaC as the material of high-melting-point container 50, and employs tantalum silicide as Si vapor supply source 55. That is, as shown in Figures 5, 7 and 9, a tantalum silicide layer is formed on the inside of high-melting-point container 50, and Si vapor is supplied from the tantalum silicide layer into the container during heating, thereby forming a Si vapor pressure environment. In addition, any other configuration may be used as long as the vapor pressure of a gaseous species containing elemental silicon is generated within the high-melting-point container 50 upon heating.

[0141] <SiC semiconductor device and method for manufacturing SiC semiconductor device> An example will be described in which a pin diode is manufactured from the SiC substrate 10 according to the embodiment. For example, consider a case in which the SiC substrate 10 according to the embodiment is an n-type and an n-channel pin diode is manufactured. In this case, the base substrate 11 serves as a cathode region, the dislocation conversion layer 12 serves as a buffer layer, and the epitaxial growth layer 13 serves as an intrinsic semiconductor layer (i-layer).

[0142] First, a p-type impurity, for example, aluminum (Al), is implanted into the surface layer on the main surface side of the epitaxial growth layer 13 by ion implantation to form ap + -type anode region. Next, a film of nickel (Ni) or the like is formed on the upper surface of the anode region and then heat-treated to form an anode electrode, and a cathode electrode is formed on the upper surface of the cathode region, thereby completing the manufacture of an n-channel pin diode.

[0143] Here, the manufacturing method of the SiC semiconductor device has been explained using an n-channel pin diode as an example, but the SiC substrate of the present invention can also be applied to bipolar elements, IGBT (Insulated Gate Bipolar Transistor) elements, parasitic diodes of MOS (Metal Oxied Semiconductor) structure, etc.

[0144] In addition, in the embodiment, an example has been shown in which the dislocation conversion layer 12 of an n+ type layer and the epitaxial growth layer 13 of an n-type layer are laminated on the main surface of the n+ type SiC substrate 10, but a configuration in which the dislocation conversion layer 12 of a p+ type layer and the epitaxial growth layer 13 of a p-type layer are laminated on the main surface of a p+ type SiC substrate may also be used. EXAMPLES

[0145] The present invention will be described more specifically below with reference to Examples 1, 2, and 3, as well as Comparative Examples 1, 2, and 3.

[0146] Example 1 SiC substrate 10 after removal of processing-affected layer 111 was housed in main container 30 and high-melting-point container 50 (see FIG. 11), and heat-treated under the following heat treatment conditions. In Example 1, main container 30 is made of polycrystalline SiC, and is configured so that main container 30 itself functions as SiC material body 20 (Si element supply source and C element supply source).

[0147] [SiC substrate 10] Polymorphism: 4H-SiC Board size: width 10mm x height 10mm x thickness 0.45mm Off direction and off angle: 4° off in the <11-20> direction Growth plane: (0001) plane Presence or absence of processing-affected layer 111: None MSB: None Step 14 height: 1.0 nm Terrace width W1: 14 nm

[0148] The presence or absence and depth of the damaged layer 111 were confirmed by SEM-EBSD. The presence or absence and depth of the damaged layer 111 can also be confirmed by TEM, μXRD, or Raman spectroscopy. In addition, the presence or absence of MSB was confirmed by AFM and the method of evaluating the contrast of SEM images described in JP 2015-179082 A. The height of the step 14 was measured by AFM. In addition, the value of the terrace width W (including terrace width W1 and terrace width W2) was calculated by drawing a line perpendicular to the steps 14 in the captured SEM image and counting the number of steps 14 present on this line, and the average terrace width was calculated (terrace width W = line length / number of steps on the line).

[0149] [Main container 30 (SiC material body 20)] Material: Polycrystalline SiC Container size: diameter 60mm x height 4mm Distance between SiC substrate 10 and top surface of main body container 30: 2 mm Atomic ratio inside the container: Si / C: 1 or less Dopant: N Doping concentration: 5×10 17 cm -3 ~5×10 18 cm -3

[0150] [High melting point container 50] Material: TaC Container size: diameter 160mm x height 60mm Si vapor source 54 (Si compound): TaSi2

[0151] [Heat treatment conditions] The SiC substrate 10 arranged under the above-mentioned conditions was subjected to a heat treatment under the following conditions. Heating temperature: 1800℃ Heating time: 8 min Growth amount: 0.5μm Temperature gradient: 1℃ / mm

[0152] By heating under the above-mentioned heat treatment conditions, the dislocation conversion layer 12 was grown on the SiC substrate 10 (crystal growth step S2). In Example 1, the dislocation conversion layer 12 was grown to a thickness of 0.5 μm, but it is possible to grow the dislocation conversion layer 12 to a thickness of 1 μm or more by extending the heating time. 12 shows the SIMS analysis result of the SiC substrate according to Example 1. As shown in FIG. 12, the doping concentration of the dislocation conversion layer 12 according to Example 1 is 3×10 17 cm -3 The doping concentration of the base substrate 11 is 6×10 18 cm -3 It was. The dislocation conversion layer 12 grown in the crystal growth step S2 according to Example 1 is as follows.

[0153] [Dislocation conversion layer 12] Dopant: N Doping concentration: 3×10 17 cm -3 MSB: Yes Step 14 height: >1.0nm Step edge shape: Zigzag shape Terrace width W2: 55 nm BPD to TED conversion rate: 100%

[0154] FIG. 13 is an explanatory diagram of a method for determining the conversion rate of BPDs to other defects / dislocations (TEDs, etc.) during the crystal growth step S2. 13(a) shows an underlying substrate 11 having a process-affected layer 111. At this stage, BPDs exist from the bulk layer 112 to the process-affected layer 111. 13(b) shows the base substrate 11 from which the damaged layer 111 has been removed by the damaged layer removing step S1. At this stage, BPDs are present in the base substrate 11 (bulk layer 112). 13(c) shows a SiC substrate 10 on which a dislocation conversion layer 12 has been grown by the crystal growth step S2. In this step, the BPDs present in the bulk layer 112 are converted to TEDs with a certain probability. Here, TEDs and BPDs will be mixed on the surface of the dislocation conversion layer 12 unless 100% is converted. 13(d) shows the state where defects in the dislocation conversion layer 12 of the SiC substrate 10 after the crystal growth step S2 are confirmed by using the KOH dissolution etching method. This KOH dissolution etching method is a technique in which the SiC substrate is immersed in molten salt (KOH, etc.) heated to about 500°C to form etch pits at the dislocation or defect portions, and the type of dislocation is identified based on the size and shape of the etch pits. This method obtains the number of BPDs that have propagated in the dislocation conversion layer 12 after the crystal growth step S2. 13(e) shows the removal of the dislocation conversion layer 12 after the KOH dissolution etching method. In this method, after planarization to the etch pit depth by mechanical polishing, CMP, or the like, the dislocation conversion layer 12 is removed by the SiVE method or the like to expose the base substrate 11 (bulk layer 112). 13(f) shows the state where defects in the underlying substrate 11 are confirmed by using a KOH dissolution etching method for the underlying substrate 11 from which the dislocation conversion layer 12 has been removed. By this method, the number of BPDs present in the underlying substrate 11 directly below the dislocation conversion layer 12 is obtained.

[0155] By comparing the number of BPDs propagated in the dislocation conversion layer 12 in FIG. 13(d) with the number of BPDs present on the surface of the base substrate 11 in FIG. 13(f) using the sequence shown in FIG. 13, the BPD-to-TED conversion rate, which is the conversion of BPDs to other defects / dislocations during the crystal growth step S2, can be obtained.

[0156] According to Example 1, the dislocation conversion layer 12 is grown under a SiC-C equilibrium vapor pressure environment on a surface on which no MSB is formed, whereby the doping concentration is 1×10 17 cm -3 In this manner, a SiC substrate having a dislocation conversion layer 12 with a high BPD→TED conversion rate can be manufactured. In Example 1, the doping concentration is 5×10 17 cm -3 ~5×10 18 cm -3 Using a SiC material body 20 with a doping concentration of 1×10 17 cm -3 Although the dislocation conversion layer 12 is formed as described above, it is also possible to increase the doping concentration by introducing a dopant gas.

[0157] Example 2 and Example 3 Next, the heat treatment conditions for improving the BPD→TED conversion rate will be described in detail with reference to Example 2, Example 3, Comparative Example 1, Comparative Example 2, and Comparative Example 3.

[0158] The SiC semiconductor substrates of Example 2, Example 3, Comparative Example 1, Comparative Example 2, and Comparative Example 3 were manufactured under the conditions shown in Table 1. The depth of the processing-affected layer 111 of the SiC substrate 10 used in these Examples and Comparative Examples was confirmed to be about 5 μm by SEM-EBSD. The size of the high-melting-point container 50 used was 160 mm in diameter × 60 mm in height, and the size of the main container 30 was 60 mm in diameter × 4 mm in height.

[0159] [Table 1]

[0160] In Example 2, the process-affected layer 111 was removed under conditions in which no MSB was formed using a Si vapor pressure etching method (process-affected layer removal step S1), and growth was performed in a SiC-C equilibrium vapor pressure environment using a sublimation method (crystal growth step S2). As a result, the BPD to TED conversion rate of the dislocation conversion layer 12 was 100%. At this time, the terrace width W1 before the crystal growth step S2 was 14 nm, and the terrace width W2 after the crystal growth step S2 was 55 nm (terrace width increase / decrease rate=292.86%).

[0161] In Example 3, the process-affected layer 111 was removed under conditions for forming MSB using a Si vapor pressure etching method (process-affected layer removal step S1), and growth was performed under the same conditions (SiC-C equilibrium vapor pressure environment) as in Example 2 (crystal growth step S2). As a result, the BPD->TED conversion rate of the dislocation conversion layer 12 was 99.7%. At this time, the terrace width W1 before the crystal growth step S2 was 26 nm, and the terrace width W2 after the crystal growth step S2 was 40 nm (terrace width increase / decrease rate=53.85%).

[0162] From this result, it is understood that when MSB is formed on the surface of the SiC substrate 10 before the growth of the dislocation conversion layer 12, the BPD→TED conversion rate is lower than that in Example 2.

[0163] In Comparative Example 1, the crystal was grown (crystal growth step S2) under the same conditions (SiC-C equilibrium vapor pressure environment) as in Examples 2 and 3, without performing the process-damaged layer removal step S1 for removing the damaged layer 111. As a result, the BPD to TED conversion rate of the dislocation conversion layer 12 was 95.65%. At this time, the terrace width W1 before the crystal growth step S2 was 7 nm, and the terrace width W2 after the crystal growth step S2 was 45 nm (terrace width increase / decrease rate=542.86%).

[0164] From this result, it is understood that when the process-affected layer 111 remains on the SiC substrate 10 in front of the dislocation conversion layer 12, the BPD→TED conversion rate is lower than in Examples 2 and 3.

[0165] In Comparative Example 2, the process-affected layer 111 was removed under conditions that allowed the formation of MSB (process-affected layer removal step S1), and growth was performed under the same conditions (SiC-C equilibrium vapor pressure environment) as in Examples 2 and 3 (crystal growth step S2). As a result, the BPD->TED conversion rate of the dislocation conversion layer 12 was 96.77%. At this time, the terrace width W1 before the crystal growth step S2 was 50 nm, and the terrace width W2 after the crystal growth step S2 was 48 nm (terrace width increase / decrease rate=-4.00%).

[0166] From this result, it can be seen that when growth is performed under conditions that reduce the terrace width of the SiC substrate in the crystal growth step S2, the BPD→TED conversion rate is lower than in Examples 2 and 3.

[0167] In addition, in the process-damaged layer removal step S1 of Example 3, the MSB is formed by introducing Ar gas at 10,000 Pa, whereas in the process-damaged layer removal step S1 of Comparative Example 2, the MSB is formed by using TaSi2 for the tantalum silicide layer.

[0168] In Comparative Example 3, similarly to Example 2, the process-affected layer 111 was removed under conditions in which no MSB was formed (process-affected layer removal step S1), and growth was performed in a SiC-Si equilibrium vapor pressure environment by sublimation (crystal growth step S2). Note that this SiC-Si equilibrium vapor pressure environment was formed by placing a Si substrate in the main body container 30. As a result, the BPD→TED conversion rate of the dislocation conversion layer 12 was 93.24%.

[0169] From this result, it can be seen that when grown under a SiC-Si equilibrium vapor pressure environment, the BPD→TED conversion rate is lower than in Example 2.

[0170] Furthermore, the present inventors have conducted extensive research and experiments to determine whether there is any rule in the BPD→TED conversion rate, and have found that, as shown in FIG. 14, the BPD→TED conversion rate is closely related to the rate of increase / decrease in the terrace width W before and after epitaxial growth (terrace width increase rate).

[0171] 14 is a graph in which the horizontal axis represents the terrace width increase rate ((terrace width W2 before growth-terrace width W1 after growth) / terrace width W1 after growth) and the vertical axis represents the BPD to TED conversion rate. The plot shown in Fig. 14 shows the results of multiple experiments in which multiple SiC substrates 10 having different terrace widths W1 from which processing-affected layer 111 had been removed were grown to 3 µm at a growth temperature of 1700°C, 1800°C, or 1900°C in a SiC-Si equilibrium vapor pressure environment or a SiC-C equilibrium vapor pressure environment.

[0172] According to these results, when the terrace width increase rate was greater than 0, i.e., when the SiC substrate 10 from which the processing-affected layer 111 had been removed was grown under conditions in which the terrace width W increased during crystal growth, the BPD→TED conversion rate was 99.00% or more.

[0173] That is, according to the manufacturing method of the SiC substrate of the present invention, by including a process-affected layer removal step S1 for removing the process-affected layer 111 of the SiC substrate 10 and a crystal growth step S2 for growing the SiC substrate 10 under conditions for increasing the terrace width W, it is possible to improve the BPD→TED conversion rate in the dislocation conversion layer 12.

[0174] Furthermore, according to the method for manufacturing a SiC substrate according to the present invention, the crystal growth step S2 grows the dislocation conversion layer 12 on the SiC substrate 10 in which no MSB is formed, thereby making it possible to achieve a BPD→TED conversion rate in the dislocation conversion layer 12 of approximately 100%.

[0175] [Thermodynamic calculation] 15(a) is a graph showing the relationship between the heating temperature and the etching rate in the etching process of the present invention, where the horizontal axis of the graph is the reciprocal of the temperature, and the vertical axis of the graph shows the etching rate in logarithm.

[0176] 15(b) is a graph showing the relationship between the heating temperature and the growth rate in the crystal growth process of the present invention. The horizontal axis of this graph is the reciprocal of the temperature, and the vertical axis of this graph shows the growth rate in logarithm.

[0177] 15, the results of heat treatment of SiC substrate 10 placed in a space (inside main container 30) where the atomic ratio Si / C exceeds 1 are indicated by circles, and the results of heat treatment of SiC substrate 10 placed in a space (inside main container 30) where the atomic ratio Si / C is 1 or less are indicated by crosses.

[0178] In addition, no MSB was formed on any of the SiC substrate 10 surface areas marked with a circle, and the height of the step 14 was the height of one unit cell. On the other hand, MSB was formed on any of the SiC substrate 10 surface areas marked with a cross.

[0179] In addition, in the graph of FIG. 15, the results of thermodynamic calculations in a SiC-Si equilibrium vapor pressure environment are shown by a dashed line (Arrhenius plot), and the results of thermodynamic calculations in a SiC-C equilibrium vapor pressure environment are shown by a two-dot chain line (Arrhenius plot). Hereinafter, the thermodynamic calculation of the etching process and the thermodynamic calculation of the crystal growth process will be separately explained in detail.

[0180] (Thermodynamic calculation of the etching process) In the thermodynamic calculation of the etching process, the amount of steam (gas phase species containing Si element and gas phase species containing C element) generated from the SiC substrate 10 when the main container 30 is heated can be converted into an etching amount. In this case, the etching rate of the SiC substrate 10 can be calculated by the following equation 1.

[0181]

number

[0182] Here, T is the temperature of the SiC substrate 10, m i is a gas phase species (Si x C y ) and k is the Boltzmann constant. Also, P i is the sum of the vapor pressures generated in the main body container 30 by heating the SiC substrate 10. i Possible gas phase species include SiC, Si2C, and SiC2.

[0183] The dashed line in Fig. 15(a) is the result of a thermodynamic calculation when etching single crystal SiC in a vapor pressure environment where SiC (solid) and Si (liquid phase) are in phase equilibrium via the gas phase. Specifically, using Equation 1, the thermodynamic calculation was performed under the following conditions (i) to (iv): (i) a constant volume SiC-Si equilibrium vapor pressure environment, (ii) the etching driving force is the temperature gradient inside the main body container 30, (iii) the source gas is SiC, Si2C, and SiC2, and (iv) the desorption coefficient for the source material sublimating from step 14 is 0.001.

[0184] The two-dot chain line in Fig. 15(a) is the result of a thermodynamic calculation when etching single crystal SiC in a vapor pressure environment where SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase. Specifically, using Equation 1, the thermodynamic calculation was performed under the following conditions (i) to (iv): (i) a constant volume SiC-C equilibrium vapor pressure environment, (ii) the etching driving force is the temperature gradient inside the main body container 30, (iii) the source gas is SiC, Si2C, and SiC2, and (iv) the desorption coefficient for the source material sublimating from step 14 is 0.001. The data for each chemical species used in the thermodynamic calculations were taken from the JANAF Thermochemical Tables.

[0185] According to the graph in Figure 15(a), it can be seen that the results (marked with circles) of etching SiC substrate 10 when SiC substrate 10 is placed in a space (inside main container 30) where the atomic ratio Si / C exceeds 1, are consistent with the trend of the thermodynamic calculation results of single crystal SiC etching in a SiC-Si equilibrium vapor pressure environment.

[0186] In addition, the SiC substrate 10 was placed in a space (inside the main container 30) where the atomic ratio Si / C was 1 or less, and the results of etching the SiC substrate 10 (marked with x) show a trend consistent with the results of thermodynamic calculations of single crystal SiC etching in a SiC-C equilibrium vapor pressure environment.

[0187] In addition, under the conditions of the points marked with circles, which were etched under a SiC-Si equilibrium vapor pressure environment, the formation of MSBs was decomposed and suppressed, and steps 14 with a height of 1 nm (1 unit cell) were aligned on the surface of the SiC substrate 10. On the other hand, under the conditions of the x marks, which were etched under the SiC-C equilibrium vapor pressure environment, MSBs were formed.

[0188] (Thermodynamic calculation of the crystal growth process) Next, in the thermodynamic calculation of the crystal growth process, the partial pressure difference between the SiC raw material and the steam generated from the SiC substrate when the inside of the main container 30 is heated can be converted into the growth amount. At this time, the growth driving force can be assumed to be a chemical potential difference or a temperature gradient. Note that this chemical potential difference can be assumed to be the partial pressure difference between the gas phase species generated on the surfaces of the polycrystalline SiC (SiC material body 20) and the single crystal SiC (SiC substrate 10). In this case, the growth rate of SiC can be calculated by the following equation 2.

[0189]

number

[0190] where T is the temperature of the SiC raw material side, m i is a gas phase species (Si x C y ) and k is the Boltzmann constant. Also, P 原料i -P 基板i is the amount of SiC deposited when the source gas becomes supersaturated, and the source gas is assumed to be SiC, Si2C, or SiC2.

[0191] That is, the dashed line in Figure 15(b) is the result of a thermodynamic calculation when single crystal SiC is grown using polycrystalline SiC as a raw material in a vapor pressure environment when SiC (solid) and Si (liquid phase) are in phase equilibrium via the gas phase.

[0192] Specifically, using Equation 2, thermodynamic calculations were performed under the following conditions (i) to (iv): (i) a SiC-Si equilibrium vapor pressure environment with constant volume, (ii) the growth driving force was the temperature gradient in main body container 30 and the vapor pressure difference (chemical potential difference) between polycrystalline SiC and single crystal SiC, (iii) the source gases were SiC, Si2C, and SiC2, and (iv) the adsorption coefficient of the source material adsorbed to the steps of SiC substrate 10 was 0.001.

[0193] The two-dot chain line in Figure 15(b) is the result of a thermodynamic calculation when single crystal SiC is grown using polycrystalline SiC as a raw material in a vapor pressure environment when SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase.

[0194] Specifically, using Equation 2, thermodynamic calculations were performed under the following conditions (i) to (iv): (i) a constant volume SiC-C equilibrium vapor pressure environment, (ii) the growth driving force was the temperature gradient in main body container 30 and the vapor pressure difference (chemical potential difference) between polycrystalline SiC and single crystal SiC, (iii) the source gases were SiC, Si2C, and SiC2, and (iv) the adsorption coefficient of the source material adsorbed to the steps of SiC substrate 10 was 0.001. The data for each chemical species used in the thermodynamic calculations were taken from the JANAF Thermochemical Tables.

[0195] According to the graph in Figure 15(b), it can be seen that the result (marked with an O) of placing a SiC substrate 10 in a space (inside the main body container 30) where the atomic ratio Si / C exceeds 1 and growing a growth layer on the SiC substrate 10 coincides with the trend of the thermodynamic calculation results of SiC growth in a SiC-Si equilibrium vapor pressure environment.

[0196] In addition, when the SiC substrate 10 is placed in a space (inside the main container 30) where the atomic ratio Si / C is 1 or less, and a growth layer is grown on the SiC substrate 10 (marked with an x), it can be seen that the trend coincides with the results of thermodynamic calculations of SiC growth in a SiC-C equilibrium vapor pressure environment.

[0197] Fig. 16(a) is an SEM image of the (0001) surface side of 4H-SiC crystal grown at 1800°C, arranged so that the atomic ratio Si / C in the main container 30 is 1 or less. That is, it is an example of the part marked with an x ​​in Fig. 15(b), and is an example of the surface of the SiC substrate 10 crystal grown under a SiC-C equilibrium vapor pressure environment. The surface shape obtained under these conditions is, for example, a step-terrace structure with a terrace width W of 40 to 200 nm and a step 14 height of 3 to 14 nm, and it can be seen that the MSB with a zigzag shape at the step edge is formed.

[0198] On the other hand, Fig. 16(b) is an SEM image of the (0001) surface side of 4H-SiC grown at 1800°C after being arranged so that the atomic ratio Si / C in the main container 30 exceeds 1. That is, it is an example of the area indicated by the circle in Fig. 15(b), and is an example of a surface grown under a SiC-Si equilibrium vapor pressure environment. It can be seen that the surface shape obtained under these conditions has a step-terrace structure with a terrace width of 14 nm and a step height of 1.0 nm (full unit cell), and no MSB is formed.

[0199] The step height and terrace width can be confirmed by AFM or the method of evaluating the contrast of an SEM image described in JP 2015-179082 A. [Explanation of symbols]

[0200] 10. SiC Substrate 11 Underlying substrate 111 Processing-affected layer 112 Bulk layer 113 Distortion 114 Wound 115 Latent injury 12 Dislocation conversion layer 13 Epitaxial growth layer 14 Steps 15. Terrace 20 SiC material body 30 Main container 31 Upper container 32 Lower container 33 Gap 34 Circuit Board Holder 35 Si vapor source 40 Furnace 41 main heating chamber 42 Pre-heating chamber 43 Transportation 44 Heater 45 Vacuum forming valve 46 Inert gas injection valve 47 Vacuum gauge 50 High melting point container 51 Upper container 52 Lower container 53 Gap 54 Si vapor source X Etching Space Y crystal growth space S1 Process-affected layer removal process S2 Crystal growth process S3 Epitaxial growth process S4 Bunching decomposition process

Claims

1. A base substrate, a dislocation conversion layer formed on the base substrate; an epitaxially grown layer formed directly on the dislocation conversion layer; The dislocation conversion layer has a conversion rate of basal plane dislocations to threading edge dislocations of greater than 95%; A SiC substrate, wherein the doping concentration of the dislocation conversion layer is 1×10 15 cm −3 or more and is higher than the doping concentration of the epitaxial growth layer.

2. The doping concentration of the dislocation conversion layer is 1×10 １７ cm －３ The SiC substrate according to claim 1 .

3. The SiC substrate according to claim 1 , wherein the dislocation conversion layer has a thickness of 1 μm or more.

4. The SiC substrate according to any one of claims 1 to 3, wherein the dislocation conversion layer has a conversion rate of basal plane dislocations to threading edge dislocations of 100%.

5. A SiC substrate described in any one of claims 1 to 4, wherein the base substrate has a processing-induced alteration layer removed.

6. A SiC substrate described in any one of claims 1 to 5, wherein the step height of the base substrate is the height of one unit cell.

7. A doping concentration of 1×10 １５ cm －３ a crystal growth step of growing the dislocation conversion layer under conditions that increase the terrace width; and an epitaxial growth step of growing an epitaxial growth layer having a doping concentration lower than that of the dislocation conversion layer directly on the dislocation conversion layer.

8. The method for producing a SiC substrate according to claim 7 , wherein the crystal growth step is a step of growing the crystal in a SiC-C equilibrium vapor pressure environment.

9. 9. The method for producing a SiC substrate according to claim 7, wherein the crystal growth step is a step of growing crystals on a surface on which no macrostep bunching is formed.

10. A method for manufacturing a SiC substrate described in any one of claims 7 to 9, comprising a process-damaged layer removal step of removing a process-damaged layer of the base substrate.

11. A method for manufacturing a SiC substrate described in any one of claims 7 to 10, comprising a bunching decomposition step of decomposing macrostep bunching on the surface of the base substrate.

12. A base substrate; a dislocation conversion layer formed on the base substrate; an epitaxially grown layer formed directly on the dislocation conversion layer; The dislocation conversion layer has a conversion rate of basal plane dislocations to threading edge dislocations of greater than 95%; The doping concentration of the dislocation conversion layer is 1×10 15 cm −3 or more and is higher than the doping concentration of the epitaxial growth layer.

13. The doping concentration of the dislocation conversion layer is 1×10 １７ cm －３ The SiC semiconductor device according to claim 12 .

14. The SiC semiconductor device according to claim 12 or 13, wherein the dislocation conversion layer has a thickness of 1 μm or more.

15. The SiC semiconductor device according to any one of claims 12 to 14, wherein the dislocation conversion layer has a conversion rate of basal plane dislocations to threading edge dislocations of 100%.

16. A SiC semiconductor device described in any one of claims 12 to 15, wherein the base substrate has a processing-induced layer removed.

17. A SiC semiconductor device described in any one of claims 12 to 16, wherein the step height of the underlying substrate is the height of one unit cell.

18. A doping concentration of 1×10 １５ cm －３ a crystal growth step of growing the dislocation conversion layer under conditions that increase the terrace width; and an epitaxial growth step of growing an epitaxial growth layer having a doping concentration lower than that of the dislocation conversion layer directly on the dislocation conversion layer.

19. The method for producing a SiC semiconductor device according to claim 18 , wherein the crystal growth step is a step of growing the crystal in a SiC-C equilibrium vapor pressure environment.

20. 20. The method for manufacturing a SiC semiconductor device according to claim 18, wherein the crystal growth step is a step of growing crystals on a surface on which no macrostep bunching is formed.

21. A method for manufacturing a SiC semiconductor device described in any one of claims 18 to 20, comprising a process-damaged layer removal step of removing a process-damaged layer of the underlying substrate.

22. A method for manufacturing a SiC semiconductor device described in any one of claims 18 to 21, comprising a bunching decomposition process for decomposing macrostep bunching on the surface of the base substrate.

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