P-type oxide semiconductor and semiconductor device including the p-type oxide semiconductor

Abstract

To provide a semiconductor device including a p-type oxide semiconductor, industrially useful, and excellent in semiconductor characteristics.SOLUTION: A p-type oxide semiconductor includes, as a principal ingredient, a metal oxide containing iridium, and at least one metal selected from group 13 metals in a periodic table, further includes a dopant, and has hole carrier density of 1.0×1019 / cm3 or less.SELECTED DRAWING: None

Description

Technical Field

[0001] The present invention relates to an oxide semiconductor and a p-type oxide semiconductor. Further, the present invention relates to a semiconductor device and / or a system including an oxide semiconductor. The present invention relates to a method for forming a p-type oxide semiconductor.

Background Art

[0002] As a next-generation switching element capable of achieving high breakdown voltage, low loss, and high heat resistance, a semiconductor device using gallium oxide (Ga 2 O 3 ) has attracted attention, and its application to power semiconductor devices such as inverters is expected. Moreover, application as a light-emitting and light-receiving device such as an LED or a sensor is also expected due to its wide bandgap. According to Non-Patent Document 1, the bandgap of this gallium oxide can be controlled by forming a mixed crystal with indium, aluminum, or a combination thereof, and it constitutes an extremely attractive material system as an InAlGaO-based semiconductor. Here, the InAlGaO-based semiconductor refers to In X Al Y Ga Z O 3 (0 ≦ X ≦ 2, 0 ≦ Y ≦ 2, 0 ≦ Z ≦ 2, X + Y + Z = 1.5 to 2.5), and it can be regarded as the same material system containing gallium oxide (Patent Document 1).

[0003] And in recent years, p-type semiconductors based on gallium oxide have been studied. For example, Patent Document 2 describes that a substrate showing p-type conductivity can be obtained by forming a β-Ga 2 O 3 -based crystal by the FZ method using MgO (p-type dopant source). Further, Patent Document 3 describes an α-(Al x Ga 1-x ) 2 O 3It has been described that a p-type semiconductor is formed by ion-implanting a p-type dopant into a single-crystalline film. However, with these methods, it is difficult to fabricate a p-type semiconductor (Non-Patent Document 1), and actually, there has been no report of success in fabricating a p-type semiconductor by these methods. Therefore, a realizable p-type oxide semiconductor and its manufacturing method have been awaited.

[0004] Also, as described in Non-Patent Document 2 and Non-Patent Document 3, for example, Rh 2 O 3 and ZnRh 2 O 4 etc. have also been considered for use in p-type semiconductors. However, Rh 2 O 3 has a problem that the raw material concentration becomes particularly thin during film formation, which affects film formation. Even when an organic solvent is used, it is difficult to fabricate a single crystal of Rh 2 O 3 . Also, even when Hall effect measurement is carried out, it is not determined to be p-type, and there is also a problem that the measurement itself cannot be performed. Moreover, regarding the measured values, for example, the Hall coefficient is only below the measurement limit (0.2 cm 3 / C), and it was completely useless. Also, ZnRh 2 O 4 has a problem that its mobility is low and its bandgap is narrow, so it cannot be used for LEDs or power devices, and these were not always satisfactory.

[0005] As wide-bandgap semiconductors, in addition to Rh 2 O 3 and ZnRh 2 O 4 etc., various p-type oxide semiconductors have been studied. Patent Document 4 describes using delafossite, oxychalcogenide, etc. as p-type semiconductors. However, these semiconductors have a mobility of about 1 cm 2 / V·s or less, and their electrical characteristics are poor. There was also a problem that a pn junction with n-type next-generation oxide semiconductors such as α-Ga 2 O 3 could not be formed well.

[0006] Incidentally, conventionally, Ir 2 O 3 has been known. For example, Patent Document 5 describes using Ir 2 O 3 as an iridium catalyst. Also, Patent Document 6 describes using Ir 2 O 3 in a dielectric. Further, Patent Document 7 describes using Ir 2 O 3 in an electrode. However, although using Ir 2 O 3 in a p-type semiconductor was not known, recently, the present applicants have considered using Ir 2 O 3 as a p-type semiconductor and research and development is underway (Patent Documents 8 to 11). Also, regarding the mixed crystal of Ir 2 O 3 and an oxide of Group 13 of the periodic table, a sufficiently satisfactory one has not yet been obtained. For example, a mixed crystal of a p-type oxide with a band gap of 3.4 eV or more has been eagerly awaited. Also, reduction of the low carrier density of an iridium-containing p-type oxide semiconductor has been eagerly awaited.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

[0008] [Non-Patent Document 1] Tatsuya Takemoto, EE Times Japan "Power Semiconductor Gallium Oxide" Thermal Conductivity, P-Type... Overcoming Challenges and Moving towards Practical Application, [online], February 27, 2014, IT Media Co., Ltd., [searched on June 21, 2016], Internet <URL:http: / / eetimes.jp / ee / articles / 1402 / 27 / news028_2.html> [Non-Patent Document 2] F.P. KOFFYBERG et al., "optical bandgaps and electron affinities of semiconducting Rh2O3(I) and Rh2O3(III)", J. Phys. Chem. Solids Vol.53, No.10, pp.1285 - 1288, 1992 [Non-Patent Document 3] Hideaki Hosono, "Functional Development of Oxide Semiconductors", Physical Property Research · Electronic Edition Vol.3, No.1, 031211 (combined issue of November 2013 and February 2014) [Summary of the Invention] [Problems to be Solved by the Invention]

[0009] One of the objectives of the present invention is to provide a p-type oxide semiconductor that is industrially useful and has excellent semiconductor characteristics. [Means for Solving the Problems]

[0010] As a result of intensive studies to achieve the above object, the inventors of the present invention have found that by using the mist CVD method to dope with an organometallic salt of magnesium (Mg) (for example, metal acetate, metal oxalate, metal citrate, etc.) to form a mixed crystal containing iridium and a Group 13 metal of the periodic table, a metal oxide containing iridium and at least one metal selected from the Group 13 metals of the periodic table, which has been difficult to produce conventionally, is mainly contained, and the hole carrier density is 1.0×10 19 / cm 3 or less, and succeeded in creating a p-type oxide semiconductor. It has been found that such an oxide semiconductor can solve the above-described conventional problems all at once.

[0011] Further, after obtaining the above findings, the inventors of the present invention have conducted further studies and completed the present invention. That is, the present invention relates to the following inventions. [1] A p-type oxide semiconductor mainly containing a metal oxide containing iridium and at least one metal selected from the Group 13 metals of the periodic table, further containing a dopant, and having a hole carrier density of 1.0×10 19 / cm 3 or less. [2] The p-type oxide semiconductor according to [1], having a corundum structure. [3] The p-type oxide semiconductor according to [1] or [2], wherein at least one metal selected from the Group 13 of the periodic table is more in atomic ratio than iridium. [4] The p-type oxide semiconductor according to [1] or [2], wherein at least one metal selected from the Group 13 of the periodic table is 50% or more in atomic ratio among all the metals contained in the metal oxide. [5] The p-type oxide semiconductor according to any one of [1] to [4], having a band gap of 3.4 eV or more. [6] The p-type oxide semiconductor according to any one of [1] to [5], having a film shape. [7] A semiconductor device comprising at least a p-type oxide semiconductor according to any one of [1] to [6] above, and an n-type oxide semiconductor disposed in contact with at least a part of the p-type oxide semiconductor. [8] The semiconductor device according to [7] above, wherein the n-type oxide semiconductor has a corundum structure. [9] The semiconductor device according to [7] or [8] above, wherein the n-type oxide semiconductor is an n-type oxide semiconductor.

[10] A semiconductor device comprising at least a p-type oxide semiconductor according to any one of [1] to [6] above, a first n-type oxide semiconductor disposed in contact with at least a part of the p-type oxide semiconductor, and a second n-type oxide semiconductor disposed in contact with at least a part of the first n-type oxide semiconductor.

[11] The semiconductor device according to

[10] above, wherein the first n-type oxide semiconductor has a corundum structure and the second n-type oxide semiconductor has a corundum structure.

[12] The semiconductor device according to any one of [7] to

[11] above, which is one selected from a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a junction field-effect transistor (JFET).

[13] The semiconductor device according to any one of [7] to

[12] above, further comprising an SOI structure having a silicon substrate and a buried insulating layer formed on the silicon substrate.

[14] The semiconductor device according to any one of [7] to

[13] above, which is a power device.

[15] The semiconductor device according to any one of [7] to

[14] above, which is a power module, an inverter, or a converter.

[16] A semiconductor system comprising a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [7] to

[15] above.

Advantages of the Invention

[0012] The p-type oxide semiconductor of the present invention is industrially useful and has excellent semiconductor characteristics.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, preferred embodiments of the present invention will be described.

[0015] In an embodiment of the p-type oxide semiconductor and / or an embodiment of the semiconductor device of the present invention, the p-type oxide semiconductor mainly contains a metal oxide containing iridium and at least one metal selected from the metals of Group 13 of the periodic table, and further contains a specific dopant, and the hole carrier density is 1.0×10 19 / cm 3 It is characterized by being as follows. Here, the "hole carrier density" refers to the carrier density of holes in the oxide semiconductor obtained by Hall effect measurement. The lower limit of the hole carrier density is not particularly limited, but about 1.0×10 14 / cm 3 or more is preferable, and about 1.0×10 15 / cm 3 or more is more preferable.

[0016] Also, in an embodiment of the p-type oxide semiconductor and / or an embodiment of the semiconductor device of the present invention, it is preferable that the metal oxide contained in the p-type oxide semiconductor has a corundum structure. The "metal oxide having a corundum structure" refers to a crystal of a metal oxide containing at least two kinds of metals, and having a crystal structure as a mixed crystal having a corundum structure. Further, in an embodiment of the present invention, it is preferable that the mixed crystal is a single crystal film.

[0017] The p-type oxide semiconductor (hereinafter also referred to as "p-type oxide semiconductor film" and / or "p-type semiconductor layer") contains a metal oxide as a main component, and the metal oxide contains iridium and at least one metal selected from the metals of Group 13 of the periodic table. In an embodiment of the present invention, it is preferable that the p-type oxide semiconductor contains the metal oxide as a main component and has a corundum structure. "Main component" means that the metal oxide which is a mixed crystal is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, still more preferably 90% or more, and may be 100% with respect to all components of the p-type oxide semiconductor film. Also, in an embodiment of the present invention, it is preferable that at least one metal selected from Group 13 of the periodic table is more in atomic ratio than iridium. Further, in an embodiment of the present invention, it is preferable that at least one metal selected from Group 13 of the periodic table is 50% or more in atomic ratio among all the metals contained in the metal oxide. In an embodiment of the present invention, it is preferable that the p-type oxide semiconductor contains, as a main component, a metal oxide containing iridium (Ir) and gallium (Ga). "Metal oxide containing iridium and gallium" refers to one containing iridium element, gallium element and oxygen, but in an embodiment of the present invention, the metal oxide is Ir 1-x Ga x O 3 is preferable, and α-Ir 1-x Ga x O 3It is more preferable. In an embodiment of the present invention, the ratio (%) of gallium (Ga) contained in the raw material solution for generating the atomized droplets is in the range of 40% or more and 60% or less. Further, when the atomized droplets contain a dopant, a p-type oxide semiconductor having a higher bandgap was obtained. Also, according to an embodiment of the present invention, it was found that a mixed crystal of a p-type oxide semiconductor having a bandgap of 3.4 eV or more can be obtained. Further, according to the above-described preferred embodiment of the present invention, a mixed crystal of a p-type oxide semiconductor having a bandgap of 4.1 eV or more can be obtained. Such a mixed crystal is excellent in heat resistance of p-type semiconductor characteristics. Therefore, in particular, it can be industrially advantageously applied to power devices and the like. Moreover, by combining it with an n-type oxide semiconductor having a large bandgap such as gallium oxide or its mixed crystal, the electrical characteristics and reliability of the semiconductor device can be further improved. Further, the shape of the p-type oxide semiconductor is not particularly limited, and it may be in a film shape, a plate shape, or a sheet shape. Also, the p-type oxide semiconductor may constitute a part of the film, for example, as a p-type oxide semiconductor region. According to an embodiment of the present invention, it is preferable that the p-type oxide semiconductor has a film shape.

[0018] Note that the "Periodic Table" refers to the periodic table defined by the International Union of Pure and Applied Chemistry (IUPAC). The "d-block" refers to elements having electrons filling the 3d, 4d, 5d, and 6d orbitals. Examples of the d-block metals include scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), lutetium (Lu), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), lawrencium (Lr), rutherfordium (Rf), dubnium (Db), seaborgium (Sg), bohrium (Bh), hassium (Hs), meitnerium (Mt), darmstadtium (Ds), roentgenium (Rg), copernicium (Cn), and two or more of these metals.

[0019] Also, the "Group 2 metals" may be any Group 2 metals in the periodic table. Examples of the Group 2 metals include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), and two or more of these metals. The "Group 9 metals" may be any Group 9 metals in the periodic table. Examples of such Group 9 metals include iridium (Ir), cobalt (Co), rhodium (Rh), and two or more of these metals. Also, the "Group 13 metals" are not particularly limited as long as they are Group 13 metals in the periodic table. Examples of the Group 13 metals include aluminum (Al), gallium (Ga), indium (In), thallium (Tl), and two or more of these metals. In the present invention, one or more selected from aluminum (Al), gallium (Ga), and indium (In) are preferred.

[0020] The dopant is not particularly limited as long as it does not inhibit the object of the present invention and may be a known one. According to an embodiment of the present invention, the dopant is preferably a p-type dopant. The content of the dopant is preferably 0.00001 atomic% or more, more preferably 0.00001 atomic% to 20 atomic%, and most preferably 0.0001 atomic% to 20 atomic% in the composition of the oxide semiconductor film. The p-type dopant is not particularly limited as long as it does not inhibit the object of the present invention and may be a known one. Examples of the p-type dopant include Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, Pb, N, P, etc. and two or more elements thereof. In an embodiment of the present invention, the p-type dopant is preferably Mg, Zn or Ca, and more preferably Mg. By using such a preferred dopant in combination with the above-mentioned preferred metal oxide, a mixed crystal of a p-type oxide semiconductor having a higher band gap (for example, 4.1 eV or more) and a lower carrier density can be realized.

[0021] The p-type oxide semiconductor of the present invention is preferably obtained by the following method. However, such a method for manufacturing a p-type oxide semiconductor is also novel and useful and is included as one of the present inventions.

[0022] In an embodiment of the present invention, a method for manufacturing a p-type oxide semiconductor is a method for manufacturing a p-type oxide semiconductor mainly composed of a mixed crystal by forming a mixed crystal of metal oxides. The method includes atomizing a raw material solution containing iridium, gallium and a dopant to suspend droplets to generate atomized droplets (including mist) (atomization step), transporting the atomized droplets to the surface of a substrate by a carrier gas (transport step), and then thermally reacting the atomized droplets to form a mixed crystal containing iridium and gallium and further containing a dopant on the surface of the substrate (film formation step).

[0023] (Atomization step) The atomization process atomizes a raw material solution containing at least two kinds of metals, iridium and gallium. In this case, a first raw material solution containing iridium and a second raw material solution containing gallium may be prepared and atomized to generate a first atomized droplet containing iridium and a second atomized droplet containing gallium. Note that the raw material solution may further contain other metals if desired, and in an embodiment of the present invention, it is preferable that the raw material solution further contains a dopant. When preparing the first raw material solution and the second raw material solution, it is preferable that the first raw material solution and / or the second raw material solution contains a dopant. The atomization method is not particularly limited as long as it can atomize the raw material solution and may be a known method. However, in the present invention, an atomization method using ultrasonic waves is preferable. The atomized droplets obtained using ultrasonic waves preferably have an initial velocity of zero and float in the air. For example, instead of spraying like a spray, they are atomized droplets that can float in space and be conveyed as a gas, so there is no damage due to collision energy, which is very suitable. The size of the atomized droplets is not particularly limited and may be about several millimeters, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0024] (Raw material solution) The raw material solution contains iridium and gallium, and is not particularly limited as long as it further contains the dopant, and may contain an inorganic material or an organic material. Further, the raw material solution may optionally contain other metals. When the raw material solution contains iridium, gallium, and other metals, it is preferable that the other metals are Group 2 metals of the periodic table, Group 9 metals other than iridium, and / or Group 13 metals other than gallium. Further, the raw material solution may contain iridium and gallium, or may be divided into a raw material solution containing iridium and a raw material solution containing gallium, and each may be subjected to an atomization step, and the atomized droplets containing iridium obtained from each raw material solution and the atomized droplets containing gallium may be combined in a transport step or a film formation step. In an embodiment of the present invention, a material in which iridium, gallium, and optionally other metals are dissolved or dispersed in an organic solvent or water in the form of a complex or a salt can be suitably used as the raw material solution. Examples of the form of the complex include acetylacetonate complex, carbonyl complex, ammine complex, hydride complex, and the like. Examples of the form of the salt include organometallic salts (such as metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphate salts, metal halide salts (such as metal chloride salts, metal bromide salts, metal iodide salts, etc.). According to the mist CVD method used in the embodiments of the present invention, a film can be suitably formed even if the raw material concentration is low.

[0025] The solvent of the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solution of an inorganic solvent and an organic solvent. In the present invention, unlike other conventional film-forming methods, it is preferable that the solvent contains water, and a mixed solvent of water and an acid is also preferable. More specifically, examples of the water include pure water, ultrapure water, tap water, well water, mineral water, mineral water, hot spring water, spring water, fresh water, seawater, etc. In the present invention, ultrapure water is preferable. Further, more specifically, examples of the acid include organic acids such as acetic acid, propionic acid, and butanoic acid; boron trifluoride, boron trifluoride etherate, boron trichloride, boron tribromide, trifluoroacetic acid, trifluoromethanesulfonic acid, p-toluenesulfonic acid, etc. In an embodiment of the present invention, acetic acid is preferable.

[0026] (Substrate) The substrate is not particularly limited as long as it can support the p-type oxide semiconductor. The material of the substrate is also not particularly limited as long as it does not inhibit the object of the present invention, and it may be a known substrate, an organic compound, or an inorganic compound. The shape of the substrate may be any shape and is effective for any shape. For example, plate-like shapes such as flat plates and disks, fibrous shapes, rod-like shapes, cylindrical shapes, prismatic shapes, tubular shapes, spiral shapes, spherical shapes, ring-shaped shapes, etc. may be mentioned. In the present invention, a substrate is preferable. The thickness of the substrate is not particularly limited in the present invention. Further, as the substrate, as described later, other layers such as a buffer layer may be laminated on the substrate. Further, a semiconductor layer having different electrical conductivity may be used as the substrate.

[0027] The substrate is plate-shaped and is not particularly limited as long as it serves as a support for the p-type oxide semiconductor. It may be an insulator substrate, a semiconductor substrate, or a conductive substrate, but it is preferably an insulator substrate and also preferably a substrate having a metal film on its surface. Examples of the substrate preferably include, for example, a substrate having a corundum structure. The substrate material is not particularly limited as long as it does not inhibit the object of the present invention and may be a known one. Examples of the substrate having a corundum structure include, for example, a base substrate mainly composed of a substrate material having a corundum structure. More specifically, examples include a sapphire substrate (preferably a c-plane sapphire substrate) and a gallium oxide α-substrate. Here, "main component" means that the substrate material having the specific crystal structure is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, still more preferably 90% or more, and may be 100% with respect to all components of the substrate material.

[0028] (Transport process) In the transfer process, the atomized droplets are transferred to the substrate by the carrier gas. The type of the carrier gas is not particularly limited as long as it does not inhibit the object of the present invention. For example, it includes oxygen, ozone, an inert gas such as nitrogen or argon, or a reducing gas such as hydrogen gas or forming gas. However, in the present invention, it is preferable to use oxygen as the carrier gas. Examples of the carrier gas using oxygen include air, oxygen gas, ozone gas, etc., and particularly oxygen gas and / or ozone gas are preferable. Also, the type of the carrier gas may be one type, but may also be two or more types. A dilution gas (for example, 10-fold dilution gas, etc.) with a changed carrier gas concentration may be further used as the second carrier gas. Also, the supply location of the carrier gas is not limited to only one location, but may be two or more locations. In the present invention, when using an atomization chamber, a supply pipe, and a film formation chamber, it is preferable to provide a supply location of the carrier gas in each of the atomization chamber and the supply pipe. It is more preferable to provide a supply location of the carrier gas in the atomization chamber and a supply location of the dilution gas in the supply pipe. Also, the flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min. In the case of the dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, and more preferably 0.1 to 1 L / min.

[0029] (Film formation process) In the film formation process, the atomized droplets are reacted near the surface of the substrate to form a film on part or all of the surface of the substrate. The thermal reaction is not particularly limited as long as it is a thermal reaction in which a film is formed from the atomized droplets, and it is sufficient that the atomized droplets react with heat, and the reaction conditions and the like are not particularly limited as long as they do not inhibit the object of the present invention. In this step, the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, but preferably at a temperature not too high. In the present invention, the thermal reaction is preferably carried out at 1200 °C or lower, more preferably at a temperature of 300 °C to 700 °C or 750 °C to 1200 °C, and most preferably at 350 °C to 600 °C or 750 °C to 1100 °C. Further, the thermal reaction may be carried out in any atmosphere of under vacuum, in a non-oxygen atmosphere, in a reducing gas atmosphere, and in an oxidizing atmosphere as long as it does not inhibit the object of the present invention, and may be carried out under any conditions of atmospheric pressure, under pressure, and under reduced pressure. However, in the present invention, it is preferably carried out in an oxidizing atmosphere, also preferably carried out under atmospheric pressure, and more preferably carried out in an oxidizing atmosphere and under atmospheric pressure. The "oxidizing atmosphere" is not particularly limited as long as it is an atmosphere in which crystals or mixed crystals of metal oxides containing iridium can be formed by the thermal reaction. For example, an oxidizing atmosphere can be obtained by using a carrier gas containing oxygen or by using atomized droplets generated from a raw material solution containing an oxidizing agent. Further, the film thickness can be set by adjusting the film formation time. In the present invention, the film thickness is preferably 1 nm to 1 mm, more preferably 1 nm to 100 μm because the semiconductor characteristics are further improved, and most preferably 1 nm to 10 μm.

[0030] In the embodiment of the present invention, it is preferable to form an n-type semiconductor layer (hereinafter, also referred to as "n-type oxide semiconductor") before or after the formation of the p-type semiconductor layer. The method for forming the n-type semiconductor layer is not particularly limited and may be a known method. In the present invention, the mist CVD method is preferable. By laminating the n-type semiconductor layer on the p-type oxide semiconductor in this way, a semiconductor device having at least the p-type oxide semiconductor and an n-type oxide semiconductor disposed in contact with at least a part of the p-type oxide semiconductor can be obtained. In the embodiment of the present invention, it is also preferable that the semiconductor device has at least the p-type oxide semiconductor, a first n-type oxide semiconductor (for example, an n-type oxide semiconductor, etc.) disposed in contact with at least a part of the p-type oxide semiconductor, and a second n-type oxide semiconductor (for example, an n+-type oxide semiconductor, etc.) disposed in contact with at least a part of the first n-type oxide semiconductor. The n-type semiconductor layer preferably contains an oxide semiconductor as a main component, and more preferably contains an oxide semiconductor containing a Group 13 metal (for example, Al, Ga, In, Tl, etc.) of the periodic table as a main component. Further, the n-type semiconductor layer preferably contains a crystalline oxide semiconductor as a main component, more preferably contains a crystalline oxide semiconductor containing Ga as a main component, and most preferably contains a crystalline oxide semiconductor having a corundum structure and containing Ga as a main component. In the present invention, it is also preferable that the lattice constant difference between the oxide semiconductor that is the main component of the n-type semiconductor and the p-type oxide semiconductor is 1.0% or less, and more preferably 0.3% or less, because a good pn junction can be formed. Here, the "lattice constant difference" is defined as a value obtained by dividing the absolute value of the number obtained by subtracting the lattice constant of the p-type oxide semiconductor from the lattice constant of the oxide semiconductor that is the main component of the n-type semiconductor by the lattice constant of the p-type oxide semiconductor and multiplying the result by 100 (%). Examples of the case where the lattice constant difference is 1.0% or less include the case where the p-type oxide semiconductor has a corundum structure and the oxide semiconductor that is the main component of the n-type semiconductor also has a corundum structure. More preferably, the p-type oxide semiconductor is a mixed crystal of Ir 2 O 3 and the oxide semiconductor that is the main component of the n-type semiconductor is Ga2 O 3 Examples include cases where it is a single crystal or mixed crystal of O. Note that the "main component" means that the oxide semiconductor is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, still more preferably 90% or more, and may be 100% with respect to all components of the n-type semiconductor layer. Further, in an embodiment of the present invention, the p-type oxide semiconductor is preferably a single crystal.

[0031] The p-type oxide semiconductor film obtained as described above can be used as a p-type semiconductor layer in a semiconductor device, and is particularly useful for power devices. By using the p-type oxide semiconductor film in a semiconductor device, roughness scattering can be suppressed, and the channel mobility of the semiconductor device can be made excellent. Further, semiconductor devices can be classified into a lateral element (lateral device) in which an electrode is formed on one side of the semiconductor layer and a vertical element (vertical device) having electrodes on both the front and back sides of the semiconductor layer. In the present invention, it can be suitably used for both lateral devices and vertical devices, but among them, it is preferably used for vertical devices. Examples of the semiconductor device include a Schottky barrier diode (SBD), a metal-semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal-oxide-semiconductor field effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light emitting diode.

[0032] Examples of semiconductor devices using the p-type oxide semiconductor film as a p-type semiconductor layer are shown in FIGS. 2 to 8, FIGS. 12, and 13. Note that the n-type semiconductor may have the same main component as the p-type oxide semiconductor and contain an n-type dopant, or may be an n-type semiconductor having a different main component or the like from the p-type oxide semiconductor. Further, the n-type semiconductor is appropriately used as an n-type semiconductor layer, an n+-type semiconductor layer, etc. by adjusting the content of the n-type dopant, for example.

[0033] Figure 2 shows a semiconductor device as one of the embodiments of the present invention. The semiconductor device in this embodiment shows a preferred example of a Schottky barrier diode (SBD) including an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a p-type semiconductor layer 102, a metal layer 103, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. The SBD in Figure 2 has a trench 70 with an arc portion, and the p-type semiconductor layer 102 is embedded in the trench 70. There is an arc portion 70c between the bottom surface 70a and the side surface 70b of the trench 70, and the radius of curvature of the arc portion is in the range of 100 nm to 500 nm, which has an excellent electric field relaxation effect and can reduce the on-resistance. When a reverse bias is applied to the SBD, due to the stress relaxation effect of the arc portion of the trench 70, a depletion layer (not shown) spreads well into the n-type semiconductor layer 101a as a crystalline oxide semiconductor layer, resulting in a high breakdown voltage SBD. Also, when a forward bias is applied, electrons flow from the ohmic electrode 105b located on the second surface side opposite to the first surface side of the crystalline oxide semiconductor layer to the Schottky electrode 105a located on the first surface side of the crystalline oxide semiconductor layer. The SBD using the semiconductor structure in this way is excellent for high breakdown voltage and high current, has a fast switching speed, and also has excellent breakdown voltage and reliability. Note that the metal layer 103 is made of a metal such as Al and covers the Schottky electrode 105a. In this embodiment, the p-type semiconductor layer 102 mainly contains a metal oxide containing iridium and at least one metal selected from Group 13 of the periodic table, further contains a dopant, and the hole carrier density is 1.0×10 19 / cm 3 or less. When the n-type semiconductor layer 101 mainly contains gallium oxide with a corundum structure, the p-type semiconductor layer 102 disposed on the n-type semiconductor layer 101 also has a corundum structure and mainly contains a mixed crystal containing gallium oxide, so that a semiconductor laminate structure with high affinity can be obtained. Also, the heat resistance of the p-type semiconductor layer is improved.

[0034] FIG. 3 shows a semiconductor device as one of the embodiments of the present invention. The semiconductor device in this embodiment shows a preferred example of a high electron mobility transistor (HEMT) including an n-type semiconductor layer 121a with a wide bandgap, an n-type semiconductor layer 121b with a narrow bandgap, an n+-type semiconductor layer 121c, a p-type semiconductor layer 123, a gate electrode 125a, a source electrode 125b, a drain electrode 125c, and a substrate 129. In this embodiment, the p-type semiconductor layer 123 mainly contains a mixed crystal including at least iridium and gallium, and the mixed crystal has a corundum structure. The p-type semiconductor layer 123 is disposed in contact with the n+-type semiconductor layer 121c. When the n+-type semiconductor layer 121c mainly contains gallium oxide having a corundum structure, the p-type semiconductor layer 123 disposed in contact with the n+-type semiconductor layer 121c also has a corundum structure and mainly contains a mixed crystal including gallium oxide, so that a semiconductor device having a semiconductor laminated structure with high affinity can be obtained.

[0035] The materials of the Schottky electrode and the ohmic electrode may be known electrode materials. Examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof.

[0036] The formation of the Schottky electrode and the ohmic electrode can be performed by a known method such as a vacuum evaporation method or a sputtering method. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are laminated, and patterning using a photolithography technique is performed on the layer made of Mo and the layer made of Al.

[0037] Examples of the material of the insulator layer include GaO, AlGaO, InAlGaO, and AlInZnGaO 4 , AlN, Hf 2 O 3 , SiN, SiON, Al 2 O 3 , MgO, GdO, SiO 2 or Si 3 N 4 etc. However, in the present invention, those having a corundum structure are preferably used. The insulator layer can be formed by a known method such as a sputtering method, a vacuum evaporation method, or a CVD method.

[0038] FIG. 4 shows a semiconductor device as one embodiment of the present invention. The semiconductor device in this embodiment is a trench-type MOSFET, and shows a preferred example of a metal-oxide-semiconductor field-effect transistor (MOSFET) including an n-type semiconductor layer 131a, a first n+-type semiconductor layer 131b, a second n+-type semiconductor layer 131c, a p-type semiconductor layer 132, a p+-type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. Further, in the n-type semiconductor layer 131a and the second n+-type semiconductor layer 131c, a plurality of trenches 70 having a depth that penetrates the first n+ semiconductor layer 131c and reaches halfway through the n-type semiconductor layer 131a are formed as grooves. Each of such trenches 70 includes the arc portion 70c between the bottom surface 70b and the side surface 70a of the trench 70. In the trench 70, for example, a gate electrode 135a is embedded and formed via a gate insulating film 134 having a thickness of 10 nm to 1 μm. Note that the p+-type semiconductor layer 132a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 132. In this embodiment, the p-type semiconductor layer 132 mainly contains a mixed crystal including at least iridium and gallium, and the mixed crystal has a corundum structure. The p+-type semiconductor layer 132a may also mainly contain a mixed crystal including at least iridium and gallium, and the mixed crystal may have a corundum structure. The p-type semiconductor layer 131c and / or the p+-type semiconductor layer 132a are arranged in contact with an n+-type semiconductor layer 121c and / or an n-type semiconductor layer 131a having a corundum structure. When the n+-type semiconductor layer 121c and / or the n-type semiconductor layer 131a contain a crystal mainly containing gallium oxide having a corundum structure, the p-type semiconductor layer 131c and the p+-type semiconductor layer 132a also have a corundum structure and mainly contain a mixed crystal including gallium oxide, so that a semiconductor device having a semiconductor laminated structure with high affinity can be obtained.

[0039] FIG. 5 shows a semiconductor device as one of the embodiments of the present invention. The semiconductor device in this embodiment shows a preferred example of a junction field effect transistor (JFET) including an n-type semiconductor layer 141a, a first n+-type semiconductor layer 141b, a second n+-type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c. FIG. 6 shows a preferred example of an insulated gate bipolar transistor (IGBT) including an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n+-type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c. In this embodiment, the p-type semiconductor layer 142 mainly contains a mixed crystal containing at least iridium and gallium, and the mixed crystal has a corundum structure. The p-type semiconductor layer 142 is disposed in contact with the n-type semiconductor layer 141a and the first n+-type semiconductor layer 141b. When the n-type semiconductor layer 141a and / or the first n+-type semiconductor layer 141b mainly contains gallium oxide having a corundum structure, the p-type semiconductor layer 123 disposed in contact with the n-type semiconductor layer 141a and the first n+-type semiconductor layer 141b also contains a corundum structure and mainly contains a mixed crystal containing gallium oxide, so that a semiconductor device having a stacked structure of semiconductors with high affinity can be obtained.

[0040] (LED) An example of the case where the semiconductor device of the present invention is a light-emitting diode (LED) is shown in FIG. 7. The semiconductor light-emitting element in FIG. 7 includes an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is laminated on the n-type semiconductor layer 161. And a p-type semiconductor layer 162 is laminated on the light-emitting layer 163. On the p-type semiconductor layer 162, a light-transmitting electrode 167 that transmits the light generated in the light-emitting layer 163 is provided, and a first electrode 165a is laminated on the light-transmitting electrode 167. The light-emitting body used for the light-emitting layer may be a known one. Note that the semiconductor light-emitting element in FIG. 7 may be covered with a protective layer except for the electrode portions. In the present embodiment, the p-type semiconductor layer 162 contains, as a main component, a mixed crystal containing at least iridium and gallium, and the mixed crystal has a corundum structure. When the layer arranged in contact with the p-type semiconductor layer 162 contains, as a main component, a corundum structure and / or gallium oxide, a semiconductor device having a laminated structure of semiconductors with high affinity can be obtained.

[0041] Examples of the material of the light-transmitting electrode include a conductive material of an oxide containing indium (In) or titanium (Ti). More specifically, for example, In 2 O 3 , ZnO, SnO 2 , Ga 2 O 3 , TiO 2 , CeO 2 or a mixed crystal of two or more of these or those doped with these can be mentioned. By providing these materials by a known method such as sputtering, a light-transmitting electrode can be formed. Further, after forming the light-transmitting electrode, heat annealing for the purpose of making the light-transmitting electrode transparent may be performed.

[0042] According to the semiconductor light-emitting element in FIG. 7, when the first electrode 165a is used as the positive electrode and the second electrode 165b is used as the negative electrode, and a current is passed through the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161 via both of them, the light-emitting layer 163 emits light.

[0043] Examples of the materials for the first electrode 165a and the second electrode 165b include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof. The method for forming the electrodes is not particularly limited, and it can be formed on the substrate according to a method appropriately selected from wet methods such as printing methods, spraying methods, and coating methods, physical methods such as vacuum evaporation methods, sputtering methods, and ion plating methods, and chemical methods such as CVD and plasma CVD methods, considering the suitability with the above materials.

[0044] Another aspect of the light-emitting element is shown in FIG. 8. In the light-emitting element of FIG. 8, an n-type semiconductor layer 161 is laminated on a substrate 169, and a second electrode 165b is laminated on a part of the semiconductor layer exposed surface of the n-type semiconductor layer 161 exposed by cutting out a part of the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161.

[0045] (HBT) An example of the case where the semiconductor device of the present invention is a heterojunction bipolar transistor (HBT) is shown in FIG. 12. The HBT of FIG. 12 can have either an npn structure or a pnp structure. Hereinafter, the npn structure will be described in detail, but the same applies to the pnp structure, and the p-type layer of the npn structure can be replaced with the n-type layer of the pnp structure, and vice versa. The substrate 60 may be a semi-insulating substrate and may have a high resistivity (for example, a resistivity exceeding 10 5 Ω·cm, etc.). Note that the substrate 60 may be n-type.

[0046] A collector layer 42 is formed above the substrate 60. The collector layer 42 has a thickness of, for example, 200 nm to 100 μm, more preferably 400 nm to 20 μm. The collector layer 42 preferably contains, as a main component, an n-type oxide semiconductor having a corundum structure. It is more preferable that the n-type oxide semiconductor is mainly composed of an oxide semiconductor containing a Group 2 metal (such as Be, Mg, Ca, Sr, Ba, etc.), a Group 9 metal (such as Co, Rh, Ir, etc.) or a Group 13 metal (such as Al, Ga, In, Tl, etc.) in the periodic table. It is even more preferable to contain one or more metals selected from aluminum, indium, and gallium, and most preferably gallium oxide or its mixed crystal. Here, the "main component" is the same as the "main component" described above. Also, in the present embodiment, the concentration of dopants (such as tin, germanium, silicon, titanium, etc.) in the n-type oxide semiconductor is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 However, for example, it can be made into an n-type semiconductor with a low concentration of about 1×10 17 / cm 3 or less. Also, according to the present invention, it can be made into an n+-type semiconductor by containing it at a high concentration of about 1×10 20 / cm 3 or more.

[0047] In this embodiment, particularly when the substrate 60 is semi-insulating, a sub-collector layer 40 may be formed between the collector layer 42 and the substrate 60. The sub-collector layer 40 preferably contains an n+-type oxide semiconductor having a corundum structure as a main component, and it is more preferable that the n+-type oxide semiconductor contains an oxide semiconductor containing a Group 13 metal (such as Al, Ga, In, Tl, etc.) of the periodic table as a main component. It is even more preferable to contain one or more metals selected from aluminum, indium, and gallium, and it is most preferable to be gallium oxide or its mixed crystal. Here, the "main component" is the same as the "main component" described above. The thickness of the sub-collector layer 40 is preferably about 0.1 to 100 μm. A collector electrode 52 is formed on the surface of the sub-collector layer 40. The purpose of the sub-collector layer 40 is to improve the performance of the ohmic collector electrode 52. Note that the sub-collector layer 40 can be omitted when the substrate 60 is conductive.

[0048] A base layer 44 is formed on the collector layer 42. The base layer 44 is not particularly limited as long as it contains the p-type oxide semiconductor of the present invention as a main component. The thickness of the base layer 44 is not particularly limited, but is preferably 10 nm to 10 μm, and more preferably 10 nm to 1 μm. It is also preferable to gradually change the base layer 44 from the contact portion of the collector layer to near the upper surface of the base layer 44. Further, as another aspect, a superlattice can be deposited on the upper surface of the base layer 44.

[0049] An emitter layer 46 is formed on a base layer 44. The emitter layer 46 preferably contains, as a main component, an n-type oxide semiconductor having a corundum structure. More preferably, the n-type oxide semiconductor is mainly composed of an oxide semiconductor containing a Group 13 metal (such as Al, Ga, In, Tl, etc.) of the periodic table. Even more preferably, it contains one or more metals selected from aluminum, indium, and gallium. Most preferably, it is gallium oxide or its mixed crystal. Here, the "main component" is the same as the "main component" described above. The thickness of the emitter layer 46 is not particularly limited, but is preferably 10 nm to 100 μm. The emitter layer 46 usually has a wider bandgap than the base layer 44. It is also preferable to optionally gradually change the composition of the emitter layer 46 from the contact portion with the base layer 44 to the vicinity of the upper surface of the emitter layer 46.

[0050] A cap layer 48 is preferably formed on the emitter layer 46. The cap layer 48 is preferably an n+-type oxide semiconductor having a corundum structure. More preferably, it is an n+-type oxide semiconductor containing one or more metals selected from aluminum, indium, and gallium. Most preferably, it is n+-type doped gallium oxide or its mixed crystal. The thickness is not particularly limited, but is preferably 10 nm to 100 μm. When these layers are subjected to, for example, etching to expose the base layer 44 and an upward collector electrode is provided, the subcollector layer 40 can be exposed by creating a deeper through-hole, for example, by etching.

[0051] Each of the collector electrode 52, the base electrode 54, and the emitter electrode 56 is preferably an ohmic metal electrode. The emitter electrode 56 is deposited on the cap layer 48, and the base electrode 54 is deposited on the base layer 44 exposed, for example, by etching. The collector electrode 52 is deposited on the subcollector layer 40 as described above. As another embodiment, when the substrate is an n-type semiconductor or the like, a collector electrode (not shown) is usually provided on the back surface of the substrate 60 on the side opposite to the device structure.

[0052] The material of each electrode is not particularly limited, and known electrode materials can be used respectively. Suitable compositions for the electrodes include known ohmic electrode materials (such as Ni, Al, Ti, Pt, Au, and laminates thereof, etc.). The thickness of each electrode m is not particularly limited, but a thickness of about 10 to about 100 μm is preferred, and the deposition of each electrode can be achieved by electron beam evaporation, thermal evaporation, sputtering, or other techniques. In addition, after the deposition of each electrode material, annealing treatment may be performed to achieve ohmic contact. The annealing temperature is not particularly limited, but about 300 to 1000 °C is preferred. Note that a pnp HBT can be formed by replacing the p-type layer of the pnp HBT with the n-type layer of an npn HBT and vice versa.

[0053] In the present invention, it is preferable to use the p-type oxide semiconductor film in the semiconductor devices of the following (1) to (3).

[0054] (1) A semiconductor device including a p-type channel layer The semiconductor device (1) is a semiconductor device including at least a gate electrode and a channel layer where a channel is formed directly on the sidewall of the gate electrode or via another layer, and a part or all of the channel layer contains a p-type oxide semiconductor as a main component. The channel layer is not particularly limited as long as a channel can be formed, and it may be a part of the semiconductor layer or the entire part. It may be formed across other semiconductor layers. By using the p-type oxide semiconductor film for the p-type semiconductor layer, it is possible to use it in a semiconductor device without ion implantation or the like, for example, without degrading the semiconductor characteristics of an n-type semiconductor (such as gallium oxide, etc.) with a high breakdown electric field strength and low loss at a high voltage much higher than SiC.

[0055] Note that the semiconductor device (1) preferably further incorporates an SBD. By incorporating an SBD, the on-voltage can be reduced and the freewheel current can be made to flow more easily, so that more excellent semiconductor characteristics can be obtained industrially advantageously.

[0056] (2) Semiconductor device including a p-well layer The semiconductor device (2) is a semiconductor device including at least an n-type semiconductor layer and a p+-type semiconductor layer, wherein the n-type semiconductor layer mainly contains a crystalline oxide semiconductor containing a Group 13 metal of the periodic table, and the p+-type semiconductor layer mainly contains the p-type oxide semiconductor film. The p-type oxide semiconductor film can be suitably used for a p-well layer.

[0057] (3) Semiconductor device including an electric field shielding layer The semiconductor device (3) is a semiconductor device including at least an n-type semiconductor layer mainly containing a crystalline oxide semiconductor having a corundum structure, and an electric field shielding layer and a gate electrode respectively laminated directly or via other layers on the n-type semiconductor layer, wherein the electric field shielding layer contains a p-type oxide semiconductor and is embedded deeper into the n-type semiconductor layer than the gate electrode. By providing the electric field shielding layer in this way, the reverse leakage current can be reduced.

[0058] An example of the semiconductor device including the above (1) to (3) is shown in FIG. 13. The semiconductor device in FIG. 13 includes a first n+-type semiconductor layer 11a, an n-type semiconductor layer 12, a p-type semiconductor layer 13, a second n+-type semiconductor layer 11b, a p+-type semiconductor layer 16, a gate electrode 14a, a gate insulating film 15, a Schottky electrode 14b, and a drain electrode 14c. In the on state of the semiconductor device in FIG. 13, when a voltage is applied between the source electrode 14b and the drain electrode 14c and a positive charge is applied to the gate electrode 14a with respect to the source electrode 14b, a channel is formed at the interface between the p-type semiconductor layer 13 and the gate insulating film 14a, and it turns on. The off state is achieved by setting the voltage of the gate electrode 14a to 0V, so that no channel can be formed and it turns off. Also, in the semiconductor device in FIG. 13, the p-type semiconductor layer 13 is embedded deeper into the n-type semiconductor layer 12 than the gate electrode 14a. With such a configuration, the reverse leakage current can be reduced and the breakdown voltage can be improved.

[0059] The method of forming each layer of the semiconductor device in FIG. 13 is not particularly limited as long as it does not impede the object of the present invention, and may be a known method. For example, after film formation by a vacuum evaporation method, a CVD method, a sputtering method, various coating techniques, etc., a method of patterning by a photolithography method, or a method of directly patterning using a printing technique, etc. may be mentioned. In the semiconductor device of FIG. 13, the second n+-type semiconductor layer 11b and the p+-type semiconductor layer 16 are connected in series via the source electrode 14b. However, the second n+-type semiconductor layer 11b and the p+-type semiconductor layer 16 may be directly connected in series without passing through the source electrode 14b. Although not shown, when the second n+-type semiconductor layer 11b and the p+-type semiconductor layer 16 are directly connected in series, if the p+-type semiconductor layer 16 is made wider than the second n+-type semiconductor layer 11b, the effect of better hole escape is achieved. Also, if the second n+-type semiconductor layer 11b is made wider than the p+-type semiconductor layer 16, the effect of reducing the on-resistance is achieved.

[0060] The semiconductor device is particularly useful for power devices. Examples of the semiconductor device include a diode (such as an SBD) or a transistor (for example, a MOSFET or a JFET, etc.). Among them, an SBD, a MOSFET, an IGBT or a JFET is more preferable, and a MOSFET or a JFET is most preferable. Further, it is also preferable that the semiconductor device includes an SOI structure having a silicon substrate and a buried insulating layer formed on the silicon substrate, or an SOS structure having a sapphire substrate and a silicon layer formed on the sapphire substrate, and can realize operation at a higher temperature.

[0061] In addition to the above-described matters, the semiconductor device of the present invention is preferably used as a power module, an inverter, or a converter by using a known method, and further, for example, it is preferably used in a semiconductor system using a power supply device. The power supply device can be manufactured by connecting the semiconductor device to a wiring pattern or the like by using a known method. An example of a power supply system is shown in FIG. 9. FIG. 9 shows a power supply system 170 configured by using a plurality of the power supply devices 171 and 172 and a control circuit 173. As shown in FIG. 10, the power supply system 170 can be used for a system device 182 in combination with an electronic circuit 181. Note that an example of a power supply circuit diagram of the power supply device is shown in FIG. 11. FIG. 11 shows a power supply circuit of a power supply device including a power circuit and a control circuit. After switching a DC voltage at a high frequency by an inverter 19 (configured by MOSFETs A to D) and converting it to AC, insulation and voltage conversion are performed by a transformer 193, rectification is performed by a rectifying MOSFET, and smoothing is performed by DCL 195 (smoothing coils L1 and L2) and a capacitor to output a DC voltage. At this time, the output voltage is compared with a reference voltage by a voltage comparator 197, and the inverter 192 and the rectifying MOSFET 194 are controlled by a PWM control circuit 196 so as to obtain a desired output voltage.

Example

[0062] (Example 1) 1. Film Forming Apparatus Using FIG. 1, the mist CVD apparatus used in the examples will be described. The mist CVD apparatus 19 includes a susceptor 21 on which a substrate 20 is placed, a carrier gas supply device 22a that supplies a carrier gas, a flow rate adjustment valve 23a for adjusting the flow rate of the carrier gas sent out from the carrier gas supply device 22a, a carrier gas (dilution) supply device 22b that supplies a carrier gas (dilution), a flow rate adjustment valve 23b for adjusting the flow rate of the carrier gas sent out from the carrier gas (dilution) supply device 22b, a mist generation source 24 that houses a raw material solution 24a, a container 25 into which water 25a is put, an ultrasonic vibrator 26 attached to the bottom surface of the container 25, a supply pipe 27 made of a quartz tube with an inner diameter of 40 mm, and a heater 28 installed in the peripheral portion of the supply pipe 27. The susceptor 21 is made of quartz, and the surface on which the substrate 20 is placed is inclined from the horizontal plane. By making both the supply pipe 27, which serves as the film formation chamber, and the susceptor 21 of quartz, it is possible to suppress the mixing of impurities derived from the apparatus into the film formed on the substrate 20. In the examples of the present invention, a c-plane sapphire substrate with an α-Ga 2 O 3 formed as a buffer layer was used as the substrate 20.

[0063] 2. Preparation of the raw material solution A solution obtained by adding hydrochloric acid to an iridium acetylacetonate aqueous solution (iridium (Ir) concentration: 0.001 mol / L) so that the volume ratio is 0.03% and a solution obtained by adding hydrochloric acid to a gallium acetylacetonate aqueous solution (gallium (Ga) concentration: 0.001 mol / L) so that the volume ratio is 2% were mixed to prepare an aqueous solution, which was used as a raw material solution. In this example, a solution containing an organometallic salt of magnesium (Mg) (Mg concentration: 0.05 mol / L) was mixed into the raw material solution such that the atomic ratio of Mg in the raw material solution was 0.75% with respect to the total atomic ratio of Ir and Ga, and the atomic ratio of Ga with respect to the total atomic ratio of Ir and Ga in the raw material solution was set to 50%. As a test example, a film was formed under the same conditions as in 1.2. above and 3.4. below except that the above-mentioned solution containing an organometallic salt of magnesium (Mg) (Mg concentration: 0.05 mol / L) was not mixed into the raw material solution, and the obtained film was identified by X-ray diffraction (XRD) measurement and XPS measurement. The obtained film was an iridium gallium oxide film α-(Ir 0.43 Ga 0.57 ) 2 O 3 with a corundum structure.

[0064] 3. Film Formation Preparation The raw material solution 24a obtained in 2. above was accommodated in the mist generation source 24. Next, as the substrate 20, a substrate 20 was placed on the susceptor 21, and the temperature of the heater 28 was set to 600 °C. Next, the flow rate control valves 23a and 23b were opened, and carrier gas was supplied into the supply pipe 27 from the carrier gas supply devices 22a and 22b which are carrier gas sources. After sufficiently replacing the atmosphere in the supply pipe 27 with the carrier gas, the flow rate of the carrier gas was adjusted to 5.0 L / min and the flow rate of the carrier gas (dilution) was adjusted to 0.5 L / min. Oxygen was used as the carrier gas.

[0065] 4. Film Formation Next, the ultrasonic oscillator was vibrated, and the vibration was propagated through the water 25 to the raw material solution 24a to atomize the raw material solution 24a and generate atomized droplets. These atomized droplets were transported by the carrier gas to the supply pipe 27, and at 600 °C under atmospheric pressure, the atomized droplets thermally reacted near the surface of the substrate 20 to form a film on the substrate 20. The film formation time was set to 60 minutes.

[0066] Regarding the film obtained in the above 4., when the film was identified by X-ray diffraction measurement and XPS measurement, the obtained film was an iridium gallium oxide film (Mg-doped) having a corundum structure, and the ratio of Ir to Ga was the same as that of the iridium gallium oxide film obtained under the condition of not containing magnesium (Mg) in the above test example. Also, when the Hall effect measurement was performed, the carrier type was "p", and the Hall carrier density was 9.85×10 18 (cm -3 ), and the mobility was 6.21×10 -1 (cm 2 / Vs). Also, it was found by spectroscopic transmittance measurement that the band gap was 4.1 eV. (Example 2)

[0067] The atomic ratio of Mg in the raw material solution was mixed to be 0.5%, 1%, 3%, and 5% with respect to the total atomic ratio of Ir and Ga, and a film was obtained in the same manner as in the above 1 to 4, and XRD measurement was performed. For reference, the results for the case of Mg 0% are also shown. As shown in Fig. 14, it was confirmed that even when Mg doping was performed to create a mixed crystal, no other phases or other domains were mixed in, and an iridium gallium oxide film having a high-quality corundum structure was obtained.

Industrial Applicability

[0068] The p-type oxide semiconductor film in the embodiment of the present invention can be used in various fields such as semiconductors (for example, compound semiconductor electronic devices, etc.), electronic component and electrical equipment parts, optical and electrophotographic related devices, and industrial members. However, because it has excellent p-type semiconductor characteristics, it is particularly useful for semiconductor devices and the like.

Explanation of Symbols

[0069] 1 Film forming apparatus 2 Quartz tube 3 Heater 4 Raw material setting table 5 Raw material 6 Substrate 7 Susceptor 11a First n+-type semiconductor layer 11b Second n+-type semiconductor layer 12 n-type semiconductor layer 13 p-type semiconductor layer 14a Gate electrode 14b Source electrode 14c Drain electrode 15 Gate insulating film 16 p+-type semiconductor layer 19 Mist CVD apparatus 20 Substrate 21 Susceptor 22a Carrier gas supply device 22b Carrier gas (diluted) supply device 23a Flow rate regulating valve 23b Flow rate regulating valve 24 Mist generation source 24a Raw material solution 25 Container 25a Water 26 Ultrasonic vibrator 27 Supply pipe 27a Supply pipe (raw material side) 27b Supply pipe (substrate side) 28 Heater 29 Exhaust port 40 Subcollector layer 42 Collector layer 44 Base layer 46 Emitter layer 48 Cap layer 52 Collector electrode 54 Base electrode 56 Emitter electrode 60 Substrate 70 Trench 70a Side surface of trench 70b Bottom surface of trench Arc portion of the 70c trench 101a n-type semiconductor layer 101b n+-type semiconductor layer 102 p-type semiconductor layer 103 Metal layer 104 Insulator layer 105a Schottky electrode 105b Ohmic electrode 121a n-type semiconductor layer with a wide bandgap 121b n-type semiconductor layer with a narrow bandgap 121c n+-type semiconductor layer 123 p-type semiconductor layer 125a Gate electrode 125b Source electrode 125c Drain electrode 128 Buffer layer 129 Substrate 131a n-type semiconductor layer 131b First n+-type semiconductor layer 131c Second n+-type semiconductor layer 132 p-type semiconductor layer 134 Gate insulating film 135a Gate electrode 135b Source electrode 135c Drain electrode 138 Buffer layer 139 Semi-insulating layer 141a n-type semiconductor layer 141b First n+-type semiconductor layer 141c Second n+-type semiconductor layer 142 p-type semiconductor layer 145a Gate electrode 145b Source electrode 145c Drain electrode 151 n-type semiconductor layer 151a n-type semiconductor layer 151b n+-type semiconductor layer 152 p-type semiconductor layer 154 Gate insulating film 155a Gate electrode 155b Emitter electrode 155c collector electrode 161 n-type semiconductor layer 162 p-type semiconductor layer 163 light-emitting layer 165a first electrode 165b second electrode 167 transparent electrode 169 substrate 170 power supply system 171 power supply device 172 power supply device 173 control circuit 180 system device 181 electronic circuit 182 power supply system 192 inverter 193 transformer 194 MOSFET 195 DCL 196 PWM control circuit 197 voltage comparator

Claims

1. The semiconductor device includes a metal oxide containing iridium and gallium as a main component, further contains a dopant, and has a hole carrier density of 1.0×10 １９ / cm ３ is as follows: The p-type oxide semiconductor, in which the gallium is greater than the iridium in terms of atomic ratio.

2. A semiconductor device comprising a metal oxide containing iridium and gallium as a main component, further containing a dopant, and having a hole carrier density of 1.0 x 10 19 / cm 3 or less; A p-type oxide semiconductor, wherein the gallium accounts for 50% or more, in terms of atomic ratio, of all metals contained in the metal oxide.

3. A p-type oxide semiconductor comprising a metal oxide containing iridium and gallium as a main component and further containing a dopant, having a hole carrier density of 1.0 x 1019 / cm3 or less and a band gap of 3.4 eV or more.

4. The p-type oxide semiconductor according to any one of claims 1 to 3, having a corundum structure.

5. The p-type oxide semiconductor according to any one of claims 1 to 4, which has a film shape.

6. 6. A semiconductor device comprising: the p-type oxide semiconductor according to claim 1; and an n-type oxide semiconductor arranged so that at least a portion of the n-type oxide semiconductor is in contact with the p-type oxide semiconductor.

7. The semiconductor device according to claim 6 , wherein the n-type oxide semiconductor has a corundum structure.

8. A semiconductor device comprising at least the p-type oxide semiconductor according to any one of claims 1 to 5, a first n-type oxide semiconductor arranged in contact with at least a portion of the p-type oxide semiconductor, and a second n-type oxide semiconductor arranged in contact with at least a portion of the first n-type oxide semiconductor.

9. The semiconductor device according to claim 8 , wherein the first n-type oxide semiconductor has a corundum structure, and the second n-type oxide semiconductor has a corundum structure.

10. The semiconductor device according to any one of claims 7 to 9, which is one selected from a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a junction field effect transistor (JFET).

11. The semiconductor device according to claim 7, further comprising: a sapphire substrate; and a buffer layer formed on the sapphire substrate and made of α-Ga 2 O 3 .

12. The semiconductor device according to any one of claims 7 to 11, which is a power device.

13. 13. The semiconductor device according to claim 7, which is a power module, an inverter or a converter.

14. A semiconductor system comprising a semiconductor device, the semiconductor device being the semiconductor device according to any one of claims 7 to 13.

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