Method for manufacturing semiconductor device, semiconductor substrate

Abstract

To provide a semiconductor device manufacturing method, a semiconductor device, an electron device, a semiconductor epitaxial substrate manufacturing method, and a semiconductor epitaxial substrate.SOLUTION: A semiconductor device manufacturing method comprises the steps of: preparing a template substrate (TK) including a base substrate (2), and a mask (3) including an open part (K) and a mask part (3a); forming a first semiconductor part (S1) on a first region (A1) of the mask part from a top of the open part; and forming a third semiconductor part (S3) that is positioned above the first semiconductor part and positioned on a second region (A2) where a second semiconductor part (S2) containing gallium and aluminum and the first conductive part are not formed, and forms the third semiconductor part (S3) containing aluminum.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices.

Background Art

[0002] After forming a semiconductor layer on a lower substrate, methods of bonding the semiconductor layer to a support substrate different from the lower substrate and separating the support substrate and the semiconductor layer have been studied using various semiconductor materials (see, for example, Patent Document 1 below), but further improvement in characteristics of semiconductor devices is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] A method for manufacturing a semiconductor device according to the present disclosure includes a step of preparing a template substrate including a lower substrate and a mask including an opening and a mask portion, a step of forming a first semiconductor portion over the opening and over a first region of the mask portion, and a step of forming a semiconductor portion including a group III element of gallium over a second region of the mask portion where the first semiconductor portion is not formed.

Brief Description of the Drawings

[0005]

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Best Mode for Carrying Out the Invention

[0006]

Embodiment 1

[0007] FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor epitaxial substrate 10 according to an embodiment of the present disclosure. The method of manufacturing the semiconductor epitaxial substrate 10 of the present embodiment includes a mask formation step, a first semiconductor layer formation step, and a second semiconductor layer formation step. In the mask formation step, a deposition suppression mask 3 for suppressing the growth of semiconductor crystals is formed on a partial region 1a, which is a first partial region of the growth surface 1 of a substrate 2 having a growth surface 1, for example, a flat first surface, including a starting point for the growth of semiconductor crystals, and a mask formation body is formed in which a surface of the growth surface 1 not covered by the deposition suppression mask 3 is a crystal growth region 1b, which is a second partial region. In the first semiconductor layer formation step, semiconductor crystals are grown by vapor phase growth from the crystal growth region 1b over the deposition suppression mask 3 to form a first semiconductor layer 4. In the second semiconductor layer formation step, semiconductor crystals are grown by vapor phase growth on the first semiconductor layer 4 to form a second semiconductor layer 5 in which at least a portion in contact with the first semiconductor layer 4 contains aluminum.

[0008] The deposition suppression mask 3 is formed to contain, for example, silicon oxide. The substrate 2 is formed to contain, for example, a gallium nitride (GaN) single crystal.

[0009] This embodiment further includes a mask removal step of removing the deposition suppression mask 3 after the second semiconductor layer formation step, and a support substrate bonding step of bonding the second semiconductor layer 5 and a support substrate after the mask removal step.

[0010] The second semiconductor layer 5 is formed to contain a nitride semiconductor AlGaN containing aluminum Al in at least a portion in contact with the first semiconductor layer 4.

[0011] In the second semiconductor layer formation step, a non-single crystal film of a nitride semiconductor containing aluminum is first formed at a site on the deposition suppression mask 3 where the first semiconductor layer 4 is not formed.

[0012] (Mask formation step) In the mask formation step according to the embodiment, first, the substrate 2 is prepared as a base substrate. The substrate 2 is an off-substrate, and the normal line of the growth surface 1 of the substrate 2 may be inclined, for example, by 0.3° from the <11-20> direction of the a-axis. However, it is possible to use a substrate with an off-angle with respect to the a-axis of 0.1° to 1°.

[0013] For such a substrate 2, for example, a GaN substrate cut out from a GaN single crystal ingot can be used so that the growth surface 1 of the substrate 2 is in a predetermined plane direction. The substrate 2 may be a nitride semiconductor substrate. Further, it may be an n-type substrate or a p-type substrate in which an impurity is doped in the nitride semiconductor.

[0014] The "nitride semiconductor" referred to here is, for example, Al X Ga Y In Z N (0 ≦ X ≦ 1; 0 ≦ Y ≦ 1; 0 ≦ Z ≦ 1; X + Y + Z = 1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. Sapphire, Si, or SiC can also be used for the substrate 2.

[0015] Next, a mask layer including the deposition suppression mask 3 is formed on the growth surface 1 of the substrate 2. First, silicon oxide (for example, SiO 2etc.) is deposited to a thickness of about 100 nm by a method such as PCVD (Plasma Chemical Vapor Deposition). Subsequently, by photolithography and wet etching with Buffered Hydrofluoric Acid (BHF), SiO 2 layer is patterned to form a mask body having a deposition suppression mask 3.

[0016] The deposition suppression mask 3 is in a stripe shape in which a plurality of strip portions 3a are arranged in parallel at a predetermined interval. The width of the opening between adjacent strip portions 3a is, for example, about 2 μm to 20 μm. The width of the strip portion 3a is, for example, about 50 μm to 200 μm.

[0017] As a mask material for forming the deposition suppression mask 3, SiO which is an example of silicon oxide 2 In addition, any material from which a semiconductor layer does not grow from the mask material by vapor phase growth may be used. The mask material can be, for example, a nitride such as silicon nitride (SiN X ) or TiN, an oxide such as ZrO X , TiO X or AlO X etc., or a transition metal such as W or Cr can also be used. In particular, since SiO 2 is easily removable with BHF etc., it can be suitably used as a mask material in terms of facilitating the removal process of the deposition suppression mask 3 described later. However, the deposition suppression mask 3 is preferably formed to contain one or more selected from silicon oxide and silicon nitride. Also, as a method for laminating the deposition suppression mask 3, a method suitable for the mask material such as vapor deposition, sputtering, or coating and curing can be appropriately used.

[0018] (First Semiconductor Layer Formation Step) Subsequently, a first semiconductor layer 4 which is a crystal growth layer of a semiconductor crystal is vapor phase grown from a crystal growth region 1b of a growth surface 1 exposed from an opening between the strip portions 3a. The first semiconductor layer 4 of the present disclosure is a nitride semiconductor layer.

[0019] The crystal growth method can use, for example, Metalorganic Vapor Phase Epitaxy (MOVPE) that uses an organometallic as a group III raw material, or Hydride Vapor Phase Epitaxy (HVPE) that uses a chloride.

[0020] When the grown crystal exceeds the opening of the deposition suppression mask 3, the crystal also grows laterally along the upper surface of the deposition suppression mask 3. The crystal growth ends before the first semiconductor layer 4 grown from the crystal growth region 1b overlaps with the adjacent first semiconductor layers 4.

[0021] In this way, a first semiconductor layer 4 in which a nitride semiconductor is grown by the ELO method is obtained. The first semiconductor layer 4 has a first surface 4a and a second surface 4b located on the side opposite to the first surface 4a. The width of the first semiconductor layer 4 is, for example, about 50 μm to 200 μm, and the height is about 10 μm to 50 μm.

[0022] (Second Semiconductor Layer Formation Step) After growing the first semiconductor layer 4, a second semiconductor layer 5 containing aluminum at least in a portion in contact with the first semiconductor layer 4 is formed on the first surface 4a of the first semiconductor layer 4. When forming a layer containing aluminum, a non-single crystal film 5' containing aluminum is simultaneously formed at a site on the deposition suppression mask 3 where the first semiconductor layer 4 is not formed. The layer structure and the composition of each layer of the second semiconductor layer 5 are appropriately designed according to an arbitrary device structure such as a Light Emitting Diode (LED), a Laser Diode (LD), or a Photodiode (PD). The thickness of the second semiconductor layer 5 is, for example, about 1 μm to 5 μm.

[0023] After forming the second semiconductor layer 5, the substrate 2, the deposition suppression mask 3, the first semiconductor layer 4, and the second semiconductor layer 5 are immersed in BHF for about 10 minutes to remove the deposition suppression mask 3. As a result, a semiconductor element portion 6 is formed on the substrate 2 in which the surface of the first semiconductor layer 4 is covered by the second semiconductor layer 5. The semiconductor element portion 6 and the substrate 2 are connected to the substrate 2 via, for example, a columnar connection portion 7 that is a part of the first semiconductor layer 4 grown in the opening of the deposition suppression mask 3.

[0024] In the above-described second semiconductor layer forming step, when growing AlGaN as the second semiconductor that composes the second semiconductor layer 5, SiO 2 A debris film is formed on the deposition suppression mask 3. In the present embodiment, the debris film refers to a film of nitride semiconductor polycrystals formed on the deposition suppression mask 3, for example, having a maximum length of about several hundred nanometers in a plan view. Such a debris film has a high reactivity of Al and is difficult to migrate, so it adheres to the surface of the deposition suppression mask 3. This becomes a nucleus, and the debris film of AlGaN shown in the electron micrograph of FIG. 2 is formed. Since the debris film of AlGaN does not function as a deposition suppression mask, the layers in the subsequent second semiconductor layer forming step are also formed on the debris film.

[0025] FIG. 3 is a diagram showing an example of the design value of the composition distribution of the main component elements in the thickness direction of the semiconductor element of the present embodiment. FIG. 4A is an electron micrograph of the semiconductor surface on which the debris film is formed, and FIG. 4B is an electron micrograph showing the semiconductor surface without the debris film.

[0026] When crystal growth is performed only on the region not covered by the deposition suppression mask 3, a phenomenon occurs in which the growth layer thickness near the boundary between the portion covered by the insulating film and the portion not covered by the insulating film becomes thick, so-called edge growth.

[0027] FIG. 5 is a diagram showing the edge growth height of the semiconductor layer when a semiconductor crystal containing aluminum is used for the portion of the second semiconductor 5 in contact with the first semiconductor layer 4 and when a semiconductor crystal not containing aluminum is used. FIG. 6A is a diagram showing an electron microscope image of a cross section of the semiconductor layer when there is no debris film. FIG. 6B is a diagram showing an electron microscope image of a cross section of the semiconductor layer when there is a debris film.

[0028] When a semiconductor crystal containing aluminum is not used for the portion of the second semiconductor layer 5 in contact with the first semiconductor layer 4, as shown in FIG. 6A, crystal growth proceeds at both ends of the upper surface of the semiconductor layer compared to the center, and edge growth is observed. On the other hand, when a semiconductor crystal containing aluminum is used for the second semiconductor layer 5, as shown in FIG. 6B, the upper surface of the semiconductor layer is substantially flat, the migration effect of group III raw materials on the deposition suppression mask 3 is reduced by the debris film, and edge growth is suppressed.

[0029] The suppression effect of mask impurities incorporated by the debris film is described below. Table 1 summarizes the relationship between the Si concentration and thickness of each layer constituting the semiconductor laminate by secondary ion mass spectrometry (SIMS). In Table 1, for simplicity, some of the numerical values are shown in floating-point numbers (mantissa part) × (base number)(exponent part) with a base number of 10. For example, "2E18" in Table 1 means "2×10 18 ".

[0030]

Table 1

[0031] Table 1 shows an example of each LED with a different layer structure, the thickness of the p-AlGaN layer and the Si impurity concentration. Here, the flat LED in Table 1 refers to an epitaxial substrate on which an LED structure is grown on the entire surface of the semiconductor substrate without using a deposition suppression mask. Also, MQW refers to a multi quantum well.

[0032] For example, when comparing the p-AlGaN layers of "LED without debris film" and "LED with debris film", the Si concentration of the "LED with debris film" is lower than that of the "LED without debris film". This is presumably because the presence of the debris film suppresses Si autodoping. The thickness is thinner for the "LED with debris film" than for the "LED without debris film" and is close to the thickness of the p-AlGaN layer of the flat LED. This is presumably because the debris film suppresses the supply of raw materials on the deposition suppression mask 3 to the second semiconductor layer 5. The above consideration is also supported by the fact that the p-AlGaN layer of the "LED with debris film" is closer to the thickness and Si concentration of the p-AlGaN layer of the "flat LED" than the "LED without debris film".

[0033] As described above, according to the present embodiment, after growing the first semiconductor layer 4 on the growth surface 1 of the substrate 2 that serves as the base of the semiconductor device layer, the second semiconductor layer 5 is grown, and the deposition suppression mask 3 is covered with the second semiconductor layer 5. Thereby, a crystal growth layer serving as a device layer can be formed uniformly, and the mixing of decomposition products of the deposition suppression mask into the second semiconductor layer 5 can be reduced.

[0034] In the present embodiment, when GaN growth is performed by epitaxial vapor phase growth (ELO), SiO is used as the deposition suppression mask. 2 In view of the usefulness of the mask, GaN growth is performed using SiO 2 such that the grown layers by ELO do not meet. According to the present embodiment, at this time, SiO 2 is decomposed, and Si, which is an n-type dopant, is not doped into the GaN crystal grown by ELO, thus not causing the problem that the p layer is difficult to grow. Further, according to the present embodiment, when forming the device layer, due to edge growth where the growth rate at the corners of the ELO grown layer is higher than that at the center, the problem of not easily forming a uniform layer does not occur. Furthermore, according to the present embodiment, the growth rate changes under the same growth conditions between the flat GaN layer and the subsequent GaN element layer, which is the grown layer, and the problem of difficulty in applying the same epitaxial vapor phase growth conditions as on the flat GaN does not occur.

[0035] Here, the deposition suppression mask is an example of silicon oxide, SiO 2 In addition to this, a material in which a semiconductor layer does not grow from the mask material by vapor deposition may be used. The deposition suppression mask may be, for example, a nitride such as silicon nitride (SiN X ) or TiN, an oxide such as ZrO X , TiO X or AlO X , or a transition metal such as W or Cr may be used, and the same effect can be achieved by these. The semiconductor epitaxial substrate of the present disclosure can be manufactured by growing the first semiconductor layer 4 on the growth surface of the substrate 2 that serves as the base of the device layer, then growing the second semiconductor layer 5, and covering the second semiconductor layer 5 with the deposition suppression mask 3. Thereby, a semiconductor crystal layer serving as a device layer can be formed uniformly, and a semiconductor epitaxial substrate 10 with excellent quality can be provided. 〔Embodiment 2〕

[0036] FIG. 7 is a plan view showing a method for manufacturing a semiconductor device according to Embodiment 2. FIG. 8 is a flowchart showing a method for manufacturing a semiconductor device according to Embodiment 2. FIG. 9 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of FIG. 8. In the manufacturing method shown in FIGS. 7 to 9, a step of preparing a template substrate TL including a lower base substrate 2 and a mask 3 including an opening K and a mask portion 3a, and using the ELO method to form a first semiconductor portion S1 from above the opening K over the first region A1 of the mask portion 3a. A step of forming a second semiconductor portion S2 located above the first semiconductor portion S1 and containing gallium (Ga) and a group 13 element which is a group of elements of gallium, and a second semiconductor portion S1 not formed in the first semiconductor portion S1 in the mask portion 3a. And a step of forming a third semiconductor portion S3 located above the region A2 and containing the group 13 element of gallium. The first and second regions A1 and A2 are adjacent to each other, and the mask portion 3a may contain at least one of silicon oxide and silicon nitride. The third semiconductor portion S3 can also be said to be a semiconductor portion located above the second region A2. The third semiconductor portion S3 may be a debris film. Here, the direction from the lower base substrate 2 toward the first semiconductor portion S1 is defined as the "upward direction" (which may be opposite to the vertically upward direction).

[0037] In the ELO method, since the first semiconductor portion S1 including a nitride semiconductor (for example, a GaN-based semiconductor) is grown laterally (X direction) from the opening K of the mask 3, a low defect portion SD can be formed on the mask portion 3a which is a selective growth mask. The low defect portion SD has a lower threading dislocation density than the dislocation inheritance portion HD (the portion that inherits the dislocations derived from the lower base substrate) on the opening K. For example, 5×10 6 / cm 2 Or less (1 / 5 or less of the threading dislocation density of the dislocation inheritance portion HD). The semiconductor crystal formed above the low defect portion SD inherits the low defect property and has excellent crystallinity. In FIGS. 7, 9, etc., the <11-20> direction of the first semiconductor portion S1 is defined as the X direction (a-axis direction), the <1-100> direction as the Y direction (m-axis direction), and the <0001> direction as the Z direction (c-axis direction). In the manufacturing method of FIGS. 7 to 9, semiconductor crystals (first semiconductor portions) that grow horizontally in opposite directions on the same mask portion 3a stop growing before meeting on the mask portion 3a, and the gap between them corresponds to the second region A2.

[0038] By forming the first to third semiconductor portions S1 to S3 on the template substrate TL, the semiconductor substrate 10, which is a semiconductor device, can be obtained. The semiconductor substrate 10 includes a template substrate TL including a base substrate 2 and a mask 3 including an opening K and a mask portion 3a, a first semiconductor portion S1 located on the first region A1 of the mask portion 3a from above the opening K, a second semiconductor portion S2 located above the first semiconductor portion S1 and containing gallium and a group III element of gallium, and a third semiconductor portion S3 located above the second region A2 of the mask portion 3a where the first semiconductor portion S1 is not formed and containing the group III element of the gallium. The first and third semiconductor portions S1 and S3 are adjacent in plan view (viewed in the Z direction). The second semiconductor portion S2 and the third semiconductor portion (the semiconductor portion located above the second region A2) S3 may be formed by the same process or by different processes.

[0039] Each of the second and third semiconductor portions S2 and S3 may include a nitride semiconductor, and the group III element of gallium contained in the second and third semiconductor portions S2 and S3 may be aluminum. For example, the second and third semiconductor portions S2 and S3 may include aluminum gallium nitride (AlGaN). In this case, since the third semiconductor portion S3 (AlGaN layer) functions as a lid for the mask portion 3a (including Si), unintentional Si doping (raw material transfer from the mask portion 3a) into the semiconductor crystal formed above the second semiconductor portion S2 can be suppressed.

[0040] The gallium aluminum nitride contained in the third semiconductor part S3 may have a composition different from that of the gallium aluminum nitride contained in the second semiconductor part S2. The thickness of the third semiconductor part S3 may be smaller than the thickness of the second semiconductor part S2. The second and third semiconductor parts S2 and S3 can be formed in the same process. However, for the third semiconductor part S3 (AlGaN layer) formed on the mask part 3a (amorphous), which is a selective growth mask, and the second semiconductor part S2 (AlGaN layer) formed on the first semiconductor part S1, which is, for example, a GaN-based semiconductor crystal, the crystal growth states are different.

[0041] The third semiconductor part S3 may be in contact with the mask part 3a. The second semiconductor part S2 may be in contact with the upper surface of the first semiconductor part S1. The second semiconductor part S2 may be formed on the first semiconductor part S1 via a buffer nitride semiconductor part (for example, a GaN layer).

[0042] In the process of forming the second and third semiconductor parts S2 and S3, a fourth semiconductor part S4 (for example, an AlGaN layer) may be formed along the side surface of the first semiconductor part S1. When the mask part 3a contains silicon, each of the first to fourth semiconductor parts S1 to S4 may contain silicon. The bandgap of the GaN-based semiconductor (for example, an AlGaN layer) contained in the second semiconductor part S2 may be larger than the bandgap of the GaN-based semiconductor (for example, a GaN layer) contained in the first semiconductor part S1.

[0043] The group III element of gallium in the second and third semiconductor parts S2 and S3 may be indium, and the second and third semiconductor parts S2 and S3 may contain indium gallium nitride (InGaN). The second and third semiconductor parts S2 and S3 may contain aluminum indium gallium nitride (AlInGaN). The group III element of gallium may be boron (B).

[0044] After forming the second and third semiconductor portions S2 and S3, a fifth semiconductor portion S5 may be formed above the second semiconductor portion S2. An active portion (active layer) SA may be formed above the second semiconductor portion S2, and then the fifth semiconductor portion S5 may be formed above the active portion SA. The active portion SA and the fifth semiconductor portion S5 may include a GaN-based semiconductor. Above the third semiconductor portion S3, a sixth semiconductor portion S6 (for example, a GaN-based semiconductor layer) may be formed.

[0045] The active portion SA may have multiple quantum wells (MQWs). The active portion SA may include a light-emitting portion that overlaps with a low-defect portion SD in plan view. The fifth semiconductor portion S5 may be p-type, and for example, may be an Mg-doped p-GaN layer. The first semiconductor portion S1 and the fifth semiconductor portion S5 may include the same GaN-based semiconductor. For example, the first semiconductor portion S1 formed by the ELO method may be an Si-doped n-GaN layer. The second to fourth semiconductor portions S2 to S4 may be n-type, and for example, may be Si-doped n-AlGaN layers.

[0046] The mask portion 3a and the first and fifth semiconductor portions S1 and S5 include silicon, and the silicon concentration of the fifth semiconductor portion S5 may be 1 / 5 or less of the silicon concentration of the first semiconductor portion S1. The third semiconductor portion S3 (for example, an AlGaN layer) functions as a lid for the mask portion 3a (including Si), and can suppress the auto-doping (raw material transfer from the mask portion 3a) of Si (n-type dopant) when forming the p-type fifth semiconductor portion S5.

[0047] The fifth semiconductor portion S5 is not limited to p-type and may be undoped (i-type). The third semiconductor portion S3 can suppress the auto-doping of Si when forming the fifth semiconductor portion S5.

[0048] As shown in FIG. 6B, the fifth semiconductor portion S5 may have a shape having an upper surface, a side surface, and a slope that is adjacent to the upper surface and the side surface and is inclined with respect to the upper surface and the side surface. When the fifth semiconductor portion 5S is formed, crystal growth of the sixth semiconductor portion S6 also proceeds above the third semiconductor portion S3 (see FIG. 9), and since the raw material is consumed, abnormal growth (edge growth) of the edge of the fifth semiconductor portion 5S is reduced.

[0049] After forming the fifth semiconductor portion S5, a step of forming electrodes EC and the like may be performed. After forming the electrodes EC and the like, a step of dividing a laminate LB including the first and second semiconductor portions S1 and S2, the fifth semiconductor portion S5, and the electrodes EC into a plurality of parts to obtain a plurality of semiconductor chips (semiconductor devices) 20, and a step of removing the mask portion 3a can be performed.

[0050] In the step of dividing the laminate LB (for example, a dry etching step), the third semiconductor portion S3 on the mask portion 3a may be removed, and after removing the third semiconductor portion S3, the mask portion 3a may be removed (for example, wet etching). After removing the mask portion 3a, a step of separating the first semiconductor portion S1 from the template substrate TL can be performed. For example, in a state where a plurality of semiconductor chips 20 are held by a support substrate SK, the connection portion 7 between the first semiconductor portion S1 and the template substrate TL may be broken. At this time, the connection portion 7 may be attached to the first semiconductor portion S1 side, may be attached to the template substrate TL side as shown in FIG. 9, or may be attached to both sides. Thereby, a plurality of semiconductor chips 20 can be obtained.

[0051] The semiconductor chip (semiconductor device) 20 is, for example, an LED (light emitting diode) chip, a laser chip, a transistor chip, or the like (described later).

[0052] FIG. 10 is a flowchart showing another manufacturing method of the semiconductor device according to Embodiment 2. FIG. 11 is a schematic cross-sectional view showing the manufacturing method of the semiconductor device of FIG. 10. In FIGS. 10 and 11, in the step of dividing the laminate LB after forming the fifth semiconductor portion S5, the electrode EC, etc., the connection portion 7 between the template substrate TL and the first semiconductor portion S1 is removed (together with the dislocation inheritance portion HD). The third semiconductor portion S3 may be removed in the step of removing the connection portion 7. In this way, a plurality of semiconductor chips (semiconductor devices) 20 can be obtained while leaving the mask portion 3a on the template substrate TL.

[0053] FIG. 12 is a cross-sectional view showing the configuration of the base substrate in Embodiment 2. The base substrate 2 may be composed of a main substrate 21 which is a bulk crystal substrate (for example, a GaN substrate, a hexagonal SiC substrate, an AlN substrate, etc.). In this case, the upper surface of the main substrate 21 exposed from the opening K of the mask 3 becomes the growth starting point of the first semiconductor portion S1.

[0054] The base substrate 2 may have a configuration including a main substrate 21 which is a heterogeneous substrate of a bulk crystal and a seed portion 23. The main substrate 21 which is a heterogeneous substrate is, for example, a Si substrate, a SiC substrate, an AlN substrate, a sapphire substrate, etc. In this case, a Si substrate may be used for the main substrate 21 and AlN or SiC may be used for the seed portion 23, or a SiC substrate may be used for the main substrate 21 and a GaN-based semiconductor (for example, GaN) may be used for the seed portion 23. When the base substrate 2 includes the seed portion 23, the upper surface of the seed portion 23 exposed from the opening K of the mask 3 becomes the growth starting point of the first semiconductor portion S1 (see FIG. 7).

[0055] Further, the base substrate 2 may have a configuration including a main substrate 21 which is a heterogeneous substrate of a bulk crystal, a buffer portion 22, and a seed portion 23. When a Si substrate and a GaN-based semiconductor come into direct contact, there is a risk of melting together, but this can be avoided by providing the buffer portion 22. For example, a Si substrate can be used for the main substrate 21, at least one of AlN or SiC can be used for the buffer portion 22, and a GaN-based semiconductor can be used for the seed portion 23.

[0056] The seed portion 23 may be formed entirely, or may be formed locally as shown in the lowermost stage of FIG. 12. For example, if the opening K of the mask 3 is slit-shaped (see FIG. 7), the seed portion 23 may have a longitudinal shape overlapping the opening K.

[0057] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. The semiconductor device (semiconductor chip) 20 in FIG. 13 includes a GaN-based semiconductor (for example, GaN), and has a threading dislocation density of 5×10 6 / cm 2 The following first semiconductor portion S1 having a low dislocation portion SD, a second semiconductor portion S2 located above the first semiconductor portion S1 and containing gallium and a group III element of gallium, an active portion SA located above the second semiconductor portion S2, a p-type GaN-based semiconductor portion GS (fifth semiconductor portion S5) located above the active portion SA, and an electrode EC (for example, an anode) in contact with the GaN-based semiconductor portion GS. Although not shown, for example, a cathode in contact with the second semiconductor portion S2 can be provided.

[0058] The semiconductor device 20 in FIG. 13 is a light-emitting diode (LED) chip, and the active portion SA includes a light-emitting portion ES that overlaps the low dislocation portion SD above the low dislocation portion SD. That is, the light-emitting portion ES is included between the second semiconductor portion S2 and the GaN-based semiconductor portion GS. The group III element of gallium is aluminum, and the second semiconductor portion S2 may be a nitride semiconductor layer containing Al (for example, an AlGaN layer). The first semiconductor portion S1 can be a nitride semiconductor layer formed by the ELO method using a selective growth mask containing silicon, and each of the first and second semiconductor portions S1 and S2 may contain silicon. The second semiconductor portion S2 may extend to the side surface of the first semiconductor portion S1.

[0059] FIG. 14 is a cross-sectional view showing another configuration of a semiconductor device according to Embodiment 2. FIG. 15 is a flowchart showing a manufacturing method of the semiconductor device in FIG. 14. The semiconductor device (semiconductor chip) 20 in FIG. 14 is a laser chip, includes a GaN-based semiconductor (for example, GaN), and has a threading dislocation density of 5×10 6 / cm 2It has a first semiconductor part S1 having the following low-transfer part SD.

[0060] Above the first semiconductor part S1, an n-type contact part SJ, a second semiconductor part S2 which is an n-type clad part, an n-type optical guide part SL, an active part (active layer) SA including a light-emitting part ES, a p-type optical guide part SB, and a GaN-based semiconductor part GS (fifth semiconductor part) including a p-type clad part SC, and an electrode EC are provided in this order. The p-type clad part SC has a ridge part RD (current constriction part), insulating films DF are provided on both sides of the ridge part RD, and the electrode EC (for example, an anode) may be in contact with the p-type clad part SC and the insulating films DF. The second semiconductor part S2 may extend to the side surface of the contact semiconductor part SJ. The first semiconductor part S1 can be a nitride semiconductor layer formed by the ELO method using a selective growth mask containing silicon, and each of the first and second semiconductor parts S1 and S2 may contain silicon. The second semiconductor part S2 may be a nitride semiconductor layer containing Al (for example, an AlGaN layer). Although not shown, for example, a cathode in contact with the contact semiconductor part SJ can be provided.

[0061] In FIG. 15, after performing the step of forming the first semiconductor part S1 (for example, a GaN layer) by the ELO method and the step of forming the n-type contact semiconductor part SJ (for example, an n-GaN layer), the step of forming the second semiconductor part S2 (for example, an n-AlGaN layer) is performed.

[0062] FIG. 16 is a cross-sectional view showing another configuration of the semiconductor device according to Embodiment 2. The semiconductor device 20 in FIG. 16 is a transistor chip (also referred to as a HEMT), includes a GaN-based semiconductor (for example, GaN), and has a threading dislocation density of 5×10 6 / cm 2A first semiconductor part S1 having the following low-transfer part SD, a second semiconductor part S2 located above the first semiconductor part S1 and containing gallium and group elements of gallium, a GaN-based semiconductor part GS (fifth semiconductor part) located on the second semiconductor part S2, a source electrode SE and a drain electrode DE in contact with the second semiconductor part S2, and a gate electrode EG located on the GaN-based semiconductor part GS. The first semiconductor part S1 can be formed by the ELO method.

[0063] The first semiconductor part S1 (for example, a GaN layer) includes a channel part CH (two-dimensional electron gas) near the interface with the second semiconductor part S2 (for example, an AlGaN layer having a larger bandgap than the GaN layer). The channel part CH is an n-channel and turns on (conducts) by applying a potential higher than the threshold potential to the gate electrode EG. The first semiconductor part S1 may be n-type or i-type (undoped type). The second semiconductor part S2 may be n-type or i-type.

[0064] The transistor chip of FIG. 16 has high electron mobility and high breakdown voltage and can be used in high-frequency devices, power devices (power control devices), etc.

[0065] FIG. 17 is a cross-sectional view showing another configuration of the semiconductor device according to Embodiment 2. The semiconductor device (semiconductor chip) 20 of FIG. 17 is a transistor chip (also referred to as an inverse HEMT), includes a GaN-based semiconductor (for example, GaN), and has a threading dislocation density of 5×10 6 / cm 2 A first semiconductor part S1 (for example, a GaN layer) having the following low-transfer part SD, a second semiconductor part S2 located above the first semiconductor part S1 and containing gallium and group elements of gallium, a GaN-based semiconductor part GS (fifth semiconductor part) located on the second semiconductor part S2, a source electrode SE and a drain electrode DE in contact with the GaN-based semiconductor part GS, and a gate electrode EG provided on the GaN-based semiconductor part GS via an insulating film DF. The first semiconductor part S1 can be formed by the ELO method.

[0066] The GaN-based semiconductor part GS (for example, a GaN layer) includes a channel part CH (two-dimensional electron gas) near the interface with the second semiconductor part S2 (for example, an AlGaN layer having a larger bandgap than the GaN layer). The channel part CH is an n-channel and turns off by applying a potential lower than the threshold potential to the gate electrode EG.

[0067] The underlying substrate 2 may be a SiC substrate, and the growth surfaces of the first and second semiconductor parts S1 and S2 may be the (000-1) plane (-c plane, nitrogen-polarity plane). The first semiconductor part S1 may be n-type or i-type (undoped type). The second semiconductor part S2 may be n-type or i-type.

[0068] The transistor chip in FIG. 17 has high electron mobility and high breakdown voltage, and can be used in high-frequency devices, power devices (power control devices), etc.

[0069] FIG. 18 is a flowchart showing a method for manufacturing the semiconductor devices in FIGS. 16 and 17. In FIG. 18, after performing the steps of forming the first semiconductor part S1 (for example, a GaN layer) by the ELO method, forming the second semiconductor part S2 (for example, an AlGaN layer), forming the GaN-based semiconductor part GS, and forming electrodes (SE, EG, DE), etc., a laminate including the first and second semiconductor parts S1 and S2 and the GaN-based semiconductor part GS and the template substrate TL are divided to obtain a semiconductor device 20 which is a semiconductor chip.

[0070] FIG. 19 is a schematic diagram showing the configuration of an electronic device according to Embodiment 2. The electronic device 40 includes a semiconductor device 20 and a control unit 50 including a processor that controls the semiconductor device 20. Examples of the electronic device 40 include a communication device, a power control device, an optical device, a display device, a lighting device, a sensor device, a measuring device, an information processing device, a medical device, an electric vehicle (EV), etc.

[0071] As described above in detail for the embodiments of the present disclosure, the present disclosure is not limited to the above-described embodiments, and various changes, improvements, etc. are possible without departing from the gist of the present disclosure. Needless to say, all or part of each of the above embodiments can be combined as appropriate within a non-contradictory range.

Explanation of Reference Numerals

[0072] 1 Growth surface 1a Partial region of growth surface 1 1b Crystal growth region 2 Substrate (lower substrate) 3 Deposition suppression mask (mask) 4 First semiconductor layer 5 Second semiconductor layer 5’ Non-single crystal film 6 Semiconductor element portion 7 Connection portion 10 Semiconductor epitaxial substrate (semiconductor substrate, semiconductor device) 20 Semiconductor chip (semiconductor device)

Claims

1. A method for manufacturing a semiconductor device comprising: preparing a template substrate including a seed portion and a non-seed portion including a first region and a second region; and preparing a first semiconductor portion located from above the seed portion to above the first region; forming a second semiconductor portion located above the first semiconductor portion and a third semiconductor portion located above the second region and including an element of the same group as gallium; A method for manufacturing a semiconductor device, wherein the third semiconductor portion includes a portion whose thickness decreases toward the first region.

2. A method for manufacturing a semiconductor device as described in claim 1, comprising a step of forming an active portion above the second semiconductor portion.

3. A template substrate including a seed portion and a non-seed portion including a first region and a second region; a first semiconductor portion located on the seed portion and on the first region; a second semiconductor portion located above the first semiconductor portion; a third semiconductor portion located on the second region and including an element of the gallium homologue; The third semiconductor portion includes a portion whose thickness decreases toward the first region.

4. A step of preparing a semiconductor substrate according to claim 3; and forming an active portion above the second semiconductor portion.

5. The method for producing a semiconductor device according to claim 2 or 4, wherein the homologous element of gallium is aluminum.

6. A method for manufacturing a semiconductor device as described in claim 1, wherein the second semiconductor portion contains a congener of the gallium and gallium.

7. A method for manufacturing a semiconductor device as described in claim 2 or 4, wherein in the process of forming the third semiconductor portion and the second semiconductor portion, a fourth semiconductor portion is formed along a side surface of the first semiconductor portion.

8. The method for manufacturing a semiconductor device according to claim 2 , wherein the second semiconductor portion is in contact with an upper surface of the first semiconductor portion.

9. The template substrate has a mask portion which is the non-seed portion and an exposed seed portion. The method for manufacturing a semiconductor device according to claim 2 or 4, further comprising a mask pattern including an opening for forming a mask pattern.

10. A method for manufacturing a semiconductor device as described in claim 2 or 4, further comprising forming a fifth semiconductor portion located above the second semiconductor portion after forming the third semiconductor portion.

11. The method of claim 10 , wherein the fifth semiconductor portion is p-type.

12. The method for manufacturing a semiconductor device according to claim 2 or 4, wherein the second semiconductor portion is of n-type.

13. The semiconductor device according to claim 1, wherein the first semiconductor portion and the fifth semiconductor portion include silicon. The method for manufacturing a semiconductor device according to claim 10 , wherein the silicon concentration of the fifth semiconductor portion is equal to or less than ⅕ of the silicon concentration of the first semiconductor portion.

14. The method for manufacturing a semiconductor device according to claim 10 , further comprising removing the third semiconductor portion after forming the fifth semiconductor portion.

15. The method for manufacturing a semiconductor device according to claim 10 , further comprising removing a connection portion between the template substrate and the first semiconductor portion after forming the fifth semiconductor portion.

16. The template substrate includes a main substrate; The method for manufacturing a semiconductor device according to claim 2 , wherein the main substrate is a heterogeneous substrate having a lattice constant different from that of the first semiconductor portion.

17. The method for manufacturing a semiconductor device according to claim 10 , wherein the fifth semiconductor portion has an upper surface, a side surface, and an inclined surface adjacent to the upper surface and the side surface and inclined relative to the upper surface and the side surface.

18. A step of preparing a template substrate including a seed portion and a non-seed portion including a first region and a second region, and a first semiconductor portion located from above the seed portion to above the first region; forming a second semiconductor portion located above the first semiconductor portion and a third semiconductor portion located above the second region and including an element of the same group as gallium; A method for manufacturing a semiconductor device, wherein the third semiconductor portion is thinner than the first semiconductor portion.

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