Semiconductor Device

Abstract

This semiconductor device comprises: a plurality of transistors electrically connected to each other in parallel, and each having a first electrode; diodes electrically connected to the plurality of transistors in parallel and having an anode electrode; a first electrically conductive pattern; a second electrically conductive pattern electrically connected to the first electrically conductive pattern; a plurality of first connection members each connecting the first electrode of the plurality of transistors and the first electrically conductive pattern directly; and a second connection member connecting the anode electrode and the second electrically conductive pattern. The first electrode is a source electrode or an emitter electrode, and the plurality of transistors are disposed adjacent to each other.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device.

[0002] This application claims priority to Japanese Application No. 2020-157444, filed on September 18, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0003] As a semiconductor device used in a power module, a semiconductor device in which a source electrode or an emitter electrode of a transistor and an anode electrode of a diode are connected to each other has been proposed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2015-154079 [Patent Document 2] Japanese Patent Application Publication No. 2019-71490 [Patent Document 3] US Patent Application Publication No. 2017 / 0125322 Summary of the Invention

[0005] The semiconductor device disclosed herein comprises a plurality of transistors electrically connected in parallel to each other, each having a first electrode, a diode electrically connected in parallel to the plurality of transistors and having an anode electrode, a first conductive pattern, a second conductive pattern electrically connected to the first conductive pattern, a plurality of first connection members each directly connecting the first electrodes of the plurality of transistors to the first conductive pattern, and a second connection member connecting the anode electrode to the second conductive pattern, wherein the first electrode is a source electrode or an emitter electrode, and the plurality of transistors are arranged adjacent to each other. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a top view showing the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view showing the relationship between the heat sink, the first insulating substrate, and the second insulating substrate in the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing the first transistor. [Diagram 5] FIG. 5 is a cross-sectional view showing the first diode. [Figure 6] FIG. 6 is a cross-sectional view showing a second transistor. [Figure 7] FIG. 7 is a cross-sectional view showing the second diode. [Figure 8] FIG. 8 is a circuit diagram showing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a schematic diagram (part 1) showing the operation of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a schematic diagram (part 2) showing the operation of the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a schematic diagram (part 3) illustrating the operation of the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a schematic diagram (part 4) illustrating the operation of the semiconductor device according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a modified example of the heat sink. [Figure 14] FIG. 14 is a schematic diagram showing the configurations of the first insulating substrate and the second insulating substrate in the semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a top view showing the semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing the relationship between a heat sink and an insulating substrate in a semiconductor device according to the third embodiment. [Figure 17]FIG. 17 is a cross-sectional view showing the relationship between a heat sink and a conductive layer in a modified example of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] [Problem that this disclosure aims to solve] It is desirable to achieve more stable operation of multiple transistors connected in parallel.

[0008] An object of the present disclosure is to provide a semiconductor device capable of realizing more stable operation of a plurality of transistors connected in parallel.

[0009] [Effects of this disclosure] According to the present disclosure, it is possible to realize more stable operation of multiple transistors connected in parallel.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0012] [1] A semiconductor device according to one embodiment of the present disclosure includes a plurality of transistors electrically connected in parallel to each other, each having a first electrode, a diode electrically connected in parallel to the plurality of transistors and having an anode electrode, a first conductive pattern, a second conductive pattern electrically connected to the first conductive pattern, a plurality of first connection members each directly connecting the first electrodes of the plurality of transistors to the first conductive pattern, and a second connection member connecting the anode electrode to the second conductive pattern, wherein the first electrode is a source electrode or an emitter electrode, and the plurality of transistors are arranged adjacent to each other.

[0013] A plurality of transistors are arranged adjacent to each other. A first electrode (source electrode or emitter electrode) and a first conductive pattern are directly connected by a first connection member, an anode electrode and a second conductive pattern are connected by a second connection member, and the first conductive pattern and the second conductive pattern are electrically connected. This makes it possible to reduce the inductance of each power loop of the plurality of transistors, and to suppress the variation in the inductance of the power loop among the plurality of transistors. This allows for more stable operation of the plurality of transistors connected in parallel. Currently Cut.

[0014] [2] A semiconductor device according to another embodiment of the present disclosure includes a plurality of transistors electrically connected in parallel to each other, each having a first electrode, a diode electrically connected in parallel to the plurality of transistors and having an anode electrode, a third conductive pattern, a plurality of first connection members each directly connecting the first electrodes of the plurality of transistors to the third conductive pattern, and a second connection member connecting the anode electrode to the third conductive pattern, wherein the first electrode is a source electrode or an emitter electrode, and the plurality of transistors are arranged adjacent to each other.

[0015] A plurality of transistors are arranged adjacent to each other. A first electrode (source electrode or emitter electrode) and a third conductive pattern are directly connected by a first connection member, and an anode electrode and a third conductive pattern are connected by a second connection member. This reduces the inductance of each power loop of the plurality of transistors, and suppresses the variation in the inductance of the power loop among the plurality of transistors. This allows the plurality of transistors connected in parallel to operate more stably.

[0016] [3] In the configuration of [1] or [2], the plurality of transistors may be concentrated within a rectangular first region. In this case, it is easy to suppress variation in inductance of a power loop.

[0017] [4] In any of [1] to [3], the plurality of transistors may be arranged side by side in a first direction. In this case, the plurality of transistors can be consolidated to easily suppress variations in inductance of a power loop.

[0018] [5] In any of [1] to [4], the second connection member may be independent of the plurality of first connection members, which makes it easier to suppress variation in inductance of a power loop.

[0019] [6] In any of [1] to [5], the diode may not be disposed between adjacent transistors among the plurality of transistors, which makes it easier to suppress variations in inductance of a power loop.

[0020] [7] In any of [1] to [6], the transistor may be a field effect transistor made of silicon carbide, in which case the transistor has excellent breakdown voltage.

[0021] [8] In any of [1] to [7], the diode may be a Schottky barrier diode made of silicon carbide, in which case the diode has excellent breakdown voltage.

[0022] [9] In any one of [1] to [8], the semiconductor device further includes a semiconductor device housing the plurality of transistors and the diode. case and a control electrode connected to the plurality of transistors; case and a control terminal attached to said case may have a pair of side walls facing each other and a pair of end walls connecting both ends of the side walls, and the control terminal may be provided on one of the side walls and the end wall that is located closest to the plurality of transistors. In this case, the plurality of transistors can be concentrated in the vicinity of the control terminal. Therefore, it is easy to reduce the difference in gate loop inductance between the plurality of transistors. Therefore, it is easy to realize a more stable operation of the plurality of transistors connected in parallel.

[0023] [Details of the embodiment of the present disclosure] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present embodiments are not limited thereto. In addition, in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description.

[0024] (First embodiment) First, the first embodiment will be described. Fig. 1 is a perspective view showing the semiconductor device according to the first embodiment. Fig. 2 is a top view showing the semiconductor device according to the first embodiment. However, in Fig. 2, the case is seen through. Fig. 3 is a cross-sectional view showing the relationship between the heat sink, the first insulating substrate, and the second insulating substrate in the semiconductor device according to the first embodiment. Fig. 3 corresponds to a cross-sectional view taken along line III-III in Fig. 2.

[0025] The semiconductor device 1 according to the first embodiment mainly includes a heat sink 2, a case 9, a P terminal 3, an N terminal 4, a first O terminal 5, and a second O terminal 6. The P terminal 3 is a power supply terminal on the positive electrode side, the N terminal 4 is a power supply terminal on the negative electrode side, and the first O terminal 5 and the second O terminal 6 are output terminals. The P terminal 3, the N terminal 4, the first O terminal 5, and the second O terminal 6 are assembled to the case 9. The case 9 further includes a first gate terminal 131, a first sense source terminal 132, a sense drain terminal 133, a second gate terminal 231, a second sense source terminal 232, a first thermistor terminal 331, and a second thermistor terminal 332.

[0026] In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane. For convenience, the Z1 direction is defined as the upward direction, and the Z2 direction is defined as the downward direction. In addition, in this disclosure, a planar view means viewing an object from the Z1 side. The X1-X2 direction is a direction along the long side of the rectangular heat sink 2 and case 9 in a planar view, the Y1-Y2 direction is a direction along the short side of the heat sink 2 and case 9, and the Z1-Z2 direction is a direction along the normal to the heat sink 2 and case 9.

[0027] The heat sink 2 is, for example, a rectangular plate-like body with a uniform thickness in a plan view. The heat sink 2 has a first main surface 2A and a second main surface 2B opposite to the first main surface 2A. The material of the heat sink 2 is a metal with high thermal conductivity, such as copper (Cu), a copper alloy, or aluminum (Al). The heat sink 2 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.

[0028] The case 9 is formed, for example, in a frame shape in a plan view, and the outer shape of the case 9 is the same as the outer shape of the heat sink 2. The material of the case 9 is an insulating material such as resin. The case 9 has a pair of side walls 91 and 92 facing each other, and a pair of end walls 93 and 94 connecting both ends of the side walls 91 and 92. The side walls 91 and 92 are arranged parallel to the ZX plane, and the end walls 93 and 94 are arranged parallel to the YZ plane. The side wall 92 is arranged on the Y2 side of the side wall 91, and the end wall 94 is arranged on the X2 side of the end wall 93. The case 9 has a terminal block 95 protruding from the end wall 93 in the X1 direction, and a terminal block 96 protruding from the end wall 94 in the X2 direction.

[0029] The P terminal 3 and the N terminal 4 are arranged on the upper surface (surface on the Z1 side) of the terminal block 95, and the first O terminal 5 and the second O terminal 6 are arranged on the upper surface (surface on the Z1 side) of the terminal block 96. For example, the N terminal 4 is arranged on the Y2 side of the P terminal 3, and the second O terminal 6 is arranged on the Y2 side of the first O terminal 5. The P terminal 3, the N terminal 4, the first O terminal 5, and the second O terminal 6 are made of metal plates. One end of each of the P terminal 3 and the N terminal 4 is exposed on the X2 side of the end wall portion 93, and the other end of each is drawn out to the upper surface of the terminal block 95. One end of each of the first O terminal 5 and the second O terminal 6 is exposed on the X1 side of the end wall portion 94, and the other end of each is drawn out to the upper surface of the terminal block 96.

[0030] The first gate terminal 131, the first sense source terminal 132, the sense drain terminal 133, the first thermistor terminal 331, and the second thermistor terminal 332 are attached to the side wall portion 91. One end of each of the first gate terminal 131, the first sense source terminal 132, the sense drain terminal 133, the first thermistor terminal 331, and the second thermistor terminal 332 is exposed on the Y2 side of the side wall portion 91, and the other end of each protrudes from the upper surface (surface on the Z1 side) of the side wall portion 91 to the outside (Z1 side) of the case 9. The sense drain terminal 133 is disposed near the end of the X2 side of the side wall portion 91. The first thermistor terminal 331 and the second thermistor terminal 332 are disposed near the end of the X1 side of the side wall portion 91. For example, the second thermistor terminal 332 is disposed on the X1 side of the first thermistor terminal 331. The first gate terminal 131 and the first sense source terminal 132 are disposed near the center in the X1-X2 direction of the side wall portion 91 and on the X2 side of the center in the X1-X2 direction. For example, the first sense source terminal 132 is disposed on the X2 side of the first gate terminal 131.

[0031] A second gate terminal 231 and a second sense source terminal 232 are attached to the side wall portion 92. One end of each of the second gate terminal 231 and the second sense source terminal 232 is exposed on the Y1 side of the side wall portion 92, and the other end of each protrudes from the upper surface (surface on the Z1 side) of the side wall portion 92 to the outside (Z1 side) of the case 9. The second gate terminal 231 and the second sense source terminal 232 are disposed near the center of the side wall portion 92 in the X1-X2 direction and on the X1 side of the center in the X1-X2 direction. For example, the second sense source terminal 232 is disposed on the X1 side of the second gate terminal 231.

[0032] A first insulating substrate 10 and a second insulating substrate 20 are disposed on the Z1 side of the heat sink 2. That is, the first insulating substrate 10 and the second insulating substrate 20 are disposed on the first main surface 2A of the heat sink 2. For example, the second insulating substrate 20 is disposed on the X1 side of the first insulating substrate 10.

[0033] The first insulating substrate 10 has conductive layers 11, 12, 13, 14, and 18 on the Z1 side surface, and a conductive layer 19 on the Z2 side surface. The conductive layer 19 is joined to the heat sink 2 by a bonding material 7 such as solder. A plurality of, for example, four, first transistors 110 are mounted on the conductive layer 13. The four first transistors 110 are lined up in the X1-X2 direction. The four first transistors 110 constitute a first transistor group 110A. A plurality of, for example, eight, second diodes 220 are mounted on the conductive layer 12. The eight second diodes 220 are lined up in two rows of four in the X1-X2 direction. The eight second diodes 220 constitute a second diode group 220A.

[0034] The four first transistors 110 are arranged adjacent to each other in a first transistor aggregated region 110R having a rectangular shape in a plan view. That is, the four first transistors 110 are aggregated in the first transistor aggregated region 110R. The eight second diodes 220 are arranged adjacent to each other in a second diode aggregated region 220R having a rectangular shape in a plan view. That is, the eight second diodes 220 are aggregated in the second diode aggregated region 220R. The first transistor aggregated region 110R is an example of a first region. The X1-X2 direction is an example of a first direction.

[0035] The second insulating substrate 20 has conductive layers 21, 22, 23, 24, 25, 26, 27, and 28 on the Z1 side surface, and a conductive layer 29 on the Z2 side surface. The conductive layer 29 is joined to the heat sink 2 by a bonding material 8 such as solder. A plurality of, for example, four second transistors 210 are mounted on the conductive layer 23. The four second transistors 210 are arranged in the X1-X2 direction. A second transistor group 210A is composed of the four second transistors 210. A plurality of, for example, eight first diodes 120 are mounted on the conductive layer 25. The eight first diodes 120 are arranged in two rows of four in the X1-X2 direction. A first diode group 120A is composed of the eight first diodes 120.

[0036] The four second transistors 210 are arranged adjacent to each other in a rectangular second transistor aggregate region 210R in a plan view. That is, the four second transistors 210 are aggregated in the second transistor aggregate region 210R. The eight first diodes 120 are arranged adjacent to each other in a rectangular first diode aggregate region 120R in a plan view. That is, the eight first diodes 120 are aggregated in the first diode aggregate region 120R. The second transistor aggregate region 210R is another example of a first region.

[0037] In a plan view, the first diode aggregate region 120R is spaced apart from the first transistor aggregate region 110R, and the first transistor aggregate region 110R and the first diode aggregate region 120R do not have an overlapping region. A first diode 120 is not arranged between adjacent first transistors 110. In a plan view, the second transistor aggregate region 210R is spaced apart from the second diode aggregate region 220R, and the second transistor aggregate region 210R and the second diode aggregate region 220R do not have an overlapping region. A second diode 220 is not arranged between adjacent second transistors 210.

[0038] The combination of the conductive layer 12, the conductive layer 24, the wire 52, and the wires 74 and 75 is an example of a combination of a first conductive pattern, a second conductive pattern, a first connecting member, and a second connecting member. The combination of the conductive layer 22, the conductive layer 14, the wire 72, and the wires 54 and 55 is another example of a combination of a first conductive pattern, a second conductive pattern, a first connecting member, and a second connecting member.

[0039] Here, the first transistor 110, the first diode 120, the second transistor 210, and the second diode 220 will be described. Fig. 4 is a cross-sectional view showing the first transistor. Fig. 5 is a cross-sectional view showing the first diode. Fig. 6 is a cross-sectional view showing the second transistor. Fig. 7 is a cross-sectional view showing the second diode.

[0040] 4, the first transistor 110 has a first gate electrode 111, a first source electrode 112, and a first drain electrode 113. The first gate electrode 111 and the first source electrode 112 are disposed on a main surface of the first transistor 110 on the Z1 side, and the first drain electrode 113 is disposed on a main surface of the first transistor 110 on the Z2 side. The first drain electrode 113 is bonded to the conductive layer 13 by a bonding material (not shown) such as solder. The first source electrode 112 is an example of a first electrode.

[0041] 5, the first diode 120 has a first anode electrode 121 and a first cathode electrode 122. The first anode electrode 121 is disposed on a main surface on the Z1 side of the first diode 120, and the first cathode electrode 122 is disposed on a main surface on the Z2 side of the first diode 120. The first cathode electrode 122 is joined to the conductive layer 25 by a joining material (not shown) such as solder.

[0042] 6, the second transistor 210 has a second gate electrode 211, a second source electrode 212, and a second drain electrode 213. The second gate electrode 211 and the second source electrode 212 are disposed on a main surface of the second transistor 210 on the Z1 side, and the second drain electrode 213 is disposed on a main surface of the second transistor 210 on the Z2 side. The second drain electrode 213 is bonded to the conductive layer 23 by a bonding material (not shown) such as solder. The second source electrode 212 is another example of a first electrode.

[0043] 7, the second diode 220 has a second anode electrode 221 and a second cathode electrode 222. The second anode electrode 221 is disposed on a main surface on the Z1 side of the second diode 220, and the second cathode electrode 222 is disposed on a main surface on the Z2 side of the second diode 220. The second cathode electrode 222 is bonded to the conductive layer 12 by a bonding material (not shown) such as solder.

[0044] The semiconductor device 1 has a plurality of wires 31, a plurality of wires 32, a plurality of wires 41, and a plurality of wires 42. The wires 31 connect the conductive layer 13 provided on the first insulating substrate 10 and the conductive layer 25 provided on the second insulating substrate 20. The wires 32 connect the conductive layer 12 provided on the first insulating substrate 10 and the conductive layer 24 provided on the second insulating substrate 20. The wires 41 connect the conductive layer 12 provided on the first insulating substrate 10 and the conductive layer 23 provided on the second insulating substrate 20. The wires 42 connect the conductive layer 14 provided on the first insulating substrate 10 and the conductive layer 22 provided on the second insulating substrate 20.

[0045] The semiconductor device 1 has a plurality of wires 51, a plurality of wires 52, a plurality of wires 53, a plurality of wires 54, and a plurality of wires 55. The wires 51 connect the first gate electrodes 111 provided on the four first transistors 110 to the conductive layer 11 provided on the first insulating substrate 10. The wires 52 connect the first source electrodes 112 provided on the four first transistors 110 to the conductive layer 12 provided on the first insulating substrate 10. The wires 53 connect the first sense source electrodes (not shown) provided on the four first transistors 110 to the conductive layer 18 provided on the first insulating substrate 10. The wires 54 connect the second anode electrodes 221 provided on the four second diodes 220 arranged on the Y1 side among the eight second diodes 220 to the conductive layer 14 provided on the first insulating substrate 10. The wire 55 connects the second anode electrodes 221 provided on the four second diodes 220 arranged on the Y1 side among the eight second diodes 220 to the second anode electrodes 221 provided on the four second diodes 220 arranged on the Y2 side.

[0046] The semiconductor device 1 has a wire 61, a plurality of wires 62, a plurality of wires 63, a wire 64, and a wire 65. The wire 61 connects the conductive layer 11 provided on the first insulating substrate 10 to the first gate terminal 131. The wire 62 connects the conductive layer 12 provided on the first insulating substrate 10 to the first O terminal 5. The wire 63 connects the conductive layer 12 provided on the first insulating substrate 10 to the second O terminal 6. The wire 64 connects the conductive layer 13 provided on the first insulating substrate 10 to the sense drain terminal 133. The wire 65 connects the conductive layer 18 provided on the first insulating substrate 10 to the first sense source terminal 132.

[0047] The semiconductor device 1 has a plurality of wires 71, a plurality of wires 72, a plurality of wires 73, a plurality of wires 74, and a plurality of wires 75. The wires 71 connect the second gate electrodes 211 provided on the four second transistors 210 to the conductive layer 21 provided on the second insulating substrate 20. The wires 72 connect the second source electrodes 212 provided on the four second transistors 210 to the conductive layer 22 provided on the second insulating substrate 20. The wires 73 connect the second sense source electrodes (not shown) provided on the four second transistors 210 to the conductive layer 28 provided on the second insulating substrate 20. The wires 74 connect the first anode electrodes 121 provided on the four first diodes 120 arranged on the Y2 side among the eight first diodes 120 to the conductive layer 24 provided on the second insulating substrate 20. The wire 75 connects the first anode electrodes 121 provided on the four first diodes 120 arranged on the Y2 side among the eight first diodes 120 to the first anode electrodes 121 provided on the four first diodes 120 arranged on the Y1 side.

[0048] The semiconductor device 1 includes a wire 81, a plurality of wires 82, a plurality of wires 83, a wire 85, a wire 86, and a wire 87. The wire 81 connects the conductive layer 21 provided on the second insulating substrate 20 to the second gate terminal 231. The wire 82 connects the conductive layer 22 provided on the second insulating substrate 20 to the N terminal 4. The wire 83 connects the conductive layer 25 provided on the second insulating substrate 20 to the P terminal 3. The wire 85 connects the conductive layer 28 provided on the second insulating substrate 20 to the second sense source terminal 232. The wire 86 connects the conductive layer 26 provided on the second insulating substrate 20 to the first thermistor terminal 331. The wire 87 connects the conductive layer 27 provided on the second insulating substrate 20 to the second thermistor terminal 332. The semiconductor device 1 includes a thermistor 330 connected to the conductive layer 26 and the conductive layer 27 .

[0049] Here, a description will be given of the circuit configuration of the semiconductor device 1 according to the first embodiment. Fig. 8 is a circuit diagram showing the semiconductor device according to the first embodiment.

[0050] A first cathode electrode 122 of the first diode 120 is connected to the P terminal 3 via a wire 83 and a conductive layer 25. A first drain electrode 113 of the first transistor 110 is connected to the P terminal 3 via a wire 83, a conductive layer 25, a wire 31, and a conductive layer 13. The conductive layer 12 is connected to the first O terminal 5 via a wire 62, and to the second O terminal 6 via a wire 63. A first source electrode 112 of the first transistor 110 is connected to the conductive layer 12 via a wire 52. A first anode electrode 121 of the first diode is connected to the conductive layer 12 via a wire 32, a conductive layer 24, and wires 74 and 75.

[0051] A first gate electrode 111 of the first transistor 110 is connected to a first gate terminal 131 via a wire 61, a conductive layer 11, and a wire 51. A first sense source electrode of the first transistor 110 is connected to a first sense source terminal 132 via a wire 65, a conductive layer 18, and a wire 53. A first drain electrode 113 of the first transistor 110 is connected to a sense drain terminal 133 via a wire 64 and a conductive layer 13. The first gate electrode 111 is an example of a control electrode, and the first gate terminal 131 is an example of a control terminal.

[0052] A second source electrode 212 of the second transistor 210 is connected to the N terminal 4 via a wire 82, a conductive layer 22, and a wire 72. A second anode electrode 221 of the second diode 220 is connected to the N terminal 4 via a wire 82, a conductive layer 22, a wire 42, and wires 54 and 55. diode 2 2 A second cathode electrode 222 of the second transistor 210 is connected to the conductive layer 12. A second drain electrode 213 of the second transistor 210 is connected to the conductive layer 12 via a wire 41 and a conductive layer .

[0053] A second gate electrode 211 of the second transistor 210 is connected to the second gate terminal 231 via a wire 81, a conductive layer 21, and a wire 71. A second sense source electrode of the second transistor 210 is connected to the second sense source terminal 232 via a wire 85, a conductive layer 28, and a wire 73. One electrode of the thermistor 330 is connected to the first thermistor terminal 331 via a wire 86 and a conductive layer 26. The other electrode of the thermistor 330 is connected to the second thermistor terminal 332 via a wire 87 and a conductive layer 27. The second gate electrode 211 is another example of a control electrode, and the second gate terminal 231 is another example of a control terminal.

[0054] As shown in FIG. 8, the first drain electrode 113 of the first transistor 110 and the first cathode electrode 122 of the first diode 120 are commonly connected to the P terminal 3, and the first source electrode 112 and the first anode electrode 121 are commonly connected to the first O terminal 5 and the second O terminal 6. That is, the first transistor 110 and the first diode 120 are connected in parallel between the P terminal 3 and the first O terminal 5 and the second O terminal 6. In addition, the second drain electrode 213 of the second transistor 210 and the second cathode electrode 222 of the second diode 220 are commonly connected to the first O terminal 5 and the second O terminal 6, and the second source electrode 212 and the second anode electrode 221 are commonly connected to the N terminal 4. That is, the second transistor 210 and the second diode 220 are connected in parallel between the N terminal 4 and the first O terminal 5 and the second O terminal 6. The upper arm 100 includes a first transistor 110 (first transistor group 110A) and a first diode 120 (first diode group 120A). The lower arm 200 includes a second transistor 210 (second transistor group 210A) and a second diode 220 (second diode group 220A). The upper arm 100 and the lower arm 200 are connected in series between the P terminal 3 and the N terminal 4. The upper arm 100 is an example of a first arm, and the lower arm 200 is an example of a second arm.

[0055] The multiple first transistors 110 included in the upper arm 100 may be provided only on the first insulating substrate 10, and the multiple first diodes 120 included in the upper arm 100 may be provided only on the second insulating substrate 20. Also, the multiple second transistors 210 included in the lower arm 200 may be provided only on the second insulating substrate 20, and the multiple second diodes 220 included in the lower arm 200 may be provided only on the first insulating substrate 10.

[0056] Next, a description will be given of the operation of the semiconductor device 1 according to the first embodiment. Figures 9 to 12 are schematic diagrams showing the operation of the semiconductor device according to the first embodiment.

[0057] 9 shows a path of a current I1 flowing from the P terminal 3 to the first O terminal 5 and the second O terminal 6. As shown in FIG. 9, the current I1 flows from the P terminal 3 to the first O terminal 5 and the second O terminal 6 via the wire 83, the conductive layer 25, the wire 31, the conductive layer 13, the first transistor group 110A, the wire 52, the conductive layer 12, and the wires 62 and 63.

[0058] 10 shows a path of a current I2 flowing from the first O terminal 5 and the second O terminal 6 to the P terminal 3. As shown in FIG 10, the current I2 flows from the first O terminal 5 and the second O terminal 6 to the P terminal 3 via the wires 62 and 63, the conductive layer 12, the wire 32, the conductive layer 24, the wires 74 and 75, the first diode group 120A, the conductive layer 25, and the wire 83.

[0059] In this way, the current I1 flowing from the P terminal 3 to the first O terminal 5 and the second O terminal 6 flows through the wire 31 but does not flow through the wire 32. On the other hand, the current I2 flowing from the first O terminal 5 and the second O terminal 6 to the P terminal 3 flows through the wire 32 but does not flow through the wire 31.

[0060] 11 shows a path of a current I3 flowing from the N terminal 4 to the first O terminal 5 and the second O terminal 6. As shown in FIG. 11, the current I3 flows from the N terminal 4 to the first O terminal 5 and the second O terminal 6 via the wire 82, the conductive layer 22, the wire 72, the second transistor group 210A, the conductive layer 23, the wire 41, the conductive layer 12, and the wires 62 and 63.

[0061] 12 shows a path of a current I4 flowing from the first O terminal 5 and the second O terminal 6 to the N terminal 4. As shown in FIG 12, the current I4 flows from the first O terminal 5 and the second O terminal 6 to the N terminal 4 via the wires 62 and 63, the conductive layer 12, the second diode group 220A, the wires 54 and 55, the conductive layer 14, the wire 42, the conductive layer 22, and the wire 82.

[0062] In this way, the current I3 flowing from the N terminal 4 to the first O terminal 5 and the second O terminal 6 flows through the wire 41 but does not flow through the wire 42. On the other hand, the current I4 flowing from the first O terminal 5 and the second O terminal 6 to the N terminal 4 flows through the wire 42 but does not flow through the wire 41.

[0063] In the semiconductor device 1 according to the first embodiment, the upper arm 100 includes a first transistor 110 and a first diode 120, the first transistor 110 is provided on the first insulating substrate 10, and the first diode 120 is provided on the second insulating substrate 20. Therefore, the wires 31 and 32 through which the current I1 flowing from the P terminal 3 to the first O terminal 5 and the second O terminal 6 and the current I2 flowing from the first O terminal 5 and the second O terminal 6 to the P terminal 3 pass are different. Therefore, the amount of heat generated in the wires 31 and 32 can be reduced compared to the case where the currents flowing between the first insulating substrate 10 and the second insulating substrate 20 pass through the same connecting member.

[0064] Similarly, the lower arm 200 includes a second transistor 210 and a second diode 220, the second transistor 210 is provided on the second insulating substrate 20, and the second diode 220 is provided on the first insulating substrate 10. Therefore, the wires 41 and 42 through which the current I3 flowing from the N terminal 4 to the first O terminal 5 and the second O terminal 6 and the current I4 flowing from the first O terminal 5 and the second O terminal 6 to the N terminal 4 pass are different. Therefore, the amount of heat generated in the wires 41 and 42 can be reduced compared to the case where the currents flowing between the first insulating substrate 10 and the second insulating substrate 20 pass through the same connecting member.

[0065] By reducing the amount of heat generated in this manner, it is possible to suppress the risk of the connection members and wires generating excessive amounts of heat, and to reduce the risk of the wires melting.

[0066] Since wires 31, 32, 41, and 42 are used for connection between first insulating substrate 10 and second insulating substrate 20, first insulating substrate 10 and second insulating substrate 20 can be easily connected. That is, conductive layer 13 can be easily connected to conductive layer 25, conductive layer 12 can be easily connected to conductive layer 24, conductive layer 14 can be easily connected to conductive layer 22, and conductive layer 12 can be easily connected to conductive layer 23. Metal plates such as bus bars may be used instead of wires 31, 32, 41, and 42. In this case, a larger current can be easily passed.

[0067] Since the wire 52 is used to connect the first source electrode 112 and the conductive layer 12, and the wire 74 is used to connect the first anode electrode 121 and the conductive layer 24, it is easy to connect the first source electrode 112 and the conductive layer 12, and it is easy to connect the first anode electrode 121 and the conductive layer 24. Furthermore, since the wire 72 is used to connect the second source electrode 212 and the conductive layer 22, and the wire 54 is used to connect the second anode electrode 221 and the conductive layer 14, it is easy to connect the second source electrode 212 and the conductive layer 22, and it is easy to connect the second anode electrode 221 and the conductive layer 14.

[0068] A plurality of first transistors 110 are arranged adjacent to each other. The first source electrode 112 and the conductive layer 12 are directly connected by the wire 52, the first anode electrode 121 and the conductive layer 24 are connected by the wires 74 and 75, and the conductive layer 12 and the conductive layer 24 are electrically connected by the wire 31. This reduces the inductance of the individual power loops of the plurality of first transistors 110, and suppresses the variation in the inductance of the power loops among the plurality of first transistors 110. This allows the plurality of first transistors 110 to operate more stably.

[0069] A plurality of second transistors 210 are arranged adjacent to each other. The second source electrode 212 and the conductive layer 22 are directly connected by the wire 72, the second anode electrode 221 and the conductive layer 14 are connected by the wires 54 and 55, and the conductive layer 22 and the conductive layer 14 are electrically connected by the wire 42. This reduces the inductance of the individual power loops of the plurality of second transistors 210, and suppresses the variation in the inductance of the power loops among the plurality of second transistors 210. This allows the plurality of second transistors 210 to operate more stably.

[0070] In plan view, the first transistor 110 is disposed between the first gate terminal 131 and the second diode 220. That is, the first transistor 110 of the upper arm 100 is disposed closer to the first gate terminal 131 than the second diode 220 of the lower arm 200. In addition, a plurality of first transistors 110 can be disposed in the vicinity of the conductive layer 11. Therefore, it is easy to reduce the inductance of the gate loop of the first transistor 110. In addition, in plan view, the second transistor 210 is disposed between the second gate terminal 231 and the first diode 120. That is, the second transistor 210 of the lower arm 200 is disposed closer to the second gate terminal 231 than the first diode 120 of the upper arm 100. In addition, a plurality of second transistors 210 can be disposed in the vicinity of the conductive layer 21. Therefore, it is easy to reduce the inductance of the gate loop of the second transistor 210.

[0071] Furthermore, the first gate electrodes 111 of the multiple first transistors 110 are connected to the first gate terminal 131, and the multiple first transistors 110 are arranged between the first gate terminal 131 and the second diode 220. This makes it easy to reduce the difference in gate loop inductance between the multiple first transistors 110. Also, the second gate electrodes 211 of the multiple second transistors 210 are connected to the second gate terminal 231, and the multiple second transistors 210 are arranged between the second gate terminal 231 and the first diode 120. This makes it easy to reduce the difference in gate loop inductance between the multiple second transistors 210.

[0072] The first transistor 110 and the second transistor 210 may be field effect transistors such as metal-oxide-semiconductor (MOS) field effect transistors made of silicon carbide. The first diode 120 and the second diode 220 may be Schottky barrier diodes made of silicon carbide. By using silicon carbide, an excellent breakdown voltage can be obtained.

[0073] 13, the second main surface 2B of the heat sink 2 is preferably curved in a convex shape. This is because it is easy to achieve good heat transfer efficiency by closely adhering the heat sink 2 to a cooler or the like using a TIM or the like.

[0074] Second embodiment Next, a second embodiment will be described below. Fig. 14 is a schematic diagram showing the configurations of a first insulating substrate and a second insulating substrate in a semiconductor device according to the second embodiment.

[0075] 14, in the semiconductor device according to the second embodiment, the first insulating substrate 10 has a third insulating substrate 10A and a fourth insulating substrate 10B, and the second insulating substrate 20 has a fifth insulating substrate 20A and a sixth insulating substrate 20B. The fourth insulating substrate 10B is disposed on the X1 side of the third insulating substrate 10A, and the sixth insulating substrate 20B is disposed on the X2 side of the fifth insulating substrate 20A.

[0076] The third insulating substrate 10A has conductive layers 11A, 12A, 13A, 14A, and 18A on the Z1 side surface, and a conductive layer (not shown) on the Z2 side surface. The conductive layer provided on the Z2 side surface is joined to the heat sink 2 by a bonding material 7 such as solder, similar to the conductive layer 19. A plurality of first transistors 110, for example, two, are mounted on the conductive layer 13A. The two first transistors 110 are lined up in the X1-X2 direction. A plurality of second diodes 220, for example, four, are mounted on the conductive layer 12A. The four second diodes 220 are lined up in two rows, two by two, in the X1-X2 direction.

[0077] The fourth insulating substrate 10B has conductive layers 11B, 12B, 12C, 13B, 14B, and 18B on the Z1 side surface, and a conductive layer (not shown) on the Z2 side surface. The conductive layer provided on the Z2 side surface is joined to the heat sink 2 by a bonding material 7 such as solder, similar to the conductive layer 19. A plurality of first transistors 110, for example, two, are mounted on the conductive layer 13B. The two first transistors 110 are lined up in the X1-X2 direction. A plurality of second diodes 220, for example, four, are mounted on the conductive layer 12C. The four second diodes 220 are lined up in two rows, two by two, in the X1-X2 direction.

[0078] A wire 411, a wire 412, a wire 413, a wire 414, a wire 415, and a wire 418 are provided. The wire 411 connects the conductive layer 11A to the conductive layer 11B. The wire 412 connects the conductive layer 12A to the conductive layer 12B. The wire 413 connects the conductive layer 13A to the conductive layer 13B. The wire 414 connects the conductive layer 14A to the conductive layer 14B. The wire 415 connects the conductive layer 12A to the conductive layer 12C. The wire 418 connects the conductive layer 18A to the conductive layer 18B.

[0079] Conductive layers 11A and 11B are part of conductive layer 11. Conductive layers 12A, 12B, and 12C are part of conductive layer 12. Conductive layers 13A and 13B are part of conductive layer 13. Conductive layers 14A and 14B are part of conductive layer 14. Conductive layers 18A and 18B are part of conductive layer 18.

[0080] The fifth insulating substrate 20A has conductive layers 21A, 22A, 23A, 24A, 25A, and 28A on the Z1 side surface, and a conductive layer (not shown) on the Z2 side surface. The conductive layer provided on the Z2 side surface is joined to the heat sink 2 by a bonding material 8 such as solder, similar to the conductive layer 29. A plurality of second transistors 210, for example, two, are mounted on the conductive layer 23A. The two second transistors 210 are lined up in the X1-X2 direction. A plurality of first diodes 120, for example, four, are mounted on the conductive layer 25A. The four first diodes 120 are lined up in two rows, two by two, in the X1-X2 direction.

[0081] The sixth insulating substrate 20B has conductive layers 21B, 22B, 23B, 24B, 25B, and 28B on the Z1 side surface, and a conductive layer (not shown) on the Z2 side surface. The conductive layer provided on the Z2 side surface is joined to the heat sink 2 by a bonding material 8 such as solder, similar to the conductive layer 29. A plurality of second transistors 210, for example, two, are mounted on the conductive layer 23B. The two second transistors 210 are lined up in the X1-X2 direction. A plurality of first diodes 120, for example, four, are mounted on the conductive layer 25B. The four first diodes 120 are lined up in two rows, two by two, in the X1-X2 direction.

[0082] A wire 421, a wire 422, a wire 423, a wire 424, a wire 425, and a wire 428 are provided. The wire 421 connects the conductive layer 21A to the conductive layer 21B. The wire 422 connects the conductive layer 22A to the conductive layer 22B. The wire 423 connects the conductive layer 23A to the conductive layer 23B. The wire 424 connects the conductive layer 24A to the conductive layer 24B. The wire 425 connects the conductive layer 25A to the conductive layer 25B. The wire 428 connects the conductive layer 28A to the conductive layer 28B.

[0083] Conductive layers 21A and 21B are part of conductive layer 21. Conductive layers 22A and 22B are part of conductive layer 22. Conductive layers 23A and 23B are part of conductive layer 23. Conductive layers 24A and 24B are part of conductive layer 24. Conductive layers 25A and 25B are part of conductive layer 25. Conductive layers 18A and 18B are part of conductive layer 18.

[0084] The other configuration is similar to that of the first embodiment.

[0085] The second embodiment also provides the same effects as the first embodiment. In the second embodiment, since the first insulating substrate 10 includes the third insulating substrate 10A and the fourth insulating substrate 10B, it is easier to bring the third insulating substrate 10A and the fourth insulating substrate 10B into closer contact with the first main surface 2A of the heat sink 2. Similarly, since the second insulating substrate 20 includes the fifth insulating substrate 20A and the sixth insulating substrate 20B, it is easier to bring the fifth insulating substrate 20A and the sixth insulating substrate 20B into closer contact with the first main surface 2A of the heat sink 2.

[0086] Third embodiment Next, a third embodiment will be described. Fig. 15 is a top view showing a semiconductor device according to the third embodiment. However, in Fig. 15, the case is seen through, as in Fig. 2. Fig. 16 is a cross-sectional view showing the relationship between the heat sink and the insulating substrate in the semiconductor device according to the third embodiment. Fig. 16 corresponds to a cross-sectional view taken along line XVI-XVI in Fig. 15.

[0087] 15 and 16, in the semiconductor device according to the third embodiment, an insulating substrate 510 is disposed on the Z1 side of the heat sink 2 in place of the first insulating substrate 10 and the second insulating substrate 20. That is, the insulating substrate 510 is disposed on the first main surface 2A of the heat sink 2.

[0088] The insulating substrate 510 has conductive layers 11, 512, 513, 514, 18, 21, 26, 27, and 28 on its Z1 side, and a conductive layer 519 on its Z2 side. The conductive layer 519 is joined to the heat sink 2 by a joining material 507 such as solder.

[0089] The conductive layer 512 includes a region 12X corresponding to the conductive layer 12 in the first embodiment, a region 23X corresponding to the conductive layer 23, a region 24X corresponding to the conductive layer 24, a region 512X connecting the region 12X and the region 23X, and a region 512Y connecting the region 12X and the region 24X. A plurality of second diodes 220, for example, eight, are mounted on the conductive layer 512, and a plurality of second transistors 210, for example, four, are mounted on the region 23X.

[0090] The conductive layer 513 includes a region 13X corresponding to the conductive layer 13 in the first embodiment, a region 25X corresponding to the conductive layer 25, and a region 513X connecting the region 13X and the region 25X. A plurality of, for example, four first transistors 110 are mounted on the region 13X, and a plurality of, for example, eight first diodes 120 are mounted on the region 25X.

[0091] The conductive layer 514 includes a region 14X corresponding to the conductive layer 14 in the first embodiment, a region 22X corresponding to the conductive layer 22, and a region 514X connecting the region 14X and the region 22X.

[0092] The semiconductor device according to the third embodiment does not have the wires 31, 32, 41 and .

[0093] The combination of the conductive layer 512, the wire 52, and the wires 74 and 75 is an example of a combination of the third conductive pattern, the first connecting member, and the second connecting member. The combination of the conductive layer 514, the wire 72, and the wires 54 and 55 is another example of a combination of the third conductive pattern, the first connecting member, and the second connecting member.

[0094] The other configuration is similar to that of the first embodiment.

[0095] The third embodiment also provides the same effects as the first embodiment.

[0096] For example, a plurality of first transistors 110 are arranged adjacent to each other. The first source electrode 112 and the conductive layer 512 are directly connected by the wire 52, and the first anode electrode 121 and the conductive layer 512 are connected by the wires 74 and 75. This reduces the inductance of each power loop of the plurality of first transistors 110, and suppresses the variation in inductance of the power loop among the plurality of first transistors 110. This allows the plurality of first transistors 110 to operate more stably.

[0097] Moreover, the multiple second transistors 210 are arranged adjacent to each other. The second source electrode 212 and the conductive layer 514 are directly connected by the wire 72, and the second anode electrode 221 and the conductive layer 514 are connected by the wires 54 and 55. This reduces the inductance of the individual power loops of the multiple second transistors 210, and suppresses the variation in inductance of the power loops among the multiple second transistors 210. This allows the multiple second transistors 210 to operate more stably.

[0098] In addition, the insulating substrate 510 does not necessarily have to be used in the third embodiment. Fig. 17 is a cross-sectional view showing the relationship between the heat sink and the conductive layer in a modified example of the third embodiment. Fig. 17 corresponds to the cross-sectional view taken along line XVI-XVI in Fig. 15. For example, as shown in Fig. 17, an insulating layer 2X of resin or the like may be provided on the heat sink 2, and conductive layers 11, 512, 513, 514, 18, 21, 26, 27, and 28 may be provided on the insulating layer 2X.

[0099] In the present disclosure, the transistor is not limited to a MOS type FET, and the transistor may be an insulated gate bipolar transistor (IGBT). When the transistor is an IGBT, the emitter electrode is an example of the first electrode.

[0100] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0101] 1: Semiconductor device 2: Heat sink 2A: 1st main surface 2B: 2nd main surface 3:P terminal 4:N terminal 5: 1st O terminal 6: 2nd O terminal 7, 8: Bonding material 9: Case 10: First insulating substrate 10A: Third insulating substrate 10B: Fourth insulating substrate 11, 11A, 11B, 12A, 12B, 12C, 13, 13A, 13B, 14A, 14B, 18, 18A, 18B, 19: Conductive layer 12: Conductive layer (first conductive pattern) 12X, 13X, 14X: area 14: Conductive layer (second conductive pattern) 20: Second insulating substrate 20A: 5th insulating substrate 20B: Sixth insulating substrate 21, 21A, 21B, 22A, 22B, 23, 23A, 23B, 24A, 24B, 25, 25A, 25B, 26, 27, 28, 28A, 28B, 29: Conductive layer 22X, 23X, 24X, 25X: area 22: Conductive layer (first conductive pattern) 24: Conductive layer (second conductive pattern) 31, 32: Wire 41, 42: Wire 51, 53: Wire 52: Wire (first connecting member) 54, 55: Wire (second connecting member) 61, 62, 63, 64, 65: Wire 71, 73: Wire 72: Wire (first connecting member) 74, 75: Wire (second connecting member) 81, 82, 83, 85, 86, 87: Wire 91, 92: Side wall 93, 94: End wall 95, 96: Terminal block 100: Upper arm 110: First transistor 110A: First transistor group 110R: First transistor aggregation region 111: First gate electrode 112: first source electrode 113: first drain electrode 120: First diode 120A: First diode group 120R: First diode aggregation area 121: first anode electrode 122: first cathode electrode 131: First gate terminal 132: First sense source terminal 133: Sense drain terminal 200: Lower arm 210: second transistor 210A: Second transistor group 210R: Second transistor aggregation region 211: second gate electrode 212: second source electrode 213: second drain electrode 220: Second diode 220A: Second diode group 220R: Second diode aggregation region 221: second anode electrode 222: second cathode electrode 231: Second gate terminal 232: Second sense source terminal 330: Thermistor 331: First thermistor terminal 332: Second thermistor terminal 411, 412, 413, 414, 415, 418: Wire 421, 422, 423, 424, 425, 428: Wire 507: Bonding material 510: Insulating substrate 512: Conductive layer (third conductive pattern) 514: Conductive layer (third conductive pattern) 513, 519: Conductive layer 512X, 512Y, 513X, 514X: Area I1, I2, I3, I4: Current

Claims

1. a plurality of transistors electrically connected in parallel with each other, each transistor having a first electrode; a diode electrically connected in parallel to the plurality of transistors and having an anode electrode; A first conductive pattern; a second conductive pattern electrically connected to the first conductive pattern; a plurality of first connection members each directly connecting the first electrodes of the plurality of transistors to the first conductive pattern; a second connection member that connects the anode electrode and the second conductive pattern; a third conductive pattern on which the plurality of transistors are mounted and to which second electrodes of the plurality of transistors are joined; a fourth conductive pattern electrically connected to the third conductive pattern, the fourth conductive pattern having the diode mounted thereon and a cathode of the diode bonded thereto; having the first electrode is a source electrode or an emitter electrode, the plurality of transistors are arranged adjacent to one another, the first and second connection members extend parallel to each other in a first direction; A semiconductor device in which the directions of a current flowing through the first conductive pattern and a current flowing through the second conductive pattern are parallel to a second direction perpendicular to the first direction.

2. A semiconductor device as described in claim 1, wherein the second conductive pattern is spaced apart from the first conductive pattern along the second direction.

3. A third conductive pattern on which the plurality of transistors are mounted and to which second electrodes of the plurality of transistors are joined; a fourth conductive pattern electrically connected to the third conductive pattern, the fourth conductive pattern having the diode mounted thereon and a cathode of the diode bonded thereto; having 3. The semiconductor device according to claim 1, wherein the fourth conductive pattern is spaced apart from the second conductive pattern in the second direction.

4. An external terminal electrically connected to the first conductive pattern, 4. The semiconductor device according to claim 1, wherein the first conductive pattern is connected between the second conductive pattern and the external terminal.

5. A semiconductor device described in any one of claims 1 to 4, wherein the second conductive pattern is spaced apart from the first conductive pattern along the second direction.

6. A semiconductor device described in any one of claims 1 to 5, having a current path through which current flows continuously through the first conductive pattern and the second conductive pattern.

7. a plurality of transistors electrically connected in parallel with each other, each transistor having a first electrode; a diode electrically connected in parallel to the plurality of transistors and having an anode electrode; A fifth conductive pattern; a plurality of first connection members each directly connecting the first electrodes of the plurality of transistors to the fifth conductive pattern; a second connection member that connects the anode electrode and the fifth conductive pattern; having the first electrode is a source electrode or an emitter electrode, the plurality of transistors are arranged adjacent to one another, the first connection members and the second connection members extend parallel to each other in a first direction; a direction of a current flowing through the fifth conductive pattern is parallel to a second direction perpendicular to the first direction; The semiconductor device, in a plan view perpendicular to the first direction and the second direction, the first connection members do not overlap with each other.

8. A semiconductor device as described in claim 7, wherein the diode is spaced apart from the plurality of transistors along the second direction.

9. A semiconductor device as described in claim 7 or claim 8, having a sixth conductive pattern in which the plurality of transistors and the diode are implemented and to which second electrodes of the plurality of transistors and the cathode of the diode are joined.

10. A first external terminal electrically connected to the fifth conductive pattern, 10. The semiconductor device according to claim 7, wherein the first connection member is connected to the fifth conductive pattern between the second connection member and the first external terminal.

11. A first external terminal electrically connected to the fifth conductive pattern, 10. The semiconductor device according to claim 7, wherein the first connection member is connected to the fifth conductive pattern between a first region to which the first external terminal of the fifth conductive pattern is electrically connected and a second region to which the second connection member of the fifth conductive pattern is connected.

12. The semiconductor device according to claim 1 , wherein the plurality of transistors are concentrated in a rectangular first region.

13. The semiconductor device according to claim 1 , wherein the plurality of transistors are arranged side by side in the second direction.

14. The semiconductor device according to claim 1 , wherein the second connection member is independent of the plurality of first connection members.

15. 15. The semiconductor device according to claim 1, wherein the diode is not disposed between adjacent transistors among the plurality of transistors.

16. 16. The semiconductor device according to claim 1, wherein the transistor is a field effect transistor made of silicon carbide.

17. 17. The semiconductor device according to claim 1, wherein the diode is a Schottky barrier diode made of silicon carbide.

18. a case that accommodates the plurality of transistors and the diode; a control terminal connected to control electrodes of the plurality of transistors and attached to the case; having The case is A pair of side walls facing each other; A pair of end wall portions connecting both ends of the side wall portion; having 18. The semiconductor device according to claim 1, wherein the control terminal is provided on one of the side wall portion and the end wall portion that is located closest to the plurality of transistors.

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