Clock signal measurement device, clock signal measurement system, clock signal measurement method, and clock signal measurement program

Abstract

To heighten the accuracy of measuring a clock signal without using a high-frequency sampling clock signal.SOLUTION: A clock signal measurement device 50 is a device that operates in synchronism with a sampling clock signal 502, and comprises: a sampling unit 51 for generating a first clock signal 510 sampled from a clock signal 501 to be measured; a clock signal generation unit 52 for generating a second clock signal 520 having a frequency of a set value 550; a discrimination unit 53 for calculating a difference between the wavenumber of the first clock signal 510 and the wavenumber of the second clock signal 520 from a prescribed time of day; an integration unit 54 for calculating an integrated value of the differences for each prescribed measurement period; and an adjustment unit 55 for adjusting the set value 550 so that the absolute value of the integrated value becomes smaller, and outputting the adjusted set value 550 as a new set value 550 to the clock signal generation unit 52 and to the outside.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a clock signal measurement device, a clock signal measurement system, a clock signal measurement method, and a clock signal measurement program.

Background Art

[0002] For example, in a system where a plurality of devices operating in synchronization with a clock signal need to operate in high-precision synchronization with each other, or in a system for observing natural phenomena with high precision in terms of time, etc., technologies for improving the measurement accuracy of the frequency and phase of the clock signal are expected.

[0003] As a technology related to such a technology, Patent Document 1 discloses a clock frequency analysis device that measures a high-precision digital clock using a limited waveform memory capacity and an arithmetic device.

[0004] Also, Patent Document 2 discloses a frequency measurement circuit that measures the period or frequency of a clock signal to be measured with high precision.

[0005] Also, Patent Document 3 discloses a frequency comparator that immediately detects a change in the frequency of a clock signal to be measured while maintaining the resolution of the frequency comparison between a reference clock signal and the clock signal to be measured.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] When measuring the advance or delay of a clock within a device with respect to a clock signal serving as a time reference input from the outside, or when measuring the frequency of a clock signal input from the outside, if the external input signal is sampled (sampled) for measurement, the measurement accuracy is based on the period of the sampling clock signal as the minimum unit. Therefore, to improve the measurement accuracy, it is necessary to increase the frequency of the sampling clock signal.

[0008] And, in order to increase the frequency of the sampling clock signal, it is essential to use components that can operate at high speed and to design the substrate so that the transmission lines on the substrate can handle high-frequency sampling clock signals, which poses the problem of increased cost. Also, for example, components mounted in space equipment, etc., are required to have high radiation resistance, weight reduction, low power consumption, etc., so there are problems such as limited selection candidates for components that can operate at high speed as described above, and the fact that there are no components that can operate at high speed in the first place. That is, the problem is to improve the measurement accuracy of the clock signal without using a high-frequency sampling clock signal. The above-mentioned Patent Documents 1 to 3 do not particularly mention such problems.

[0009] The main object of the present invention is to provide a clock signal measuring device and the like that can achieve an improvement in the measurement accuracy of a clock signal without using a high-frequency sampling clock signal.

Means for Solving the Problems

[0010] A clock signal measurement device according to an aspect of the present invention is a device that operates in synchronization with a sampling clock signal, and includes a sampling unit that generates a first clock signal obtained by sampling a clock signal to be measured, a clock signal generation unit that generates a second clock signal having a set frequency, a discrimination unit that calculates a difference between the frequency of the first clock signal from a predetermined time and the frequency of the second clock signal, an integration unit that calculates an integrated value obtained by integrating the difference for each predetermined measurement period, and an adjustment unit that adjusts the set value so that the absolute value of the integrated value becomes smaller, outputs the adjusted set value as a new set value to the clock signal generation unit and to the outside.

[0011] In another aspect for achieving the above object, a clock signal measurement method according to an aspect of the present invention is an information processing device that operates in synchronization with a sampling clock signal, generates a first clock signal obtained by sampling a clock signal to be measured, generates a second clock signal having a set frequency, calculates a difference between the frequency of the first clock signal from a predetermined time and the frequency of the second clock signal, calculates an integrated value obtained by integrating the difference for each predetermined measurement period, adjusts the set value so that the absolute value of the integrated value becomes smaller, sets the adjusted set value as a new set value, and outputs the new set value to the outside.

[0012] Furthermore, in a further aspect for achieving the above object, a clock signal measurement program according to an aspect of the present invention causes a computer that operates in synchronization with a sampling clock signal to execute a sampling process for generating a first clock signal obtained by sampling a clock signal to be measured, a clock signal generation process for generating a second clock signal having a set frequency, a discrimination process for calculating a difference between the frequency of the first clock signal from a predetermined time and the frequency of the second clock signal, an integration process for calculating an integrated value obtained by integrating the difference for each predetermined measurement period, and an adjustment process for adjusting the set value so that the absolute value of the integrated value becomes smaller, outputting the adjusted set value as a new set value to the clock signal generation process and to the outside.

[0013] Furthermore, the present invention can also be realized by a computer-readable non-volatile recording medium storing such a clock signal measurement program (computer program).

Advantages of the Invention

[0014] According to the present invention, a clock signal measurement device or the like that realizes an improvement in the measurement accuracy of a clock signal without using a high-frequency sampling clock signal can be obtained.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Modes for Carrying Out the Invention

[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0017] <First Embodiment> FIG. 1 is a block diagram showing the configuration of a clock signal measurement device 10 according to a first embodiment of the present invention. The clock signal measurement device 10 is a device that operates in synchronization with a sampling clock signal 102 and measures the frequency and phase of a clock signal 101 to be measured (the clock signal to be measured). However, it is assumed that the clock signal 101 to be measured according to this embodiment is a rectangular wave (a digital signal representing "0" or "1").

[0018] The clock signal measurement device 10 includes a sampling unit 11, a measurement target clock counter 110, a clock signal generation unit 12, a replicated clock counter 120, a discrimination unit 13, a match count counter 130, an integration unit 14, an adjustment unit 15, a tracking determination unit 16, and a phase output unit 17. The sampling unit 11, the clock signal generation unit 12, the discrimination unit 13, the integration unit 14, the adjustment unit 15, the tracking determination unit 16, and the phase output unit 17 are examples of sampling means, clock signal generation means, discrimination means, integration means, adjustment means, tracking determination means, and phase output means, respectively.

[0019] The clock signal generation unit 12 generates a clock signal (an example of the second clock signal) whose frequency is set by a frequency setting value 150 described later, for example, by including a numerically controlled oscillator. The oscillator included in the clock signal generation unit 12 is not limited to a numerically controlled oscillator, and the clock signal generation unit 12 may include, for example, a voltage controlled oscillator. The clock signal generation unit 12 generates the clock signal so as to be a replica of the measurement target clock signal 101. In the present embodiment, hereinafter, the clock signal generated by the clock signal generation unit 12 will be referred to as a replica clock signal.

[0020] FIG. 2 is a diagram showing a general operation of the numerically controlled oscillator included in the clock signal generation unit 12 according to the present embodiment. The numerically controlled oscillator operates in synchronization with a sampling clock signal 102 having a frequency of f SMPL Hertz. The numerically controlled oscillator includes an N-bit (N is an arbitrary integer) counter, and the counter can take values from 0 to 2 N -1. The counter adds its value by δ shown below every cycle of the sampling clock signal 102, and when the value reaches 2 N -1, it generates a carry (sets the carry signal to "1") and repeatedly resets its value to 0.

[0021] The numerically controlled oscillator generates a replica clock signal having one cycle as the time from when the value of the counter becomes 0 to 2 N -1 (that is, the period in which the value of the carry signal is set to "1"). That is, in one cycle of the replica clock signal, the phase of the replica clock signal when the value of the counter is 0 is 0, and the phase of the replica clock signal when the value of the counter is 2 N -1 is 2π (that is, one cycle). However, π represents the ratio of a circle's circumference to its diameter.

[0022] In the example of FIG. 2, the numerically controlled oscillator generates a replica clock that is a sine wave represented by sin(2πf rep t). However, "sin" is a trigonometric function representing sine, and f repis the desired frequency of the replica clock, and t represents time. The numerically controlled oscillator gives the value δ of the frequency setting value 150 as shown in Equation 1, so that the frequency is f rep to generate a replica clock signal.

[0023] δ = f rep / f SMPL x 2 N ······(Equation 1) However, in Equation 1, " / " and "x" are operators representing division and multiplication, respectively.

[0024] The measurement resolution of the numerically controlled oscillator is 1 / 2 N cycles. And the frequency f of the sampling clock signal 102 and the number of bits N of the numerically controlled oscillator can be set according to the desired measurement accuracy. Note that in FIG. 2, the replica clock generated by the numerically controlled oscillator is represented by a sine wave, but the measurement target clock signal 101 according to this embodiment may generate a replica clock that is a rectangular wave. SMPL

[0025] Next, the operation of the clock signal measuring device shown in FIG. 1 will be described with reference to the time charts shown in FIGS. 3A and 3B.

[0026] As illustrated in FIG. 3A, the frequency of the sampling clock signal 102 according to this embodiment is about 10 times the frequency of the measurement target clock signal 101.

[0027] The sampling unit 11 generates a clock signal (an example of the first clock signal) obtained by sampling the measurement target clock signal 101 at the frequency of the sampling clock signal 102. The sampling unit 11 detects the rising edge in the clock signal obtained by sampling the measurement target clock signal 101 as the measurement target clock rising edge detection signal.

[0028] ​Upon receiving the measurement start signal 103, the measurement target clock counter 110 resets its value to "0" and then counts the number of rising edges of the sampled measurement target clock signal 101 detected by the sampling unit 11.

[0029] Upon receiving the measurement start signal 103, the clock signal generation unit 12 starts the operation of generating the replicated clock signal by the numerically controlled oscillator described above with reference to FIG. 2. It is assumed that the initial value of the frequency setting value used for generating the replicated clock signal is given by the user or the like of the clock signal measurement device 10 as the expected value (nominal value) of the measurement target clock signal 101.

[0030] Upon receiving the measurement start signal 103, the replicated clock counter 120 resets its value to "0" and then counts the number of carry-overs (i.e., the frequency of the replicated clock signal) generated in the numerically controlled oscillator of the clock signal generation unit 12.

[0031] Upon receiving the measurement start signal 103, the discrimination unit 13 calculates a value (discrimination value) obtained by subtracting the value represented by the replicated clock counter 120 from the value represented by the measurement target clock counter 110. In the examples shown in FIGS. 3A and 3B, immediately after starting the measurement, since the value represented by the measurement target clock counter 110 and the value represented by the replicated clock counter 120 are both "0", the discrimination unit 13 calculates the discrimination value as "0". Thereafter, the value represented by the measurement target clock counter 110 is updated to "1" ahead of the value represented by the replicated clock counter 120, and the discrimination unit 13 calculates the discrimination value as "1" at this timing. Further thereafter, the value represented by the replicated clock counter 120 is updated to "1", and the discrimination unit 13 calculates the discrimination value as "0" at this timing. In this way, as the value represented by the measurement target clock counter 110 increases ahead of the value represented by the replicated clock counter 120, the discrimination unit 13 calculates the discrimination value as "0" or "1".

[0032] The integration unit 14 calculates a discrimination integration value obtained by integrating the above-described discrimination values. As described above, since the discrimination value is either "0" or "1", when the discrimination value is "1", the integration unit 14 adds 1 to the discrimination integration value, and when the discrimination value is "0", the integration unit 14 maintains the discrimination integration value. The integration unit 14 resets the discrimination integration value to "0" in response to the measurement timing signal 104 becoming "1". That is, the integration unit 14 calculates the discrimination integration value every predetermined period (the time interval (cycle) during which the measurement timing signal 104 is "1"). As the replicated clock signal correctly tracks the measurement target clock signal 101 sampled by it, the period during which the value indicated by the measurement target clock counter 110 and the value indicated by the replicated clock counter 120 match becomes longer, so the discrimination integration value approaches "0".

[0033] The match count counter 130 measures the number of times the discrimination value becomes "0" every time the measurement timing signal 104 becomes "1". The match count counter 130 resets the measured number of times the discrimination value becomes "0" to "0" in response to the measurement timing signal 104 becoming "1". The value indicated by the match count counter 130 is T when the time interval during which the measurement timing signal 104 is "1" is set as T mes seconds. As the replicated clock signal correctly tracks the measurement target clock signal 101 sampled by it, the value approaches T mes xf SMPL times.

[0034] The adjustment unit 15 has a function as a delay lock loop filter (hereinafter referred to as a loop filter). The adjustment unit 15 performs a tracking process of adjusting the frequency setting value 150 of the numerically controlled oscillator in the clock signal generation unit 12 so that the replicated clock signal correctly tracks the measurement target clock signal 101 sampled by it. The adjustment unit 15 adjusts the frequency setting value 150 so that the absolute value of the discrimination integration value calculated by the integration unit 14 becomes smaller (i.e., approaches "0").

[0035] More specifically, for example, as illustrated in FIGS. 3A and 3B, when the discrimination integrated value is a positive value, the phase of the sampled measurement target clock signal 101 is advanced with respect to the phase of the replicated clock signal. In this case, the adjustment unit 15 increases the frequency setting value 150 to increase the phase advancement speed of the replicated clock signal with respect to the sampled measurement target clock signal 101. Further, for example, conversely to that illustrated in FIGS. 3A and 3B, when the discrimination integrated value is a negative value, the phase of the sampled measurement target clock signal 101 lags behind the phase of the replicated clock signal. In this case, the adjustment unit 15 decreases the frequency setting value 150 to decrease the phase advancement speed of the replicated clock signal with respect to the sampled measurement target clock signal 101.

[0036] The adjustment unit 15 outputs the adjusted frequency setting value 150 as a measurement result of the frequency of the measurement target clock signal 101.

[0037] When starting the measurement of the measurement target clock signal 101, the adjustment unit 15 increases the response speed of the loop filter by setting the gain of the loop filter to be larger as a pull-in (frequency pull-in) process. While executing the tracking process, the adjustment unit 15 decreases the response speed of the filter by setting the gain of the loop filter to be smaller than when executing the pull-in process. Thereby, the adjustment unit 15 can stably perform the tracking process.

[0038] The tracking determination unit 16 performs a tracking determination as to whether the replicated clock signal can track the sampled measurement target clock signal 101 by comparing the value indicated by the match count counter 130 with a threshold value. The tracking determination unit 16 makes the tracking determination true when the value indicated by the match count counter 130 is equal to or greater than the threshold value.

[0039] Once the collision determination becomes true, if the value indicated by the match count counter 130 becomes less than the threshold value, the collision determination unit 16 determines that the tracking of the replicated clock signal with respect to the sampled measurement target clock signal 101 has been lost, and sets the collision determination to false. In this case, the adjustment unit 15 interrupts the tracking process and returns to the pull-in process. At this time, the clock signal measurement device 10 is initialized by the measurement start signal 103.

[0040] The phase output unit 17 calculates and outputs a phase measurement value 170 representing the phase of the sampled measurement target clock signal at the measurement timing indicated by the measurement timing signal 104. The phase output unit 17 calculates the phase measurement value 170 based on the value indicated by the N-bit counter of the numerically controlled oscillator in the clock signal generation unit 12 and the value indicated by the replicated clock counter 120.

[0041] Let the value indicated by the replicated clock counter 120 be k rep cycles, and let the phase value (number of waves after the decimal point) indicated by the N-bit counter of the numerically controlled oscillator be NCO rep cycles. In this case, the relative time difference (advance or delay of time) between the sampled measurement target clock signal and the replicated clock signal at the nth measurement timing from the start of measurement is { (k rep + NCO rep ) / f rep - nxT mes} seconds and can be calculated.

[0042] The frequency of the sampling clock signal 102 according to this embodiment needs to be a value that is relatively prime (the greatest common divisor is 1) to the frequency (nominal value) of the measurement target clock signal 101. The reason is that if the frequency of the sampling clock signal 102 and the frequency of the measurement target clock signal 101 are not relatively prime, the clock signal measurement device 10 may perform an incorrect process of causing the replicated clock signal to track a frequency that is a multiple of the frequency of the measurement target clock signal 101.

[0043] As illustrated in FIGS. 3A and 3B, the clock signal measurement device 10 includes a latch circuit that holds the measured or calculated value at the timing when the measurement timing signal 104 becomes "1" in order to update the measured or calculated value in synchronization with the measurement timing signal 104. For example, the discrimination integration value latch in FIG. 3B holds discrimination values such as "d + 7" and "d' + 7" when the measurement timing signal 104 becomes "1". Also, the match count latch in FIG. 3B holds values such as "c + 1" and "c'" of the match counter 130 when the measurement timing signal 104 becomes "1". Then, the adjustment unit 15 calculates the frequency setting value 150 based on the values held in the above-described latch circuit.

[0044] Next, with reference to the flowcharts of FIGS. 4A and 4B, the operation (processing) of the clock signal measurement device 10 according to the present embodiment will be described in detail.

[0045] In response to the measurement start signal 103 becoming "1", the clock signal measurement device 10 initializes itself and starts measuring the measurement target clock signal 101 (step S101). The sampling unit 11 starts sampling the measurement target clock signal 101 (step S102). The clock signal generation unit 12 is given an expected value (nominal value) of the frequency of the measurement target clock signal 101 as an initial value of the frequency setting value 150 (step S103).

[0046] The numerically controlled oscillator in the clock signal generation unit 12 generates a replica clock signal having the frequency indicated by the frequency setting value 150 (step S104). The measurement target clock counter 110 counts the number of waves of the sampled measurement target clock signal 101 after the start of measurement of the measurement target clock signal 101 (step S105). The replica clock counter 120 counts the number of waves of the replica clock signal after the start of measurement of the measurement target clock signal 101 (step S106).

[0047] The discrimination unit 13 calculates a discrimination value obtained by subtracting the value represented by the replicated clock counter 120 from the value represented by the measurement target clock counter 110 (step S107). The integration unit 14 calculates a discrimination integrated value from the discrimination value (step S108).

[0048] The clock signal measuring device 10 receives a measurement timing signal 104 representing the measurement timing (step S109). The adjustment unit 15 checks the discrimination integrated value (step S110). When the discrimination integrated value is a positive value (Yes in step S111), the adjustment unit 15 adjusts the frequency setting value 150 to a larger value (step S112), and the process proceeds to step S115. When the discrimination integrated value is not a positive value (No in step S111), the process proceeds to step S113.

[0049] When the discrimination integrated value is a negative value (Yes in step S113), the adjustment unit 15 adjusts the frequency setting value 150 to a smaller value (step S114), and the process proceeds to step S115. When the discrimination integrated value is not a negative value (No in step S113), the process proceeds to step S115.

[0050] The adjustment unit 15 outputs the new frequency setting value 150 to the clock signal generation unit 12 and to the outside (step S115). The integration unit 14 resets the discrimination integrated value to 0 (step S116), and the process returns to step S104.

[0051] The clock signal measuring device 10 according to the present embodiment can improve the measurement accuracy of the clock signal without using a high-frequency sampling clock signal. The reason is that the clock signal measuring device 10 calculates a discrimination integrated value obtained by integrating the difference in wave numbers over a predetermined period between the clock signal obtained by sampling the measurement target clock signal 101 and the generated replicated clock signal, and adjusts the frequency setting value 150 when generating the replicated clock signal so that the discrimination integrated value approaches 0.

[0052] Hereinafter, the effects achieved by the clock signal measuring device 10 according to the present embodiment will be described in detail.

[0053] When measuring the advance or delay of the clock in the device with respect to the clock signal serving as the time reference input from the outside, or when measuring the frequency of the clock signal input from the outside, if the external input signal is sampled and measured, the measurement accuracy is based on the period of the sampling clock signal as the minimum unit. Therefore, to improve the measurement accuracy, it is necessary to increase the frequency of the sampling clock signal. And to increase the frequency of the sampling clock signal, it is essential to use components that can operate at high speed and perform substrate design so that the transmission lines on the substrate can support the sampling clock signal with a high frequency, which poses the problem of increased cost. Therefore, it is an issue to improve the measurement accuracy of the clock signal without using a sampling clock signal with a high frequency.

[0054] In response to such a problem, the clock signal measurement device 10 according to the present embodiment operates in synchronization with the sampling clock signal 102 and includes a sampling unit 11, a clock signal generation unit 12, a discrimination unit 13, an integration unit 14, and an adjustment unit 15, and operates as described above with reference to FIGS. 1 to 4B. That is, the sampling unit 11 generates a signal (first clock signal) obtained by sampling the clock signal 101 to be measured. The clock signal generation unit 12 generates a replicated clock signal (second clock signal) having a frequency equal to the frequency set value 150. The discrimination unit 13 calculates the difference between the wave number of the signal obtained by sampling the clock signal 101 to be measured from a predetermined time and the wave number of the replicated clock signal. The integration unit 14 calculates an integrated value obtained by integrating the difference for each predetermined measurement period. Then, the adjustment unit 15 adjusts the frequency set value 150 so that the absolute value of the integrated value becomes smaller, outputs the adjusted frequency set value 150 as a new frequency set value 150 to the clock signal generation unit 12 and to the outside.

[0055] That is, the clock signal measurement device 10 does not improve the measurement accuracy of the measurement target clock signal 101 by sampling using a high-frequency sampling clock signal. Instead, it acquires, as the measurement result of the frequency of the measurement target clock signal 101, a frequency setting value 150 adjusted so that the replicated clock signal correctly tracks the measurement target clock signal 101. The measurement resolution of the measurement target clock signal 101 is defined by the number of stages (value of N) of the numerically controlled oscillator of the clock signal generation unit 12, and the measurement accuracy is defined by the tracking accuracy of the replicated clock. Therefore, the clock signal measurement device 10 can improve the measurement accuracy of the clock signal without using a high-frequency sampling clock signal.

[0056] Also, the clock signal measurement device 10 according to the present embodiment uses, as the initial value of the frequency setting value 150, the expected value (nominal value) of the measurement target clock signal 101, and calculates the integrated value of the discrimination value obtained by subtracting the frequency of the replicated clock signal from the wave number of the signal obtained by sampling the measurement target clock signal 101. Then, when the integrated value is a positive value, the clock signal measurement device 10 adjusts the frequency setting value 150 to be a larger value, and when the integrated value is a negative value, the clock signal measurement device 10 adjusts the frequency setting value 150 to be a smaller value. Thereby, the clock signal measurement device 10 can surely improve the measurement accuracy of the clock signal without using a high-frequency sampling clock signal.

[0057] Also, the clock signal measurement device 10 according to the present embodiment determines that the replicated clock signal can track the signal obtained by sampling the measurement target clock signal 101 when the integrated value of the time during which the discrimination value is 0 is equal to or greater than the threshold value. Then, when the replicated clock signal cannot track the signal obtained by sampling the measurement target clock signal 101, the clock signal measurement device 10 performs frequency pulling-in processing using a loop filter. Thereby, the clock signal measurement device 10 can more surely improve the measurement accuracy of the clock signal without using a high-frequency sampling clock signal.

[0058] <Second Embodiment> FIG. 5 is a block diagram showing the configuration of a clock signal measurement device 20 according to a second embodiment of the present invention. The clock signal measurement device 20 is a device that operates in synchronization with the sampling clock signal 102, similar to the clock signal measurement device 10 according to the first embodiment described above, and is a device that measures the frequency and phase of a clock signal 201 to be measured (clock signal under measurement). However, it is assumed that the clock signal 201 to be measured according to this embodiment is a sine wave (analog signal).

[0059] The clock signal measurement device 20 includes a sampling unit 21, an ADC value integration unit 210, a DC offset correction unit 211, an ADC value amplitude integration unit 212, a clock signal generation unit 22, a replicated clock counter 220, a discrimination unit 23, a discrimination maximum value holding unit 230, an integration unit 24, an adjustment unit 15, a tracking determination unit 26, and a phase output unit 17. The sampling unit 21, the clock signal generation unit 22, the discrimination unit 23, the integration unit 24, the adjustment unit 15, the tracking determination unit 26, and the phase output unit 17 are examples of a sampling means, a clock signal generation means, a discrimination means, an integration means, an adjustment means, a tracking determination means, and a phase output means, respectively. In addition, for components having the same functions as the components in the clock signal measurement device 10 according to the first embodiment, the same numbers as those in the first embodiment are assigned, and the description of their operations will be omitted.

[0060] The sampling unit 21 samples the clock signal 201 to be measured using an analog / digital converter (hereinafter referred to as ADC (Analog Digital Converter)). The ADC is preferably a low-distortion component according to the required measurement accuracy. The aperture jitter of the ADC also affects the measurement accuracy. Also, depending on the input voltage level to the ADC, a low-distortion amplifier may be required in the front stage of the ADC. The ADC of the sampling unit 21 according to this embodiment is to perform sampling at the falling edge of the sampling clock signal 102. For this reason, the sampling unit 21 includes a D flip-flop (not shown) for synchronization at the subsequent stage of the ADC so as to process in synchronization with the rising edge of the sampling clock signal 102.

[0061] Until the sampling unit 21 analog / digitally converts the measurement target clock signal 201 and outputs the converted signal from the ADC, there is a unique conversion delay time for each type of component of the ADC. Similar to the clock signal measurement device 10 according to the first embodiment, the clock signal measurement device 20 according to the present embodiment measures the phase of the sampled measurement target clock signal 201 based on the discrimination result by the discrimination unit 23. At this time, since the phase of the sampled measurement target clock signal 201 is delayed by the above-described unique conversion delay time, the clock signal measurement device 20 according to the present embodiment needs to perform a process of correcting by the above-described conversion delay time of the ADC.

[0062] The ADC value integration unit 210 calculates an ADC integrated value obtained by integrating the ADC value, which is the result of sampling the measurement target clock signal 201 output from the ADC, for the time interval during which the measurement timing signal 104 is "1".

[0063] The DC offset correction unit 211 calculates the average value of the ADC values as a DC offset corresponding to the 0 level of the output from the ADC. The DC offset correction unit 211 calculates (ADC integrated value) / (T mes xf SMPL ) representing the average value of the ADC values. The DC offset correction unit 211 performs DC offset correction by subtracting the calculated DC offset from the ADC values.

[0064] The ADC value amplitude integration unit 212 integrates the absolute value of the ADC value after the DC offset correction by the DC offset correction unit 211 for the time interval during which the measurement timing signal 104 is "1", and outputs an ADC value amplitude integrated value after the DC offset correction. When this integrated value is Q, the ADC value amplitude A after the DC offset correction is expressed as in Equation 2.

[0065] A = (π / 2)xQ / (T mes xf SMPL ) ······(Equation 2) The DC offset correction unit 211 generates the previous sampling value of the ADC value after DC offset correction, which is latched by the sampling clock signal 102 using, for example, a D flip-flop or the like, from the ADC value after DC offset correction.

[0066] When the previous sampling value of the ADC value after DC offset correction is less than 0 and the current sampling value of the ADC value after DC offset correction is 0 or more, the DC offset correction unit 211 generates a rising edge (0 crossing) detection signal of the measured clock signal 201 that has been sampled.

[0067] Similar to the clock signal generation unit 12 according to the first embodiment, the clock signal generation unit 22 starts the generation operation of the replicated clock signal by the numerically controlled oscillator upon the measurement start signal 103. Note that as the initial value of the frequency setting value used for generating the replicated clock signal, it is assumed that the expected value (nominal value) of the measured clock signal 201 is given by the user or the like of the clock signal measuring device 20.

[0068] Similar to the replicated clock counter 120 according to the first embodiment, the replicated clock counter 220 resets its value to "0" upon the measurement start signal 103, and then counts the number of carry-overs (i.e., the number of waves of the replicated clock signal) generated in the numerically controlled oscillator of the clock signal generation unit 22.

[0069] The discrimination unit 23 generates a discrimination condition establishment signal as true when the absolute value of the phase value of the numerically controlled oscillator of the replicated clock is within the range of the threshold value for performing comparison and discrimination, and the rising edge (0 crossing) detection signal of the sampled measured clock signal 201 is true. That is, the discrimination unit 23 detects the rising edge (0 crossing) of the sampled measured clock signal 201, and when the phase of the replicated clock is close to 0 within a predetermined range, performs the same discrimination process as the discrimination unit 13 according to the first embodiment.

[0070] Regarding the discrimination process by the discrimination unit 23, it will be described with reference to FIG. 6. As shown in FIG. 6, in the vicinity of a phase of 0 in a sine wave, the error due to linear approximation is small. By using only the vicinity of a phase of 0 for the discrimination process, the discrimination unit 23 can linearly approximate the phase itself of the replicated clock signal with the sine wave of the replicated clock. Therefore, the discrimination unit 23 can simply generate an approximate sine wave of the replicated clock signal from the phase of the replicated clock signal without performing a sine wave approximation generation process using a look-up table or a plurality of multiplications and divisions, thereby reducing the circuit scale. Outside the vicinity of the zero-crossing point, the quantization distortion and sine wave approximation error due to the ADC of the measurement target clock signal 201 become large. Therefore, it is easier to improve the tracking accuracy by using only the vicinity of the zero-crossing point for the discrimination process. Also, as the timing of the clock signal, it is usually defined by the rising edge or the falling edge (zero-crossing point). Therefore, it is important to improve the tracking accuracy in the vicinity of the rising edge.

[0071] The discrimination unit 23 calculates, as a discrimination value, the difference between the sum of the previous sampling value and the current sampling value of the ADC value after DC offset correction of the sampled measurement target clock signal 201 and the value obtained by multiplying the phase of the replicated clock signal output by the numerically controlled oscillator of the clock signal generation unit 22 by the amplitude coefficient setting value.

[0072] FIG. 6 shows the relationship between the sampled measurement target clock signal 201 after DC offset correction and the replicated clock signal in the vicinity of the zero-crossing point. In FIG. 6, let the time (i.e., the phase difference) from the intermediate timing, which is the middle between the current sampling timing and the previous sampling timing, to the zero-crossing point be Δ seconds. Since the clock signal measurement device 20 according to the present embodiment uses an ADC that samples at the falling edge of the sampling clock signal 102, the above-described intermediate timing is the rising edge timing of the sampling clock signal 102. Therefore, Δ represents the time deviation from the rising edge timing of the sampling clock signal 102 to the zero-crossing point.

[0073] Assuming that the frequency of the clock signal 201 to be measured is f Hz, the current sampling value q when the rising edge of the clock to be measured is detected c and the previous sampling value q p are respectively expressed as in Equation 3 and Equation 4.

[0074] q c =Asin(2πf(T SMPL / 2 - Δ)) ······(Equation 3) q p =Asin(2πf(-T SMPL / 2 - Δ)) ······(Equation 4) The sum q of the previous sampling value and the current sampling value c +q p is expressed as in Equation 5.

[0075] q c +q p =-2Acos(2πf(T SMPL / 2))sin(2πfΔ)······(Equation 5) However, in Equation 5, "cos" is a trigonometric function representing cosine.

[0076] Near the 0 - crossing point, that is, under the condition 2πfΔ << 1, the sum q of the previous sampling value and the current sampling value c +q p can be approximated as in Equation 6.

[0077] q c +q p ≒ - 4πAcos(πfT SMPL )Δ ······(Equation 6) The discrimination unit 23 can thus directly extract the time deviation amount (phase difference) Δ between the 0 - crossing point and the rising - edge timing of the sampling clock signal 102 in a state multiplied by a constant by calculating the sum q of the previous sampling value and the current sampling value c +q p .

[0078] Assuming that the time deviation amount from the rising timing of the sampling clock signal 102 to the zero-crossing point of the phase of the replicated clock signal is Δ^ seconds, the reading value of the phase of the replicated clock signal generated by the numerically controlled oscillator in the clock signal generation unit 22 when it is closest to the zero-crossing point is -f rep It becomes Δ^ cycles. However, as shown in FIG. 6, the symbol “^” is a symbol that is originally described directly above Δ. From the above, the amplitude coefficient multiplying the phase of the replicated clock signal may be 4πAcos(πfT SMPL ).

[0079] From the above, when the discrimination condition determination in the vicinity of the zero-crossing point is true, the discrimination unit 23 calculates the discrimination value as shown in Equation 7.

[0080] Discrimination value = 4πAcos(πfT SMPL )({fΔ - f rep Δ^) ······(Equation 7) The closer the phase and frequency of the replicated clock signal correctly track the phase and frequency of the sampled measurement target clock signal 201, the closer the discrimination value approaches 0.

[0081] When the determination of the above-described discrimination condition is true, the integration unit 24 integrates the discrimination value calculated by the discrimination unit 23 at every predetermined period (the time interval during which the measurement timing signal 104 is “1”), in the same manner as the integration unit 14 according to the first embodiment. The discrimination integration value calculated by the integration unit 24 approaches 0 as the replicated clock signal correctly tracks the sampled measurement target clock signal 201.

[0082] The integration unit 24 calculates a discrimination integration count representing the number of times the discrimination condition determination is true for the time interval during which the measurement timing signal 104 is “1”. The average value of the discrimination integration counts calculated by the integration unit 24 for each such time interval is about fxT mes times.

[0083] The integration unit 24 inputs the discrimination result to the adjustment unit 15 as (discrimination integration value) / (discrimination integration count) / (amplitude coefficient) / 2 mIt is calculated as follows. Here, the amplitude coefficient is 4πAcos(πfT SMPL ) described above. m is an integer representing the number of bits of the ADC in the sampling unit 21.

[0084] Based on the discrimination result input from the integration unit 24, the adjustment unit 15 adjusts the frequency setting value 250 for the numerically controlled oscillator in the clock signal generation unit 22 so that the replicated clock signal correctly tracks the measurement target clock signal 201 sampled, in the same manner as the adjustment unit 15 according to the first embodiment. The function of the adjustment unit 15 as a loop filter is the same as that of the adjustment unit 15 according to the first embodiment.

[0085] The discrimination maximum value holding unit 230 holds the maximum value of the discrimination value when the determination of the discrimination condition by the discrimination unit 23 is true during the time interval when the measurement timing signal 104 is "1".

[0086] The tracking determination unit 26 divides the maximum value of the discrimination value held by the discrimination maximum value holding unit 230 by the above-described amplitude coefficient and 2 m and compares the calculated value with the threshold value. When the calculated value is smaller than the threshold value, the tracking determination as to whether the replicated clock signal can track the measurement target clock signal 201 sampled by the replicated clock signal is set to true.

[0087] At the start of measurement of the measurement target clock signal 201, the clock signal measurement device 20 according to the present embodiment initializes only the numerically controlled oscillator and the replicated clock counter 220 in the clock signal generation unit 22 that generates the replicated clock signal. The clock signal measurement device 20 performs initialization by taking the logical product of the measurement start signal 103 and the rising edge (0 crossing) detection signal of the measurement target clock signal 201. Thereby, at the start of measurement of the measurement target clock signal 201, the clock signal measurement device 20 makes the phases of the sampled measurement target clock signal 201 and the replicated clock signal substantially coincide in the vicinity of 0. The reason is that if this phase is not adjusted at the start of measurement, the determination process of the discrimination condition will not be driven, making it difficult to perform tracking control of the replicated clock signal with respect to the sampled measurement target clock signal 201.

[0088] The clock signal measuring device 20 according to the present embodiment can measure the frequency of the clock signal to be measured 201 with the frequency setting value 150 for the replicated clock signal, which is the same as the clock signal measuring device 10 according to the first embodiment. Also, the clock signal measuring device 20 according to the present embodiment can measure the phase measurement value 170 of the clock signal to be measured 201 from the phase indicated by the replicated clock counter 120 and the numerically controlled oscillator in the clock signal generation unit 22, which is the same as the clock signal measuring device 10 according to the first embodiment.

[0089] Also, the clock signal measuring device 20 according to the present embodiment, similar to the clock signal measuring device 10 according to the first embodiment, updates the measured or calculated value in synchronization with the measurement timing signal 104. Therefore, the clock signal measuring device 20 is provided with a latch circuit that holds the measured value or calculated value at the timing when the measurement timing signal 104 becomes "1".

[0090] The clock signal measuring device 20 according to the present embodiment can improve the measurement accuracy of the clock signal without using a high-frequency sampling clock signal. The reason is as described for the first embodiment.

[0091] Also, the clock signal measuring device 20 according to the present embodiment performs discrimination processing only for a period in the vicinity of the zero-crossing point, which is the time when the value of the clock signal to be measured 201 sampled by analog / digital conversion becomes 0 and in which the linear approximation of the sine wave holds. Thereby, the clock signal measuring device 20 can realize the improvement of the measurement accuracy of the clock signal, which is an analog signal, with a simple configuration without using a high-frequency sampling clock signal.

[0092] Furthermore, the clock signal 201 to be measured according to the present embodiment is not limited to a sine wave. Even if the clock signal 201 to be measured is an analog signal such as a triangular wave or a sawtooth wave, the clock signal measuring apparatus 20 can similarly measure the clock signal 201 to be measured.

[0093] In addition, when the clock signal generation unit 12 according to the present embodiment generates a replicated clock signal using a voltage controlled oscillator, the clock signal measuring apparatus 20 may perform discrimination processing using the replicated clock signal having an analog waveform, or may perform analog / digital conversion or rectangular wave conversion on the replicated clock signal.

[0094] Furthermore, in the present embodiment, unlike the first embodiment, the frequency of the sampling clock signal 102 does not have to be a value that is relatively prime to the frequency (nominal value) of the clock signal 201 to be measured, which is a sine wave.

[0095] <The Third Embodiment> FIG. 7 is a block diagram showing the configuration of a clock signal measurement system 3 according to the third embodiment of the present invention. The clock signal measurement system 3 includes a detection device 30-1 that detects the occurrence of a detection target event 106-1, and a detection device 30-2 that detects the occurrence of a detection target event 106-2. The configurations of the detection devices 30-1 and 30-2 are equivalent. In the present embodiment, hereinafter, either one of the detection target events 106-1 and 106-2, or both of them may be collectively referred to as the detection target event 106. Also, either one of the detection devices 30-1 and 30-2, or both of them may be collectively referred to as the detection device 30.

[0096] The detection target event 106 may be, for example, a natural phenomenon or a failure in the system. Also, the detection target events 106-1 and 106-2 may be the same event or different events.

[0097] The number of detection devices 30 included in the clock signal measurement system 3 according to this embodiment is not limited to two. The clock signal measurement system 3 may include one detection device 30, or may include three or more detection devices 30.

[0098] The detection devices 30-1 and 30-2 sequentially include clock signal measurement devices 10A-1 and 10A-2. In this embodiment, hereinafter, either one of the clock signal measurement devices 10A-1 and 10A-2, or both of them may be collectively referred to as the clock signal measurement device 10A.

[0099] In addition to the clock signal measurement device 10A, the detection device 30 includes an event detection unit 31. The event detection unit 31 is an example of event detection means. The event detection unit 31 is, for example, a sensor that detects the occurrence of the detection target event 106. When the event detection unit 31 detects the occurrence of the detection target event 106, the event detection unit 31 inputs a signal indicating the detection of the occurrence of the detection target event 106 to the clock signal measurement device 10A.

[0100] The clock signal measurement device 10A includes the configuration included in the clock signal measurement device 10 according to the first embodiment, and a time specifying unit 18. The time specifying unit 18 is an example of time specifying means. In FIG. 7, for convenience of the drawing, a part of the configuration included in the clock signal measurement device 10 shown in FIG. 1 is omitted.

[0101] The same reference time clock signal 105 is input to the sampling units 11 in the clock signal measurement devices 10A-1 and 10A-2. The reference time clock signal 105 is a signal that represents time with high accuracy, such as a clock signal synchronized with a GNSS (Global Navigation Satellite System) signal or a clock signal synchronized with a radio-controlled clock.

[0102] Sampling clock signals 102-1 and 102-2 are sequentially input to the clock signal measurement devices 10A-1 and 10A-2. The frequencies of the sampling clock signals 102-1 and 102-2 may be the same or different.

[0103] The time specifying unit 18 includes a latch circuit that holds the phase of the replicated clock signal generated by the clock signal generation unit 12 at the timing when it receives a signal indicating that the event detection unit 31 has detected the occurrence of the detection target event 106. The phase of the replicated clock signal is represented by the value of the N-bit counter of the numerically controlled oscillator in the clock signal generation unit 12. The clock signal measurement device 10A according to the present embodiment uses a signal indicating that the event detection unit 31 has detected the occurrence of the detection target event 106 as a signal corresponding to the measurement timing signal 104 according to the first embodiment. The time specifying unit 18 calculates the event detection time 180-1 or 180-2 from the phase of the replicated clock signal that has tracked the reference time clock signal 105 and is held as described above, and outputs the calculated event detection time 180-1 or 180-2.

[0104] The clock signal measurement system 3 according to the present embodiment can specify the detection time of the event to be detected with high accuracy without using a high-frequency sampling clock signal. The reason is that the clock signal measurement system 3 can specify the detection time of the event according to the resolution of the numerically controlled oscillator in the clock signal generation unit 12 by using the function of the clock signal measurement device 10 according to the first embodiment.

[0105] In addition, since the clock signal measurement system 3 according to the present embodiment uses the reference time clock signal 105 that represents time with high accuracy, the detection time of the event to be detected can be specified with high accuracy.

[0106] In addition, in the clock signal measurement system 3 according to the present embodiment, since a plurality of detection devices 30 use the same reference time clock signal 105, the detection times of events by the respective detection devices 30 can be compared with high accuracy.

[0107] Note that the clock signal measurement system 3 according to the present embodiment may have a configuration in which the time specifying unit 18 is added to the clock signal measurement device 20 according to the second embodiment.

[0108] The clock signal measurement system 3 according to this embodiment can be used, for example, in the following technical fields. · Precise measurement of the arrival time of gravitational waves in gravitational wave astronomy, · Precise measurement of the pulse period of pulsar celestial bodies and its variations in radio astronomy, X-ray astronomy, gamma-ray astronomy, etc., · Synchronous observation of each wavelength observation system in multi-wavelength astronomy. For example, measurement of the time relationship between a burst phenomenon such as a gamma-ray burst and candidate celestial body event data in other wavelength regions, · Precise synchronization of time in a system incorporating multiple devices and subsystems, · Improvement in the accuracy of earthquake wave arrival prediction time by improving the earthquake detection time accuracy of seismographs in various locations, · Improvement in image resolution by improving the accuracy of the output pulse time and the reflected pulse observation time during image reconstruction in synthetic aperture radar.

[0109] <Fourth Embodiment> FIG. 8 is a block diagram showing the configuration of a clock signal measurement system 4 according to the fourth embodiment of the present invention. The clock signal measurement system 4 includes clock signal measurement devices 10-1 to 10-3 having the same configuration as the clock signal measurement device 10 according to the first embodiment. In this embodiment, hereinafter, any one of the clock signal measurement devices 10-1 to 10-3, or all of them may be collectively referred to as the clock signal measurement device 10. In FIG. 8, for convenience of the drawing, a part of the configuration included in the clock signal measurement device 10 shown in FIG. 1 is omitted.

[0110] The number of clock signal measurement devices 10 included in the clock signal measurement system 4 according to this embodiment is not limited to three. The clock signal measurement system 4 may include two clock signal measurement devices 10, or may include four or more.

[0111] In the sampling units 11 in the clock signal measurement devices 10-1 to 10-3, measurement target clock signals 101-1 to 101-3 that are different from each other are sequentially input. The measurement target clock signals 101-1 to 101-3 are, for example, clock signals generated by a high-stability clock signal generation device. Specifically, the high-stability clock signal generation device is, for example, an atomic clock, a hydrogen maser clock, an optical lattice clock, or the like. The high-stability clock signal generation devices that generate the measurement target clock signals 101-1 to 101-3 may be clock signal generation devices based on the same principle or clock signal generation devices based on different principles. The frequencies of the measurement target clock signals 101-1 to 101-3 may be the same or different. Incidentally, in the present embodiment, hereinafter, any one of the measurement target clock signals 101-1 to 101-3, or all of them may be collectively referred to as the measurement target clock signal 101.

[0112] The same sampling clock signal 102 is input to the clock signal measurement devices 10-1 to 10-3, and the clock signal measurement devices 10-1 to 10-3 operate in synchronization with the sampling clock signal 102. As a result of measuring the measurement target clock signals 101-1 to 101-3, the clock signal measurement devices 10-1 to 10-3 output frequency setting values 150-1 to 150-3 and phase measurement values 170-1 to 170-3.

[0113] The clock signal measurement system 4 according to the present embodiment can measure the relative frequency stability of a plurality of measurement target clock signals 101 with high accuracy without using a high-frequency sampling clock signal. The reason is that the clock signal measurement system 4 measures a plurality of measurement target clock signals 101 using a plurality of clock signal measurement devices 10 according to the first embodiment that operate in synchronization with the same sampling clock signal 102.

[0114] For example, when it is measured that a plurality of clock signals 101 to be measured have similar frequency fluctuations, as one of the factors of the measured frequency fluctuations, there is a frequency fluctuation of the sampling clock signal 102. Since the clock signal measurement system 4 according to the present embodiment uses the same sampling clock signal 102 for a plurality of clock signal measurement devices 10, by comparing the measurement results of the plurality of clock signals 101 to be measured by the plurality of clock signal measurement devices 10, the factor of the frequency fluctuation of the sampling clock signal 102 can be removed (offset).

[0115] Also, in the clock signal measurement system 4 according to the present embodiment, for example, by comparing the measurement results by the clock signal measurement devices 10-1 and 10-2, the measurement results by the clock signal measurement devices 10-2 and 10-3, and the measurement results by the clock signal measurement devices 10-3 and 10-1, respectively, it is possible to specify with high accuracy which clock signal 101 to be measured has a frequency fluctuation.

[0116] Note that the clock signal measurement system 4 according to the present embodiment may include the clock signal measurement device 20 according to the second embodiment.

[0117] <Fifth Embodiment> FIG. 9 is a block diagram showing the configuration of a clock signal measurement device 50 according to the fifth embodiment of the present invention.

[0118] The clock signal measurement device 50 according to the present embodiment includes a sampling unit 51, a clock signal generation unit 52, a discrimination unit 53, an integration unit 54, and an adjustment unit 55. The sampling unit 51, the clock signal generation unit 52, the discrimination unit 53, the integration unit 54, and the adjustment unit 55 are examples of sampling means, clock signal generation means, discrimination means, integration means, and adjustment means, respectively.

[0119] The clock signal measurement device 50 is a device that operates in synchronization with the sampling clock signal 502. The sampling clock signal 502 is, for example, a signal similar to the sampling clock signal 102 according to the first embodiment or the second embodiment.

[0120] The sampling unit 51 generates a first clock signal 510 obtained by sampling (sampling) the clock signal 501 to be measured. The first clock signal 510 is, for example, a signal similar to the measurement target clock signal 101 sampled by the sampling unit 11 according to the first embodiment, or the measurement target clock signal 201 sampled by the sampling unit 21 according to the second embodiment. The sampling unit 51 operates in the same manner as, for example, the sampling unit 11 according to the first embodiment or the sampling unit 21 according to the second embodiment.

[0121] The clock signal generation unit 52 generates a second clock signal 520 having a set value 550 for the frequency. The second clock signal 520 is, for example, a signal similar to the replicated clock signal generated by the clock signal generation unit 12 according to the first embodiment, or the replicated clock signal generated by the clock signal generation unit 22 according to the second embodiment. The clock signal generation unit 52 operates in the same manner as, for example, the clock signal generation unit 12 according to the first embodiment or the clock signal generation unit 12 according to the second embodiment.

[0122] The discrimination unit 53 calculates the difference between the frequency of the first clock signal 510 from a predetermined time and the frequency of the second clock signal 520. The discrimination unit 53 operates in the same manner as, for example, the discrimination unit 13 according to the first embodiment or the discrimination unit 23 according to the second embodiment.

[0123] The integrating unit 54 calculates an integrated value obtained by integrating the difference for each predetermined measurement period. The predetermined period is, for example, a period such as the time interval during which the measurement timing signal 104 according to the first embodiment or the second embodiment becomes "1". The integrating unit 54 operates in the same manner as, for example, the integrating unit 14 according to the first embodiment or the integrating unit 24 according to the second embodiment.

[0124] The adjusting unit 55 adjusts the set value 550 so that the absolute value of the integrated value becomes smaller, and outputs the adjusted set value 550 as a new set value 550 to the outside of the clock signal generation unit 52. The adjusting unit 55 operates in the same manner as, for example, the adjusting unit 15 according to the first embodiment or the second embodiment.

[0125] The clock signal measuring device 50 according to the present embodiment can improve the measurement accuracy of the clock signal without using a high-frequency sampling clock signal. The reason is that the clock signal measuring device 50 calculates an integrated value obtained by integrating the difference in frequency over a predetermined period between the clock signal obtained by sampling the clock signal 501 to be measured and the generated replica clock signal, and adjusts the set value 550 of the frequency when generating the replica clock signal so that the integrated value approaches 0.

[0126] <Hardware Configuration Example> In each of the above-described embodiments, each unit in the clock signal measuring device shown in FIGS. 1, 5, and 7 to 9 can be realized by dedicated HW (HardWare) (electronic circuit). Further, in FIGS. 1, 5, and 7 to 9, at least the following configurations can be regarded as functional (processing) units (software modules) of a software program including instructions executed by a processor. · Sampling units 11 and 21, and sampling unit 51, · Clock counter 110 of the clock signal to be measured, · Control functions for generating clock signals in clock signal generation units 12, 22, and 52, · Replica clock counters 120 and 220 · Discrimination units 13, 23, and 53, · Match count counter 130, · Integration units 14, 24, and 54, · Adjustment units 15 and 55, · Tracking determination units 16 and 26, · Phase output unit 17, · Time determination unit 18, · ADC value integration unit 210, · DC offset correction unit 211, · ADC value amplitude integration unit 212, · Discrimination maximum value holding unit 230, · Event detection unit 31.

[0127] However, the classification of each part shown in these drawings is a configuration for convenience of explanation, and various configurations can be assumed in implementation. An example of the hardware environment in this case will be described with reference to FIG. 10.

[0128] FIG. 10 is a diagram exemplarily explaining the configuration of an information processing apparatus 900 (computer) capable of realizing a clock signal measurement apparatus according to each embodiment of the present invention. That is, FIG. 10 shows the configuration of a computer (information processing apparatus) capable of realizing the clock signal measurement apparatuses shown in FIGS. 1, 5, and 7 to 9, and represents a hardware environment capable of realizing each function in the above-described embodiments.

[0129] The information processing apparatus 900 shown in FIG. 10 includes the following as components. · CPU (Central_Processing_Unit) 901, · ROM (Read_Only_Memory) 902, · RAM (Random_Access_Memory) 903, · Hard disk (storage device) 904, · Communication interface 905, · Bus 906 (communication line), · Reader / writer 908 capable of reading and writing data stored in a recording medium 907 such as a CD-ROM (Compact_Disc_Read_Only_Memory), · Input / output interfaces 909 such as monitors, speakers, keyboards, etc.

[0130] That is, the information processing apparatus 900 including the above components is a general computer in which these components are connected via a bus 906. The information processing apparatus 900 may include a plurality of CPUs 901, or may include a CPU 901 configured by a multi-core.

[0131] Then, the above-described embodiment may supply a computer program capable of realizing the following functions to the information processing apparatus 900 shown in FIG. 10. For example, the functions are the above-described configurations in the block diagrams (FIGS. 1, 5, and 7 to 9) referred to in the description of the embodiment, or the functions of the flowcharts (FIGS. 4A and 4B). The functions of the clock signal measuring apparatus according to the present embodiment are then achieved by reading, interpreting, and executing the computer program by the CPU 901 of the hardware. Further, the computer program supplied into the apparatus may be stored in a readable and writable volatile memory (RAM 903), or a non-volatile storage device such as a ROM 902 or a hard disk 904.

[0132] Also, in the above case, a general procedure can be adopted as a method for supplying the computer program into the hardware. As the procedure, for example, there are a method of installing it into the apparatus via various recording media 907 such as a CD-ROM, and a method of downloading it from the outside via a communication line such as the Internet. And in such a case, the computer program supplied to the information processing apparatus according to the present embodiment can be regarded as being constituted by the code constituting the program or the recording medium 907 in which the code is stored.

[0133] The present invention has been described by taking the above-described embodiments as exemplary examples. However, the present invention is not limited to the above-described embodiments. That is, within the scope of the present invention, various aspects understandable by those skilled in the art can be applied.

Explanation of Signs

[0134] 10 Clock signal measurement device 10A Clock signal measurement device 101 Clock signal to be measured 102 Sampling clock signal 103 Measurement start signal 104 Measurement timing signal 105 Reference time clock signal 106 Event to be detected 11 Sampling unit 110 Clock counter for signal to be measured 12 Clock signal generation unit 120 Replica clock counter 13 Discrimination unit 130 Match count counter 14 Integration unit 15 Adjustment unit 150 Frequency set value 16 Tracking determination unit 17 Phase output unit 170 Phase measurement value 18 Time determination unit 180-1 or 180-2 Event detection time 20 Clock signal measurement device 201 Clock signal to be measured 21 Sampling unit 210 ADC value integration unit 211 DC offset correction unit 212 ADC value amplitude integration unit 22 Clock signal generation unit 220 Replica clock counter 23 Discrimination unit 230 Discrimination maximum value holding unit 24 Integration unit 26 Tracking determination unit 3 Clock Signal Measurement System 30 Detection Device 31 Event Detection Unit 4 Clock Signal Measurement System 50 Clock Signal Measuring Device 501 Clock Signal to be Measured 502 Sampling Clock Signal 51 Sampling Unit 510 First Clock Signal 52 Clock Signal Generation Unit 520 Second Clock Signal 53 Discrimination Unit 54 Integration Unit 55 Adjustment Unit 550 Set Value 900 Information Processing Device 901 CPU 902 ROM 903 RAM 904 Hard Disk (Storage Device) 905 Communication Interface 906 Bus 907 Recording Medium 908 Reader / Writer 909 Input / Output Interface

Claims

1. An apparatus that operates in synchronization with a sampling clock signal, comprising: sampling means for generating a first clock signal obtained by sampling a clock signal to be measured; clock signal generation means for generating a second clock signal having a set frequency; discrimination means for calculating a difference between the frequency of the first clock signal from a predetermined time and the frequency of the second clock signal; integration means for calculating an integrated value obtained by integrating the difference for each predetermined measurement period; adjustment means for adjusting the set value so that the absolute value of the integrated value becomes smaller, and outputting the adjusted set value as the new set value to the clock signal generation means and externally; A clock signal measurement apparatus comprising the above.

2. The clock signal generation means uses an expected value of the clock signal to be measured as an initial value of the set value. The discrimination means calculates the difference obtained by subtracting the frequency of the second clock signal from the frequency of the first clock signal. When the integrated value is a positive value, the adjustment means adjusts the set value to be a larger value, and when the integrated value is a negative value, the adjustment means adjusts the set value to be a smaller value. The clock signal measurement apparatus according to Claim 1.

3. The clock signal generation means includes a numerically controlled oscillator or a voltage controlled oscillator. The clock signal measurement apparatus according to Claim 1 or Claim 2.

4. The apparatus further comprises phase output means for outputting the phase of the second clock signal indicated by the value of a counter included in the numerically controlled oscillator. The clock signal measurement apparatus according to Claim 3.

5. The apparatus further comprises tracking determination means for determining that the second clock signal can track the first clock signal when a value obtained by integrating the time during which the difference is 0 in the predetermined measurement period is equal to or greater than a threshold value. When the second clock signal cannot track the first clock signal, the adjustment means performs frequency pull-in processing by a loop filter provided therein. The clock signal measurement apparatus according to any one of Claims 1 to 4.

6. One or more detection apparatuses comprising the clock signal measurement apparatus according to any one of Claims 1 to 5, and event detection means for detecting the occurrence of an event to be detected and notifying the occurrence of the event to the clock signal measurement apparatus. Comprising the above. The clock signal measurement device further includes a time specifying means for specifying the detection time of the event based on the value of the first clock signal and the value of the second clock signal at the timing when the event detection means notifies the occurrence of the event. The clock signal measurement devices in one or more of the detection devices use the same measurement target clock signal representing time. Clock signal measurement system.

7. A plurality of the clock signal measurement devices according to any one of Claims 1 to 5 are provided. The measurement target clock signals used by the plurality of clock signal measurement devices are different from each other. The sampling clock signals used by the plurality of clock signal measurement devices are the same signal. Clock signal measurement system.

8. An information processing device operating in synchronization with a sampling clock signal generates a first clock signal obtained by sampling a measurement target clock signal, generates a second clock signal having a set value as a frequency, calculates a difference between the wave number of the first clock signal from a predetermined time and the wave number of the second clock signal, calculates an integrated value obtained by integrating the difference for each predetermined measurement period, adjusts the set value so that the absolute value of the integrated value becomes smaller, sets the adjusted set value as a new set value, and outputs the new set value to the outside. Clock signal measurement method.

9. A computer operating in synchronization with a sampling clock signal is caused to execute a sampling process for generating a first clock signal obtained by sampling a measurement target clock signal, a clock signal generation process for generating a second clock signal having a set value as a frequency, a discrimination process for calculating a difference between the wave number of the first clock signal from a predetermined time and the wave number of the second clock signal, an integration process for calculating an integrated value obtained by integrating the difference for each predetermined measurement period, and an adjustment process for adjusting the set value so that the absolute value of the integrated value becomes smaller, setting the adjusted set value as a new set value, and outputting the new set value to the outside and to the clock signal generation process. A clock signal measurement program for causing the above to be executed. ​ ​

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