Radio frequency transistor amplifier having enlarged and / or asymmetric source / drain regions for improved on-resistance performance

Abstract

The gallium nitride based RF transistor amplifier comprises a semiconductor layer structure 150 comprising a barrier layer 156 on a channel layer 154, first and second source / drain regions 164, 166 on the semiconductor layer structure, first and second source / drain contacts 124, 126 on the respective first and second source / drain regions, and a longitudinally extending gate finger 122 between the first and second source / drain contacts. The first and second source / drain contacts each have an inner sidewall facing the gate finger and an opposite outer sidewall. The first source / drain region extends a first distance from a lower edge of the inner sidewall of the first source / drain contact towards the second source / drain region and a second smaller distance from a lower edge of the outer sidewall of the first source / drain contact in a direction away from the second source / drain region along a lateral axis extending parallel to a plane defined by a top surface of the semiconductor layer structure.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 17 / 144,346, filed on January 8, 2021, the entire content of which is incorporated herein by reference.

[0002] The inventive concept described herein relates to microelectronic devices, and more particularly, gallium nitride-based radio frequency (“RF”) transistor amplifiers.

Background Art

[0003] Electrical circuits that operate at high frequencies such as conventional cellular communication frequency bands (0.5 - 2.7 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12 - 18 GHz), K-band (18 - 27 GHz), Ka-band (27 - 40 GHz), and V-band (40 - 75 GHz) and require high power handling capabilities are becoming more widespread. In particular, there is currently a high demand for RF transistor amplifiers used to amplify RF signals at frequencies of, for example, 500 MHz and above (including microwave frequencies). These RF transistor amplifiers often need to exhibit high reliability, good linearity, and handle high output power levels.

[0004] RF transistor amplifiers may be implemented in silicon or wide bandgap semiconductor materials such as silicon carbide (“SiC”) and group III nitride materials. As used herein, the term “wide bandgap” refers to semiconductor materials having a bandgap greater than 1.40 eV. As used herein, the term “group III nitride” refers to those semiconductor compounds formed between nitrogen and elements in group III of the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). This term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have an empirical formula in which 1 mole of nitrogen is combined with a total of 1 mole of group III elements.

[0005] Silicon-based RF transistor amplifiers are typically implemented using laterally diffused metal oxide semiconductor ("LDMOS") transistors. Silicon LDMOS RF transistor amplifiers can exhibit a high level of linearity and can be manufactured relatively inexpensively. Group III nitride-based RF transistor amplifiers are typically implemented as high electron mobility transistors ("HEMTs") and are used mainly in applications that require high power and / or high frequency operation where LDMOS RF transistor amplifiers may have inherent performance limitations.

[0006] An RF transistor amplifier may include one or more amplification stages, and each stage is typically implemented as a transistor amplifier. To increase the output power and current handling capability, RF transistor amplifiers are typically implemented in a "unit cell" configuration where a number of individual "unit cell" transistors are electrically arranged in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die", or may include multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0007] One important performance parameter for group III nitride-based RF transistor amplifiers is the drain-source resistance (R ds-on ) during on-state operation, which is commonly also referred to as the "on-resistance". The on-resistance can affect various performance parameters of the RF transistor amplifier, including the power added efficiency. Group III nitride-based RF transistor amplifiers also have various parasitic intrinsic capacitances within the device, including the drain-source capacitance ("C ds ") and the gate-drain capacitance ("C gd "). These parasitic intrinsic capacitances also affect the performance of the RF transistor amplifier.

[0008] FIG. 1 is a schematic cross-sectional view of a unit cell transistor 2 of a conventional group III nitride-based RF transistor amplifier. As shown in FIG. 1, the unit cell 2 includes a gate contact 22, a drain contact 24, and a source contact 26, each formed on the upper surface of a semiconductor layer structure 50. The gate contact 22 is positioned between the drain contact 24 and the source contact 26. A first interlayer insulating layer 30 electrically isolates the gate contact, the drain contact, and the source contacts 22, 24, 26 from each other. A second interlayer insulating layer 32 covers the gate contact 22, and a field plate 28 is formed on the second interlayer insulating layer 32. The field plate 28 may be positioned above the semiconductor layer structure 50 in a region between the gate contact 22 and the drain contact 24 and may overlap the gate contact 22 in the vertical direction. In this specification, when an axis perpendicular to the upper surface of the semiconductor layer structure of an RF transistor amplifier intersects both elements, another element and an element of the RF transistor amplifier are "vertically overlapping". The field plate 28 may be electrically connected to the source contact 26 by an electrical connection outside the cross-sectional view of FIG. 1. A passivation layer 34 covers the field plate 28.

[0009] The semiconductor layer structure 50 includes a substrate 52 and a plurality of epitaxial layers grown on the substrate 52. The epitaxial layers include at least a channel layer 54 and a barrier layer 56. The barrier layer 56 may include a moderately doped n-type semiconductor layer and may include one or more layers. A highly doped drain region 64 is formed under the drain contact 24, and a highly doped source region 66 is formed under the source contact 26. The highly doped drain region 64 and the highly doped source region 66 are each formed in the barrier layer 56 and may selectively extend into the channel layer 54. When the gate contact, the drain contact, and the source contacts 22, 24, 26 are connected to appropriate DC bias voltages and an RF signal is applied to the gate contact 22, a two-dimensional electron gas (2DEG) is induced in the channel layer 54 at the junction between the channel layer 54 and the barrier layer 56. The 2DEG functions as a highly conductive channel 62 that permits conduction between the source region 66 and the drain region 64. Summary of the Invention Means for Solving the Problems

[0010] According to an embodiment of the present invention, there is provided an RF transistor amplifier, comprising: a semiconductor layer structure including a gallium nitride-based channel layer and a gallium nitride-based barrier layer having a higher bandgap than the gallium nitride-based channel layer on the upper surface of the gallium nitride-based channel layer; a first source / drain region in the semiconductor layer structure; a second source / drain region in the semiconductor layer structure; a gate finger on the upper surface of the semiconductor layer structure, the gate finger having a longitudinal axis extending parallel to the upper surface of the semiconductor layer structure; a first source / drain contact on the first source / drain region, the first source / drain contact having an inner sidewall facing the gate finger and an outer sidewall opposite to the inner sidewall; and a second source / drain contact on the second source / drain region, the second source / drain contact having an inner sidewall facing the gate finger and an outer sidewall opposite to the inner sidewall. The first source / drain region extends along a lateral axis parallel to a plane defined by the upper surface of the semiconductor layer structure by a first distance from a lower edge of the inner sidewall of the first source / drain contact towards the second source / drain region, and extends by a second distance from a lower edge of the outer sidewall of the first source / drain contact in a direction away from the second source / drain region, and the first distance exceeds the second distance.

[0011] In an exemplary embodiment, the first distance may exceed the second distance by at least 50%, at least 100%, at least 150% or at least 200%.

[0012] In some embodiments, the second source / drain region may extend along the lateral axis by a third distance from a lower edge of the inner sidewall of the second source / drain contact towards the first source / drain contact, and the first distance exceeds the third distance by at least 100%.

[0013] In some embodiments, the first source / drain region may have a first width along a lateral axis, the second source / drain region may have a second width along the lateral axis, and the first width exceeds the second width.

[0014] In some embodiments, the ratio of a first distance to a distance between a lower edge of an inner sidewall of a first source / drain contact and a lower edge of a sidewall of a gate fin facing the first source / drain contact along the lateral axis is at least 0.1.

[0015] In some embodiments, the first distance is at least 0.3 micrometers and the doping density of the first source / drain region is at least 3×10 19 dopants / cm 3 .

[0016] In some embodiments, the position where the first source / drain region has a maximum depth is closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact. In such embodiments, the position of the peak doping density of the first source / drain region is closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

[0017] In some embodiments, the first source / drain region is a drain region and the first source / drain contact is a drain contact.

[0018] In some embodiments, the RF transistor amplifier may further comprise a field plate extending above the upper surface of the gate fingers, the field plate being electrically connected to one of the first and second source / drain contacts. The first source / drain region may not intersect a first plane disposed between the field plate and the lower surface of the first source / drain contact, the first plane being perpendicular to the upper surface of the semiconductor layer structure and perpendicular to the lateral axis.

[0019] According to a further embodiment of the present invention, there is provided an RF transistor amplifier comprising a semiconductor layer structure including a gallium nitride-based channel layer and a gallium nitride-based barrier layer having a higher bandgap than the gallium nitride-based channel layer on the upper surface of the gallium nitride-based channel layer. The first and second source / drain regions are formed in the semiconductor layer structure. The gate fingers are provided on the upper surface of the semiconductor layer structure, the gate fingers having a longitudinal axis extending parallel to the upper surface of the semiconductor layer structure. The first source / drain contact is provided on the first source / drain region, the first source / drain contact having an inner sidewall facing the gate fingers and an outer sidewall opposite the inner sidewall. The second source / drain contact is provided on the second source / drain region, the second source / drain contact having an inner sidewall facing the gate fingers and an outer sidewall opposite the inner sidewall. A first longitudinal axis extending through the center of the upper surface of the first source / drain region is closer to the first sidewall of the gate fingers than a second longitudinal axis extending through the center of the lower surface of the first source / drain contact.

[0020] In some embodiments, a third longitudinal axis extending through the center of the upper surface of the second source / drain region may be laterally aligned with a fourth longitudinal axis extending through the center of the lower surface of the second source / drain contact.

[0021] In some embodiments, a third longitudinal axis extending through the center of the upper surface of the second source / drain region may be closer to the second sidewall of the gate fin than a fourth longitudinal axis extending through the center of the lower surface of the second source / drain contact.

[0022] In some embodiments, the first source / drain region may be a drain region, and the first source / drain contact may be a drain contact. In such embodiments, the first source / drain region may extend a first distance from the lower edge of the inner sidewall of the first source / drain contact toward the gate fin, the second source / drain region may extend a third distance from the lower edge of the inner sidewall of the second source / drain contact toward the gate fin, and the first distance may exceed the third distance.

[0023] In some embodiments, the position of the peak doping density of the first source / drain region may be closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

[0024] In some embodiments, the position of the peak doping density of the first source / drain region may be at least 3×10 19 dopants / cm 3 or more.

[0025] In some embodiments, the position where the first source / drain region has a maximum depth may be closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

[0026] According to a further embodiment of the present invention, there is provided an RF transistor amplifier comprising a semiconductor layer structure including a gallium nitride-based channel layer and a gallium nitride-based barrier layer having a higher bandgap than the gallium nitride-based channel layer on the upper surface of the gallium nitride-based channel layer. First and second source / drain regions are formed in the semiconductor layer structure. Gate fingers are provided on the upper surface of the semiconductor layer structure, and the gate fingers have a longitudinal axis extending parallel to the upper surface of the semiconductor layer structure. A first source / drain contact is provided on the first source / drain region, and the first source / drain contact has an inner sidewall facing the gate fingers and an outer sidewall opposite the inner sidewall. A second source / drain contact is provided on the second source / drain region, and the second source / drain contact has an inner sidewall facing the gate fingers and an outer sidewall opposite the inner sidewall. The center of the upper surface of the first source / drain region is laterally offset from the center of the lower surface of the first source / drain contact by a first amount, and the center of the upper surface of the second source / drain region is laterally offset from the center of the lower surface of the second source / drain contact by a second amount different from the first amount.

[0027] In some embodiments, the second amount may be zero or approximately zero.

[0028] In some embodiments, the RF transistor amplifier may further include an intermetallic insulating layer on the upper surface of the semiconductor layer structure between the gate fingers and the first source / drain contact, and the center of the upper surface of the first source / drain region is in direct contact with the intermetallic insulating layer.

[0029] In some embodiments, the first source / drain contact may be a drain contact and the first source / drain region may be a drain region. In other embodiments, the first source / drain contact may be a source contact and the first source / drain region may be a source region.

[0030] In some embodiments, the width of the first source / drain region along the lateral axis may exceed the width of the second source / drain region along the lateral axis.

[0031] In some embodiments, the position of the peak doping density of the first source / drain region may be closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

[0032] In some embodiments, the inner edge of the upper surface of the first source / drain region may be 0.3 to 0.7 microns from the lower edge of the inner sidewall of the first source / drain contact. In such an embodiment, the outer edge of the upper surface of the first source / drain region may be less than 0.2 microns from the lower edge of the outer sidewall of the first source / drain contact.

[0033] In some embodiments, the position where the first source / drain region has a maximum depth may be closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

[0034] According to a further embodiment of the present invention, there is provided an RF transistor amplifier including a semiconductor layer structure including a gallium nitride-based channel layer and a gallium nitride-based barrier layer having a higher bandgap than the gallium nitride-based channel layer on the upper surface of the gallium nitride-based channel layer. First and second source / drain regions are formed in the semiconductor layer structure. A gate finger is provided on the upper surface of the semiconductor layer structure, and the gate finger has a longitudinal axis extending parallel to the upper surface of the semiconductor layer structure. A first source / drain contact is provided on the first source / drain region, and the first source / drain contact has an inner sidewall facing the gate finger and an outer sidewall opposite to the inner sidewall. A second source / drain contact is provided on the second source / drain region, and the second source / drain contact has an inner sidewall facing the gate finger and an outer sidewall opposite to the inner sidewall. An insulating layer in direct contact with the semiconductor layer structure is provided, including a first portion between the first source / drain contact and the gate finger and a second portion between the second source / drain contact and the gate finger. A first area where the first portion of the insulating layer overlaps the first source / drain region in the vertical direction is larger than a second area where the second portion of the insulating layer overlaps the second source / drain region in the vertical direction.

[0035] In some embodiments, the first area is at least 50% or at least 100% larger than the second area.

[0036] In some embodiments, the first portion of the insulating layer may overlap in the vertical direction with a position where the first source / drain region has a maximum depth.

[0037] In some embodiments, the first portion of the insulating layer may overlap in the vertical direction with a position where the first source / drain region has a peak doping density.

[0038] In some embodiments, the first source / drain contact may be a drain contact, the first source / drain region may be a drain region, the second source / drain contact may be a source contact, and the second source / drain region may be a source region. In such embodiments, the RF transistor amplifier may further include a field plate extending above the upper surface of the gate fingers, and the field plate is electrically connected to the source contact. The field plate may not overlap the drain region in the vertical direction.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0040] Referring back to FIG. 1, the drain contact 24 has an inner sidewall 25-1 facing the gate contact 22 and an outer sidewall 25-2 facing a first adjacent unit cell (not shown). Similarly, the source contact 26 has an inner sidewall 27-1 facing the gate contact 22 and an outer sidewall 27-2 facing a second adjacent unit cell (not shown). Also as shown in FIG. 1, the conduction path between the source region 66 and the drain region 64 includes three primary regions (or segments when viewed in cross-section) and two additional regions / segments. The on-resistance for the unit cell transistor 2 may be defined as the resistance of these five regions / segments.

[0041] The three primary regions / segments are each disposed along a channel 62 formed at the junction between the channel layer 54 and the barrier layer 56. In FIG. 1, the first primary region / segment denoted by the reference letter L GS refers to a portion of the channel that extends from below the lower edge of the inner sidewall 27-1 of the source contact 26 to below the lower edge of the sidewall of the gate contact 22 facing the source contact 26. In FIG. 1, the second primary region / segment denoted by the reference letter L G refers to a portion of the channel 62 that extends from below the lower edge of the sidewall of the gate contact 22 facing the source contact 26 to below the lower edge of the sidewall of the gate contact 22 facing the drain contact 24. In FIG. 1, the third primary region / segment denoted by the reference letter L GD refers to a portion of the channel 62 that extends from below the lower edge of the sidewall of the gate contact 22 facing the drain contact 24 to below the lower edge of the inner sidewall 25-1 of the drain contact 24.

[0042] In FIG. 1, the first additional region / segment denoted by the reference letter L S refers to the vertical distance from the bottom of the source contact 26 to the junction between the channel layer 54 and the barrier layer 56. In FIG. 1, the reference letter L DThe second additional region / segment shown by refers to the vertical distance from the bottom of the drain contact 24 to the junction between the channel layer 54 and the barrier layer 56. Usually, the portion of the barrier layer 56 between the source region 66 and the drain region 64 is doped less severely than the source region and the drain regions 66, 64. Therefore, the primary segments L GS 、L G 、L GD usually have a higher sheet resistance than the additional segments L S 、L D and the primary segments L GS 、L G 、L GD usually are significantly longer than the additional segments L S 、L D . Thus, the on-resistance may be determined primarily by the resistance of the three primary regions / segments L GS 、L G 、L GD .

[0043] The on-resistance can be reduced, for example, by reducing the size of the unit cell transistor 2 by reducing the length of segment L GS and / or L GD . However, reducing the length of segment L GS and / or L GD acts to increase the intrinsic parasitic capacitances C gd and / or C ds . In particular, the intrinsic gate-drain capacitance C gd is mainly a function of the capacitive coupling between the gate contact 22 and the drain contact 24. Thus, reducing the length of segment L GD acts to increase both of the intrinsic parasitic capacitances C gd and C ds . The intrinsic drain-source capacitance C dsis mainly a function of (1) the capacitive coupling between the drain contact 24 and the source contact 26 and (2) the capacitive coupling between the drain contact 24 and the field plate 28 (because the field plate 28 is electrically connected to the source contact 26). Thus, reducing the length of segment L GS acts to increase the intrinsic parasitic capacitance C ds . Therefore, an inherent trade-off exists between the on-resistance and the parasitic intrinsic capacitances C gd , C ds in the group-III nitride-based RF transistor amplifier. In particular, the on-resistance can be reduced by shrinking the size of the unit cell, but this results in an increase in the intrinsic parasitic capacitances C gd , C ds . The reverse is also true, i.e., the parasitic intrinsic capacitances C gd , C ds can be reduced by increasing the size of each unit cell transistor, but this increases the on-resistance.

[0044] At very high frequencies (e.g., frequencies above 10 GHz), particularly for a multistage RF transistor amplifier implemented on a single die as a monolithic microwave integrated circuit or "MMIC" device, it can be difficult to impedance-match the inner stages of the multistage RF transistor amplifier. The difficulty in impedance-matching the inner stages of these amplifiers can be due, at least in part, to the intrinsic parasitic capacitances within the individual RF transistor amplifier stages. The degraded impedance matching can reduce the gain, drain efficiency, and power-added efficiency of the RF transistor amplifier.

[0045] According to an embodiment of the present invention, there is provided a group-III nitride-based RF transistor amplifier that can exhibit a lower on-resistance value without any significant increase in the parasitic intrinsic capacitances C gd and C ds . As described above, the parasitic intrinsic capacitances C gd and C dsThe value is driven almost exclusively by various capacitive couplings between the gate contact 22, each of which is a large metal structure, the drain contact 24, the source contact 26, and the field plate 28. On the other hand, the capacitive coupling between the drain region 64 and the gate contact 22 has little effect on C gd and similarly, the capacitive coupling between the source region 66 and the gate contact 22 has little effect on C ds . Further, due to the higher doping levels of the drain region and the source regions 64, 66 compared to the channel region 62 therebetween, the resistance of the drain region and the source regions 64, 66 can be significantly smaller than the resistance of the channel region 62. Thus, the on-resistance can be reduced by expanding the drain region and / or the source regions 64, 66 so as to extend closer to each other. This is because this effectively replaces a portion of the higher-resistance channel region 62 with the lower-resistance drain region and / or source regions 64, 66. Further, since the capacitive coupling between the gate contact 22 and the drain region and the source regions 64, 66 can be ignored (unless the drain region and the source regions 64, 66 come extremely close to the gate contact 22), the reduction in on-resistance can be achieved without any significant increase in the parasitic capacitance C gd or C ds . In other words, replacing a portion of the channel region 62 with an extension of the drain region 64 or the source region 66 reduces the on-resistance without changing the size of the unit cell 2 (i.e., without changing the relative positions of the gate contact 22, the drain contact 24, the source contact 26, and the field plate 28), and thus does not act to significantly increase the parasitic capacitance.

[0046] III-nitride-based RF transistor amplifiers according to some embodiments of the present invention may have an asymmetric drain region that extends further beyond the lower edge of the inner sidewall of the drain contact toward the source region than beyond the lower edge of the outer sidewall of the drain contact in a direction away from the source region. These RF transistor amplifiers may additionally or alternatively have an asymmetric source region that extends further beyond the lower edge of the inner sidewall of the source contact toward the drain region than beyond the lower edge of the outer sidewall of the source contact in a direction away from the drain region. In an exemplary embodiment, the magnitude of these asymmetries may be at least 25%, at least 50%, at least 100%, at least 200%, at least 300% or at least 400%. For example, the drain region may extend twice as far beyond the lower edge of the inner sidewall of the drain contact toward the source region as beyond the lower edge of the outer sidewall of the drain contact in a direction away from the source region, resulting in an asymmetry of 100%.

[0047] III-nitride-based RF transistor amplifiers according to embodiments of the present invention may also have an asymmetry with respect to how far the drain region and the source region extend toward each other beyond the lower edges of the inner sidewalls of their respective drain and source contacts. For example, the drain region may extend further beyond the lower edge of the inner sidewall of the drain contact toward the source region compared to how far the source region extends beyond the lower edge of the inner sidewall of the source contact toward the drain region.

[0048] In some embodiments, the drain region may not extend far enough beyond the lower edge of the inner sidewall of the drain contact toward the source region such that the field plate overlaps the drain region in the vertical direction.

[0049] III-nitride-based RF transistor amplifiers according to embodiments of the present invention may exhibit a reduced on-resistance value and, thus, may exhibit a higher drain current during on-state operation. Further, this improvement in on-resistance may be achieved without a significant increase in the gate-drain or drain-source parasitic capacitance because the distances between the gate contact, the drain contact, and the source contact cannot change. Thus, the reduction in on-resistance may be obtained without any significant reduction in the gain, drain efficiency, or power-added efficiency of the RF transistor amplifier.

[0050] According to an embodiment of the present invention, there is provided an RF transistor amplifier including a semiconductor layer structure including a gallium nitride-based channel layer and a gallium nitride-based barrier layer having a higher bandgap than the gallium nitride-based channel layer on an upper surface of the gallium nitride-based channel layer. Spaced-apart first and second source / drain regions are provided in the semiconductor layer structure. A gate finger is provided on the upper surface of the semiconductor layer structure, and the gate finger has a longitudinal axis extending parallel to the upper surface of the semiconductor layer structure. The first and second source / drain regions extend longitudinally on the upper surface of the semiconductor layer structure. A first source / drain contact is on the first source / drain region and has an inner sidewall facing the gate finger and an outer sidewall opposite the inner sidewall, and a second source / drain contact is on the second source / drain region and has an inner sidewall facing the gate finger and an outer sidewall opposite the inner sidewall. The gate finger is disposed between the first source / drain contact and the second source / drain contact.

[0051] In some embodiments, the first source / drain region extends a first distance from the lower edge of the inner sidewall of the first source / drain contact along a lateral axis extending parallel to the plane defined by the upper surface of the semiconductor layer structure towards the second source / drain region, and extends a second distance from the lower edge of the outer sidewall of the first source / drain contact in a direction away from the second source / drain region, and the first distance exceeds the second distance. The first distance may exceed the second distance by at least 25%, at least 50%, at least 100%, at least 200%, at least 300% and at least 400% in various embodiments of the present invention.

[0052] In some embodiments, a first longitudinal axis extending through the center of the upper surface of the first source / drain region is closer to the first sidewall of the gate fin than a second longitudinal axis extending through the center of the lower surface of the first source / drain contact.

[0053] In some embodiments, the center of the upper surface of the first source / drain region is laterally offset by a first amount from the center of the lower surface of the first source / drain contact, and the center of the upper surface of the second source / drain region is laterally offset by a second amount different from the first amount from the center of the lower surface of the second source / drain contact.

[0054] In some embodiments, the center of the upper surface of the second source / drain region is laterally aligned with the center of the lower surface of the second source / drain contact. In other embodiments, the center of the upper surface of the second source / drain region is laterally offset from the center of the lower surface of the second source / drain contact. The position where the first source / drain region has a maximum depth may be closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

[0055] In some embodiments, the first source / drain region is the drain region and the second source / drain region is the source region. In other embodiments, the first source / drain region is the source region and the second source / drain region is the drain region.

[0056] In some embodiments, the ratio of the first distance to the distance between the lower edge of the inner sidewall of the first source / drain contact and the lower edge of the sidewall portion of the gate fin facing the first source / drain contact along the lateral axis is at least 0.1.

[0057] In some embodiments, the second source / drain region extends along the lateral axis by a third distance from the lower edge of the inner sidewall of the second source / drain contact towards the first source / drain contact. The first distance may exceed the third distance by at least 25%, at least 50%, at least 100%, at least 200% and at least 300% in various embodiments of the present invention.

[0058] In some embodiments, the first source / drain region has a first width along the lateral axis, the second source / drain region has a second width along the lateral axis, and the first width exceeds the second width.

[0059] In some embodiments, the first distance may be at least 0.3 microns. The position where the first source / drain region has the maximum depth may be closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact. The peak doping density of the first source / drain region may be closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

[0060] In some embodiments, the RF transistor amplifier may include an insulating layer on the top surface of the semiconductor layer structure. This insulating layer may be in direct contact with the semiconductor layer structure and may include a first portion between the first source / drain contact and the gate finger and a second portion between the second source / drain contact and the gate finger. The first area where the first portion of the insulating layer overlaps the first source / drain region in the vertical direction may be larger than the second area where the second portion of the insulating layer overlaps the second source / drain region in the vertical direction. For example, the first area may be at least 50% or at least 100% larger than the second area. The first portion of the insulating layer may overlap in the vertical direction with the position where the first source / drain region has a maximum depth and / or may overlap in the vertical direction with the position where the first source / drain region has a peak doping density. Two elements are considered to "overlap in the vertical direction" if an axis perpendicular to the bottom surface of the semiconductor layer structure extends through both elements.

[0061] Embodiments of the present invention will be described in more detail below with reference to FIGS. 2A to 9B.

[0062] FIG. 2A is a schematic perspective view of a unit cell 102 of a group III nitride-based RF transistor amplifier according to an embodiment of the present invention. As shown in FIG. 2A, the unit cell 102 includes a gate contact 122, a drain contact 124, and a source contact 126, each formed on the upper surface of a semiconductor layer structure 150. The longitudinal axes of each of the gate contact, drain contact, and source contacts 122, 124, 126 extend parallel to each other in the longitudinal direction L, and the gate contact 122 is disposed between the drain contact 124 and the source contact 126 along the transverse direction T. In the present specification, the gate contact 122 may be referred to as a "gate finger" 122. In the present specification, the drain contact and the source contacts 124, 126 may generally be referred to as "source / drain contacts". The term "source / drain contact" is understood to refer to either a source contact or a drain contact. A first intermetallic insulating layer 130 electrically isolates the gate contact, drain contact, and source contacts 122, 124, 126 from each other. A second intermetallic insulating layer 132 covers the gate contact 122, and a field plate 128 is formed on the second intermetallic insulating layer 132. The field plate 128 may be disposed above the semiconductor layer structure 150 in the region between the gate contact 122 and the drain contact 124 and may overlap the gate contact 122. The field plate 128 may be electrically connected to the source contact 126 by an electrical connection outside the cross-sectional view of FIG. 2A.

[0063] The semiconductor layer structure 150 includes a substrate 152 and a plurality of epitaxial layers grown on the substrate 152. The epitaxial layers include at least a channel layer 154 and a barrier layer 156. The barrier layer 156 may be a moderately doped n-type semiconductor layer (or a multilayer structure). A highly doped drain region 164 is formed under the drain contact 124, and a highly doped source region 166 is formed under the source contact 126. The highly doped drain region 164 and the highly doped source region 166 may be formed in the barrier layer 156 and, optionally, may extend into the channel layer 154. The drain region 164 and the source region 166 may each have a maximum doping density of, for example, at least 1×10 19 dopants / cm 3 . In some embodiments, the maximum doping density of the drain region 164 and the source region 166 may each be at least 3×10 19 dopants / cm 3 , at least 5×10 19 dopants / cm 3 or at least 1×10 20 dopants / cm 3 . The drain region 164 and the source region 166 may have a uniform doping density, for example, except at their peripheries. The edges of the drain region 164 and the source region 166 are regions where the doping density is 2.5 orders of magnitude lower than the peak doping density. In this specification, the drain region and the source region 164, 166 may generally be referred to as the "source / drain region." It will be understood that the term "source / drain region" may refer to either the source region or the drain region.

[0064] The gate contact, drain contact, and source contacts 122, 124, 126 are connected to appropriate DC bias voltages, and when an RF signal is applied to the gate contact 122, a two-dimensional electron gas (2DEG) is induced in the channel layer 154 at the junction between the channel layer 154 and the barrier layer 156. The 2DEG acts as a highly conductive channel 162 (also referred to herein as the "channel region 162") that permits conduction between the source region 166 and the drain region 164.

[0065] As can be seen by comparing FIG. 1 and FIG. 2A, the unit cell 102 of FIG. 2A differs from the conventional unit cell 2 of FIG. 1 in that the drain region 164 extends more significantly toward the source region 166 than the drain region 64 extends toward the source region 66. Further, in some embodiments, only one side of the drain region 164, i.e., the side closest to the corresponding source region 166 of the unit cell 102, may be enlarged. As a result, when looking at the unit cell 102 from above, the drain region 164 may be asymmetric with respect to the drain contact 124.

[0066] FIG. 2B is a schematic cross-sectional view taken along line 2B-2B of FIG. 2A. The cross-sectional view of FIG. 2B is taken along a plane defined by the upper surface of the semiconductor layer structure 150. For clarity, the positions of the bottoms of the gate contact, drain contact, and source contacts 122, 124, 126 are shown in FIG. 2B, but these contacts are actually just above the cross-section of FIG. 2B. FIG. 2C is an enlarged view of the portion of FIG. 2B outlined in the dotted box indicated by reference numeral 2C in FIG. 2B.

[0067] As shown in FIG. 2B, the unit cell 102 of the group III nitride-based RF transistor amplifier 100 has a conduction path between the source region 166 and the drain region 164, and carriers pass through this conduction path when an appropriate bias voltage is applied to the device. This conduction path is shown in FIG. 2B and consists of a total of six regions (or segments when viewed in cross-section), namely, four primary regions / segments L GS , L G , L GD1 , L GD2 and two additional regions / segments L S , L D . The regions / segments L GS , L G , L S and L D may be the same as the corresponding regions / segments of the conventional unit cell 2 described above with reference to FIG. 1, and therefore, further description thereof is omitted. As further shown in FIG. 2B, the region / segment L GD of the conventional unit cell 2 is replaced by two regions / segments L GD1 , L GD2 in the unit cell 102. The region / segment L GD1 corresponds generally to the region / segment L GD of the conventional unit cell 2, except that the region / segment L GD1 is narrower than the region / segment L GD of the conventional unit cell 2. The region / segment L GD2 corresponds to the distance by which the drain region 164 extends beyond the lower edge of the inner sidewall 125-1 of the drain contact 124. In a conventional device, this distance is usually extremely small (e.g., 0.1 micron or less) and is therefore not individually labeled in the conventional unit cell 2 of FIG. 1. However, in the RF transistor amplifier according to an embodiment of the present invention, the distance L GD2 is increased in order to reduce the on-resistance of the unit cell 102.

[0068] Referring to FIG. 2C, the drain region 164 in the unit cell 102 of the RF transistor amplifier according to an embodiment of the present invention extends a first distance D beyond the lower edge of the inner sidewall 125-1 of the drain contact 124 toward the gate finger 122 when viewed from above (i.e., along an axis perpendicular to the upper surface of the semiconductor layer structure 150). 1 extends only by. In some embodiments, the first distance D 1 may be at least 0.25 microns, at least 0.3 microns, at least 0.4 microns, at least 0.5 microns or at least 0.6 microns. The drain region 164 may extend a second distance D beyond the lower edge of the outer sidewall 125-2 of the drain contact 124 in a direction away from the gate finger 122 when viewed from above. 2 extends only by. In some embodiments, the second distance D 2 may be less than 0.2 microns, less than 0.1 microns or less than 0.05 microns, and in some embodiments, the drain region 164 may not extend beyond the lower edge of the outer sidewall 125-2 of the drain contact 124. If the drain region 164 does not completely extend to the lower edge of the outer sidewall 125-2 of the drain contact 124, it may be considered to extend a negative distance beyond the lower edge of the outer sidewall 125-2 of the drain contact 124 in a direction away from the gate finger 122 (i.e., the distance D 2 is a negative number). In such embodiments, as long as the first distance D 1 is a positive number (i.e., as long as the drain region 164 extends beyond the lower edge of the inner sidewall 125-1 of the drain contact 124 toward the gate finger 122), the first distance D 1 exceeds the second distance D 2 .

[0069] Generally speaking, the second distance D 2 does not significantly affect the performance of the device. This is because any portion of the drain region 164 that extends beyond the lower edge of the outer sidewall 125-2 of the drain contact 124 is not part of the conduction path during device operation. Conventionally, the second distance D 2is kept small (e.g., 0.1 micron or less) to enhance the breakdown performance of the device and / or to enable increased device integrity (i.e., packing the unit cells 102 closer together).

[0070] As seen in FIG. 2B, the first distance D 1 is significantly greater than the second distance D 2 . Since the first distance D 1 is greater than the corresponding first distance of a conventional device, the on-resistance of the RF transistor amplifier according to an embodiment of the present invention can be smaller than the on-resistance of a conventional RF transistor amplifier. However, if the first distance D 1 is increased too much (i.e., the drain region 164 begins to get too close to the gate contact 122), the breakdown voltage of the RF transistor amplifier 100 can start to decrease significantly. Thus, in some embodiments, the first distance D 1 can be, for example, 0.25 to 0.8 microns in some embodiments, 0.3 to 0.7 microns in other embodiments, 0.4 to 0.6 microns in other embodiments, and 0.3 to 0.5 microns in still other embodiments. In an exemplary embodiment, the drain region 164 extends at least 25% further beyond the lower edge of the inner sidewall 125-1 of the drain contact 124 (i.e., the sidewall facing the source contact 126 of the unit cell 102) than the drain region 164 extends beyond the lower edge of the outer sidewall 125-2 of the drain contact 124. In other embodiments, the drain region 164 can extend at least 50%, at least 100%, at least 200%, at least 300% or at least 400% further beyond the lower edge of the inner sidewall 125-1 of the drain contact 124 than the drain region 164 extends beyond the lower edge of the outer sidewall 125-2 of the drain contact 124.

[0071] As shown in FIG. 2B, when viewed from above (i.e., along an axis perpendicular to the top surface of the semiconductor layer structure 150), the source region 166 extends a third distance D beyond the lower edge of the inner sidewall 127-1 of the source contact 126 towards the gate fin 122. 3 In an exemplary embodiment, the first distance D 1 may exceed the third distance D by at least 100%, at least 200%, at least 300% or at least 400%. 3

[0072] As shown in FIG. 2B, the lateral axis A 1 extends along the top surface of the semiconductor layer structure 150. The gate contact 122, the drain contact 124 and the source contact 126 each extend longitudinally (direction L) on the top surface of the semiconductor layer structure 150. The lateral axis A 1 extends in a lateral direction T perpendicular to the longitudinal axes of the gate contact, the drain contact and the source contact 122, 124, 126. The first distance D 1 includes the distance along the lateral axis A 1 . The second distance D 2 similarly includes the distance along the lateral axis A 1 .

[0073] As shown in FIG. 2C, the drain region 164 has a maximum width W (generally occurring on or immediately below the top surface of the semiconductor layer structure 150). As shown in FIG. 2B, the source region 166 has a maximum width W (also generally occurring on or immediately below the top surface of the semiconductor layer structure 150). The maximum width W of the drain region 164 1 exceeds the maximum width W of the source region 166. 2 1 2

[0074] The distances L GD1 and L GD2The total may be 2.0 to 5.0 microns in some embodiments and 3.0 to 4.0 microns in other embodiments. In some embodiments, L GD2 / L GD1 The ratio may be at least 0.1. In other embodiments, L GD2 / L GD1 The ratio may be at least 0.13, or at least 0.15, or at least 0.17.

[0075] As shown in FIG. 2C, the drain region 164 may have a maximum depth D in the vertical direction V that is approximately in the middle of the drain region 164 in the horizontal direction T. M The position where the drain region 164 reaches the maximum depth D M may be closer to the lower edge of the inner sidewall 125-1 of the drain contact 124 than to the lower edge of the outer sidewall 125-2 of the drain contact 124. This position may overlap the first inter-metal insulating layer 130 in the vertical direction. In contrast, the position where the drain region 64 of a conventional unit cell reaches its depth overlaps the bottom surface of the drain contact 24 in the vertical direction and is not below the first inter-metal insulating layer 30.

[0076] The position of the peak doping density of the drain region 164 may be closer to the lower edge of the inner sidewall 125-1 of the first drain contact 124 than to the lower edge of the outer sidewall 125-2 of the drain contact 124.

[0077] A first longitudinal axis A extending through the center of the upper surface of the drain region 164 L1 is closer to the lower edge of the sidewall facing the gate fin 122 than a second longitudinal axis A extending through the center of the lower surface of the drain contact 124. L2 In contrast, a third longitudinal axis A extending through the center of the upper surface of the source region 166 L3 is at the same distance from the lower edge of the sidewall facing the gate fin 122 as a fourth longitudinal axis A extending through the center of the lower surface of the source contact 126. L4

[0078] Referring back to FIG. 2A, a first intermetallic insulating layer 130 is formed directly on the upper surface of the semiconductor layer structure 150. The first intermetallic insulating layer 130 includes a first portion between the drain contact 124 and the gate finger 122 and a second portion between the source contact 126 and the gate finger 122. The first area where the first portion of the first intermetallic insulating layer 130 overlaps the drain region 164 in the vertical direction is larger than the second area where the second portion of the first intermetallic insulating layer 130 overlaps the source region 166 in the vertical direction. The first area may be at least 50% larger than the second area, but generally is significantly larger than the second area (e.g., 2 times, 5 times, or even 10 times larger). The first portion of the first intermetallic insulating layer 130 may overlap in the vertical direction with the position where the drain region 164 has the maximum depth and / or the position where the drain region 164 has the peak doping density.

[0079] As described above, any significant increase in the drain-source parasitic capacitance C ds can adversely affect the performance of the RF transistor amplifier 100. The drain contact 124 and the source contact 126 are widely spaced apart, so they do not tend to capacitively couple to each other significantly. However, the field plate 128 is electrically connected to the source, so any coupling between the drain contact 124 and the field plate 128 contributes to C ds Although the drain region 164 is at a different level from the field plate 128 in the device structure, there is a possibility of capacitive coupling between the drain region 164 and the field plate 128, especially when the field plate 128 overlaps the drain region 164 in the vertical direction. Thus, in some embodiments of the present invention, the drain region 164 extends vertically from the lower edge of the inner sidewall 125-1 of the drain contact 124 to a first longitudinally extending plane P that contacts the edge of the field plate 128 closest to the drain region 164 with respect to the upper surface of the semiconductor layer structure 150 1 up to a transverse axis A 1 along a distance smaller than the transverse axis A1 extends only along the distance along. The plane P extending in the first longitudinal direction 1 is graphically shown in FIG. 2A. This ensures that the field plate 128 does not overlap the drain region 164 in the vertical direction, and helps to ensure that the parasitic capacitance C is not significantly increased by the expansion of the drain region 164. ds is not significantly increased.

[0080] The enlarged drain region 164 may be formed using conventional manufacturing techniques, except that the ion implantation mask used to perform the ion implantation step to form the drain region 64 of the conventional device may be enlarged to form the enlarged drain region 164. In the two unit cells of a conventional RF transistor amplifier, the ion implantation mask may have an opening having a width substantially equal to the width of the bottom surface of the drain contact 24. As a result, the drain region 64 has a width that is only slightly larger than the width of the lower surface of the drain contact 24, and the maximum doping density of the drain region 64 is below the center of the lower surface of the drain contact 24 (in the lateral direction T). In contrast, the ion implantation mask used to form the unit cell 102 of the RF transistor amplifier 100 may have an opening that extends closer to, for example, the gate contact 122, whereby the center of the drain region 164 is on the lower side of the intermetal dielectric layer 130, opposite to the lower side of the lower surface of the drain contact 124.

[0081] The use of source / drain regions that extend beyond the lower edge of the inner sidewalls of the source / drain contacts is known in the art. In particular, MOSFETs that always have ultrashort channel regions are formed to have a normal drain region below the drain contact and a so-called "lightly doped drain region" that extends inward from the normal drain region toward the gate contact. These lightly doped drain regions are typically (1) doped at a lower concentration than the normal drain region and (2) have a shallower depth than the normal drain region. The provision of the lightly doped drain region reduces the electric field in the channel in the vicinity of the normal drain region, which can reduce the hot carrier injection effect. In the hot carrier injection effect, carriers acquire sufficient kinetic energy and the carriers can be injected into the gate dielectric layer of the MOSFET, where the carriers can degrade the gate dielectric layer, which can lead to adverse effects such as increased leakage current and / or early breakdown of the gate dielectric layer. In such devices, a lightly doped source region is also typically provided to simplify manufacturing.

[0082] The enlarged source / drain regions included in the RF transistor amplifier according to an embodiment of the present invention may be provided for a completely different purpose, namely, to reduce the on-resistance of the RF transistor amplifier without significantly increasing the parasitic capacitance of the device. In addition, the enlarged source / drain regions included in the RF transistor amplifier according to an embodiment of the present invention may have a different shape compared to the lightly doped drain regions (shallower than the normal drain region) used in conventional MOSFETs and may have a different doping density compared to the lightly doped drain regions used in conventional MOSFETs (i.e., the enlarged drain regions disclosed herein may have a higher doping density and may have a generally uniform doping density both below the lower surface of the drain contact and below the intermetal dielectric layer).

[0083] Figures 3A to 3C are various diagrams schematically showing a group III nitride RF transistor amplifier die 100 including the unit cell 102 described above with reference to FIG. 2. In particular, FIG. 3A is a schematic plan view of the RF transistor amplifier die 100. In FIG. 3A, only the lowermost portion of the metallization formed on the upper surface of the semiconductor layer structure 150 is shown. FIGS. 3B and 3C are schematic cross-sectional views of the RF transistor amplifier die 100 taken along lines 3B-3B and 3C-3C of FIG. 3A, respectively. FIGS. 3A to 3C (and many of the other drawings of the present application) are highly simplified diagrams, and it will be appreciated that an actual RF transistor amplifier may include many more unit cells as well as various circuits and elements not shown in the simplified drawings herein.

[0084] As shown in FIG. 3A, the RF transistor amplifier die 100 includes an upper metallization structure 110 formed on the semiconductor layer structure 150. The upper metallization structure 110 includes a gate bus 112 and a drain bus 114, a plurality of gate fingers 122, a plurality of drain contacts, and a plurality of source contacts 126, all of which are formed on the upper surface of the semiconductor layer structure 150. The gate fingers 122, the drain contacts 124, and the source contacts 126 may extend parallel to each other, the gate fingers 122 extending from the gate bus 112 in a first direction, and the drain contacts 124 extending from the drain bus 114 in a direction opposite to the first direction. Each gate finger 122 may be disposed between the drain contact 124 and the source contact 126.

[0085] The gate bus 112 and the gate fingers 122 may be implemented as a first monolithic metal pattern. The gate fingers 122 may be formed from a material capable of forming a Schottky contact to a group III nitride-based semiconductor material, such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. The gate bus 112 and the gate fingers 122 are part of the gate electrode structure of the RF transistor amplifier die 100. The upper portion (not shown) of the gate electrode may function as the gate terminal of the RF transistor amplifier die 100. A first circuit element (not shown) may be connected to the gate terminal, for example, by a bond wire (not shown). The first circuit arrangement may transmit an input RF signal to be amplified to the RF transistor amplifier die 100.

[0086] The drain bus 114 and the drain contacts 124 may be implemented as a second monolithic metal pattern. The drain contacts 124 may include a metal such as TiAlN capable of forming a resistive contact to a group III nitride-based material. The drain bus 114 and the drain contacts 124 are part of the drain electrode of the RF transistor amplifier die 100. The upper portion (not shown) of the drain electrode may function as the drain terminal of the RF transistor amplifier die 100. A second circuit element (not shown) may be connected to the drain terminal, for example, by a bond wire (not shown). The second circuit element may receive the amplified RF signal output by the RF transistor amplifier die 100. The gate terminal and the drain terminal are not shown in FIG. 3A.

[0087] The source contact 126 may include a metal such as TiAlN that can form a resistive contact to the Group-III nitride-based material. The source contact 126 may be physically and electrically connected to a source terminal (not shown) of the RF transistor amplifier die 100 disposed on the bottom side of the semiconductor layer structure 150 by a plurality of metal-plated source vias 146. Each metal-plated source via 146 may extend from the upper metallization structure 110 through the semiconductor layer structure 150. Each metal-plated source via 146 may be implemented by forming an opening through the semiconductor layer structure 150 (e.g., by anisotropic etching) and then depositing a metal plating that coats the sidewalls of the opening. In some applications, the metal may completely fill the opening such that the metal-plated via is a metal-filled via. However, in many applications, the RF transistor amplifier die 100 may operate over a wide temperature range (due to high levels of heat that may occur within the RF transistor amplifier die 100 during outdoor use and / or device operation), which can lead to high stress levels in the device due to the significantly different coefficients of thermal expansion of the metal and semiconductor materials. In such cases, the center of the metal-plated source via 146 may remain open (i.e., air-filled) in order to reduce the amount of stress caused by thermal cycling. In some cases, it will also be recognized that the source terminal may be formed on the top surface of the semiconductor layer structure 150, in which case the via 146 may be omitted.

[0088] As described above with reference to FIGS. 2A-2B, various inter-metal insulation layers and / or passivation layers 130, 132, 134 may be formed to isolate the gate metallizations 112, 122, the drain metallizations 114, 124, and the source metallization 126 from each other. The inter-metal insulation layers and / or passivation layers 130, 132, 134 may include a dielectric material such as SiN, SiO 2 and the like.

[0089] The RF transistor amplifier die 100 includes a plurality of unit cell transistors 102, one of which has been described above with reference to FIGS. 2A to 2C. The positions of the unit cell transistors 102 in FIGS. 2A to 2C are shown by dotted boxes in FIG. 3A. The unit cell transistor 102 includes the gate finger 122, a part of the drain contact 124 and a part of the source contact 126 together with a part of the semiconductor layer structure 150 located under the identified gate finger 122, drain contact 124 and source contact 126. Since all the gate fingers 122 are electrically connected to a common gate bus 112, all the drain contacts 124 are electrically connected to a common drain bus 114, and all the source contacts 126 are electrically connected to a common source terminal, it can be seen that all the unit cell transistors 102 are electrically connected in parallel.

[0090] The RF transistor amplifier die 100 may include a group-III nitride-based HEMT RF transistor amplifier. Suitable structures for group-III nitride-based HEMT devices that may utilize embodiments of the present invention are described, for example, in U.S. Patent Application Publication No. 2002 / 0066908, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride-based Cap Segment And Methods Of Fabricating Same", published on January 6, 2002, U.S. Patent Application Publication No. 2002 / 0167023, entitled "Group-III Nitride-based High Electron Mobility Transistor(HEMT) With Barrier / Spacer Layer", published on November 14, 2002, U.S. Patent Application Publication No. 2004 / 0061129, entitled "Nitride-based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses", published on April 1, 2004, U.S. Patent No. 7,906,799, entitled "Nitride-Based Transistors With A Ptotective Layer And A Low-Damage Recess", issued on March 15, 2011, and U.S. Patent No. 6,316,793, entitled "Nitride-based Transistors On Semi-Insulating Silicon Carbide Substrates", issued on November 13, 2001, the disclosures of which are hereby incorporated by reference in their entirety.

[0091] Figures 3B and 3C show the semiconductor layer structure 150 in more detail. As shown in Figures 3B and 3C, the semiconductor layer structure 150 includes a plurality of semiconductor layers. In the illustrated embodiment, a total of two semiconductor layers are shown, namely, a channel layer 154 and a barrier layer 156 on top of the channel layer 154. The semiconductor layer structure 150 may (and usually does) include additional semiconductor and / or non-semiconductor layers. For example, the semiconductor layer structure 150 may include a growth substrate 152 on which other semiconductor layers are grown. The growth substrate 152 may include, for example, a 4H-SiC or 6H-SiC substrate. In other embodiments, the growth substrate 152 may include different semiconductor materials (e.g., silicon or group III nitride-based materials, GaAs, ZnO, InP) or non-semiconductor materials (e.g., sapphire). Even if the growth substrate 152 is formed from a non-semiconductor material, it is considered to be part of the semiconductor layer structure 150.

[0092] Optional buffer, nucleation and / or transition layers (not shown) may be provided on the growth substrate 152 below the channel layer 154. For example, an AlN buffer layer may be included to provide an appropriate crystal structure transition between the SiC growth substrate 152 and the rest of the semiconductor layer structure 150. Additionally, a strain balancing transition layer may also be provided as described, for example, in U.S. Patent Application Publication No. 2003 / 0102482 to the same applicant, entitled "Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Blanaced Nitride Heterojunction Transistors", published on June 5, 2003, the disclosure of which is incorporated herein by reference as if fully set forth herein.

[0093] In some embodiments, assuming that at the interface between the channel layer and the barrier layers 154, 156, the energy of the conduction band edge of the channel layer 154 is less than the energy of the conduction band edge of the barrier layer 156, the channel layer 154 is Al with 0 ≦ x < 1 x Ga1-x It is a group III nitride material such as N. In an embodiment of the present invention, x = 0 indicates that the channel layer 154 is gallium nitride ("GaN"). The channel layer 154 may be other group III nitrides such as InGaN, AlInGaN, etc. The channel layer 154 may be undoped or unintentionally doped, and may be grown to a thickness greater than about 20 Å, for example. The channel layer 154 may be a multilayer structure such as a superlattice or combination of GaN, AlGaN or the like.

[0094] The channel layer 154 may have a bandgap smaller than at least a part of the bandgap of the barrier layer 156, and the channel layer 154 may also have a larger electron affinity than the barrier layer 156. In an embodiment, the barrier layer 156 is AlN, AlInN, AlGaN or AlInGaN having a thickness of about 0.1 nm to about 10 nm or more. In a specific embodiment, the barrier layer 156 is thick enough and has a high Al composition and doping to induce a significant carrier concentration at the interface between the channel layer 154 and the barrier layer 156.

[0095] The barrier layer 156 may be a group III nitride and may have a larger bandgap than that of the channel layer 154 and a smaller electron affinity than that of the channel layer 154. Thus, in an embodiment of the present invention, the barrier layer 156 may include AlGaN, AlInGaN and / or AlN or a combination of those layers. The barrier layer 156 may have a thickness of, for example, about 0.1 nm to about 30 nm. In an embodiment, the barrier layer 156 is undoped or doped with an n-type dopant at a concentration less than about 10 19 cm -3 -. In some embodiments of the present invention, the barrier layer 156 is Al x Ga 1-xIt is N. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 156 comprises AlGaN having an aluminum concentration of about 5% to about 100%. In certain embodiments of the present invention, the aluminum concentration is greater than about 10%.

[0096] Due to the difference in bandgap between the barrier layer 156 and the channel layer 154 and the piezoelectric effect at the interface between the barrier layer 156 and the channel layer 154, a two-dimensional electron gas (2DEG) is induced in the channel layer 154 at the junction between the channel layer 154 and the barrier layer 156. The 2DEG functions as a highly conductive layer that allows conduction between the source region and its associated drain region of each unit cell transistor 102.

[0097] FIG. 4 is a schematic perspective view of a unit cell 202 of a group III nitride-based RF transistor amplifier die according to a further embodiment of the present invention. The unit cell 202 is very similar to the unit cell 102 of FIGS. 2A-2C, except that the unit cell 202 has (1) a drain region 64 having a conventional design of the unit cell 2 (FIG. 1) and (2) an enlarged source region 266. The following description focuses on the differences between the unit cell 202 and the unit cell 102.

[0098] As shown in FIG. 4, the source region 266 extends a third distance D beyond the lower edge of the inner sidewall 127-1 of the source contact 126 towards the gate finger 122 when viewed from above 3 by. In some embodiments, the third distance D 3 may be at least 0.25 microns, at least 0.3 microns or at least 0.4 microns. The source region 266 may extend a fourth distance D beyond the lower edge of the outer sidewall 127-2 of the source contact 126 in a direction away from the gate finger 122 when viewed from above 4 by. In some embodiments, the fourth distance D 4may be less than 0.2 microns, less than 0.1 microns, or less than 0.05 microns. In some embodiments, the source region 266 may not extend beyond the lower edge of the outer sidewall 127-2 of the source contact 126. Generally speaking, the fourth distance D 4 does not significantly affect the performance of the device. This is because any portion of the source region 266 that extends beyond the lower edge of the outer sidewall 127-2 of the source contact 126 is not part of the conduction path during device operation. Conventionally, the fourth distance D 4 is kept small (e.g., 0.1 microns or less).

[0099] As also shown in FIG. 4, the third distance D 3 may exceed the fourth distance D 4 . The third distance D 3 is formed larger than the corresponding third distance of the conventional unit cell 2 of FIG. 1, so the on-resistance of the unit cell 202 may be reduced. However, if the third distance D 3 is increased too much (i.e., the source region 266 begins to approach the gate contact 122 too closely), the breakdown voltage of the device may start to decrease significantly. Thus, in some embodiments, the third distance D 3 may be, for example, 0.25 to 0.5 microns in some embodiments and 0.3 to 0.5 microns in other embodiments. In an exemplary embodiment, the source region 266 extends at least 25%, at least 50%, at least 100%, or at least 200% further beyond the lower edge of the inner sidewall 127-1 of the source contact 126 than the source region 266 extends beyond the lower edge of the outer sidewall 127-2 of the source contact 126.

[0100] As also shown in FIG. 4, the drain region 64 extends by a first distance D 1 beyond the lower edge of the inner sidewall 125-1 of the drain contact 124 towards the gate fin 122 when viewed from above. The third distance D 3In an exemplary embodiment, it may exceed the first distance D by at least 50%, at least 100%, or at least 200%. 1 It may exceed.

[0101] The source region 266 has a maximum width W 2 whereas the drain region 64 has a maximum width W 1 The maximum width W of the source region 266 2 exceeds the maximum width W of the drain region 64 1 The position of the peak doping density of the source region 266 may be closer to the lower edge of the inner sidewall 127-1 of the source contact 124 than to the lower edge of the outer sidewall 127-2 of the source contact 126.

[0102] The source region 266 may have a maximum depth D in the vertical direction V at approximately the middle of the source region 266 in the lateral direction T M The position where the source region 266 reaches the maximum depth D M may be closer to the lower edge of the inner sidewall 127-1 of the source contact 126 than to the lower edge of the outer sidewall 127-2 of the source contact 126. This position may overlap with the first inter-metal insulating layer 130 in the vertical direction.

[0103] FIG. 5 is a schematic perspective view of a unit cell 302 of a group III nitride-based RF transistor amplifier die according to yet another embodiment of the present invention. The unit cell 302 is very similar to the unit cell 102 of FIGS. 2A-2C, except that the unit cell 302 includes an enlarged source region 266 of the unit cell 202 such that the unit cell 302 has both an enlarged drain region 164 and an enlarged source region 266. Since all aspects of the unit cell 302 have been described above with respect to the unit cell 102 or the unit cell 202, further description thereof is omitted.

[0104] The technology disclosed above can be particularly advantageous in an implementation form where an RF transistor amplifier is implemented as a monolithic microwave integrated circuit (MMIC). An MMIC refers to an integrated circuit that operates in radio and / or microwave frequency signals, in which all circuits for specific functions are integrated on one semiconductor chip. An exemplary MMIC device is a transistor amplifier that includes associated matching circuits, a power supply network, etc., all mounted on a common substrate. An MMIC RF transistor amplifier typically includes a plurality of unit cell HEMT transistors connected in parallel.

[0105] FIG. 6 is a plan view of an MMIC RF transistor amplifier 400 according to an embodiment of the present invention. As shown in FIG. 6, the MMIC RF transistor amplifier 400 includes an integrated circuit chip 430 contained within a package 410. The package 410 may include a protective housing that surrounds and protects the integrated circuit chip 430. The package 410 may be formed of, for example, a ceramic material. The package 410 includes an input lead 412 and an output lead 418. The input lead 412 may be attached to an input lead pad 414, for example, by soldering. One or more input bond wires 420 may electrically connect the input lead pad 414 to an input bond pad on the integrated circuit chip 430.

[0106] The integrated circuit chip 430 includes an input power supply network 438, an input impedance matching network 450, a first RF transistor amplifier stage 460, an intermediate impedance matching network 440, a second RF transistor amplifier stage 462, an output impedance matching stage 470, and an output power supply network 482. The package 410 further includes output leads 418 connected, for example, by soldering to the output lead pads 416. One or more output bond wires 490 may electrically connect the output lead pads 416 to output bond pads on the integrated circuit chip 430. The first RF transistor amplifier stage 460 and / or the second RF transistor amplifier stage 462 may be implemented using any of the RF transistor amplifiers according to embodiments of the present invention.

[0107] RF transistor amplifiers according to embodiments of the present invention may be designed to operate in a variety of different frequency bands. In some embodiments, these RF transistor amplifier dies may be configured to operate in at least one of the frequency bands of 0.6 - 2.7 GHz, 3.4 - 4.2 GHz, 5.1 - 5.8 GHz, 12 - 18 GHz, 18 - 27 GHz, 27 - 40 GHz, or 40 - 75 GHz or sub-portions thereof. The techniques according to embodiments of the present invention may be particularly advantageous for RF transistor amplifiers operating at frequencies above 10 GHz.

[0108] Figures 7A and 7B are graphs showing the simulated performance of the RF transistor amplifiers of Figures 2A - 3C. In particular, Figure 7A is a graph of the drain current I d during on-state operation as a function of the drain voltage V d for the RF transistor amplifiers of Figures 2A - 3C compared to the conventional RF transistor amplifier of Figure 1 (effectively showing the on-state resistance of the device), and Figure 7B is the drain-source capacitance C dsIt is a graph of responses. As can be seen in FIG. 7A, an RF transistor amplifier according to an embodiment of the present invention (whose performance is indicated by the small square) shows an increased drain current for the same drain voltage as compared to a conventional RF transistor amplifier (whose performance is indicated by the small circle). From FIG. 7A, it can be seen that a reduction of about 5% in on-resistance was achieved by expanding the drain region to extend closer by only an additional 0.4 microns to the gate fingers. FIG. 7B shows the drain-source capacitance response for two RF transistor amplifiers used to generate FIG. 7A. As shown, an RF transistor amplifier according to an embodiment of the present invention (solid curve) shows only a slight increase in drain-source capacitance as compared to a conventional RF transistor amplifier.

[0109] As described above, an RF transistor amplifier according to an embodiment of the present invention can be particularly useful in an MMIC device including a plurality of amplifier stages. FIGS. 8A-8C show a plurality of examples of a multistage MMIC device in which the techniques according to embodiments of the present invention can be used.

[0110] First, referring to FIG. 8A, an RF transistor amplifier 500A including a preamplifier 510 and a main amplifier 530 electrically connected in series is schematically shown. As shown in FIG. 8A, the RF transistor amplifier 500A includes an RF input 501, a preamplifier 510, an inter-stage impedance matching network 520, a main amplifier 530, and an RF output 502. The inter-stage impedance matching network 520 may include inductors and / or capacitors arranged in any suitable configuration to form a circuit for improving impedance matching between the output of the preamplifier 510 and the input of the main amplifier 530. Although not shown in FIG. 8A, the RF transistor amplifier 500A may further include an input matching network arranged between the RF input 501 and the preamplifier 510, and / or an output matching network arranged between the main amplifier 530 and the RF output 502. An RF transistor amplifier according to an embodiment of the present invention may be used to implement one or both of the preamplifier 510 and the main amplifier 530.

[0111] Referring to FIG. 8B, an RF transistor amplifier 500B including an RF input 501, a pair of preamplifiers 510-1, 510-2, a pair of inter-stage impedance matching networks 520-1, 520-2, a pair of main amplifiers 530-1, 530-2, and an RF output 502 is schematically shown. A splitter 503 and a combiner 504 are also provided. The preamplifier 510-1 and the main amplifier 530-1 (electrically connected in series) are electrically arranged in parallel with the preamplifier 510-2 and the main amplifier 530-2 (electrically connected in series). Similar to the RF transistor amplifier 500A of FIG. 8A, the RF transistor amplifier 500B may further include an input matching network disposed between the RF input 501 and the preamplifiers 510-1, 510-2, and / or an output matching network disposed between the main amplifiers 530-1, 530-2 and the RF output 502.

[0112] As shown in FIG. 8C, an RF transistor amplifier according to an embodiment of the present invention may be used to implement a Doherty amplifier. As is known in the art, a Doherty amplifier circuit includes first and second (or more) power combining amplifiers. The first amplifier is referred to as the "main" or "carrier" amplifier, and the second amplifier is referred to as the "peaking" amplifier. The two amplifiers may be biased differently. For example, the main amplifier may include a class AB or class B amplifier, while the peaking amplifier may be a class C amplifier in one common Doherty amplifier implementation. The Doherty amplifier can operate more efficiently than a balanced amplifier when operating at a power level backed off from saturation. The RF signal input to the Doherty amplifier is split (e.g., using a quadrature coupler), and the outputs of the two amplifiers are combined. The main amplifier is configured to be turned on first (i.e., at a lower input power level), whereby only the main amplifier operates at a lower power level. As the input power level increases towards saturation, the peaking amplifier turns on, and the input RF signal is split between the main amplifier and the peaking amplifier.

[0113] As shown in FIG. 8C, Doherty RF transistor amplifier 500C includes an RF input 501, an input splitter 503, a main amplifier 540, a peaking amplifier 550, an output combiner 504, and an RF output 502. The Doherty RF transistor amplifier 500C may optionally include an input matching network and / or an output matching network (not shown). The main amplifier 540 and / or the peaking amplifier 550 may be implemented using any of the above-described RF transistor amplifiers according to embodiments of the present invention.

[0114] FIGS. 9A and 9B are schematic cross-sectional views showing a plurality of exemplary ways in which an RF transistor amplifier die according to embodiments of the present invention may be packaged to provide packaged RF transistor amplifiers 600A and 600B, respectively.

[0115] FIG. 9A is a schematic side view of a packaged group-III nitride-based RF transistor amplifier 600A. As shown in FIG. 9A, the packaged RF transistor amplifier 600A includes an RF transistor amplifier die 100 packaged in an open cavity package 610A. The package 610A includes a metal gate lead 622A, a metal drain lead 624A, a metal submount 630, sidewalls 640, and a lid 642.

[0116] The submount 630 may include materials configured to assist in the thermal management of the package 600A. For example, the submount 630 may include copper and / or molybdenum. In some embodiments, the submount 630 may consist of multiple layers and / or may include vias / interconnections. In an exemplary embodiment, the submount 630 may be a multi-layer copper / molybdenum / copper metal flange including a core molybdenum layer with copper cladding layers on its respective major surfaces. In some embodiments, the submount 630 may include a metal heat sink that is part of a lead frame or a metal slug. The sidewalls 640 and / or the lid 642 may be formed from an insulating material or may include an insulating material in some embodiments. For example, the sidewalls 640 and / or the lid 642 may be formed from or may include a ceramic material. In some embodiments, the sidewalls 640 and / or the lid 642 may be formed from, for example, Al 2 O 3 from. The lid 642 may be adhered to the sidewalls 640 using an epoxy adhesive. The sidewalls 640 may be attached to the submount 630, for example, via brazing. The gate lead 622A and the drain lead 624A may be configured to extend through the sidewalls 640, but embodiments of the present invention are not limited thereto.

[0117] The RF transistor amplifier die 100 is mounted on the upper surface of the metal submount 630 in an air-filled cavity 612 defined by the metal submount 630, the ceramic sidewall 640, and the ceramic lid 642. The gate terminal and the drain terminal of the RF transistor amplifier die 100 may be on the upper side of the semiconductor layer structure 150, while the source terminal is on the bottom side of the semiconductor layer structure 150. The gate lead 622A may be connected to the gate terminal of the RF transistor amplifier die 100 by one or more bond wires 654. Similarly, the drain lead 624A may be connected to the drain terminal of the RF transistor amplifier die 100 by one or more bond wires 654. The source terminal may be mounted on the metal submount 630 using, for example, a conductive die attachment material (not shown). The metal submount 630 may provide an electrical connection to the source terminal 136 and may function as a heat dissipation structure for dissipating heat generated by the RF transistor amplifier die 100. Heat is mainly generated in the upper portion of the RF transistor amplifier die 100 where a relatively high current density is generated in the channel region of the unit cell transistor 102. This heat may be transferred to the source terminal through the source via 146 and the semiconductor layer structure 150, and then to the metal submount 630.

[0118] FIG. 9B is a schematic side view of another packaged group III nitride-based RF transistor amplifier 600B. The RF transistor amplifier 600B is different from the RF transistor amplifier 600A in that it includes a different package 610B. The package 610B includes the metal submount 630 and the metal gate and drain leads 622B, 624B. The RF transistor amplifier 600B also includes a plastic overmold 660 that at least partially surrounds the RF transistor amplifier die 100, the leads 622B, 624B, and the metal submount 630. Other components of the RF transistor amplifier 600B may be the same as the components of the RF transistor amplifier 600A with the same reference numerals, and thus, further description thereof is omitted.

[0119] Embodiments of the present invention have been described above with respect to gallium nitride-based RF transistor amplifiers, but it will be appreciated that the embodiments of the present invention are not limited thereto. For example, the transistors described above may be used as power transistors in switching and other applications.

[0120] Embodiments of the present invention have been described above with reference to the accompanying drawings in which embodiments of the invention are shown. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the inventive concept to those skilled in the art. Like numbers refer to like elements throughout.

[0121] In this specification and the drawings, two-part reference numerals (i.e., 100-1, etc., two numbers separated by a dash) may be used to identify the same element. When such two-part reference numerals are used, the complete reference numeral may be used to refer to a particular instance of the element, whereas the first part of the reference numeral may be used to refer to the element collectively.

[0122] Terms such as first, second, etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0123] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used in this specification, the terms "comprises", "comprising", "includes" and / or "including" indicate the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0124] When an element such as a layer, region or substrate is described as being "on" or extending "onto" another element, it will be understood that it can be directly on or extend directly onto the other element or intervening elements may be present. In contrast, when an element is described as being "directly on" or extending "directly onto" another element, no intervening elements are present. When an element is described as being "connected" or "coupled" to another element, it will also be understood that it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0125] Relative terms such as "under", "above", "upper", "lower", "horizontal", "lateral" or "vertical" may be used in this specification to describe the relationship of one element, layer or region to another element, layer or region as shown in the drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the drawings.

[0126] In the drawings and specification, typical embodiments of the invention are disclosed and specific terms are used, but these terms are used for descriptive purposes only and not for limitation, and the scope of the invention is set forth in the following claims.

Claims

1. A transistor comprising: a semiconductor layer structure including a gallium nitride-based channel layer and a gallium nitride-based barrier layer having a higher bandgap than the gallium nitride-based channel layer on an upper surface of the gallium nitride-based channel layer; an intermetallic insulating layer on the gallium nitride-based barrier layer; a first source / drain region in the semiconductor layer structure; a second source / drain region in the semiconductor layer structure; a gate finger on an upper surface of the semiconductor layer structure, the gate finger having a longitudinal axis extending parallel to the upper surface of the semiconductor layer structure, the gate finger being disposed between the first source / drain contact and the second source / drain contact; a first source / drain contact on the first source / drain region and a second source / drain contact on the second source / drain region, the first source / drain contact having an inner sidewall facing the second source / drain contact and an outer sidewall opposite to the inner sidewall, the second source / drain contact having an inner sidewall facing the first source / drain contact and an outer sidewall opposite to the inner sidewall; a field plate extending above an upper surface of the gate finger, the field plate being electrically connected to one of the first and second source / drain contacts, the first source / drain region not intersecting a first plane disposed between the field plate and a lower surface of the first source / drain contact, the first plane being perpendicular to the upper surface of the semiconductor layer structure and perpendicular to the lateral axis; and comprising. The first source / drain region extends along a lateral axis parallel to a plane defined by the upper surface of the semiconductor layer structure by a first distance from a lower edge of the inner sidewall of the first source / drain contact toward the second source / drain region, and extends along the lateral axis by a second distance from a lower edge of the outer sidewall of the first source / drain contact in a direction away from the second source / drain region, the first distance exceeding the second distance, A transistor in which a center of an upper surface of the first source / drain region is in direct contact with the intermetallic insulating layer. **Claim 2** The transistor according to claim 1, wherein the first distance exceeds the second distance by at least three times. **Claim 3** The transistor according to any one of claims 1 to 2, wherein the second source / drain region extends along the lateral axis by a third distance from a lower edge of the inner sidewall of the second source / drain contact toward the first source / drain contact, and the first distance exceeds the third distance by at least 100%. **Claim 4** The transistor according to any one of claims 1 to 2, wherein the first source / drain region has a first width along the lateral axis, the second source / drain region has a second width along the lateral axis, and the first width exceeds the second width. **Claim 5** The transistor according to any one of claims 2 to 4, wherein a ratio of the first distance to a distance between a lower edge of the inner sidewall of the first source / drain contact and a lower edge of a sidewall of the gate fin facing the first source / drain contact along the lateral axis is at least 0.

1. **Claim 6** A transistor comprising: a semiconductor layer structure including a gallium nitride-based channel layer and a gallium nitride-based barrier layer having a higher bandgap than the gallium nitride-based channel layer on an upper surface of the gallium nitride-based channel layer; an intermetallic insulating layer on the gallium nitride-based barrier layer; a first source / drain region in the semiconductor layer structure; a second source / drain region in the semiconductor layer structure; A gate finger on the upper surface of the semiconductor layer structure, the gate finger having a longitudinal axis extending parallel to the upper surface of the semiconductor layer structure, A first source / drain contact on the first source / drain region and a second source / drain contact on the second source / drain region, the first source / drain contact having an inner sidewall facing the second source / drain contact and an outer sidewall opposite the inner sidewall, and the second source / drain contact having an inner sidewall facing the first source / drain contact and an outer sidewall opposite the inner sidewall, the first source / drain contact on the first source / drain region and the second source / drain contact on the second source / drain region, comprising, The first source / drain region extends a first distance from the lower edge of the inner sidewall of the first source / drain contact along a lateral axis extending parallel to the plane defined by the upper surface of the semiconductor layer structure toward the second source / drain region, and extends a second distance from the lower edge of the outer sidewall of the first source / drain contact in a direction away from the second source / drain region, the first distance exceeding the second distance, The center of the upper surface of the first source / drain region is in direct contact with the intermetallic insulating layer, The first distance is at least 0.3 microns, and the doping density of the first source / drain region is at least 3×10 １９ dopants / cm ３ for a transistor.

7. The transistor according to claim 6, wherein the position of the peak doping density of the first source / drain region is closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

8. The transistor according to any one of claims 1 to 5, wherein the first source / drain region is a drain region and the first source / drain contact is a drain contact.

9. The transistor according to claim 1, wherein the position having the maximum depth of the first source / drain region is closer to the lower edge of the inner sidewall of the first source / drain contact than to the lower edge of the outer sidewall of the first source / drain contact.

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