Semiconductor integrated circuit, image reading device, image forming device, and camera system

Abstract

To accurately execute timing adjustment between circuit blocks each including an analog circuit that performs sequential operation.SOLUTION: A semiconductor integrated circuit has: a first circuit block including a first analog circuit that outputs an analog signal based on a first control signal generated by a first logical circuit based on a clock signal; and a second circuit block including a second logical circuit that generates a second control signal based on a first delay clock signal generated by a first delay circuit in which a delay amount is adjusted according to a delay adjustment signal, a second analog circuit that acquires the analog signal output from the first analog circuit with the second control signal, a second delay circuit that has a delay time determined from reception of the clock signal and output of the first control signal performed by the first logical circuit and generates a second delay clock signal based on the clock signal, and a delay adjustment circuit that generates a delay adjustment signal for adjusting the phase of the second control signal and the phase of the second delay clock signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, an image reading apparatus, an image forming apparatus, and a camera system.

Background Art

[0002] In a semiconductor integrated circuit having a plurality of processing circuits including a sample and hold circuit, a technique is known in which a timing signal is supplied in order from a subsequent processing circuit to a preceding processing circuit to ensure a timing margin between the processing circuits (see, for example, Patent Document 1).

Summary of the Invention

Problems to be Solved by the Invention

[0003] When sequentially shifting the operation cycles of a plurality of processing circuits, it is possible to ensure a timing margin in each processing circuit by delaying the supply of the timing signal for the processing circuit on the preceding stage side. However, when sequentially operating a plurality of processing circuits within a clock cycle, it is difficult to accurately set the supply timing of the timing signal to each processing circuit by a delay circuit or the like. This is because the delay time of the delay circuit also varies due to variations in the manufacturing process of the semiconductor integrated circuit on which the processing circuit is mounted. For example, in order to accurately set the supply timing of the timing signal, it is necessary to mount a redundant delay circuit on each processing circuit. This increases the circuit scale and cost.

[0004] The disclosed technology has been made in view of the above problems, and an object thereof is to accurately perform timing adjustment between circuit blocks each including a processing circuit that operates sequentially.

Means for Solving the Problems

[0005] To solve the above technical problem, a semiconductor integrated circuit according to one embodiment of the present invention includes a first logic circuit that outputs a first control signal based on a clock signal, and a first analog circuit that operates based on the first control signal and outputs an analog signal, a first circuit block including the first analog circuit, a first delay circuit that delays the clock signal to generate a first delayed clock signal and whose delay amount is adjusted according to a delay adjustment signal, a second logic circuit that generates a second control signal based on the first delayed clock signal, a second analog circuit that acquires the analog signal output by the first analog circuit by the second control signal, a second delay circuit that has a delay time corresponding to a time determined by reception of the clock signal by the first logic circuit and output of the first control signal and generates a second delayed clock signal based on the clock signal, and a delay adjustment circuit that receives the second control signal and the second delayed clock signal and generates the delay adjustment signal for the phase of the second control signal and the phase of the second delayed clock signal, a second circuit block including the delay adjustment circuit, and is characterized by having the second circuit block. to The phase of the second delayed clock signal match with for the phase of the second control signal and the phase of the second delayed clock signal, and includes a second circuit block including the delay adjustment circuit, and is characterized by having the second circuit block.

Advantages of the Invention

[0006] Timing adjustment between circuit blocks each including a processing circuit that operates sequentially can be accurately performed.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, the same reference numerals as the signal names and clock names are used for the signal lines and clock lines, respectively. In each drawing, the same reference numerals are given to the same components, and duplicate descriptions may be omitted.

[0009] (First Embodiment of Semiconductor Integrated Circuit) FIG. 1 is a block diagram showing a first embodiment of the semiconductor integrated circuit of the present invention. The semiconductor integrated circuit 100 shown in FIG. 1 has circuit blocks 10 and 20. The circuit block 10 has a logic circuit 12 that generates a hold signal HLD based on a clock signal CLK, and an analog circuit 14 that operates based on the hold signal HLD and outputs an analog output signal AOUT corresponding to an analog input signal AIN.

[0010] The analog circuit 14 is an example of a first analog circuit. For example, the analog circuit 14 includes an amplifier, amplifies the voltage of the analog input signal AIN, and outputs the amplified voltage as the analog output signal AOUT. The circuit block 10 is an example of a first circuit block, and the circuit block 20 is an example of a second circuit block. The logic circuit 12 is an example of a first logic circuit, and the hold signal HLD is an example of a first control signal.

[0011] The circuit block 20 includes a delay circuit 21, a logic circuit 22, an analog circuit 23, a logic circuit 12', and a DLL (Delay-Locked Loop) circuit 24. The delay circuit 21 is an example of a first delay circuit, and the logic circuit 22 is an example of a second logic circuit. The analog circuit 23 is an example of a second analog circuit, and the logic circuit 12' is an example of a second delay circuit. The DLL circuit 24 is an example of a delay adjustment circuit. The symbol td indicates the wiring delay of the clock signal CLK from the vicinity of the logic circuit 12' to the vicinity of the logic circuit 12.

[0012] The delay circuit 21 adjusts the delay amount of the clock signal CLK based on the delay adjustment signal ADJ and generates a delayed clock signal CLK1. The logic circuit 22 generates a sampling signal SMPL for operating the analog circuit 23 based on the delayed clock signal CLK1. The delayed clock signal CLK1 is an example of a first delayed clock signal. The sampling signal SMPL is an example of a second control signal.

[0013] The analog circuit 23 operates in synchronization with the sampling signal SMPL and acquires the output signal AOUT output from the analog circuit 14. The analog circuit 23 outputs the acquired output signal AOUT to the outside of the circuit block 20 as a data signal DATA. For example, the analog circuit 23 includes an AD (Analog-to-Digital) converter, converts the voltage value of the output signal AOUT into a digital value, and outputs the converted digital value as the data signal DATA.

[0014] The logic circuit 12' is, for example, a replica of the logic circuit 12. The logic circuit 12' has a delay time corresponding to the time determined by the reception of the clock signal CLK by the logic circuit 12 and the output of the hold signal HLD. Based on the clock signal CLK, the logic circuit 12' outputs a delayed clock signal CLK2 at the same timing as the hold signal HLD output by the logic circuit 12. The delayed clock signal CLK2 is an example of a second delayed clock signal. For example, in order to reduce power consumption, the logic circuit 12' masks the operation of non-logic logic existing on the path from the input terminal of the clock signal CLK to the output terminal of the delayed clock signal CLK2.

[0015] Note that the logic circuit 12' may be composed of a delay circuit as long as the delay time from the input of the clock signal CLK to the output of the delayed clock signal CLK2 is the same as the timing (delay time) from the input of the clock signal CLK of the logic circuit 12 to the output of the hold signal HLD. However, by using a replica of the logic circuit 12 as the logic circuit 12', the delayed clock signal CLK2 can be output at the same timing as the hold signal HLD regardless of the variations in the manufacturing process of the semiconductor integrated circuit 100.

[0016] The DLL circuit 24 generates a delay adjustment signal ADJ for aligning the phase of the sampling signal SMPL and the phase of the delayed clock signal CLK2. In this embodiment, the replica logic circuit 12' and the DLL circuit 24 can make the generation timings of the hold signal HLD and the sampling signal SMPL substantially the same. Thereby, the analog circuit 23 can acquire the output signal AOUT output from the analog circuit 14 in synchronization with the sampling signal SMPL set at an appropriate timing.

[0017] Figure 2 is a timing diagram showing an example of the operation of the semiconductor integrated circuit of Figure 1. In Figure 2, the description of the clock signal CLK, the delayed clock signals CLK1, CLK2, the input signal AIN, and the delay adjustment signal ADJ is omitted. In Figure 2, the sampling signal SMPL shown within the braces indicates an example when the timing with respect to the hold signal HLD is shifted.

[0018] The analog circuit 14 in FIG. 1 starts an amplification operation in synchronization with the rising edge of the hold signal HLD, and increases the voltage of the output signal AOUT by amplifying the voltage of the input signal AIN (not shown). The analog circuit 14 performs the amplification operation of the input signal AIN during the period when the hold signal HLD is at a high level.

[0019] The analog circuit 23 in FIG. 1 samples the output signal AOUT during the high-level period of the sampling signal SMPL, and converts the voltage of the sampled output signal AOUT into a digital value. The analog circuit 23 determines the voltage value of the output signal AOUT in synchronization with the falling edge of the sampling signal SMPL, and outputs the determined voltage value as a data signal DATA.

[0020] In this embodiment, the falling edge of the hold signal HLD and the falling edge of the sampling signal SMPL are at the same timing. In reality, the output signal AOUT output from the analog circuit 14 is delayed in reaching the analog circuit 23 due to the wiring delay of the output signal line AOUT. As a result, the analog circuit 23 can obtain the output signal AOUT sufficiently amplified during the high-level period of the hold signal HLD by the sampling signal SMPL that falls slightly earlier than the falling edge of the hold signal HLD (FIG. 2(a)).

[0021] On the other hand, for example, assume that the delay circuit 21, the logic circuit 12', and the DLL circuit 24 are not formed in the circuit block 20, and the sampling signal SMPL is generated by the delay element of the logic circuit 22. In this case, due to variations in the manufacturing process of the semiconductor integrated circuit 100, the timing (phase) of the sampling signal SMPL with respect to the hold signal HLD may shift.

[0022] When the falling edge of the sampling signal SMPL is delayed compared to the falling edge of the hold signal HLD, the analog circuit 23 cannot acquire the output signal AOUT (Fig. 2(b)). When the falling edge of the sampling signal SMPL is earlier than the falling edge of the hold signal HLD, the analog circuit 23 may acquire the output signal AOUT before it is sufficiently amplified (Fig. 2(c)).

[0023] Fig. 3 is a block diagram showing an example of another semiconductor integrated circuit. In the circuit block 10 of the semiconductor integrated circuit 110 shown in Fig. 3, a logic circuit 22' and a delay circuit 16 are added to the circuit block 10 of Fig. 1. In the circuit block 20 of the semiconductor integrated circuit 110, the delay circuit 21 and the DLL circuit 24 are removed from the circuit block 20 of Fig. 1, and the connection relationship of the logic circuits 12', 22 is changed.

[0024] The circuit block 10 has a logic circuit 12, a logic circuit 22' which is a replica of the logic circuit 22, a delay circuit 16, and an analog circuit 14 connected in series. The circuit block 20 has a logic circuit 12', a logic circuit 22, and an analog circuit 23 connected in series. By arranging replicas in both of the circuit blocks 10 and 20, the timings of the signals output from the logic circuit 22' of the circuit block 10 and the signals output from the logic circuit 22 of the circuit block 20 become the same as each other.

[0025] Therefore, the hold signal HLD is output with a delay corresponding to the delay time of the delay circuit 16 with respect to the sampling signal SMPL. However, when replicas of the logic circuit 12 (or the logic circuit 22) are arranged in both of the circuit blocks 10 and 20, the timing variation due to the manufacturing process variation of the semiconductor integrated circuit 100 becomes larger than when no replica is arranged. For this reason, considering the timing variation, the delay time of the delay circuit 16 is set longer than when no replica is arranged. As a result, when the falling edge of the sampling signal SMPL becomes earlier than, for example, the timing (c) shown in Fig. 2, there is a possibility of acquiring the output signal AOUT before it is sufficiently amplified.

[0026] In the above first embodiment, the replica logic circuit 12' and the DLL circuit 24 can make the generation timings of the hold signal HLD and the sampling signal SMPL the same. As a result, the analog circuit 23 can acquire the output signal AOUT output from the analog circuit 14 in synchronization with the sampling signal SMPL set at an appropriate timing. Consequently, the accuracy of the generation timings of the hold signal HLD and the sampling signal SMPL can be improved.

[0027] By generating the delayed clock signal CLK2 using the replica of the logic circuit 12 instead of a CR time constant circuit or the like, the delayed clock signal CLK2 can be output at the same timing as the hold signal HLD regardless of variations in the manufacturing process of the semiconductor integrated circuit 100.

[0028] (Second Embodiment of Semiconductor Integrated Circuit) FIG. 4 is a block diagram showing a second embodiment of the semiconductor integrated circuit of the present invention. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The semiconductor integrated circuit 100A shown in FIG. 4 has circuit blocks 10 and 20A. The circuit block 20A has a delay circuit 26 added to the circuit block 20 in FIG. 1. The delay circuit 26 is an example of a third delay circuit.

[0029] The delay circuit 26 delays the clock signal CLK and outputs it as a delayed clock signal CLK3 to the logic circuit 12 of the circuit block 10. Note that the delay circuit 26 may be mounted on the circuit block 10. In this case, the clock output terminal of the delay circuit 26 may be connected to the clock input terminal of the logic circuit 12. Alternatively, the clock input terminal of the delay circuit 26 may be connected to the output terminal of the hold signal HLD of the logic circuit 12, and the hold signal HLD delayed by the delay circuit 26 may be output to the analog circuit 14.

[0030] In this embodiment, by providing a delay circuit in the generation path of the hold signal HLD of the semiconductor integrated circuit 100A, the falling timing of the sampling signal SMPL can be surely set before the falling timing of the hold signal HLD. Note that, the larger the delay time of the delay circuit 26 is, the lower the voltage value of the output signal AOUT acquired by the analog circuit 23 becomes.

[0031] That is, when the delay time of the delay circuit 26 is large, sampling ends before the output signal AOUT reaches the desired voltage (before it is fully settled). Therefore, even when the circuit characteristics of the circuit blocks 10 and 20A vary, the delay time of the delay circuit 26 is preferably set to the minimum within the range where the falling timing of the sampling signal SMPL does not lag behind the falling timing of the hold signal HLD.

[0032] Normally, when sampling an analog output signal, the settling error (error) can be expressed by the transient response shown in Equation (1). Time (t) = -loge (settling error) * RC ‥(1) In Equation (1), the symbol * indicates multiplication, and RC indicates the time constant due to the load connected to the output signal line AOUT.

[0033] For example, when the resolution of the AD converter mounted in the analog circuit 23 is 12 bits and 10 bits, from Equation (1), the time (t) of the high-level period of the hold signal HLD can be expressed by Equations (2) and (3), respectively. Time (t) = -log(1 / 2^12) * RC = 8.32 * RC ‥(2) Time (t) = -log(1 / 2^10) * RC = 6.93 * RC ‥(3)

[0034] For example, when the accuracy of the data signal DATA output by the analog circuit 23 in FIG. 4 may be 10 bits, from Equation (4), there is no problem as the data signal DATA until 83% of the high-level period of the hold signal HLD. Time (t) = (6.93 * RC / 8.32 * RC) * 100 = 83 [%] ‥(4)

[0035] Therefore, the delay time of the falling edge of the hold signal HLD with respect to the rising edge of the sampling signal SMPL is preferably set within the range of 0% to 17% (100% - 83%) of the high-level period of the hold signal HLD.

[0036] Note that the timing design of a circuit including an analog circuit is implemented using a circuit simulator. However, due to factors such as the accuracy of the simulation model, the simulation results do not necessarily match the actual circuit timing. For this reason, in order to adjust the delay time of the delay circuit 26, the delay circuit 26 is preferably a variable delay circuit with an adjustable delay time.

[0037] As described above, also in this embodiment, similar to the above-described embodiment, the accuracy of the generation timing of the hold signal HLD and the sampling signal SMPL can be improved. Furthermore, in this embodiment, by providing a delay circuit in the generation path of the hold signal HLD of the semiconductor integrated circuit 100A, the falling timing of the sampling signal SMPL can be surely set before the falling timing of the hold signal HLD.

[0038] (Third Embodiment of Semiconductor Integrated Circuit) FIG. 5 is a block diagram showing a third embodiment of the semiconductor integrated circuit of the present invention. The same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit 100B shown in FIG. 5 has circuit blocks 10B and 20B. The circuit blocks 10B and 20B are arranged in adjacent regions. The circuit configuration of the circuit block 10B is the same as that of the circuit block 10 in FIG. 1 except that the positions where the circuits are arranged are different. The circuit configuration of the circuit block 20B is the same as that of the circuit block 20 in FIG. 1 except that the positions where the circuits are arranged are different.

[0039] The logic circuit 12 and the analog circuit 14 of the circuit block 10B are arranged on the circuit block 20B side in the circuit block 10B. The delay circuit 21, the logic circuits 22, 12', the analog circuit 23, and the DLL circuit 24 of the circuit block 20B are arranged on the circuit block 10B side in the circuit block 20B.

[0040] When the wiring lengths of the clock signal lines CLK from the supply source of the clock signal CLK to the respective logic circuits 12 and 12' are different, the timings of the clock signal CLK input to the logic circuits 12 and 12' are deviated. For example, the signal lines formed on the semiconductor integrated circuit 100B are formed using metal wirings such as copper or aluminum provided between the interlayer insulating films laminated on each other.

[0041] The thickness and width of the metal wiring and the thickness of the interlayer insulating film vary due to variations in the manufacturing process of the semiconductor integrated circuit 100B. For this reason, the resistance value and the load capacitance of the clock signal line CLK change according to the variations in the manufacturing process, and the delay time of the clock signal CLK changes.

[0042] Therefore, in this embodiment, by arranging the circuits in the circuit block 10B and the circuits in the circuit block 20B in positions close to each other, the difference in the wiring lengths of the clock signal lines CLK is reduced. Thereby, it is possible to reduce the variations in the propagation delay time of the clock signal CLK due to variations in the manufacturing process of the semiconductor integrated circuit 100B. For example, the wiring delay td' of the clock signal CLK from the vicinity of the clock input terminal of the logic circuit 12' to the vicinity of the clock input terminal of the logic circuit 12 can be made smaller than the wiring delay td in FIG. 1.

[0043] As described above, also in this embodiment, similar to the above-described embodiment, the accuracy of the generation timing of the hold signal HLD and the sampling signal SMPL can be improved. Further, in this embodiment, by minimizing the wiring delay of the clock signal line CLK, the variation in the propagation delay time of the clock signal CLK caused by the variation in the manufacturing process of the semiconductor integrated circuit 100B can be reduced. As a result, the accuracy of the generation timing of the hold signal HLD and the sampling signal SMPL can be further improved.

[0044] (Fourth Embodiment of Semiconductor Integrated Circuit) FIG. 6 is a block diagram showing a fourth embodiment of the semiconductor integrated circuit of the present invention. The same elements as those in FIGS. 1 and 5 are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit 100C shown in FIG. 6 includes circuit blocks 10C and 20C. The circuit block 10C adds a delay circuit 18 to the circuit block 10B shaped like a capital letter Z. The circuit block 20C deletes the logic circuit 12' from the circuit block 20B in FIG. 5.

[0045] The circuit block 10C includes a logic circuit 12, a delay circuit 18, and an analog circuit 14 connected in series. The delay circuit 18 delays the hold signal HLD by a predetermined time and outputs it as a hold signal HLD2 to the analog circuit 14. The delay circuit 18 is arranged to set the delay of the hold signal HLD2 with respect to the sampling signal SMPL, for example, within the range of 0% to 17% of the high level period of the hold signal HLD. The hold signal HLD2 is an example of a first delay control signal.

[0046] The DLL circuit 24 receives a sampling signal SMPL and a hold signal HLD. The DLL circuit 24 outputs a delay adjustment signal ADJ for matching the falling edge of the sampling signal SMPL with the falling edge of the hold signal HLD to the delay circuit 21. Thereby, regardless of the deviation in the propagation delay time of the clock signal CLK to the delay circuits 18 and 21, the sampling signal SMPL and the hold signal HLD at a desired timing can be generated according to the delay time of the delay circuit 18. In other words, even when the manufacturing process of the semiconductor integrated circuit 100C varies, the sampling signal SMPL and the hold signal HLD at a desired timing can be respectively supplied to the analog circuits 14 and 23.

[0047] Note that when the phase of the falling edge of the hold signal HLD can be compensated to be delayed from the phase of the falling edge of the sampling signal SMPL due to the wiring delay of the output signal line AOUT, the delay circuit 18 may not be arranged. Also, in FIG. 6, similar to FIG. 5, the circuits in the circuit block 10B and the circuits in the circuit block 20B are arranged at adjacent positions. However, in this embodiment, since there is no influence on the circuit operation due to the deviation in the propagation delay time of the clock signal CLK to the logic circuits 12 and 21, for example, a circuit arrangement similar to FIG. 1 may be used.

[0048] As described above, also in this embodiment, similar to the above-described embodiments, the accuracy of the generation timing of the hold signal HLD and the sampling signal SMPL can be improved. Further, in this embodiment, the constraint on the wiring length of the clock signal line CLK can be reduced. By directly inputting the hold signal HLD to the DLL circuit 24, the accuracy of the generation timing of the hold signal HLD and the sampling signal SMPL can be further improved. At this time, by providing the delay circuit 18 for delaying the hold signal HLD, even when the manufacturing process of the semiconductor integrated circuit 100C varies, the sampling signal SMPL and the hold signal HLD at a desired timing can be respectively supplied to the analog circuits 14 and 23.

[0049] (One Embodiment of an Image Reading Device) FIG. 7 is a block diagram showing one embodiment of the image reading device of the present invention. For elements similar to those in FIG. 1, the same reference numerals are given and detailed descriptions are omitted. The image reading device 200 shown in FIG. 7 includes a scanner unit 210 and an operation control unit 220. For example, the image reading device 200 is a scanner device.

[0050] The scanner unit 210 includes an imaging device 211 including the semiconductor integrated circuit 100 of FIG. 1, an LED (Light Emitting Diode) driver 212, and an LED 213 as a light source. For example, the imaging device 211 is a line sensor. The operation control unit 220 includes a CPU (Central Processing Unit) 221 and an image processing unit 222. The CPU 221 has a function of controlling the overall operation of the image reading device 200.

[0051] The image reading device 200 photoelectrically converts the reflected light from a document (not shown) irradiated with light from the LED 213 by a photoelectric conversion element mounted on the imaging device 211. The LED 213 is driven by the LED driver 212. The semiconductor integrated circuit 100 (FIG. 1) holds the charges obtained by photoelectric conversion in a capacitive element (not shown), amplifies the voltage (AIN) obtained according to the charges held in the capacitive element by the analog circuit 14, and generates a voltage (AOUT).

[0052] Also, the semiconductor integrated circuit 100 converts the voltage (AOUT) obtained by amplification into a digital value (image data) by the analog circuit 23. The semiconductor integrated circuit 100 transfers the digital value obtained by the conversion to the image processing unit 222 as a data signal DATA. The image processing unit 222 performs image processing such as performing various corrections on the data signal DATA (image data), for example.

[0053] As described above, in this embodiment as well, the same effects as those in the first embodiment can be obtained. That is, by improving the accuracy of the generation timing of the hold signal HLD and the sampling signal SMPL, image data with a sufficient signal amount can be acquired, and the performance of the image reading apparatus 200 can be improved. Note that the imaging device 211 may have the semiconductor integrated circuit 100A in FIG. 4, the semiconductor integrated circuit 100B in FIG. 5, or the semiconductor integrated circuit 100C in FIG. 6 instead of the semiconductor integrated circuit 100.

[0054] (An embodiment of an image forming apparatus) FIG. 8 is a block diagram showing an embodiment of an image forming apparatus of the present invention. The same elements as those in FIGS. 1 and 7 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The image forming apparatus 300 shown in FIG. 8 includes a scanner unit 210, an operation control unit 220, and a printer engine 230. For example, the image forming apparatus 300 is an MFP (Multi-Function Peripheral) having a copy function, a printer function, a scanner function, a fax function, etc., and is a so-called multifunction device. Note that the image forming apparatus 300 may be a printer having a scanner function.

[0055] The CPU 221 has a function of controlling the overall operation of the image forming apparatus 300 including the printer engine 230. The printer engine 230 forms (prints) the image data processed by the image processing unit 222 on a recording medium such as recording paper.

[0056] As described above, in this embodiment as well, the same effects as those in the first embodiment can be obtained. That is, by improving the accuracy of the generation timing of the hold signal HLD and the sampling signal SMPL, image data with a sufficient signal amount can be acquired, and the performance of the image forming apparatus 300 can be improved. Note that the imaging device 211 may have the semiconductor integrated circuit 100A in FIG. 4, the semiconductor integrated circuit 100B in FIG. 5, or the semiconductor integrated circuit 100C in FIG. 6 instead of the semiconductor integrated circuit 100.

[0057] (An embodiment of a camera system) FIG. 9 is a block diagram showing an embodiment of the camera system of the present invention. The same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The camera system 400 shown in FIG. 9 includes a lens 410, an imaging device 420 including the semiconductor integrated circuit 100 of FIG. 1, a drive control unit 430, and a signal processing unit 440. For example, the camera system 400 is a digital camera.

[0058] The lens 410 forms an image of incident light on the imaging surface of the pixel region of the imaging device 211. The lens 410 is an example of an optical system that guides incident light to a photoelectric conversion element. The imaging device 420 has a lens that forms an image of incident light on the imaging surface in the pixel region of the device received through the lens 410. The drive control unit 430 has a timing generator that generates a drive timing signal for driving the circuits in the imaging device 420. The drive control unit 430 drives the imaging device 420 with the generated drive timing signal.

[0059] The imaging device 420 photoelectrically converts the light received through the lens 410 for each pixel and outputs it to the signal processing unit 440 as an image signal. The image signal is an example of an output signal. Here, the semiconductor integrated circuit 100 amplifies the voltage (AIN) obtained by photoelectric conversion and obtained according to the charge held in the capacitor element by the analog circuit 14 (FIG. 1) to generate a voltage (AOUT). Further, the semiconductor integrated circuit 100 converts the voltage (AOUT) obtained by amplification into a digital value (image data) by the analog circuit 23 (FIG. 1). The semiconductor integrated circuit 100 outputs the digital value obtained by the conversion to the signal processing unit 440 as an image signal.

[0060] The signal processing unit 440 performs predetermined signal processing on the image signal from the imaging device 420. When the image signal processed by the signal processing unit 440 is an analog signal, the image information included in the image signal is recorded in a recording medium such as a memory (not shown) through an analog-to-digital conversion circuit (AFE; Analog Front End). When the image signal processed by the signal processing unit 440 is an analog signal, the image information included in the image signal is recorded in a recording medium such as a memory (not shown) through a digital signal processing circuit (DFE; Digital Front End).

[0061] The image information recorded in the recording medium is hard-copied as an image by a printer or the like. Also, when the camera system 400 continuously captures incident light, the image signal processed by the signal processing unit 440 may be projected as a moving image onto a monitor such as a liquid crystal display connected to the camera system 400. By mounting the semiconductor integrated circuit 100 on the imaging device 420 of the camera system 400, a highly accurate camera system 400 can be realized.

[0062] As described above, also in this embodiment, the same effects as those of the first embodiment can be obtained. That is, by improving the accuracy of the generation timing of the hold signal HLD and the sampling signal SMPL, an image signal with a sufficient signal amount can be acquired, and the performance of the camera system 400 can be improved. Note that the imaging device 420 may have the semiconductor integrated circuit 100A of FIG. 4, the semiconductor integrated circuit 100B of FIG. 5, or the semiconductor integrated circuit 100C of FIG. 6 instead of the semiconductor integrated circuit 100.

[0063] As described above, the present invention has been described based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiments. In this regard, it can be changed without departing from the gist of the present invention, and can be appropriately determined according to the application form.

Description of Reference Numerals

[0064] 10, 10B, 10C Circuit blocks 12, 12' Logic circuits 14 Analog circuit 16, 18 Delay circuits 20, 20A, 20B, 20C Circuit blocks 21 Delay circuit 22, 22' Logic circuits 23 Analog circuit 24 DLL circuit 26 Delay circuit 100, 100A, 100B, 100C Semiconductor integrated circuits 110 Semiconductor integrated circuit 200 Image reading device 210 Scanner unit 211 Imaging device 212 LED driver 213 LED 220 Operation control unit 221 CPU 222 Image processing unit 230 Printer engine 300 Image forming apparatus 400 Camera system 410 Lens 420 Imaging device 430 Drive control unit 440 Signal processing unit ADJ Delay adjustment signal AIN Input signal AOUT Output signal CLK Clock signal CLK1, CLK2, CLK3 Delayed clock signals DATA Data signal HLD, HLD2 Hold signals SMPL Sampling signal

Prior art documents

Patent documents

[0065]

Patent Document 1

Claims

1. a first logic circuit that outputs a first control signal based on a clock signal; a first circuit block including a first analog circuit that operates based on the first control signal and outputs an analog signal; a first delay circuit that delays the clock signal to generate a first delayed clock signal, and whose delay amount is adjusted according to a delay adjustment signal; a second logic circuit that generates a second control signal based on the first delayed clock signal; a second analog circuit that acquires the analog signal output by the first analog circuit by the second control signal; a second delay circuit that has a delay time corresponding to the time determined by the reception of the clock signal by the first logic circuit and the output of the first control signal, and generates a second delayed clock signal based on the clock signal; a second circuit block including a delay adjustment circuit that receives the second control signal and the second delayed clock signal, and generates the delay adjustment signal for matching the phase of the second control signal with the phase of the second delayed clock signal; A semiconductor integrated circuit, characterized by comprising the same.

2. The second delay circuit is a replica of the first logic circuit that masks the operation of non-logic logic from the input terminal of the clock signal in the first logic circuit to the output terminal of the first control signal. The semiconductor integrated circuit according to claim 1, characterized by the above.

3. The semiconductor integrated circuit according to claim 1 or claim 2, characterized by comprising a third delay circuit that delays the clock signal input to the first logic circuit or the first control signal output from the first logic circuit. The semiconductor integrated circuit according to claim 1 or claim 2, characterized by the above.

4. The first circuit block and the second circuit block are arranged adjacent to each other, The first logic circuit and the first analog circuit are arranged on the second circuit block side in the first circuit block, The second logic circuit, the second analog circuit, the second delay circuit, and the delay adjustment circuit are arranged on the first circuit block side in the second circuit block. The semiconductor integrated circuit according to any one of claims 1 to 3, characterized by the above.

5. a first logic circuit that outputs a first control signal based on a clock signal; a first circuit block including a first analog circuit that operates based on the first control signal and outputs an analog signal; A first delay circuit that delays the clock signal to generate a first delayed clock signal, and the delay amount is adjusted according to a delay adjustment signal; A second logic circuit that generates a second control signal based on the first delayed clock signal; A second analog circuit that acquires the analog signal output by the first analog circuit by the second control signal; A delay adjustment circuit that receives the second control signal and the first control signal and generates the delay adjustment signal for matching the phase of the second control signal with the phase of the first control signal, and a second circuit block including the same; A semiconductor integrated circuit characterized by having the same.

6. The first circuit block has a third delay circuit that delays the first control signal to generate a first delayed control signal; The first analog circuit operates based on the first delayed control signal instead of the first control signal The semiconductor integrated circuit according to claim 5, characterized by the above.

7. An image reading apparatus, characterized by having a photoelectric conversion element including the semiconductor integrated circuit according to any one of claims 1 to 6.

8. An image forming apparatus, characterized by having a photoelectric conversion element including the semiconductor integrated circuit according to any one of claims 1 to 6.

9. A photoelectric conversion element including the semiconductor integrated circuit according to any one of claims 1 to 6; An optical system that guides incident light to the photoelectric conversion element; A drive control unit that controls the operation of the photoelectric conversion element; A signal processing unit that processes an output signal output from the photoelectric conversion element; A camera system characterized by having the same.

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