Method of manufacturing a semiconductor device

Abstract

To provide a manufacturing method for a semiconductor device that can suppress restrictions on design freedom and the complexity of a manufacturing process.SOLUTION: After applying photoresist 2 on an SiC substrate 1, which serves as a translucent substrate, apertures 2a, 2b are formed in a device formation area and an alignment formation area out of the SiC substrate 1 by exposing and developing the photoresist 2. An impurity layer 4 is then formed in the device formation area through apertures 2a, 2b and at the same time an alignment mark 3 is formed in the alignment formation area by coloring impurity by ion implanting impurities using the photoresist 2 as an ion implantation mask. Then, after removing the photoresist 2, mask alignment is carried out with reference to the alignment mark 3.SELECTED DRAWING: Figure 2B

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device based on an alignment mark.

Background Art

[0002] As a next-generation switching element capable of achieving high breakdown voltage, low loss, and high heat resistance, a semiconductor element using silicon carbide (hereinafter referred to as SiC) is regarded as promising, and its application to power semiconductor devices such as inverters is expected.

[0003] In particular, research on layout miniaturization, such as shortening the trench pitch, is being advanced toward the realization of a low-loss SiC trench MOSFET device. A trench MOSFET device is generally designed by combining several structures such as an n + -type source region, a p-type base region, a p + -type contact region, and a trench gate structure, and is also manufactured through several processes. Therefore, in order to realize layout miniaturization, each structure needs to be formed in a state where they are accurately aligned in the planar direction.

[0004] Generally, in order to align a plurality of structures, a step of forming an alignment mark is often provided in the first half of the process flow. This forms a stepped shape on the SiC surface by etching, and by reading the contrast generated at this step portion in the photolithography process when forming each structure later, the exposure position of the reticle for forming the target structure can be accurately adjusted.

[0005] However, since the step of forming this alignment mark generates a step on the SiC surface, it needs to be a process different from the process of forming the structure of the trench MOSFET. Therefore, the aforementioned n + -type source region, p-type base region, p +In addition to the type contact area and the reticle for forming the trench gate structure, it is necessary to prepare a dedicated reticle, which complicates the manufacturing process, resulting in longer manufacturing time and increased costs as issues.

[0006] In contrast, Patent Document 1 proposes a technique of making one reticle have both functions by mixing the reticle with an alignment mark part and an ion implantation part, each made of a normal pattern and a halftone pattern that attenuates the effective exposure amount.

[0007] In this technique, for the alignment mark part, that is, the part where a step is to be formed, a normal pattern is used to open the resist after exposure. On the other hand, for the ion implantation part, a halftone pattern is used to intentionally provide a resist residual film after exposure. When dry etching is performed in this state, in the alignment mark part, the base layer is etched away, that is, dry etched to the base layer to form a step. Also, in the ion implantation part, the resist residual film functions as a protective film, and an alignment mark can be formed without generating a step in the ion implantation part.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] However, in order to control the amount of resist residual film in the halftone pattern part that functions as an etching protective film, it is necessary to finely adjust the exposure amount. For this reason, the opening width of the normal pattern part formed simultaneously cannot be adjusted by the exposure amount, which restricts the design freedom. Furthermore, an additional dry etching process is required between the photolithography process and the ion implantation process, which complicates the manufacturing process, resulting in longer manufacturing time and increased costs as issues.

[0010] In addition, regarding the resist residual film in the halftone pattern portion, due to the influence of the in-plane variation in the etching rate, there is a possibility that the in-plane variation in the residual film after etching becomes large locally, or that substrate erosion occurs. The variation in the residual film may affect the variation in the ion implantation profile and cause fluctuations in the electrical characteristics. Further, when substrate erosion occurs, it may cause process defects due to uneven film formation or resist coating in subsequent processes, or may cause fluctuations in the electrical characteristics due to electric field concentration at the step edge.

[0011] A first object of the present disclosure is to provide a method for manufacturing a semiconductor device that can suppress restrictions on the design freedom and complexity of the manufacturing process. A second object of the present disclosure is to provide a method for manufacturing a semiconductor device that can suppress variations in the ion implantation profile and substrate erosion in addition to suppressing restrictions on the design freedom and complexity of the manufacturing process.

Means for Solving the Problems

[0012] In a method for manufacturing a semiconductor device that forms a device using a light-transmissive substrate (1) that transmits visible light in one aspect of the present disclosure, applying a photoresist (2) on the light-transmissive substrate, by exposing and developing the photoresist, forming openings (2a, 2b) in the device formation region and the alignment formation region of the light-transmissive substrate, using the photoresist as an ion implantation mask to implant impurities, thereby forming an impurity layer (4) in the device formation region through the openings and simultaneously forming an alignment mark (3) due to impurity coloring in the alignment formation region, removing the photoresist after forming the alignment mark, and performing mask alignment using the alignment mark as a reference, including one or more times.

[0013] In such a manufacturing method, an alignment mark is formed by ion implantation using a photoresist as an ion implantation mask when forming an impurity layer in a device formation region. That is, conventionally, mask alignment has been performed by reading the contrast generated by a step pattern, but in this manufacturing method, coloring by ion implantation is used as a substitute, and an alignment mark is formed by an ion implantation layer.

[0014] In this way, since the alignment mark is formed by ion implantation using a photoresist without using a halftone pattern, it is not necessary to control the resist residue amount, and it is possible to suppress the occurrence of restrictions on the design freedom. Furthermore, since the alignment mark can be formed simultaneously when forming the impurity layer in the device formation region, it is not necessary to add a dry etching process between the photolithography process and the ion implantation process, and the complication of the manufacturing process can also be suppressed. Furthermore, by forming the alignment mark by ion implantation, it is also possible to suppress variations in the ion implantation profile and substrate erosion.

[0015] In a method for manufacturing a semiconductor device that forms a device using a light-transmissive substrate (1) that transmits visible light from another aspect of the present disclosure, forming a mask film (5) on the light-transmissive substrate; applying a photoresist (2) on the mask film; by exposing and developing the photoresist, forming openings (2a, 2b) in the device formation region and the alignment formation region of the light-transmissive substrate; using the photoresist as an etching mask, etching the mask film through the openings, and forming openings (5a, 5b) in the device formation region and the alignment formation region of the mask film; after removing the photoresist, using the mask film as an ion implantation mask and ion implanting impurities, thereby forming an impurity layer (4) in the device formation region through the openings and simultaneously forming an alignment mark (3) by coloring of impurities in the alignment formation region; Removing the mask film after forming the alignment mark, and performing device formation using the alignment mark as a reference, and including the above steps one or more times.

[0016] In such a manufacturing method, an alignment mark is formed by performing ion implantation using a mask film as an ion implantation mask for forming an impurity layer in a device formation region. In this way, since the alignment mark is formed by ion implantation without using a halftone pattern, it is not necessary to control the resist residue amount, and the restriction on the design freedom can be suppressed. Furthermore, since the alignment mark can be formed simultaneously when forming the impurity layer in the device formation region, the complication of the manufacturing process can also be suppressed.

[0017] Note that the reference numerals in parentheses attached to each component etc. show an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of Drawings

[0018]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 3A

Figure 3B

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 6

Embodiments for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals for description.

[0020] (First Embodiment) The first embodiment will be described. In this embodiment, a manufacturing method of a semiconductor device in the case of forming an alignment mark on a semiconductor substrate and performing device formation based on this alignment mark will be described. The alignment mark formation process is performed as one step of the semiconductor device manufacturing method, but various known methods can be applied to each step of device formation based on the alignment mark. Therefore, in this embodiment, while referring to FIGS. 1 and 2A to 2C, the alignment mark formation process will be mainly described.

[0021] FIG. 1 is a process flow mainly showing the details of the alignment mark formation process in the manufacturing method of the semiconductor device. Also, FIGS. 2A to 2C are cross-sectional views showing the state during the process shown in the process flow shown in FIG. 1.

[0022] The alignment mark is formed in the alignment formation region of the semiconductor substrate. The alignment formation region is typically a region different from the device formation region where semiconductor elements are formed and taken out as chips, for example, an outer peripheral region located around the chip region of the wafer-shaped semiconductor substrate or a dicing region when cutting each chip. The left side of the paper in FIGS. 2A to 2C shows the state of the alignment formation region, and the right side of the paper shows the state of the device formation region.

[0023] First, as shown in FIG. 2A, a SiC substrate 1 is prepared as the semiconductor substrate. The SiC substrate 1 is a translucent substrate that transmits visible light. Depending on the type and concentration of impurities doped in the SiC substrate 1, the coloring method of the SiC substrate 1 may be different, but as long as it transmits visible light, the SiC substrate 1 may be either colorless transparent or colored transparent. The SiC substrate 1 may be a bulk substrate cut out from a SiC ingot or an epi-substrate obtained by epitaxially growing a SiC layer on the bulk substrate.

[0024] Then, after applying the photoresist 2 to the surface of the SiC substrate 1 by performing the photoresist coating step shown in FIG. 1, the photoresist 2 is patterned by performing the exposure and development steps. At this time, openings 2a and 2b are formed in the photoresist 2 simultaneously for both the alignment formation region and the device formation region.

[0025] Subsequently, as the ion implantation step shown in FIG. 1, as shown in FIG. 2B, impurities are ion-implanted using the photoresist 2 as an ion implantation mask. The type of ions to be implanted is arbitrary, but here B (boron) which is a p-type impurity is used. For example, the acceleration energy and dose amount of ion implantation are set so that the depth is 0.2 to 0.5 μm and the impurity concentration is 3.0×10 18 cm -3

[0026] As a result, impurities are doped into the surface layer of the SiC substrate 1 through the openings 2a and 2b, the alignment mark 3 is formed in the alignment formation region, and an impurity layer 4 that constitutes a part of a semiconductor element, for example, is formed in the device formation region. At this time, since the alignment mark 3 and the impurity layer 4 are simultaneously formed using the photoresist 2 as an ion implantation mask, they are formed without misalignment. Also, in the region where ion implantation is performed, the SiC substrate 1 is locally colored depending on the type and concentration of the doped impurities. When the surface layer of the SiC substrate 1 where ion implantation is performed is n-type, the color of that region changes when a p-type impurity different from the n-type impurity contained in the surface layer is implanted. Also, when the surface layer of the SiC substrate 1 where ion implantation is performed is p-type, the color of that region changes because the impurity concentration in that region becomes higher compared to other regions. And since the light transmittance decreases due to the local coloring of the SiC substrate 1, it can be used as the alignment mark 3.

[0027] In this way, by forming an ion implantation layer in the alignment formation region of the SiC substrate 1, the alignment mark 3 composed of the colored portion can be formed. Regarding the formation depth and thickness of the alignment mark 3, for example, when performing mask alignment with the alignment mark 3 as a reference, it may be arbitrarily set as long as the alignment mark 3 can be read by a stepper used as an exposure device and alignment recognition can be performed. Also, although the pattern shape of the alignment mark 3 is arbitrary, it is preferable to use the pattern shape recommended by the manufacturer of the stepper used. For example, the alignment mark 3 can be formed by arranging a plurality of line-shaped dots with one direction as the longitudinal direction in parallel.

[0028] Subsequently, as the photoresist stripping process in FIG. 1, the photoresist 2 is stripped and removed by performing SPM (sulfuric acid-hydrogen peroxide mixture cleaning) cleaning or ashing. As a result, as shown in FIG. 2C, the surface of the SiC substrate 1 is exposed, and it becomes possible to confirm the alignment mark 3 from the surface of the SiC substrate 1 based on the color change between the ion implantation portion and the portion around it where ion implantation has not been performed.

[0029] After this, as a method for manufacturing a semiconductor device, various processes for device formation will be performed. By performing the alignment mark detection process in FIG. 1 to perform mask alignment, it becomes possible to perform accurate mask alignment. That is, since the alignment mark 3 can be visually recognized based on coloring and can be recognized by a stepper, mask alignment can be accurately performed with the alignment mark 3 as a reference. Therefore, when forming an ion implantation mask for forming an impurity layer or a trench formation mask for forming a trench in the SiC substrate 1, the mask pattern can be accurately formed, and the deviation in the formation position of the impurity layer and the trench can be suppressed.

[0030] As described above, in the method for manufacturing a semiconductor device according to this embodiment, as an alignment formation process, the alignment mark 3 is formed by ion implantation using the photoresist 2 as an ion implantation mask when forming the impurity layer 4 in the device formation region. That is, conventionally, mask alignment has been performed by reading the contrast caused by the step pattern with a stepper, but in this embodiment, it is substituted by coloring by ion implantation, and the alignment mark 3 is formed by the ion implantation layer.

[0031] Conventionally, as shown in FIG. 3A, after forming an oxide film J2 on a SiC substrate J1, an opening J2a is formed in the oxide film J2 by etching using a photoresist (not shown) as a mask. Then, after removing the photoresist, the SiC substrate J1 is etched using the oxide film J2 as an etching mask. In this way, a recess J3 that constitutes a step pattern is formed on the surface of the SiC substrate J1. Therefore, as shown in FIG. 3B, during subsequent mask alignment or the like, an alignment mark is recognized by reading, with a stepper, the contrast generated by the step pattern constituted by the recess J3. When the alignment mark is constituted by the recess J3 in this way, it is necessary to prevent the recess J3 from being formed in the device formation region. In Patent Document 1, a halftone pattern is used so that the recess J3 is formed only in the alignment formation region. However, in order to control the resist residue amount in the halftone pattern portion that functions as an etching protection film, it is necessary to finely adjust the exposure amount. For this reason, the opening width of the normal pattern portion formed simultaneously cannot be adjusted by the exposure amount, which restricts the design freedom. Furthermore, an additional dry etching process is required between the photolithography process and the ion implantation process, complicating the manufacturing process.

[0032] In contrast, in the present embodiment, the alignment mark 3 is formed by ion implantation using the photoresist 2 without using a halftone pattern. For this reason, it is no longer necessary to control the resist residue amount, and it is possible to suppress the occurrence of restrictions on the design freedom. Furthermore, since the alignment mark 3 can be formed simultaneously when forming the impurity layer 4 in the device formation region, it is no longer necessary to add a dry etching process between the photolithography process and the ion implantation process, and the complication of the manufacturing process can also be suppressed.

[0033] Furthermore, by forming the alignment mark 3 by ion implantation as in the present embodiment, it is possible to suppress variations in the ion implantation profile, substrate erosion, and in the case of the present embodiment, erosion of the surface of the SiC substrate 1.

[0034] When intentionally providing a resist residual film after exposure by using a halftone pattern as in Patent Document 1, due to the influence of in-plane variations in the etching rate, local variations in the residual film after etching may increase in the plane, or substrate erosion may occur.

[0035] On the other hand, when forming the alignment mark 3 by ion implantation, since it is not necessary to provide a resist residual film like a halftone pattern, residual film variations do not occur, and since etching is not performed, substrate erosion can be prevented from occurring.

[0036] Therefore, it is possible to provide a method for manufacturing a semiconductor device that can suppress variations in the profile of the ion implantation mask and substrate erosion, as well as restrictions on the design freedom and complexity of the manufacturing process.

[0037] (Second Embodiment) The second embodiment will be described. This embodiment is a modification of the first embodiment in which the ion implantation mask is changed, and since the rest is the same as the first embodiment, only the parts different from the first embodiment will be described.

[0038] In the first embodiment described above, the photoresist 2 was used as the ion implantation mask, but in this embodiment, the alignment mark forming step when using an oxide film as the mask film serving as the ion implantation mask will be described with reference to FIGS. 4 and 5A to 5D.

[0039] FIG. 4 is a process flow mainly showing the details of the alignment mark forming step in the method for manufacturing a semiconductor device. FIGS. 5A to 5D are cross-sectional views showing the state during the steps shown in the process flow shown in FIG. 4.

[0040] First, as shown in FIG. 5A, a SiC substrate 1 is prepared as a semiconductor substrate. Then, after forming an oxide film 5 on the surface of the SiC substrate 1 as the oxide film forming step shown in FIG. 4, through a photoresist coating step and an exposure / development step, an oxide film dry etching step is performed using the photoresist 2 as an etching mask to form openings 5a and 5b in the oxide film 5. The film thickness of the oxide film 5 is arbitrary, and it may be any thickness that can be used as an ion implantation mask. The photoresist coating step and the exposure / development step may be performed by the same method as in the first embodiment.

[0041] Here, during the oxide film dry etching step, a thin residual film 5c is left at the bottom of the openings 5a and 5b so that the openings 5a and 5b do not penetrate the oxide film 5. For example, the residual film 5c can be left by adjusting the etching time when dry etching the oxide film 5. When dry etching the oxide film 5, due to the in-plane variation of the etching rate, a film thickness variation of the residual film 5c occurs, for example, up to about 50 nm. Based on this, if the residual film 5c is left expecting a film thickness of 10 nm when the etching rate is the highest, the film thickness will be 10 nm at the thinnest and 60 nm at the thickest.

[0042] In this way, if a thin residual film 5c is left at the bottom of the openings 5a and 5b, the surface of the SiC substrate 1 can be prevented from being etched, and substrate undercut can be suppressed. Of course, since the etching amount of the surface of the SiC substrate 1 changes according to the etching conditions, if the etching conditions are such that substrate undercut is acceptable, the residual film 5c does not have to remain.

[0043] Subsequently, as the photoresist stripping process in FIG. 4, SPM cleaning or ashing is performed to strip and remove the photoresist 2. As a result, only the oxide film 5 with openings 5a and 5b formed on the surface of the SiC substrate 1 remains as shown in FIG. 5B. Thereafter, as the ion implantation process shown in FIG. 4, impurities are ion-implanted using the oxide film 5 as an ion implantation mask as shown in FIG. 5C. As described above, since a thin residual film 5c remains at the bottom of the openings 5a and 5b, ion implantation is performed using this as a through-film. The type of ions to be implanted is arbitrary, but here Al (aluminum) which is a p-type impurity is used. For example, the acceleration energy and dose amount of ion implantation are set so that the depth is 0.4 to 0.6 μm and the impurity concentration is 2.0×10 18 cm -3 .

[0044] As a result, impurities are doped into the surface layer portion of the SiC substrate 1 below the residual film 5c through the openings 5a and 5b. And, similar to the first embodiment, an alignment mark 3 is formed in the alignment formation region, and an impurity layer 4 constituting a part of a semiconductor element, for example, is formed in the device formation region.

[0045] Furthermore, as the oxide film stripping process in FIG. 4, the oxide film 5 is stripped and removed by performing, for example, HF (hydrogen fluoride) cleaning. As a result, the surface of the SiC substrate 1 is exposed as shown in FIG. 5D, and it becomes possible to confirm the alignment mark 3 from the surface of the SiC substrate 1 based on the color change between the ion implantation portion and the portion where ion implantation has not been performed around it.

[0046] Thereafter, as a method for manufacturing a semiconductor device, various processes for device formation will be performed. However, by performing the alignment mark detection process in FIG. 1 to perform mask alignment, it becomes possible to perform accurate mask alignment. Therefore, when forming an ion implantation mask for forming an impurity layer or a trench formation mask for forming a trench in the SiC substrate 1, the mask pattern can be accurately formed, and the displacement of the formation position of the impurity layer and the trench can be suppressed.

[0047] As described above, in the method for manufacturing a semiconductor device according to the present embodiment, the alignment mark 3 is formed by performing ion implantation using the oxide film 5 as an ion implantation mask. In this way, since the alignment mark 3 is formed by ion implantation without using a halftone pattern, it is not necessary to control the resist residue amount, and the restriction on the design freedom can be suppressed. Furthermore, since the alignment mark 3 can be formed simultaneously when the impurity layer 4 is formed in the device formation region, complication of the manufacturing process can also be suppressed.

[0048] When leaving the remaining film 5c on the oxide film 5, it is necessary to control the remaining amount of the oxide film in the oxide film dry etching. However, when forming a step pattern serving as an alignment mark in the alignment formation region using a photoresist as a mask as in the prior art, it is necessary to completely remove the resist in the alignment formation region and appropriately leave a resist residue in the device formation region. It is difficult to appropriately leave a resist residue using a halftone pattern, and the restriction on the design freedom increases. On the other hand, when leaving the remaining film 5c on the oxide film 5, since it is only necessary to leave the remaining film 5c on the oxide film 5 in both the alignment formation region and the device formation region, the remaining film 5c can be left with good controllability without requiring fine adjustment of the exposure amount or the like. Therefore, it is possible to suppress the occurrence of restrictions on the design freedom as compared with the case of using a halftone pattern.

[0049] Also, when leaving the remaining film 5c at the bottoms of the openings 5a and 5b of the oxide film 5, since the SiC substrate 1 is not exposed, the surface of the SiC substrate 1 can be prevented from being etched, and undercut can be suppressed. Furthermore, even if the remaining film 5c is not left, since a large step pattern for the alignment mark is not formed on the surface of the SiC substrate 1, the undercut is small and can be made to be an undercut at an acceptable level. Therefore, it is possible to suppress the occurrence of process defects due to unevenness in film formation or resist coating in subsequent processes caused by the influence of undercut, or fluctuations in electrical characteristics due to electric field concentration at the step edge.

[0050] (Third Embodiment) The third embodiment will be described. This embodiment is an example of a semiconductor device to which the manufacturing methods shown in the first and second embodiments are applied, and an application example thereof. The process of forming the alignment mark 3 is the same as that in the first and second embodiments.

[0051] The semiconductor device of this embodiment shown in FIG. 6 is one in which a MOSFET having a trench gate structure is formed as a switching element. The chip constituting the semiconductor device includes a cell region in which a MOSFET is formed and an outer peripheral breakdown voltage region formed around the cell region, and these regions correspond to the device formation regions described above. FIG. 6 shows a cross-sectional configuration of one cell of the MOSFET in the cell region.

[0052] As shown in FIG. 6, the semiconductor device is formed using an n + -type substrate 101 made of SiC, and each part constituting the vertical MOSFET is formed on the main surface of the n + -type substrate 101.

[0053] Specifically, an n + -type low-concentration layer 102 having a lower impurity concentration than the n + -type substrate 101 is epitaxially grown on the main surface of the n - -type substrate 101. P-type deep layers 103 are formed at predetermined intervals at positions away from the n - -type substrate 101 in the surface layer portion of the n + -type low-concentration layer 102. Further, a p-type base region 104 is formed on the n - -type low-concentration layer 102 and the p-type deep layer 103, and an n + -type source region 105 and a p + -type contact region 106 are formed on the p-type base region 104. The n + -type source region 105 is formed on a portion corresponding to a region of the n - -type low-concentration layer 102 where the p-type deep layer 103 is not formed, and the p +The p-type contact region 106 is formed on the portion corresponding to the p-type deep layer 103.

[0054] These n + -type substrate 101, n - -type low-concentration layer 102, p-type deep layer 103, p-type base region 104, n + -type source region 105, and p + -type contact region 106 are formed with a gate trench 107 in the surface layer portion of the SiC as a portion composed of SiC. Specifically, n + -type source region 105 and p-type base region 104 penetrate through to reach the n - -type low-concentration layer 102, and a gate trench 107 is formed. The p-type base region 104 and n + -type source region 105 are arranged so as to be in contact with the side surface of this gate trench 107. The gate trench 107 is formed in a linear layout with the horizontal direction in the plane of FIG. 6 as the width direction, one direction normal to the plane of the paper as the longitudinal direction, and the vertical direction in the plane of the paper as the depth direction. Also, although only one is shown in FIG. 6, a plurality of gate trenches 107 are arranged at equal intervals in the horizontal direction in the plane of the paper, and are arranged so as to be sandwiched between the p-type deep layers 103, and are formed in a stripe shape.

[0055] Also, the portion of the p-type base region 104 located on the side surface of the gate trench 107 serves as a channel region connecting between the n + -type source region 105 and the n - -type low-concentration layer 102 during the operation of the vertical MOSFET. And a gate insulating film 108 is formed on the inner wall surface of the gate trench 107 including this channel region. A gate electrode 109 composed of doped Poly-Si is formed on the surface of the gate insulating film 108, and these gate insulating film 108 and gate electrode 109 are embedded in the gate trench 107. For this reason, the gate electrode 109 also extends in the same one direction as the longitudinal direction of the gate trench 107. And such a structure constitutes a trench gate structure.

[0056] Also, as shown in FIG. 6, n + -type source region 105, p + -type contact region 106, on the surface of the gate electrode 109 including the gate lead-out portion 109a, an interlayer insulating film 110 is formed. Then, on the interlayer insulating film 110, as a conductor pattern, a source electrode 111 corresponding to the surface electrode and a gate wiring layer (not shown) are formed. Further, a contact hole 110a is formed in the interlayer insulating film 110. Thereby, the source electrode 111 is electrically contacted with the n + -type source region 105 and the p + -type contact region 106.

[0057] Also, on the back side of the n + -type substrate 101, that is, on the side opposite to the side where the source electrode 111 is formed, a drain electrode 112 corresponding to the back surface electrode electrically connected to the n + -type substrate 101 is formed. With such a structure, a vertical MOSFET having an n-channel type inversion type trench gate structure is configured. By arranging a plurality of such vertical MOSFETs, a cell region is configured.

[0058] In a semiconductor device having a vertical MOSFET configured as described above, for example, on an n + -type substrate 101, an epitaxial substrate obtained by epitaxially growing an n - -type low concentration layer 102 is used as a SiC substrate, and a p-type deep layer 103 is formed in the surface layer portion of the n - -type low concentration layer 102 by ion implantation. At this time, using the photoresist 2 shown in the first embodiment or the oxide film 5 shown in the second embodiment as an ion implantation mask, a p-type deep layer 103 is formed in the cell region which is the device formation region in the SiC substrate, and an alignment mark 3 is formed in the alignment formation region.

[0059] Thus, in the case of the vertical MOSFET as shown in this embodiment, for example, when forming the p-type deep layer 103, the alignment mark 3 can be simultaneously formed. Also in this case, since the alignment mark 3 is formed by ion implantation without using a halftone pattern, it is not necessary to control the resist residue amount, and it is possible to suppress the occurrence of restrictions on the design freedom, and the same effects as those of the first and second embodiments can be obtained.

[0060] Furthermore, it is also possible to perform the alignment mark 3 forming process a plurality of times. In the case of the vertical MOSFET having the structure of this embodiment, after forming the p-type deep layer 103, that is, after forming the alignment mark 3, the p-type base region 104 is epitaxially grown thereon. Even when the alignment mark 3 is covered with such an epitaxial film, an ion implantation mask is formed based on the first alignment mark 3 formed simultaneously with the p-type deep layer 103, and the n + type source region 105 and the p + type contact region 106 can also be formed.

[0061] However, mask misalignment occurs when forming the n + type source region 105, and mask misalignment also occurs when forming the p + type contact region 106. Therefore, at most, the formation positions of the n + type source region 105 and the p + type contact region 106 can be misaligned by the total value of the maximum misalignment amounts of the respective masks. High accuracy is required for the formation positions of the n + type source region 105 and the p + type contact region 106. Therefore, in order to form with high accuracy even slightly, it is preferable to perform the following steps.

[0062] That is, first, for the p-type base region 104, the n + type source region 105 and the p +When forming one of the type - contact regions 106 by ion implantation, simultaneously form the second alignment mark 3. Then, when forming the other by ion implantation, form an ion - implantation mask with reference to the second alignment mark 3. In this way, the mask misalignment can be reduced by one, and n + type source region 105 and p + the formation position of the type - contact region 106 can be accurately formed.

[0063] Thus, when forming an epitaxial film so as to cover the first alignment mark 3 formed in the lower layer and forming an impurity layer 4 on the epitaxial film, it is preferable to form the second alignment mark 3 on the epitaxial film. And by using the second alignment mark 3, the same effects as those of the first and second embodiments can be obtained.

[0064] (Other embodiments) Although the present disclosure has been described in accordance with the above - described embodiments, it is not limited to those embodiments and includes various modifications and modifications within the equivalent scope. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, are within the scope and spirit of the present disclosure.

[0065] For example, in the above - described embodiment, SiC was cited as a translucent substrate made of a semiconductor material that transmits visible light, but the translucent substrate may be composed of other semiconductor materials. For example, a translucent substrate can be composed of semiconductor materials such as GaN (gallium nitride), Ga 2 O 3 (gallium oxide), diamond, etc. In particular, it is preferable to apply the present disclosure when forming a device on a wide - bandgap semiconductor substrate such as SiC whose bandgap is 2 eV or more.

[0066] Also, in the above - described embodiment, B and Al were cited as ion species for forming the impurity layer 4, but other ion species such as N (nitrogen) and P (phosphorus) may be used.

[0067] That is, when forming a device on a light-transmitting substrate that transmits visible light, if an alignment mark 3 is formed in the alignment formation region using an ion implantation mask used for forming the impurity layer 4 in the device formation region, the material of the light-transmitting substrate and the type of ion species do not matter.

[0068] Also, in the first and second embodiments, the case of forming one alignment mark 3 and, in the third embodiment, the case of preferably forming a second alignment mark 3 in addition to the first alignment mark 3 were each described. However, the number of alignment marks 3 is also arbitrary. For example, when a light-transmitting film such as an epitaxial film of SiC is formed on a light-transmitting substrate on which the first alignment mark 3 is formed, a second alignment mark 3 can be formed simultaneously when the impurity layer 4 is formed in the light-transmitting film by ion implantation. That is, after reapplying the photoresist 2 on the light-transmitting film, openings 2a and 2b are formed in the device formation region and the alignment formation region, and the alignment mark 3 and the impurity layer 4 are formed by ion implanting impurities using the photoresist 2 as an ion implantation mask. Further, when a light-transmitting film such as an epitaxial film of SiC is formed on the light-transmitting film on which the second alignment mark 3 is formed, a third alignment mark 3 can be formed simultaneously when the impurity layer 4 is formed in the light-transmitting film by ion implantation. And when a further light-transmitting film is formed on the light-transmitting film on which the third alignment mark 3 is formed, alignment marks 3 of the fourth or more can be formed.

[0069] In addition, in the above-described third embodiment, a semiconductor device including a vertical MOSFET is taken as an example, but other switching elements such as a vertical IGBT or a JBS (junction barrier schottky diode) may also be used. Further, a semiconductor device including a combination of multiple types of elements may also be used. In each of the above embodiments, an n-channel type MOSFET with the first conductivity type being n-type and the second conductivity type being p-type has been described as an example, but a p-channel type MOSFET with the conductivity types of each component inverted may also be used. Further, the element is not limited to a trench gate structure, and a planar type element may also be used. Note that for the IGBT, it is only necessary to change the conductivity type of the n + type substrate 101 from n-type to p-type, and the other structures and manufacturing methods are the same as those in the above embodiments.

[0070] Furthermore, in each of the above embodiments, an example of the dose amount in the case of ion implanting B or Al as an impurity has been given, but it is not limited thereto. For example, if the dose amount of at least the impurity to be ion implanted is 1×10 15 cm -2 or more, a difference will occur with respect to the original impurity concentration of the light-transmissive substrate, and the ion implantation layer can be visually recognized and can be used as the alignment mark 3. In the second embodiment, the case of using an oxide film as the mask film has been described as an example, but it is not limited to the oxide film, and a mask film made of other materials such as a metal film may also be used.

Description of Reference Numerals

[0071] 1... SiC substrate, 2... photoresist, 2a, 2b... openings, 3... alignment mark, 4... impurity layer, 5... oxide film, 5a, 5b... openings, 5c... remaining film

Claims

1. A method for manufacturing a semiconductor device that forms a device using a light-transmissive substrate (1) that transmits visible light, applying a photoresist (2) on the light-transmissive substrate, forming openings (2a, 2b) in a device formation region and an alignment formation region of the light-transmissive substrate by exposing and developing the photoresist, forming an impurity layer (4) in the device formation region through the openings and simultaneously forming an alignment mark (3) due to coloring of impurities implanted in the alignment formation region by using the photoresist as an ion implantation mask and implanting impurities, removing the photoresist after forming the alignment mark, performing mask alignment using the alignment mark as a reference, including one or more times, further, forming a light-transmissive film (104) on the light-transmissive substrate after forming the alignment mark, applying a photoresist (2) again on the light-transmissive film, forming openings (2a, 2b) again in the device formation region and the alignment formation region of the light-transmissive film by exposing and developing the photoresist, forming an impurity layer (105) in the device formation region through the openings and simultaneously forming an alignment mark (3) due to coloring of impurities in the alignment formation region by using the photoresist as an ion implantation mask and implanting impurities, including, A method for manufacturing a semiconductor device, which performs at least once forming the light-transmissive film, applying the photoresist again, forming the openings again, and forming the alignment mark again.

2. A method for manufacturing a semiconductor device that forms a device using a light-transmissive substrate (1) that transmits visible light, forming a mask film (5) on the light-transmissive substrate, applying a photoresist (2) on the mask film, forming openings (2a, 2b) in a device formation region and an alignment formation region of the light-transmissive substrate by exposing and developing the photoresist, Using the photoresist as an etching mask, etching the mask film through the opening to form openings (5a, 5b) in the device formation region and the alignment formation region of the mask film; After removing the photoresist, using the mask film as an ion implantation mask to implant impurities, thereby forming an impurity layer (4) in the device formation region through the opening and simultaneously forming an alignment mark (3) by coloring the impurities implanted in the alignment formation region; Removing the mask film after forming the alignment mark; Performing device formation using the alignment mark as a reference; Including one or more times; Furthermore, by forming the opening in the mask film, Etching only a part of the mask film so that a remaining film (5c) remains at the bottom of the opening; By forming the impurity layer and simultaneously forming the alignment mark, A method for manufacturing a semiconductor device, wherein the remaining mask film with the remaining film is used as an ion implantation mask to implant the impurities, thereby forming the impurity layer inside the light-transmissive substrate below the remaining film and simultaneously forming the alignment mark.

3. By forming the impurity layer and simultaneously forming the alignment mark, the dose amount of the ion implantation is set to 1×10 １５ cm －２ or more. The method of manufacturing a semiconductor device according to claim 1 or 2.

4. The light-transmissive substrate is a wide-bandgap semiconductor substrate having a bandgap of 2 eV or more. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

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