Sheet conveying device

Abstract

To achieve the efficiency improvement and simplification of calibration work for double feed detection.SOLUTION: A sheet conveying apparatus includes a conveyance path, an oscillator, a receiver, an amplifier circuit, a comparator, a detection section, and a calibration section. The conveyance path conveys the sheet. The oscillator emits ultrasonic waves on the sheet being conveyed along the conveyance path. The receiver is provided at a position opposed to the oscillator across the conveyance path. The receiver receives ultrasonic waves emitted by the oscillator. The amplifier circuit amplifies an output signal of the receiver. The comparator compares the voltage of the output signal amplified by the amplifier circuit with a threshold voltage. Based on a comparison result of the comparator, the detection section detects the double feeding of the sheet to be conveyed along the conveyance path. The calibration section calibrates the threshold voltage based on an offset voltage of the amplifier circuit when the receiver receives no ultrasonic wave.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiments of the present invention relate to a sheet conveying device.

Background Art

[0002] There is a sheet conveying device for conveying sheets such as paper. The sheet conveying device is used, for example, in printers, copiers, facsimile machines, multifunction devices, and the like. In a sheet conveying device, so-called double feeding may occur, in which a plurality of sheets are conveyed while overlapping. Double feeding can cause errors such as jams. Therefore, the sheet conveying device is provided with a double feeding detection function.

[0003] As an example of the double feeding detection function, a technique using an ultrasonic sensor is known. When there is a sheet between the oscillator and the receiver of the ultrasonic sensor, the ultrasonic wave from the oscillator is attenuated and reaches the receiver. The amount of attenuation increases as the thickness of the sheet increases. In particular, when double feeding occurs, the ultrasonic wave is more greatly attenuated due to the influence of the air layer between the sheets. When the ultrasonic wave is attenuated, the output voltage of the receiver decreases. The double feeding detection function compares the output voltage of the receiver with a threshold voltage for double feeding determination, and detects that double feeding has occurred when the output voltage falls below the threshold voltage.

[0004] Generally, ultrasonic sensors have variations in sensitivity. For this reason, even in sheet conveying devices having the same configuration, it is difficult to uniquely determine the threshold voltage for double feeding determination, and calibration, so-called calibration, is required. In conventional calibration work, a calibration sheet in which a plurality of sheets are bonded together is placed between the oscillator and the receiver. Then, the threshold voltage is generally calibrated based on the output level of the receiver when the ultrasonic wave is oscillated from the oscillator.

[0005] However, such calibration work is inefficient because the ultrasonic wave must be oscillated from the oscillator. In addition, since a calibration sheet is required, the work is complicated.

Prior Art Documents

Patent Documents

[0006] Patent Document 1 Japanese Patent Application Laid-Open No. 2014-047075 Summary of the Invention Problems to be Solved by the Invention

[0007] The problem to be solved by the embodiment of the present invention is to provide a sheet conveying device capable of improving and simplifying the calibration work related to duplicate detection. Means for Solving the Problems

[0008] In one embodiment, the sheet conveying device includes a conveyance path, an oscillator, a receiver, an amplifier circuit, a comparator, a detection unit, and a calibration unit. The conveyance path conveys a sheet. The oscillator oscillates ultrasonic waves to the sheet conveyed on the conveyance path. The receiver is provided at a position facing the oscillator with the conveyance path in between. The receiver receives the ultrasonic waves oscillated from the oscillator. The amplifier circuit amplifies the output signal of the receiver. The comparator compares the voltage of the output signal amplified by the amplifier circuit with a threshold voltage. The detection unit detects the double feed of the sheet conveyed on the conveyance path based on the comparison result of the comparator. The calibration unit The input applied to one input terminal of the comparator calibrates the offset voltage of the amplifier circuit when the receiver is not receiving ultrasonic waves and the binarized output obtained by comparing it with the threshold voltage applied to the other input terminal of the comparator and the threshold voltage. The calibration unit raises the threshold voltage from a voltage lower than the offset voltage of the amplifier circuit and sets the voltage exceeding the offset voltage as the threshold voltage. Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the sheet conveying device will be described with reference to the drawings. This embodiment is a case where the ADF (Auto Document Feeder) of an MFP (Multi-Functional Peripheral: digital multi-function peripheral) is taken as one aspect of the sheet conveying device.

[0011] [Explanation of the Configuration of the MFP] FIG. 1 is a perspective view showing the external configuration of the MFP1. As shown in FIG. 1, the MFP1 has a scanner unit 2, a printer unit 3, a paper feed cassette unit 4, an operation panel 5, and an ADF6.

[0012] The scanner unit 2 is located at the upper part of the MFP main body including the printer unit 3. The scanner unit 2 scans a document and optically reads the image of the document. The scanner unit 2 includes a document glass 21 for placing the document to be scanned and an image reading mechanism. The image reading mechanism scans the document placed on the document glass 21 from below the document glass 21 through the glass and reads the image thereof. The image reading mechanism includes a carriage 22 and a photoelectric conversion unit 23. The carriage 22 is equipped with an optical system such as illumination and a mirror. The illumination is installed on the carriage 22 so that the emitted light irradiates the reading position on the document glass 21 from below the document glass 21. The reading position corresponds to an image for one line or a plurality of lines in the main scanning direction. The optical system such as a mirror is installed on the carriage 22 so as to guide the reflected light from the reading position irradiated by the illumination to the photoelectric conversion unit 23.

[0013] The carriage 22 is moved in the sub-scanning direction below the document glass 21 by a moving mechanism 24 (Fig. 5) including a stepping motor or the like. By moving in the sub-scanning direction, the carriage 22 continuously guides the images of each line in the main scanning direction in the area where the document is placed on the document glass 21, that is, the document reading area, to the photoelectric conversion unit 23.

[0014] The photoelectric conversion unit 23 has a lens, a photoelectric conversion sensor, etc. The lens condenses the light guided by the optical system of the carriage 22 and guides it to the photoelectric conversion sensor. The photoelectric conversion sensor is a line sensor in which photoelectric conversion elements such as CCDs or CISs are arranged in a line. The photoelectric conversion sensor converts the image for one line in the main scanning direction into pixel data for one line.

[0015] The printer unit 3 outputs the image information as an output image called, for example, a hard copy or a printout. Details of the printer unit 3 will be described later with reference to Fig. 2.

[0016] The paper feed cassette unit 4 is located at the lower part of the MFP main body. The paper feed cassette unit 4 supplies sheets used for image output to the printer unit 3. The sheets are generally papers of any size such as "A3", "B4", "A4", "B5", etc. The paper feed cassette unit 4 includes a first paper feed cassette 41, a second paper feed cassette 42, and a third paper feed cassette 43. The first paper feed cassette 41, the second paper feed cassette 42, and the third paper feed cassette 43 each accommodate one type of size of sheet.

[0017] The operation panel 5 is a user interface. The operation panel 5 displays guidance and accepts inputs of operation buttons or icons. The user is not limited to the user of the MFP1. The user includes, for example, the administrator of the MFP1, the service technician, etc. The operation panel 5 has a touch panel 51 and a plurality of operation buttons 52. The touch panel 51 serves as both an input device and a display device of the MFP1. The touch panel 51 arranges a touch sensor on the screen of the display. The display displays various images or texts including icons. The touch sensor detects the position on the screen touched by the user. The operation buttons 52 include a power button, a mode selection button, a numeric keypad button, a clear button, etc.

[0018] The ADF 6 is connected to the scanner unit 2. Details of the ADF 6 will be described later with reference to FIGS. 3 and 4.

[0019] FIG. 2 is a cross-sectional view schematically showing the internal configuration of the MFP1. As shown in FIG. 2, the first paper feed cassette 41, the second paper feed cassette 42, and the third paper feed cassette 43 in the paper feed cassette unit 4 each have a paper feed roller 411, 421, 431. Each paper feed roller 411, 421, 431 takes out sheets one by one from the first to third paper feed cassettes 41, 42, 43. The sheets taken out from the first to third paper feed cassettes 41, 42, 43 are conveyed to the printer unit 3 by the conveyance system 31.

[0020] The conveyance system 31 conveys the sheet within the MFP main body. The conveyance system 31 includes a plurality of conveyance rollers 311, 312, 313, 314 and a registration roller 315, etc. Further, the conveyance system 31 includes a motor for driving each of the conveyance rollers 311, 312, 313, 314 and the registration roller 315. The conveyance system 31 conveys the sheet taken out by any one of the paper feed rollers 411, 421 or 431 to the registration roller 315. The registration roller 315 conveys the sheet to the transfer position at the timing of transferring the image.

[0021] The printer unit 3 includes a plurality of image forming units 321, 322, 323, 324, an exposure device 33, an intermediate transfer belt 34, a transfer unit 35, and a fixing device 36.

[0022] Each of the image forming units 321, 322, 323, 324 has an image carrier 325 respectively. The exposure device 33 forms an electrostatic latent image on each image carrier 325 by scanning the image carriers 325 of each of the image forming units 321, 322, 323, 324 with light that emits according to the image data. Each of the image forming units 321, 322, 323, 324 develops the electrostatic latent image on each image carrier 325 with toner of each color, for example, yellow, magenta, cyan, and black.

[0023] The intermediate transfer belt 34 is an intermediate transfer member. Each of the image forming units 321, 322, 323, 324 transfers the toner images of each color developed with toner of each color on their respective image carriers 325 onto the intermediate transfer belt 34 by overlapping them. This transfer is called primary transfer. The intermediate transfer belt 34 holds the transferred toner image and sends it to the secondary transfer position.

[0024] The secondary transfer position is the position where the toner image on the intermediate transfer belt 34 is transferred to the sheet. There is a transfer unit 35 at the secondary transfer position. The transfer unit 35 has a support roller 351 and a secondary transfer roller 352. The secondary transfer position is the position where the support roller 351 and the secondary transfer roller 352 face each other. The registration roller 315 conveys the sheet to the secondary transfer position in synchronization with the toner image on the intermediate transfer belt 34. The transfer unit 35 transfers the toner image held on the intermediate transfer belt 34 to the sheet at the secondary transfer position.

[0025] The conveyance system 31 conveys the sheet onto which the toner image has been transferred at the transfer position to the fixing position. There is a fixing device 36 at the fixing position. The fixing device 36 has a heating unit 361, a heat roller 362, and a pressure roller 363. The fixing position is the position where the heat roller 362 and the pressure roller 363 face each other.

[0026] The heating unit 361 heats the heat roller 362. The heat roller 362 and the pressure roller 363 perform a fixing process of heating the sheet onto which the toner image has been transferred by the transfer unit 35 in a pressurized state. The fixing device 36 fixes the toner image to the sheet by the fixing process. The heat roller 362 and the pressure roller 363 send the sheet that has undergone the fixing process to the conveyance roller 314. The conveyance roller 314 discharges the sheet onto which the toner image has been fixed by the fixing device 36 to the paper discharge tray 30.

[0027] [Description of the ADF Configuration] FIG. 3 is a perspective view of the ADF 6. FIG. 4 is a schematic diagram showing a cross-section of the ADF 6. The ADF 6 has a sheet feeding unit 62 that feeds the sheet placed on the sheet feeding tray 61, and a paper discharging unit 64 that discharges the sheet conveyed inside the ADF 6 to the paper discharge tray 63.

[0028] ADF6 includes a conveyance path 65 for guiding the sheet fed from the sheet feeding unit 62 to the sheet discharging unit 64. Along the conveyance path 65, ADF6 arranges a plurality of conveyance rollers 661, 662, 663, 664 and a registration roller 67. Each of the conveyance rollers 661, 662, 663, 664 is arranged at various positions in the conveyance path 65 with the sheet feeding unit 62 of ADF6 as the conveyance start position and the sheet discharging unit 64 as the conveyance end position so as to be able to convey the sheet from the sheet feeding unit 62 to the sheet discharging unit 64. The registration roller 67 temporarily stops the conveyed sheet and conveys it downstream at an arbitrary timing.

[0029] ADF6 is a DSDF (Dual Scan Document Feeder). That is, ADF6 has a slit 68 at a position facing the scanner unit 2 of the conveyance path 65. ADF6 conveys the sheet fed from the sheet feeding unit 62 so that the sheet peeks out from the slit 68. The scanner unit 2 reads the image of the first side of the sheet conveyed along the conveyance path 65 from the slit 68. ADF6 includes a scanner 69 on the downstream side of the slit 68 in the conveyance path 65. The scanner 69 reads the image of the second side of the sheet opposite to the first side of the sheet conveyed along the conveyance path 65.

[0030] ADF6 is provided with a paper feed sensor 71 and a double feed sensor 72 in the vicinity of the paper feed unit 62 in the conveyance path 65. Specifically, ADF6 arranges the paper feed sensor 71 and the double feed sensor 72 between a conveyance roller 661 and a registration roller 67 which are arranged along the conveyance path 65. The paper feed sensor 71 is a sensor for detecting a sheet fed from the paper feed unit 62. The paper feed sensor 71 uses, for example, a reflective or transmissive optical sensor or the like. The double feed sensor 72 is a sensor for detecting double feeding in which a plurality of sheets are conveyed overlapping each other. The double feed sensor 72 uses an ultrasonic sensor. That is, the double feed sensor 72 includes an oscillator 721 that oscillates ultrasonic waves and a receiver 722 that receives the ultrasonic waves oscillated from the oscillator 721. The double feed sensor 72 arranges the oscillator 721 and the receiver 722 at positions facing each other with the conveyance path 65 interposed therebetween. Note that the arrangement relationship between the oscillator 721 and the receiver 722 is not limited to the arrangement shown in FIG. 4. In FIG. 4, the oscillator 721 is arranged below the conveyance path 65 and the receiver 722 is arranged above, but the up and down may be reversed.

[0031] [Circuit Description of MFP] FIG. 5 is a block diagram showing the main circuit configuration of MFP1. MFP1 includes a system control unit 8. The system control unit 8 is connected to the operation panel 5. Further, the system control unit 8 controls the scanner unit 2 and the printer unit 3.

[0032] The system control unit 8 has a processor 81, a memory 82, an image memory 83, an image processing unit 84, a storage device 85, a communication interface 86, and the like. The system control unit 8 connects the processor 81 to the memory 82, the image memory 83, the image processing unit 84, the storage device 85, the communication interface 86, and the like via a control signal line 87. Further, the system control unit 8 connects the operation panel 5 to the processor 81 via the control signal line 87.

[0033] The processor 81 realizes various processing functions as an MFP by executing the programs stored in the memory 82 or the storage device 85. For example, by executing a program, the processor 81 outputs operation instructions to each unit such as the scanner unit 2, the printer unit 3, or the ADF 6, and processes various information from each unit. Further, the processor 81 executes processing according to the operation input of the touch panel 51 or the operation button 52 of the operation panel 5. Also, the processor 81 controls the display on the touch panel 51 of the operation panel 5.

[0034] The memory 82 includes a RAM (Random Access Memory) and a ROM (Read Only Memory), etc. The RAM functions as a working memory or a buffer memory, etc. The ROM functions as a program memory, etc.

[0035] The image memory 83 stores image data. For example, the image memory 83 functions as a page memory for expanding the image data to be processed. The image processing unit 84 processes image data. The image processing unit 84 outputs, for example, image data obtained by performing image processing such as correction, compression, or decompression on the input image data.

[0036] The storage device 85 stores data such as control data, control programs, and setting information. The storage device 85 is a rewritable non-volatile memory. An HDD (Hard Disk Drive) or an SSD (Solid State Drive), etc. can be the storage device 85.

[0037] The communication interface 86 is an interface for performing data communication with an external device. For example, the communication interface 86 functions as an image acquisition unit that acquires an image to be printed on paper from an external device such as a PC.

[0038] The system control unit 8 has interfaces 91 and 92 with the scanner unit 2 and the printer unit 3. The processor 81 of the system control unit 8 is connected to the processor 25 of the scanner unit 2 via the interface 91. The processor 81 of the system control unit 8 is connected to the processor 37 of the printer unit 3 via the interface 92.

[0039] In addition to the carriage 22, the photoelectric conversion unit 23, and the moving mechanism 24 described above, the scanner unit 2 includes a processor 25, a memory 26, and the like. The scanner unit 2 connects the processor 25 to the memory 26, the carriage 22, the photoelectric conversion unit 23, the moving mechanism 24, and the like via the control signal line 27. The scanner unit 2 also connects the ADF 6 to the processor 25 via the control signal line 27.

[0040] By executing the program stored in the memory 26, the processor 25 realizes various processing functions as the scanner unit 2. For example, the processor 25 executes a scanning process in response to an operation instruction from the system control unit 8. The processor 25 also controls the driving of the ADF 6 in response to an operation instruction from the system control unit 8.

[0041] The memory 26 includes a RAM, a ROM, and the like. The RAM functions as a working memory or a buffer memory, etc. The ROM functions as a program memory, etc.

[0042] In addition to the conveyance system 31, the image forming units 321, 332, 323, 324, the exposure device 33, the transfer unit 35, and the fixing unit 36 described above, the printer unit 3 includes a processor 37, a memory 38, and the like. The printer unit 3 connects the processor 37 to the memory 38, the conveyance system 31, the image forming units 321, 322, 323, 324, the exposure device 33, the transfer unit 35, the fixing unit 36, and the like via the control signal line 39.

[0043] By executing the program stored in the memory 38, the processor 37 realizes various processing functions as the printer unit 3. For example, the processor 37 executes a printing process in response to an operation instruction from the system control unit 8.

[0044] The memory 38 includes a RAM, a ROM, etc. The RAM functions as a working memory or a buffer memory, etc. The ROM functions as a program memory, etc.

[0045] [Circuit description of ADF] FIG. 6 is a block diagram showing the main circuit configuration of the ADF 6. The ADF 6 includes, in addition to the scanner 69 described above, a processor 73, a memory 74, a conveyance system 75, a communication interface 76, a signal input circuit 77, a signal processing circuit 78, etc. The ADF 6 connects the processor 73 to the memory 74, the conveyance system 75, the communication interface 76, the signal input circuit 77, the signal processing circuit 78, etc. via a control signal line 79.

[0046] The conveyance system 75 is a mechanism for conveying the sheet fed from the sheet feeding unit 62 along the conveyance path 65 and discharging it from the sheet discharging unit 64. The conveyance system 75 includes a plurality of conveyance rollers 661, 662, 663, 664 and a registration roller 67. The conveyance system 75 also includes a motor for driving each of the conveyance rollers 661, 662, 663, 664 and the registration roller 67. The communication interface 76 functions as an interface with the scanner unit 2. The signal input circuit 77 inputs a signal from the sheet feeding sensor 71. The signal processing circuit 78 processes a signal related to the double feed sensor 72. Details of the signal processing circuit 78 will be described later with reference to FIG. 7.

[0047] The processor 73 controls each part according to the operation instructions given from the system control unit 8 via the scanner unit 2. For example, the processor 73 controls the conveyance system 75 to convey the sheet along the conveyance path 65. Also, when double-sided reading is instructed from the system control unit 8, the processor 73 controls the scanner 69 to read the image of the second side of the sheet. Then, the processor 7 outputs the image data read by the scanner 69 to the scanner unit 2 via the communication interface 76. The scanner unit 2 outputs the image data of the second side of the sheet received from the ADF 6, together with the image data of the first side of the sheet read by the scanner unit 2, to the system control unit 8 via the interface 91.

[0048] Figure 7 is a block diagram showing the main circuit configurations of the signal processing circuit 78 and the double-feed sensor 72. The signal processing circuit 78 includes a drive circuit 781, an amplifier circuit 782, a DAC (Digital Analog Converter) 783, and a comparator 784. The double-feed sensor 72 includes an ultrasonic oscillator 721 and a receiver 722.

[0049] The drive circuit 781 drives the oscillator 721 according to the oscillation signal osc given from the processor 73. By this drive, the oscillator 721 oscillates ultrasonic waves. The ultrasonic waves oscillated from the oscillator 721 are received by the receiver 722. The receiver 722 outputs a voltage signal according to the level of the received ultrasonic waves.

[0050] The amplifier circuit 782 amplifies the voltage signal output from the receiver 722. The amplifier circuit 782 supplies the amplified voltage signal to the inverting input terminal (-) of the comparator 784.

[0051] The DAC 783 converts the digital data Dx given from the processor 73 into an analog voltage signal. The DAC 783 supplies the converted voltage signal to the non-inverting input terminal (+) of the comparator 784.

[0052] Comparator 784 compares the voltage of the signal input to the inverting input terminal (-), i.e., the inverting input voltage, with the voltage of the signal input to the non-inverting input terminal (+), i.e., the non-inverting input voltage. When the inverting input voltage is lower than the non-inverting input voltage, comparator 784 outputs a binary signal E at a low level "L". When the inverting input voltage is higher than the non-inverting input voltage, comparator 784 outputs a binary signal E at a high level "H".

[0053] As shown in FIG. 6, processor 73 has a function as a detection unit 731 and a function as a calibration unit 732. Based on the comparison result of comparator 784 in signal processing circuit 78, detection unit 731 detects double feeding of the sheet conveyed on conveyance path 65. Specifically, when the binary signal output from comparator 784 is at a high level "H", detection unit 731 determines that double feeding has occurred. When the binary signal is at a low level "L", detection unit 731 determines that double feeding has not occurred.

[0054] Calibration unit 732 calibrates the threshold voltage input to comparator 784 based on the offset voltage of amplifier circuit 782 in signal processing circuit 78 when receiver 722 of double feed sensor 72 is not receiving ultrasonic waves. The threshold voltage is the voltage of the signal obtained by analog-converting digital data Dx given from processor 73 to DAC 783. Hereinafter, this threshold voltage is represented as Vx.

[0055] For processor 73 to function as calibration unit 732, ADF6 forms in memory 74 a storage area for digital data Dx corresponding to threshold voltage Vx, a storage area for the default value Ddef of digital data Dx, and a storage area for counter C.

[0056] [Description of the Detection Unit] FIG. 8 is an explanatory diagram of the voltage signal input to the inverting input terminal (-) of the comparator 784. In FIG. 8, the voltage signal in the section SEa is the voltage signal when an ultrasonic wave is oscillated from the oscillator 721 at the start point of the section SEa in a state where no medium such as a sheet is interposed between the oscillator 721 and the receiver 722. The voltage signal in the section SEb is the voltage signal when an ultrasonic wave is oscillated from the oscillator 721 at the start point of the section SEb in a state where one sheet is interposed between the oscillator 721 and the receiver 722. The voltage signal in the section SEc is the voltage signal when an ultrasonic wave is oscillated from the oscillator 721 at the start point of the section SEc in a state where one sheet thicker than the sheet in the section SEb is interposed between the oscillator 721 and the receiver 722. The voltage signal in the section SEd is the voltage signal when an ultrasonic wave is oscillated from the oscillator 721 at the start point of the section SEd in a state where two sheets identical to the sheet in the section SEb are stacked and interposed between the oscillator 721 and the receiver 722.

[0057] In FIG. 8, the voltage Va is the peak voltage of the voltage signal in the section SEa. The voltage Vb is the peak voltage of the voltage signal in the section SEb. The voltage Vc is the peak voltage of the voltage signal in the section SEc. The voltage Vd is the peak voltage of the voltage signal in the section SEd. The voltage Vs is the offset voltage of the amplifier circuit 782. As shown in FIG. 8, there is a relationship of the following formula (1) between the offset voltage Vs and each peak voltage Va, Vb, Vc, Vd, Ve. Va > Vb > Vc > Vs > Vd …(1) That is, the peak voltage of the voltage signal amplified by the amplifier circuit 782 from the output signal of the receiver 722 is highest when no medium such as a sheet is interposed between the oscillator 721 and the receiver 722. When a sheet is interposed between the oscillator 721 and the receiver 722, the ultrasonic wave reaching the receiver 722 is attenuated, so the peak voltage decreases. And the rate of decrease becomes larger as the thickness of the sheet increases. In particular, when double feeding occurs where two sheets overlap, attenuation occurs due to the air layer between the sheets, and the rate of decrease becomes even larger, and the peak voltage becomes lower than the offset voltage Vs. Incidentally, when the peak voltage is lower than the offset voltage Vs, the offset voltage Vs is input to the inverting input terminal (-) of the comparator 784.

[0058] FIGS. 9 and 10 are waveform diagrams showing the transition of the voltage signal input to the inverting input terminal (-) of the comparator 784. FIG. 9 represents the case where the state changes from the section SEa where no medium such as a sheet is interposed between the oscillator 721 and the receiver 722 to the section SEb where one sheet is interposed, that is, to the normal conveyance state, and then returns to the section SEa where no medium is interposed again. FIG. 10 represents the case where the state changes from the section SEa where no medium is interposed to the section SEb where two sheets are interposed, that is, to the state where double feeding has occurred, and then returns to the section SEa where no medium is interposed again.

[0059] In FIGS. 9 and 10, the waveform SW represents the ultrasonic wave signal oscillated from the oscillator 721. When the oscillation signal osc is given from the processor 73 to the drive circuit 781, the oscillator 721 starts oscillating. When the processor 73 detects the feeding of a sheet by the sheet feeding sensor 71, the oscillator signal osc is stopped for a fixed time P. When the oscillation signal osc stops, the oscillator 721 stops oscillating. When the fixed time P has elapsed, again, the oscillation signal osc is given from the processor 73 to the drive circuit 781. Thereby, the oscillator 721 resumes oscillation.

[0060] As shown in FIGS. 9 and 10, before reaching section SEa, that is, when the oscillator 721 is not oscillating, no signal is output from the receiver 722. Therefore, the offset voltage Vs of the amplifier circuit 782 is input to the inverting input terminal (-) of the comparator 784. That is, the inverting input voltage is the offset voltage Vs.

[0061] When the oscillator 721 starts oscillating upon entering section SEa, a signal corresponding to the reception level is output from the receiver 722. As a result, the inverting input voltage becomes the peak voltage Va of the state SEa where no medium is intervening.

[0062] Thereafter, when the paper feed sensor 71 detects the paper feed upon entering section SEb or section SEd and the oscillation of the oscillator 721 stops, the inverting input voltage becomes the offset voltage Vs of the amplifier circuit 782. Then, when a certain time P elapses and the oscillator 721 resumes oscillation, the level of the inverting input voltage is different in the case of FIG. 9 and the case of FIG. 10. That is, in the normal state SEb where one sheet is conveyed, the inverting input voltage becomes the peak voltage Vb of the state SEb. In the double-feed state SEd where sheets are conveyed overlapping each other, the inverting input voltage becomes the offset voltage Vs of the amplifier circuit 782.

[0063] Thereafter, when it becomes the state SEa, in both cases of FIGS. 9 and 10, the inverting input voltage becomes the peak voltage Va of the state SEa where no medium is intervening. Then, when the oscillation of the oscillator 721 stops, the inverting input voltage becomes the offset voltage Vs of the amplifier circuit 782.

[0064] As described with reference to FIGS. 8 to 10, when there is no double feed in the sheet conveyed through the conveyance path 65 by the conveyance system 75 of the ADF6, the inverting input voltage becomes a voltage higher than the offset voltage Vs of the amplifier circuit 782. On the other hand, when double feed occurs, the inverting input voltage becomes the offset voltage Vs of the amplifier circuit 782. Therefore, the non-inverting input voltage, that is, the threshold voltage Vx is set to a voltage slightly higher than the offset voltage Vs of the amplifier circuit 782. Then, the binary output from the comparator 784 becomes the low level "L" when there is no double feed, and becomes the high level "H" when double feed occurs. The detection unit 731 detects double feed when the binary output of the comparator 784 changes to the high level "H".

[0065] [Description of the calibration unit] As described above, when the threshold voltage Vx input to the non-inverting input terminal (+) of the comparator 784 is set to a voltage slightly higher than the offset voltage Vs of the amplifier circuit 782, the detection unit 731 can correctly detect double feed. On the other hand, the offset voltage Vs of the amplifier circuit 782 varies depending on the amplifier circuit 782. Therefore, for example, before shipping the product, it is necessary to calibrate so that the threshold voltage Vx becomes a voltage slightly higher than the offset voltage Vs of the amplifier circuit 782. Such calibration processing is realized by the calibration unit 732.

[0066] FIG. 11 is a flowchart showing the main procedure of the calibration process realized by the function of the calibration unit 732 by the processor 73. Note that the procedure described below is an example. The procedure and content are not particularly limited as long as the same operation result can be obtained.

[0067] For example, the user operates the operation panel 5 to select the calibration mode of the threshold voltage Vx. Then, a calibration of the threshold voltage Vx is commanded from the processor 81 of the system control unit 8 via the processor 25 of the scanner unit 2 to the processor 73 of the ADF6. In response to this command, the processor 73 starts the operation of the procedure shown in the flowchart of FIG. 11.

[0068] The processor 73 resets the counter C to “0” as ACT1. The processor 73 sets the digital data Dx output to the DAC 783 of the signal processing circuit 78 as the default value Ddef stored in the memory 74 as ACT2. Then, the processor 73 acquires the binarization signal E output from the comparator 784 of the signal processing circuit 78 as ACT3.

[0069] At this time, the oscillator 721 of the retransmission sensor 72 is not oscillating ultrasonic waves. Therefore, the offset voltage Vs of the amplifier circuit 782 is input to the inverting input terminal (-) of the comparator 784. On the other hand, the voltage of the voltage signal obtained by analog-converting the digital data Dx, i.e., the so-called threshold voltage Vx, is input to the non-inverting input terminal (+) of the comparator 784. When the threshold voltage Vx is higher than the offset voltage Vs of the amplifier circuit 782, the binarization signal E becomes the high level “H”. When the threshold voltage Vx is lower than the offset voltage Vs of the amplifier circuit 782, the binarization signal E becomes the low level “L”. The processor 73 checks whether the binarization signal E is at the high level “H” as ACT4.

[0070] Assume that the voltage of the signal obtained by analog-converting the default value Ddef with the DAC 783 is higher than the offset voltage Vs of the amplifier circuit 782. In this case, the binarization signal E becomes the high level “H”. The processor 73 determines YES in ACT4 and proceeds to ACT5. The processor 73 increments the counter C by “1” as ACT5.

[0071] The processor 73 checks whether the counter C has reached the set value “5” as ACT6. If the counter C has not reached the set value “5”, the processor 73 determines NO in ACT6 and returns to ACT3. The processor 73 executes the processing after ACT3 in the same manner as described above.

[0072] When the voltage of the signal obtained by analog-converting the default value Ddef with the DAC783 is higher than the offset voltage Vs of the amplifier circuit 782, the binarized signal E maintains the high level “H”. Therefore, since the closed loop of ACT3 to ACT6 is repeated, the counter C reaches the set value “5”. When the counter C reaches the set value “5”, the processor 73 determines YES in ACT6 and proceeds to ACT7. The processor 73 resets the counter C to “0” as ACT7. The processor 73 reduces the digital data Dx output to the DAC783 of the signal processing circuit 78 by 1 bit as ACT8. Then the processor 73 acquires the binarized signal E as ACT9.

[0073] The processor 73 checks whether the binarized signal E has become the “L” level as ACT10. Even if the digital data Dx is reduced by 1 bit from the default value Ddef, when the threshold voltage Vx is still higher than the offset voltage Vs of the amplifier circuit 782, the binarized signal E maintains the high level “H”. When the binarized signal E is at the high level “H”, the processor 73 determines NO in ACT10 and returns to ACT8. The processor 73 executes the processing after ACT8 in the same manner as described above.

[0074] Therefore, each time the closed loop of ACT8 to ACT10 is repeated, the digital data Dx becomes smaller by 1 bit. Accordingly, the threshold voltage Vx decreases step by step. When the threshold voltage Vx becomes lower than the offset voltage Vs of the amplifier circuit 782, the binarized signal E becomes the low level “L”.

[0075] When the binarized signal E becomes the low level “L”, the processor 73 determines YES in ACT10 and proceeds to ACT11. The processor 73 increments the counter C by “1” as ACT11. Then the processor 73 checks whether the counter C has reached the set value “5” as ACT12. If the counter C has not reached the set value “5”, the processor 73 determines NO in ACT12 and returns to ACT8. The processor 73 executes the processing after ACT8 in the same manner as described above.

[0076] In the closed loop of ACT8 to ACT12, the digital data Dx decreases by 1 bit at a time. Therefore, the threshold voltage Vx will not be higher than the offset voltage Vs of the amplifier circuit 782. That is, the binarization signal E maintains the low level "L", so the counter C counts up by "1". When the counter C reaches the set value "5", the processor 73 determines YES in ACT12 and proceeds to ACT13.

[0077] The processor 73 resets the counter C to "0" as ACT13. The processor 73 increases the digital data Dx by 1 bit as ACT14. Then the processor 73 acquires the binarization signal E as ACT15. The processor 73 checks whether the binarization signal E has become the high level "H" as ACT16.

[0078] By increasing the digital data Dx, the threshold voltage Vx increases. However, if the threshold voltage Vx is still lower than the offset voltage Vs of the amplifier circuit 782, the binarization signal E maintains the low level "L". When the binarization signal E maintains the low level "L", the processor 73 determines NO in ACT16 and returns to ACT14. The processor 73 executes the processing after ACT14 in the same manner as described above.

[0079] Therefore, until the threshold voltage Vx exceeds the offset voltage Vs of the amplifier circuit 782, the processor 73 repeats the closed loop of ACT14 to ACT16. That is, the processor 73 increases the digital data Dx by 1 bit at a time. As a result, when the threshold voltage Vx exceeds the offset voltage Vs of the amplifier circuit 782, the binarization signal E becomes the high level "H".

[0080] When the binary signal E becomes high level "H", the processor 73 determines YES in ACT16 and proceeds to ACT17. The processor 73 increments the counter C by "1" as ACT17. The processor 73 checks whether the counter C has reached the set value "5" as ACT18. If the counter C has not reached the set value "5", the processor 73 determines NO in ACT18 and returns to ACT14. The processor 73 executes the processes after ACT14 in the same manner as described above.

[0081] In the closed loop of ACT14 to ACT18, the digital data Dx increases by 1 bit at a time. Therefore, the threshold voltage Vx will not be lower than the offset voltage Vs of the amplifier circuit 782. That is, since the binary signal E maintains the high level "H", the counter C increments by "1". When the counter C reaches the set value "5", the processor 73 determines YES in ACT18 and proceeds to ACT19.

[0082] The processor 73 stores the current digital data Dx in the digital data Dx storage area of the memory 74 as ACT19. Thus, the processor 73 finishes the calibration process by the function of the calibration unit 732.

[0083] In this way, when the voltage of the signal obtained by analog-converting the default value Ddef by the DAC 783 is higher than the offset voltage Vs of the amplifier circuit 782, the processor 73 executes the processes of ACT3 to ACT19 to set the digital data Dx for determining the threshold voltage Vx.

[0084] In addition, when the voltage of the signal obtained by analog-converting the default value Ddef by the DAC783 is higher than the offset voltage Vs of the amplifier circuit 782, the processor 73 determines NO in ACT4. The processor 73 skips the processes of ACT5 to ACT12 and proceeds to ACT13. Then, the processor 73 executes the processes after ACT13 in the same manner as described above. That is, the processor 73 increases the digital data Dx by one bit from the default value Ddef. Then, when the binarization signal E becomes the high level "H", the digital data Dx is further increased by one bit until the counter C counts up to the set value "5". Then, when the counter C reaches the set value "5", the digital data Dx at that time is stored in the digital data Dx storage area of the memory 74.

[0085] FIG. 12 is a waveform diagram of the threshold voltage Vx and the binarization signal E that transition by the above calibration process. In FIG. 12, the voltage Vs is the offset voltage of the amplifier circuit 782. The voltage GND is the ground potential.

[0086] The time point ta corresponds to the time point of ACT2. When the digital data Dx of the default value Ddef is supplied to the DAC783, the threshold voltage Vx obtained by analog-converting the digital data Dx rises to a value higher than the offset voltage Vs of the amplifier circuit 782. Then, at the time point tb, a high-level "H" binarization signal E is output from the comparator 784. As a result, the processor 73 repeats the closed loop of ACT3 to ACT6.

[0087] The section Ha from the time point tb to the time point tc corresponds to the closed loop section of ACT3 to ACT6. The time point tc is the time point when YES is determined in ACT6, that is, the time point when the counter C reaches the set value "5". After this time point Tc, the digital data Dx becomes smaller by one bit from the default value Ddef. Therefore, the threshold voltage Vx decreases step by step. Then, at the time point td, the threshold voltage Vx becomes lower than the offset voltage Vs of the amplifier circuit 782. As a result, the binarization signal E becomes the low level "L".

[0088] The interval La from time point td to time point te corresponds to the closed-loop interval of ACT8 to ACT12. That is, in this interval La, the digital data Dx becomes smaller by "1" bit each time. Therefore, the threshold voltage Vx also becomes lower.

[0089] Time point te is the time point when it is determined as YES in ACT12, that is, the time point when the counter C reaches the set value "5". After this time point te, the digital data Dx becomes larger by 1 bit each time. Therefore, the threshold voltage Vx rises step by step. And at time point tf, the threshold voltage Vx becomes higher than the offset voltage Vs of the amplifier circuit 782. As a result, the binary signal E becomes high level "H".

[0090] The interval Hb from time point tf to time point tg corresponds to the closed-loop interval of ACT14 to ACT18. That is, in this interval Hb, the digital data Dx becomes larger by "1" bit each time. Therefore, the threshold voltage Vx also becomes higher.

[0091] Time point tg is the time point when it is determined as YES in ACT18, that is, the time point when the counter C reaches the set value "5". The digital data Dx at this time is stored in the memory. That is, after the threshold voltage Vx exceeds the offset voltage Vs of the amplifier circuit 782, it becomes a voltage with a value larger by 5 bits as the digital data Dx.

[0092] In this way, the calibration unit 732 calibrates the threshold voltage Vx based on the offset voltage Vs of the amplifier circuit 782 when the receiver 722 is not receiving ultrasonic waves. Therefore, the threshold voltage Vx can be calibrated without oscillating ultrasonic waves from the oscillator 721, so that the calibration of the threshold voltage Vx can be performed efficiently. Also, a calibration sheet is not required. Therefore, the calibration work is simple.

[0093] Further, the calibration unit 732 calibrates the threshold voltage Vx according to the output level of the binarization signal E obtained by comparing the offset voltage Vs of the amplifier circuit 782 input to one input terminal of the comparator 784 with the threshold voltage Vx input to the other input terminal of the comparator 784. Therefore, since the threshold voltage Vx can be calibrated by processing the binarization signal E, the calibration process can be automated as information processing by the processor 7.

[0094] Also, the calibration unit 732 increases the threshold voltage Vx from a voltage lower than the offset voltage Vs of the amplifier circuit 782 and sets a voltage exceeding the offset voltage Vs as the threshold voltage Vx. Therefore, even when the offset voltage Vs of the amplifier circuit 782 differs for each ADF6, a desired voltage higher than the offset voltage Vs can be surely set as the threshold voltage Vx.

[0095] Also, the calibration unit 732 uses a voltage higher than the offset voltage Vs of the amplifier circuit 782 as an initial value during threshold voltage calibration, decreases the threshold voltage Vx from the initial voltage, and after falling below the offset voltage Vs, increases it step by step to calibrate the threshold voltage Vx. Therefore, a desired voltage higher than the offset voltage Vs can be more surely set as the threshold voltage Vx.

[0096] In particular, the ADF6 includes a counter C that counts the number of times the same value is repeated after the binarization output value of the comparator 784 is inverted. Then, the calibration unit increases the threshold voltage Vx step by step and sets the voltage at the time when the counter C counts a predetermined value as the threshold voltage Vx. Therefore, by simply setting an appropriate value for the predetermined value for the counter C, it is possible to easily determine how much higher the voltage should be than the offset voltage Vs as the threshold voltage Vx.

[0097] The embodiments of the sheet conveying apparatus have been described above, but such embodiments are not limited thereto.

[0098] In the above embodiment, the set value compared with the counter C is set to "5". The set value is not limited to "5". The set value may be any value of "1" or more.

[0099] In the above embodiment, in ACT8 and ACT14 of FIG. 11, the case where the digital data Dx is changed bit by bit was exemplified. As another embodiment, the digital data Dx may be changed by two bits at a time. Alternatively, using the binary search technique, the digital data Dx that can obtain an appropriate threshold voltage Vx may be determined.

[0100] In the above embodiment, the calibration operation was described as being performed before the product is shipped. The calibration operation may be performed regularly or irregularly as part of maintenance after the product is shipped.

[0101] In the above embodiment, the ADF6 was described as a device that feeds paper to simultaneously scan both sides of the document, that is, a so-called DSDF. The ADF6 may be a device that feeds paper to scan one side of the document.

[0102] Also, the sheet conveyance device is not limited to the ADF6 of the MFP1. It may be a sheet conveyance device applied to a printer, a copier, a facsimile device, or the like.

[0103] In addition, although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope of the invention and are included in the invention described in the claims and its equivalent scope. The invention described in the original claims of the present application is appended below. [1] A sheet conveying device comprising: a conveyance path for conveying a sheet; an oscillator that oscillates ultrasonic waves to the sheet conveyed on the conveyance path; a receiver provided at a position facing the oscillator with the conveyance path therebetween, for receiving the ultrasonic waves oscillated from the oscillator; an amplifier circuit for amplifying the output signal of the receiver; a comparator for comparing the voltage of the output signal amplified by the amplifier circuit with a threshold voltage; a detection unit for detecting double feeding of the sheet conveyed on the conveyance path based on the comparison result of the comparator; and a calibration unit for calibrating the threshold voltage based on the offset voltage of the amplifier circuit when the receiver is not receiving the ultrasonic waves. [2] The sheet conveying device according to appended [1], wherein the calibration unit calibrates the threshold voltage by a binarized output obtained by comparing the offset voltage of the amplifier circuit input to one input terminal of the comparator with the threshold voltage input to the other input terminal of the comparator. [3] The sheet conveying device according to appended [2], wherein the calibration unit raises the threshold voltage from a voltage lower than the offset voltage of the amplifier circuit and sets the voltage exceeding the offset voltage as the threshold voltage. [4] The sheet conveying device according to appended [3], wherein the calibration unit uses a voltage higher than the offset voltage of the amplifier circuit as an initial value during threshold voltage calibration, lowers the threshold voltage from the voltage of the initial value, and then raises it step by step after falling below the offset voltage for calibration. [5] The sheet conveying device according to appended [4], further comprising a counter for counting the number of times the same value is repeated after the binarized output value of the comparator is inverted, and the calibration unit raises the threshold voltage step by step and sets the voltage when the counter counts a predetermined value as the threshold voltage.

Explanation of Reference Numerals

[0104] 1...MFP, 2...Scanner unit, 3...Printer unit, 4...Paper cassette unit, 5...Operation panel, 6...ADF, 61...Paper feed tray, 62...Paper feed section, 63...Paper discharge tray, 64...Paper discharge section, 65...Conveyor path, 69...Scanner, 71...Paper feed sensor, 72...Double feed sensor, 73...Processor, 74...Memory, 75...Conveyor system, 76...Communication interface, 77...Signal input circuit, 78...Signal processing circuit, 721...Oscillator, 722...Receiver, 731...Detection section, 732...Calibration section, 781...Drive circuit, 782...Amplifier circuit, 783...DAC, 784...Comparator.

Claims

1. A conveyance path for conveying a sheet, An oscillator that oscillates ultrasonic waves to the sheet conveyed on the conveyance path, A receiver provided at a position facing the oscillator with the conveyance path therebetween, for receiving the ultrasonic waves oscillated from the oscillator, An amplifier circuit for amplifying the output signal of the receiver, A comparator for comparing the voltage of the output signal amplified by the amplifier circuit with a threshold voltage, A detection unit for detecting double feeding of the sheet conveyed on the conveyance path based on the comparison result of the comparator, A calibration unit for calibrating the threshold voltage by a binary output obtained by comparing the offset voltage of the amplifier circuit when the receiver input to one input terminal of the comparator is not receiving the ultrasonic waves with the threshold voltage input to the other input terminal of the comparator, and comprising: The calibration unit raises the threshold voltage from a voltage lower than the offset voltage of the amplifier circuit and sets a voltage exceeding the offset voltage as the threshold voltage, a sheet conveyance device.

2. The calibration unit uses a voltage higher than the offset voltage of the amplifier circuit as an initial value during threshold voltage calibration, lowers the threshold voltage from the voltage of the initial value, and then raises it step by step after falling below the offset voltage for calibration. The sheet conveyance device according to Claim 1.

3. A counter for counting the number of times the same value is repeated after the binary output value of the comparator is inverted, is provided, The calibration unit raises the threshold voltage step by step and sets the voltage when the counter counts a predetermined value as the threshold voltage. The sheet conveyance device according to Claim 2.

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