Thin film transistor, thin film transistor array, screen display device using the same, and planar sensor

Abstract

To provide a bottom gate type organic / inorganic hybrid thin film transistor having excellent transistor characteristics and high flexibility.SOLUTION: A thin film transistor includes: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed of one or more films formed on the gate electrode; an inorganic semiconductor layer formed on the gate insulating layer; and source / drain electrodes formed on the inorganic semiconductor layer. The gate insulating layer has a first gate insulating layer formed using an organic material and a second gate insulating layer formed using an inorganic material. The second gate insulating layer is formed on a part of the first gate insulating layer. The first gate insulating layer is not in contact with the inorganic semiconductor layer. The second gate insulating layer has a film thickness of 2 nm or more and 50 nm or less, and contacts at least partially the inorganic semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a thin film transistor and a thin film transistor array.

Background Art

[0002] Currently, there is an increasing demand for flexible devices in which devices such as displays and sensors are formed on a flexible substrate.

[0003] Generally, devices that do not require flexibility are driven by inorganic TFTs (thin film transistors) in which an inorganic semiconductor such as amorphous silicon or an oxide semiconductor is formed as a semiconductor layer on a glass substrate.

[0004] As the gate insulating film of the inorganic TFT, generally, an inorganic insulating film such as silicon oxide, silicon nitride, or silicon oxynitride formed by chemical vapor deposition or the like is used, and is deposited with a film thickness of about several hundred nm in order to maintain electrical breakdown voltage.

[0005] However, since the above-mentioned inorganic gate insulating film is inferior in flexibility, when a flexible device is manufactured using an amorphous silicon TFT formed on a resin substrate, there is a problem that cracks easily occur when it is bent and used.

[0006] On the other hand, an organic TFT having an organic semiconductor as a semiconductor layer can use an organic insulating film excellent in flexibility as a gate insulating layer, and thus is excellent in flexibility. Therefore, it is expected to be applied to flexible devices.

[0007] However, the organic TFT has disadvantages such as inferior air stability and long-term reliability compared with the amorphous silicon TFT. This disadvantage mainly stems from the organic semiconductor material.

[0008] Therefore, a manufacturing technique for an organic / inorganic hybrid TFT that combines an organic gate insulating film and an inorganic semiconductor has attracted attention. Non-Patent Document 1 reports a top-gate type hybrid TFT that combines an organic insulating film and an oxide semiconductor. (Non-Patent Document 1).

Prior Art Documents

Non-Patent Documents

[0009]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] As a TFT structure, the bottom-gate type is considered preferable for ease of manufacturing. However, as also described in Non-Patent Document 1, it is difficult to realize a bottom-gate type hybrid TFT with a simple configuration.

[0011] The reason for the difficulty in realization is that when an inorganic semiconductor is deposited on an organic gate insulating film using a vacuum deposition apparatus utilizing plasma, the surface of the organic gate insulating film is exposed to the plasma and damaged, resulting in the generation of carrier traps at the insulating film / semiconductor interface, preventing the construction of a good interface state and thus unable to obtain the desired TFT characteristics.

[0012] In view of the above points, an object of the present invention is to provide a thin-film transistor that has good characteristics and high flexibility even in a bottom-gate type structure in an organic / inorganic hybrid TFT.

Means for Solving the Problem

[0013] The thin film transistor for solving the above problems includes an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed of one or more layers of films formed on the gate electrode, an inorganic semiconductor layer formed on the gate insulating layer, and a source / drain electrode formed on the inorganic semiconductor layer. The gate insulating layer has a first gate insulating layer formed using an organic material and a second gate insulating layer formed using an inorganic material. The second gate insulating layer is formed on a part of the first gate insulating layer. The first gate insulating layer is not in contact with the inorganic semiconductor layer. The second gate insulating layer has a film thickness of 2 nm or more and 50 nm or less, and at least a part thereof is in contact with the inorganic semiconductor layer. Moreover, the area of the second region where the second gate insulating layer is formed is 5% or less of the area of the first region where the first gate insulating layer is formed. 。

[0014] Also, The area of the second region where the second gate insulating layer is formed is 2% or more of the area of the first region where the first gate insulating layer is formed. it may be.

[0015] Also, the second gate insulating layer may contain any one of oxides, nitrides, and oxynitrides selected from silicon, aluminum.

[0016] Also, the inorganic semiconductor layer may be an oxide containing at least one of indium, gallium, zinc, and tin.

Advantages of the Invention

[0017] According to the present invention, it is possible to provide an organic / inorganic hybrid thin film transistor having good transistor characteristics and high flexibility.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Mode for Carrying Out the Invention

[0019] Hereinafter, with reference to the drawings, an embodiment of a thin-film transistor will be described. In the embodiments, the same reference numerals are given to the same components, and overlapping descriptions between the embodiments are omitted.

[0020] FIGS. 1 to 4 show schematic diagrams representing a cross-sectional structure and a planar structure of a thin-film transistor 100 according to the present embodiment and a thin-film transistor 101 according to a modified example of the thin-film transistor 100. Both the thin-film transistors 100 and 101 are bottom-gate-top-contact type thin-film transistors including an insulating substrate 0, a gate electrode 1 formed on the insulating substrate 0, a first gate insulating layer 2 formed at least on the gate electrode 1, a second gate insulating layer 3 formed on a part of the first gate insulating layer 2, an inorganic semiconductor layer 4 formed on the second gate insulating layer 3, and a source electrode 5 and a drain electrode 6 formed on the inorganic semiconductor layer 4 and the first gate insulating layer 2 and the second gate insulating layer 3. The gate insulating layer 7 has a first gate insulating layer 2 formed using an organic material and a second gate insulating layer 3 formed using an inorganic material. The first gate insulating layer 2 is not in contact with the inorganic semiconductor layer 4, and the second gate insulating layer 3 is in contact with the inorganic semiconductor layer 4 at least partially.

[0021] In thin film transistors 100 and 101, an example of a second gate insulating layer 3 provided on a part of the first gate insulating layer 2 is shown. At this time, the area of the second region where the second gate insulating layer 3 is formed and the area of the region where the inorganic semiconductor layer 4 is formed may be equal as shown in FIG. 3, or as shown in FIG. 4, the area of the second gate insulating layer 3 may be larger than the area of the region where the inorganic semiconductor layer 4 is formed. Further, the structures of the thin film transistors 100 and 101 of the present embodiment are not limited to the bottom gate-top contact type shown in FIGS. 1 to 2, and may be a top gate-top contact type, a top gate-bottom contact type, a bottom gate-bottom contact type, etc., but are not limited to this.

[0022] As materials to be used for the insulating substrate 0, for example, a flexible substrate using polyimide, polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone (PES), polyolefin, polyethylene terephthalate, polyethylene naphthalate (PEN), cycloolefin polymer, polyethersulfene, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, fluorine-based resin, cyclic polyolefin-based resin, etc. can be used. These materials can be used alone, or a composite substrate in which two or more kinds are laminated can be used, but are not limited thereto.

[0023] The thickness of the insulating substrate 0 is preferably 2 μm or more and 100 μm or less. Since the thinner the insulating substrate 0 is, the more difficult it is to handle during manufacturing, the thickness of the insulating substrate 0 is preferably 2 μm or more. Also, the thicker the insulating substrate 0 is, the lower the flexibility is and the higher the material cost of the insulating substrate becomes. Therefore, the thickness of the insulating substrate 0 is preferably 100 μm or less. Considering the three points of handling during manufacturing, maintaining flexibility, and material cost, it is more preferable that the thickness of the insulating substrate 0 is 15 μm or more and 30 μm or less.

[0024] The gate electrode 1, source electrode 5, and drain electrode 6 can be obtained by patterning a single-layer or laminated film of a metal film such as Mo, Al, Ag, Cu, etc. formed by a vacuum film-forming apparatus such as sputtering, or a metal oxide film such as ITO (indium tin oxide), IZO (indium zinc oxide), etc. using a photolithography method or the like. Further, the gate electrode 1, source electrode 5, and drain electrode 6 of the present invention can also be formed by applying, by screen printing, transfer printing, letterpress printing, inkjet method, etc., and firing, a material obtained by making a metal material such as Ag, Cu, Au, etc., a metal oxide material such as ITO (indium tin oxide), IZO (indium zinc oxide), etc., or an organic conductive material such as PEDOT (polyethylenedioxythiophene) into an ink or paste form, but is not limited thereto.

[0025] The first gate insulating layer 2 is a layer formed using an organic substance. For example, a polymer solution such as polyvinylphenol, polymethyl methacrylate, polyimide, polyvinyl alcohol, cycloolefin polymer, etc. can be applied using a spin coating method, slit die coating method, etc., and formed by firing. Further, if a resin material having photosensitivity is added to the above-described materials and a material enabling patterning by photolithography is used for the first gate insulating layer 2 of the present invention, patterning becomes easy, which is particularly preferable.

[0026] The film thickness of the first gate insulating layer 2 is preferably 0.2 μm or more and 2.0 μm or less. From the viewpoint of suppressing the gate voltage for driving the thin film transistor, the thickness of the first gate insulating layer 2 is preferably 2.0 μm or less. From the viewpoint of suppressing current leakage, the thickness of the first gate insulating layer 2 is preferably 0.2 μm or more. Further, from the viewpoint of enhancing the effectiveness of obtaining these effects, enhancing the uniformity of the thickness of the first gate insulating layer 2, and improving the productivity of the first gate insulating layer 2, the thickness of the first gate insulating layer 2 is more preferably 0.5 μm or more and 1.0 μm or less.

[0027] The second gate insulating layer 3 is a layer formed mainly of an inorganic substance, and examples thereof include oxides, nitrides, oxynitrides, etc. containing any one of silicon, aluminum, tantalum, hafnium, zirconium, yttrium, lanthanum, europium, niobium, strontium. Specific materials include, but are not limited to, inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconia, and tantalum oxide. Among these, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide are more preferably used because of the easier process control and lower raw material prices. Also, these may be used as a single layer or multiple layers may be laminated.

[0028] The second gate insulating layer 3 is preferably formed using a vacuum film forming apparatus such as a sputtering apparatus or a chemical vapor deposition apparatus. The second gate insulating layer 3 formed using a vacuum film forming apparatus has higher plasma resistance than when formed by coating. Therefore, even when the inorganic semiconductor layer 4 is formed using a vacuum film forming apparatus utilizing plasma, it is possible to construct a good gate insulating film / semiconductor layer interface with few carrier traps and achieve high transistor characteristics.

[0029] In this embodiment, during the film formation of the second gate insulating layer 3, the surface of the first gate insulating layer 2 will be damaged by plasma. However, since the interface (channel) with the inorganic semiconductor layer 4, which is important as the operating region of the thin film transistors 100 and 101, is the surface of the second gate insulating layer 3, even if the surface of the first gate insulating layer 2 is damaged by plasma, it does not affect the transistor characteristics.

[0030] The film thickness of the second gate insulating layer 3 is preferably 2 nm or more and 50 nm or less. If the film thickness is less than 2 nm, a continuous film cannot be formed and an island-like film is formed, which is not preferable because a good gate insulating film / semiconductor layer interface cannot be constructed. Also, if the film thickness exceeds 50 nm, cracks are likely to occur when formed on a flexible substrate and bent, which is not preferable.

[0031] It is preferable that the area of the second region where the second gate insulating layer 3 is formed is 10% or less of the area of the first region where the first gate insulating layer 2 is formed. If the area of the second region exceeds 10% of the area of the first region, when a film is formed on the flexible substrate and bent, the second gate insulating layer 3 is likely to crack, deteriorating the transistor characteristics, which is not preferable. The second gate insulating layer 3 may be present on the first gate insulating layer, and the area of the second region may be larger than 0% of the area of the first region. Also, the smaller the area of the second region is compared to the area of the first region, the higher the flexibility becomes.

[0032] The first region and the second region may each be formed of one region, or the first region may be formed of one region and the second region may be formed of a plurality of regions, or both the first region and the second region may be formed of a plurality of regions. When formed of a plurality of regions, the sum of the areas of the respective regions is taken as the area of the first region and the area of the second region.

[0033] The specific first region and second region will be described with reference to FIGS. 5 to 7. FIGS. 5 and 6 show a plan view and a cross-sectional view of the thin film transistor 103 in one pixel. A pixel indicates the minimum display or minimum detection unit of a display or sensor created using a transistor. In the present embodiment, the unit shown in FIG. 5 is defined as one pixel. FIG. 7 shows a plan view of a TFT (Thin Film Transistor) array in which a plurality of pixels are arranged in an array.

[0034] The area of the first region in FIG. 5 indicates the area of the region where the first gate insulating layer 12 is formed within one pixel. The area of the second region indicates the area of the region where the second gate insulating layer 13 is formed within one pixel. FIG. 5 shows an example where one transistor exists within one pixel, but a plurality of transistors may exist. When a plurality of transistors exist, since the second gate insulating layer 13 is formed at a plurality of locations, the area of the second region is indicated by the total area of the regions where each second gate insulating layer 13 is formed. FIG. 5 shows an example where the first gate insulating layer 12 is formed over the entire area within one pixel, but the first gate insulating layer 12 may be formed in a part within one pixel.

[0035] FIG. 7 shows an example in which six pixels (3×2) are arranged. If a display body is formed on a TFT (Thin Film Transistor) array in which transistors are arranged in an array, it can be used as a display, and if a sensor member is formed, it can be applied to a planar sensor. Examples of the display body include, but are not limited to, liquid crystal, organic electroluminescence, quantum dots, micro LEDs, electrophoretic type electronic full panels, etc. Examples of the sensor member include, but are not limited to, a pressure-sensitive member, a temperature-sensitive member, etc.

[0036] When arrayed as shown in FIG. 7, the area of the region obtained by summing the first gate insulating layers formed in each pixel is defined as the area of the first region, and the area of the region obtained by summing the second gate insulating layers formed in each pixel is defined as the area of the second region. When arraying, the first gate insulating layer may be divided for each pixel, may be divided for every plurality of pixels, or may be a continuous layer without division.

[0037] The material of the inorganic semiconductor layer 4 is preferably an oxide containing at least one of indium, gallium, zinc, and tin. More specifically, known metal oxide semiconductor materials such as indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, and indium gallium zinc oxide can be used. In addition, those obtained by mixing aluminum, silicon, hafnium, tungsten, magnesium, lanthanum, etc. into these metal oxides can also be used. Further, other materials such as metal oxide semiconductors other than the above, non-single crystal silicon, molybdenum disulfide, gallium nitride, cadmium telluride, and gallium arsenide may be used for the inorganic semiconductor layer 4.

[0038] The inorganic semiconductor layer 4 is preferably formed using a vacuum film forming apparatus such as sputtering or CVD. The above-mentioned film formed using a vacuum film forming apparatus becomes a film with higher purity, higher density, and uniformity than a coating-type inorganic film, so it has high mobility and can realize high transistor characteristics when used for the thin film transistors 100 and 101.

Example

[0039] Hereinafter, specific examples and comparative examples of the thin film transistor according to the present embodiment will be described. Note that the present embodiment is not limited to each example.

[0040] (Example 1) Example 1 will be described. FIGS. 8 and 9 show schematic views showing the cross-sectional structure of the thin film transistor 103 according to Example 1. On a 15-μm-thick polyimide film as the insulating substrate 10, AlNd with a film thickness of 80 nm was formed at room temperature using a DC magnetron sputtering apparatus. After film formation, a resist pattern was formed using a photolithography method, and then wet etching and resist stripping were performed to form the gate electrode 11. The input power during AlNd film formation was 100 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa.

[0041] Next, as the first gate insulating layer 12, an acrylic polymer film having a thickness of 1 μm was formed. When forming the acrylic polymer film, first, a coating film was formed by applying an acrylic polymer solution containing an acrylic polymer, which is an organic polymer compound, onto the upper surfaces of the insulating substrate 10 and the gate electrode 11 using the spin coating method. Then, the acrylic polymer film was obtained by baking the coating film.

[0042] <Film formation conditions of the acrylic polymer film> · Substrate rotation speed: 800 rpm / 30 seconds · Baking temperature: 230 °C · Baking time: 1 hour The area of the first region where the first gate insulating layer 12 is formed was formed to be 200 μm × 200 μm.

[0043] Next, using a plasma CVD apparatus, SiOx with a film thickness of 50 nm was formed.

[0044] The film formation conditions of the silicon oxide film using the plasma CVD apparatus are shown below. <Film formation conditions of the silicon oxide film> · Reaction gas: Silane / Dinitrogen monoxide · Reaction gas flow rate: 65 sccm (silane), 500 sccm (dinitrogen monoxide) · Film formation pressure: 200 Pa · High-frequency power: 500 W · High-frequency power frequency: 13.56 MHz · Substrate temperature: 200 °C · Film formation time: 120 seconds After film formation, after forming a resist pattern using the photolithography method, dry etching and resist stripping were performed to form the second gate insulating layer 13. The area of the second region where the second gate insulating layer 13 is formed is 50 μm × 80 μm, which is 10% of the area of the first region.

[0045] Next, InGaZnO with a film thickness of 40 nm was deposited at room temperature using a DC magnetron sputtering apparatus. The input power during film deposition was 100 W, the gas flow rates were Ar = 100 SCCM and O2 = 1 SCCM, and the film deposition pressure was 1.0 Pa. Next, after forming a resist pattern using photolithography, wet etching and resist stripping were performed to form an inorganic semiconductor layer 14 on the second gate insulating layer 13. The area of the inorganic semiconductor layer 14 is 50 μm × 80 μm.

[0046] Finally, Mo with a film thickness of 80 nm was deposited at room temperature using a DC magnetron sputtering apparatus. After forming a resist pattern using photolithography, wet etching and resist stripping were performed to form a source electrode 15 and a drain electrode 16, obtaining a thin film transistor 103. The channel length of the fabricated thin film transistor 103 is 10 μm, and the channel width is 50 μm.

[0047] With the gate voltage set to ±20 V, the Transfer characteristics of the thin film transistor 103 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin film transistor 103 was 10.9 cm 2 / Vs, and the ON / OFF ratio when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16 was approximately six digits, indicating good transistor characteristics.

[0048] The fabricated thin film transistor 103 was wound around a metal rod with a diameter of 1 mm, and after performing a static bending test, the mobility of the thin film transistor 103 was 10.6 cm 2 / Vs, and the ON / OFF ratio when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16 was approximately six digits, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin film transistor 103 with an optical microscope after the test, no cracks or the like were found, and no abnormalities were particularly observed.

[0049] (Example 2) Example 2 will be described. As shown in FIGS. 10 and 11, it was fabricated in the same manner as in Example 1, except that the area of the inorganic semiconductor layer 14 was formed to be 40 μm × 60 μm.

[0050] With the gate voltage set to ±20 V, the Transfer characteristics of the thin film transistor 104 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin film transistor 104 was 10.8 cm 2 / Vs, and the ON / OFF ratio was approximately six digits when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, indicating good transistor characteristics.

[0051] The fabricated thin film transistor 104 was wound around a metal rod with a diameter of 1 mm. After performing a static bending test, the mobility of the thin film transistor 104 was 10.7 cm 2 / Vs, and the ON / OFF ratio was approximately six digits when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin film transistor 104 with an optical microscope after the test, no cracks or other abnormalities were found.

[0052] (Example 3) Example 3 will be described. As shown in FIGS. 8 and 9, it was fabricated in the same manner as in Example 1, except that the film formation time of the second gate insulating layer 12 was set to 72 seconds and the film thickness was formed to be 30 nm.

[0053] With the gate voltage set to ±20 V, the Transfer characteristics of the thin film transistor 103 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin film transistor 103 was 11.0 cm 2 / Vs, and the ON / OFF ratio was approximately six digits when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, indicating good transistor characteristics.

[0054] The fabricated thin film transistor 103 was wound around a metal rod with a diameter of 1 mm. After performing a static bending test, the mobility of the thin film transistor 103 was 11.0 cm 2When a voltage of 10 V was applied between the / Vs, source electrode 15 and drain electrode 16, the ON / OFF ratio was about six digits, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin-film transistor 103 with an optical microscope after the test, no cracks or the like were found, and no abnormalities were observed in particular.

[0055] (Example 4) Example 4 will be described. It was fabricated in the same manner as in Example 1, except that the film formation time of the second gate insulating layer 12 was set to 5 seconds and the film thickness was formed to be 2 nm.

[0056] With the gate voltage set to ±20 V, the Transfer characteristics of the thin-film transistor 103 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin-film transistor 103 was 11.0 cm 2 / Vs. When a voltage of 10 V was applied between the source electrode 15 and drain electrode 16, the ON / OFF ratio was about six digits, indicating good transistor characteristics.

[0057] The fabricated thin-film transistor 103 was wound around a metal rod with a diameter of 1 mm, and after a static bending test, the mobility of the thin-film transistor 103 was 11.0 cm 2 / Vs. When a voltage of 10 V was applied between the source electrode 15 and drain electrode 16, the ON / OFF ratio was about six digits, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin-film transistor 103 with an optical microscope after the test, no cracks or the like were found, and no abnormalities were observed in particular.

[0058] (Example 5) Example 5 will be described. It was fabricated in the same manner as in Example 1, except that the substrate rotation speed of spin coating when forming the first gate insulating layer 12 was changed to 2000 rpm / 30 seconds and the film thickness was formed to be 0.5 μm.

[0059] With the gate voltage set to ±20 V, the Transfer characteristics of the thin-film transistor 107 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin-film transistor 103 was 11.0 cm 2 / Vs. When a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, the ON / OFF ratio was approximately six digits, indicating good transistor characteristics.

[0060] The fabricated thin-film transistor 103 was wound around a metal rod with a diameter of 1 mm, and after performing a static bending test, the mobility of the thin-film transistor 103 was 10.9 cm 2 / Vs. When a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, the ON / OFF ratio was approximately six digits, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin-film transistor 103 with an optical microscope after the test, no cracks or other abnormalities were found.

[0061] (Example 6) Example 6 will be described. FIGS. 12 and 13 show schematic diagrams representing the cross-sectional structure of the thin-film transistor 108 according to Example 6. The thin-film transistor 108 was fabricated in the same manner as in Example 1, except that the area of the second region where the second gate insulating layer 13 was formed and the inorganic semiconductor layer 14 was set to 10 μm × 20 μm. The second region where the second gate insulating layer 13 was formed is 5% of the first region where the first gate insulating layer 12 was formed. The channel length of the fabricated thin-film transistor 108 is 8 μm, and the channel width is 10 μm.

[0062] With the gate voltage set to ±20 V, the Transfer characteristics of the thin-film transistor 108 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin-film transistor 108 was 11.2 cm 2 / Vs. When a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, the ON / OFF ratio was approximately six digits, indicating good transistor characteristics.

[0063] The fabricated thin-film transistor 108 was wound around a metal rod with a diameter of 1 mm. After the static bending test, the mobility of the thin-film transistor 108 was 11.2 cm 2 / Vs, and the ON / OFF ratio was about six digits when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin-film transistor 108 with an optical microscope after the test, no cracks or other abnormalities were found.

[0064] (Example 7) Example 7 will be described. FIGS. 14 and 15 show schematic views of the cross-sectional structure of the thin-film transistor 109 according to Example 7. The thin-film transistor 109 was fabricated in the same manner as in Example 1, except that the area of the second region where the second gate insulating layer was formed and the inorganic semiconductor layer 14 was 10 μm × 8 μm. The second region where the second gate insulating layer 13 was formed is 5% of the first region where the first gate insulating layer 12 was formed. The channel length of the fabricated thin-film transistor 109 is 8 μm, and the channel width is 8 μm.

[0065] With the gate voltage set to ±20 V, the Transfer characteristics of the thin-film transistor 109 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin-film transistor 109 was 11.0 cm 2 / Vs, and the ON / OFF ratio was about six digits when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, indicating good transistor characteristics.

[0066] The fabricated thin-film transistor 109 was wound around a metal rod with a diameter of 1 mm. After the static bending test, the mobility of the thin-film transistor 109 was 10.0 cm 2 / Vs, and the ON / OFF ratio was about six digits when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin-film transistor 109 with an optical microscope after the test, no cracks or other abnormalities were found.

[0067] (Example 8) Example 8 will be described. FIGS. 20 and 21 show a cross-sectional view and a plan view of one pixel of an image display device according to Example 8. On a polyimide substrate with a thickness of 15 μm as the insulating substrate 10, AlNd with a film thickness of 80 nm was deposited at room temperature using a DC magnetron sputtering apparatus. After the film deposition, a resist pattern was formed using photolithography, and then wet etching and resist stripping were performed to form the gate electrode 11, the gate wiring 21, and the capacitor wiring 26. The input power during AlNd film deposition was 100 W, the gas flow rate was Ar = 50 SCCM, and the film deposition pressure was 1.0 Pa.

[0068] Next, a photosensitive acrylic resin was applied by spin coating, patterned using photolithography, and baked at 230° C. to obtain a first gate insulating layer 12 with a thickness of 1 μm.

[0069] Next, SiOx with a film thickness of 50 nm was deposited using a plasma CVD apparatus.

[0070] The film deposition conditions of the silicon oxide film using the plasma CVD apparatus are shown below. <Film Deposition Conditions of Silicon Oxide Film> ·Reaction gas: silane / dinitrogen monoxide ·Reaction gas flow rate: 65 sccm (silane), 500 sccm (dinitrogen monoxide) ·Film deposition pressure: 200 Pa ·RF power: 500 W ·RF power frequency: 13.56 MHz ·Substrate temperature: 200° C. ·Film deposition time: 120 seconds After the film deposition, a resist pattern was formed using photolithography, and then dry etching and resist stripping were performed to form the second gate insulating layer 13.

[0071] Next, using a DC magnetron sputtering apparatus, InGaZnO with a film thickness of 40 nm was deposited at room temperature. The input power during film deposition was 100 W, the gas flow rate was Ar = 100 SCCM, O2 = 1 SCCM, and the film deposition pressure was 1.0 Pa. Next, after forming a resist pattern using photolithography, wet etching and resist stripping were performed to form an inorganic semiconductor layer 14 on the second gate insulating layer 13.

[0072] Next, using a DC magnetron sputtering apparatus, AlNd with a film thickness of 80 nm was deposited at room temperature. The input power during AlNd film deposition was 100 W, the gas flow rate was Ar = 50 SCCM, and the film deposition pressure was 1.0 Pa. After forming a resist pattern using photolithography, wet etching and resist stripping were performed to form a source electrode 15, a source wiring 22, and a drain electrode 16.

[0073] Next, a photosensitive acrylic resin solution was applied, patterned by photolithography, and baked at 220 °C to obtain an interlayer insulating layer 23 and an opening 24 in the interlayer insulating layer. The film thickness of the interlayer insulating layer 23 was 3 μm.

[0074] Next, using a DC magnetron sputtering apparatus, AlNd with a film thickness of 80 nm was deposited at room temperature. The input power during AlNd film deposition was 100 W, the gas flow rate was Ar = 50 SCCM, and the film deposition pressure was 1.0 Pa. After film deposition, after forming a resist pattern using photolithography, wet etching and resist stripping were performed to form a top electrode 25, and a thin film transistor array substrate 200 was obtained. The pixel size of the fabricated thin film transistor array substrate 200 was 100 μm × 100 μm, and the number of pixels was 480 pixels × 640 pixels. Also, the area of the second region where the second gate insulating layer is formed is 10% of the area of the first region.

[0075] Finally, the mobility of the thin film transistor array after a static bending test of the fabricated thin film transistor array substrate 200 was 10.0 cm 2When a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, the ON / OFF ratio was about six digits, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin-film transistor array with an optical microscope after the test, no cracks or other abnormalities were found.

[0076] Furthermore, an image display device 300 was fabricated by sandwiching an electrophoretic medium 31 between the thin-film transistor array substrate 200 and the counter electrode 32 and driving it. As a result, the display was good and reproducible without change before and after bending.

[0077] (Example 9) Example 9 will be described. FIGS. 21 and 22 show a cross-sectional view and a plan view of one pixel of a pressure sensor according to Example 9. On a polyimide substrate with a thickness of 15 μm as the insulating substrate 10, AlNd with a film thickness of 80 nm was deposited at room temperature using a DC magnetron sputtering apparatus. The input power during AlNd film deposition was 100 W, the gas flow rate was Ar = 50 SCCM, and the film deposition pressure was 1.0 Pa. After film deposition, a resist pattern was formed using photolithography, and then wet etching and resist stripping were performed to form the gate electrode 11 and the gate wiring 21.

[0078] Next, a photosensitive acrylic resin was applied by spin coating, patterned using photolithography, and baked at 230° C. to obtain a first gate insulating layer 12 with a thickness of 0.7 μm.

[0079] Next, SiOx with a film thickness of 50 nm was deposited using a plasma CVD apparatus.

[0080] The film deposition conditions of the silicon oxide film using the plasma CVD apparatus are shown below. <Film Deposition Conditions of Silicon Oxide Film> ·Reaction gas: silane / dinitrogen monoxide ·Reaction gas flow rate: 65 sccm (silane), 500 sccm (dinitrogen monoxide) ·Film deposition pressure: 200 Pa ·High-frequency power: 500 W · High-frequency power frequency: 13.56 MHz · Substrate temperature: 200 °C · Film formation time: 120 seconds After film formation, a resist pattern was formed using photolithography. Then, dry etching and resist stripping were performed to form the second gate insulating layer 13.

[0081] Next, using a DC magnetron sputtering apparatus, InGaZnO with a film thickness of 40 nm was deposited at room temperature. The input power during film formation was 100 W, the gas flow rate was Ar = 100 SCCM, O2 = 1 SCCM, and the film formation pressure was 1.0 Pa. Next, after forming a resist pattern using photolithography, wet etching and resist stripping were performed to form the inorganic semiconductor layer 14 on the second gate insulating layer 13. The area of the inorganic semiconductor layer 14 is 10 μm × 20 μm.

[0082] Next, using a DC magnetron sputtering apparatus, AlNd with a film thickness of 80 nm was deposited at room temperature. The input power during AlNd film formation was 100 W, the gas flow rate was Ar = 50 SCCM, and the film formation pressure was 1.0 Pa. After forming a resist pattern using photolithography, wet etching and resist stripping were performed to form the source electrode 15, source wiring 22, and drain electrode 16.

[0083] Next, a photosensitive acrylic resin solution was applied, patterned by photolithography, and baked at 220 °C to obtain the interlayer insulating layer 23. The film thickness of the interlayer insulating layer 23 was set to 3 μm.

[0084] Next, an adhesive containing Ag particles to be the upper electrode 25 was formed by screen printing to obtain the thin-film transistor array substrate 201. The film thickness of the upper electrode 25 was set to 5 μm. The pixel size of the thin-film transistor array substrate 201 is 200 μm × 200 μm, and the number of pixels is 10 pixels × 10 pixels. Also, the area of the second region where the second gate insulating layer is formed is 2% of the area of the first region.

[0085] The mobility of the thin film transistor after the static bending test of the finally fabricated thin film transistor array substrate 200 was 10.0 cm 2 / Vs. When a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, the ON / OFF ratio was about six digits, indicating good transistor characteristics equivalent to those after fabrication. As a result of observing the surface of the thin film transistor array with an optical microscope after the test, no cracks or the like were found, and no abnormalities were particularly observed.

[0086] Next, as the pressure-sensitive layer 41, a film of a polarized polyvinylidene fluoride-trifluoroethylene copolymer (P(VDF)-TrFE) with a film thickness of 20 μm was bonded to the thin film transistor 201. Finally, Ag paste was printed by the screen printing method and fired to form a counter electrode 42 with a film thickness of 30 μm, thereby fabricating the pressure sensor 301.

[0087] When the finally fabricated pressure sensor was driven, there was no change before and after bending, and a pressure-electric signal could be obtained reproducibly.

[0088] (Comparative Example 1) Comparative Example 1 will be described. FIGS. 16 and 17 show schematic views of the cross-sectional structure of the thin film transistor 110 according to Comparative Example 1. The thin film transistor 110 was fabricated in the same manner as in Example 1 except that the second gate insulating layer 12 forming step was omitted.

[0089] With the gate voltage set to ±20 V, the Transfer characteristics of the thin film transistor 110 were measured using a semiconductor parameter analyzer. As a result, no off characteristics were observed, and the ON / OFF ratio when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16 was less than one digit, and good transistor characteristics could not be obtained.

[0090] (Comparative Example 2) A description will be given of Comparative Example 2. FIGS. 8 and 9 show schematic views representing the cross-sectional structure of the thin-film transistor 103 according to Comparative Example 2. The thin-film transistor 103 was fabricated in the same manner as in Example 1, except that the film formation time of the second gate insulating layer 13 was 168 seconds and the film thickness was 70 nm.

[0091] With the gate voltage set to ±20 V, the Transfer characteristics of the thin-film transistor 103 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin-film transistor 103 was 10.8 cm 2 / Vs, and the ON / OFF ratio was six digits when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16.

[0092] Next, the fabricated thin-film transistor 103 was wound around a metal rod with a diameter of 1 mm, and a dynamic bending test was performed 10,000 times. After the dynamic bending test, the mobility of the thin-film transistor 103 was 3.8 cm 2 / Vs, and the ON / OFF ratio was approximately three digits when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16. A decrease in mobility and ON / OFF ratio was confirmed as compared with after fabrication. When the surface of the thin-film transistor 103 was observed with an optical microscope after the test, slight cracks were observed in the second gate insulating layer 13.

[0093] (Comparative Example 3) A description will be given of Comparative Example 3. FIGS. 18 and 19 show schematic views representing the cross-sectional structure of the thin-film transistor 111 according to Comparative Example 3. The thin-film transistor 111 was fabricated in the same manner as in Example 1, except that the area of the second region where the second gate insulating layer was formed was 100 μm × 80 μm. The second region where the second gate insulating layer 13 was formed is 20% of the first region where the first gate insulating layer 12 was formed.

[0094] With the gate voltage set to ±20 V, the Transfer characteristics of the thin-film transistor 111 were measured using a semiconductor parameter analyzer. As a result, the mobility of the thin-film transistor 111 was 10.6 cm 2When a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16, the ON / OFF ratio was about six digits, indicating good transistor characteristics.

[0095] The fabricated thin-film transistor 111 was wound around a metal rod with a diameter of 1 mm, and a static bending test was performed. After the static bending test, no on characteristics were observed for the thin-film transistor 111, and the ON / OFF ratio when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16 was less than one digit. When the surface of the thin-film transistor 111 was observed with an optical microscope after the test, cracks were found in the second gate insulating layer 13.

[0096] (Comparative Example 4) Comparative Example 4 will be described. It was fabricated in the same manner as in Example 1, except that the film formation time of the second gate insulating layer was 2.5 seconds and the film thickness was 1 nm.

[0097] With the gate voltage set at ±20 V, the Transfer characteristics of the thin-film transistor 103 were measured using a semiconductor parameter analyzer. As a result, no off characteristics were observed, and the ON / OFF ratio when a voltage of 10 V was applied between the source electrode 15 and the drain electrode 16 was one digit, and good transistor characteristics could not be obtained.

[0098] Table 1 shows the main part dimensions and measurement results of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, Comparative Example 1, Comparative Example 2, Comparative Example 3, and Comparative Example 4, respectively.

[0099] As shown in Table 1, in Examples 1 to 9, good transistor characteristics were obtained before and after the static bending test, and no cracks occurred. From these results, it was confirmed that when the film thickness of the second gate insulating layer was 2 nm or more and 50 nm or less, and the area of the second region was 10% or less of the area of the first region, a thin-film transistor and a thin-film transistor array with both good transistor characteristics and flexibility could be obtained.

[0100] In Comparative Example 1, the inorganic semiconductor layer 14 was formed using a vacuum film-forming apparatus (DC magnetron sputtering apparatus) that utilized plasma without providing the second gate insulating layer 13 on the first gate insulating layer 12. For this reason, carrier traps were generated at the insulator / semiconductor interface, and a good interface state could not be constructed, resulting in poor transistor characteristics.

[0101] In Comparative Example 2, although the second gate insulating layer 13 was formed on the first gate insulating layer 12, the film thickness of the second gate insulating layer 13 exceeded 50 nm. For this reason, although good transistor characteristics were obtained before the static bending test, sufficient flexibility could not be ensured, and cracks occurred in the second gate insulating layer 13 after the static bending test, resulting in poor transistor characteristics.

[0102] In Comparative Example 3, although the second gate insulating layer 13 was formed on the first gate insulating layer 12, the area of the second region exceeded 10% of the area of the first region. For this reason, although good transistor characteristics were obtained before the static bending test, sufficient flexibility could not be ensured, and cracks occurred in the second gate insulating layer 13 after the static bending test, resulting in poor transistor characteristics.

[0103] In Comparative Example 4, although the second gate insulating layer 13 was formed on the first gate insulating layer 12, the film thickness of the second gate insulating layer 13 was 2 nm or less, and the first gate insulating layer 12 could not be sufficiently covered by the second gate insulating layer 13. Carrier traps were generated at the insulator / semiconductor interface due to plasma damage during the film formation of the inorganic semiconductor layer 14 with respect to the second gate insulating layer 12, and a good interface state could not be constructed, resulting in poor transistor characteristics.

[0104]

Table 1

[0105] As described above, according to the present invention, there are provided an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed of one or more layers of films formed on the gate electrode, an inorganic semiconductor layer formed on the gate insulating layer, and source / drain electrodes formed on the inorganic semiconductor layer. The gate insulating layer includes a first gate insulating layer formed using an organic material and a second gate insulating layer formed using an inorganic material. The second gate insulating layer is formed on a part of the first gate insulating layer. The first gate insulating layer is not in contact with the inorganic semiconductor, and the second gate insulating layer has a film thickness of 2 nm or more and 50 nm or less and is in contact with at least a part of the inorganic semiconductor layer, thereby providing a thin film transistor having good characteristics and high flexibility.

Industrial Applicability

[0106] The thin film transistor fabricated according to the present invention can be applied to display devices such as electronic paper display devices, liquid crystal display devices, and organic electroluminescence display devices, and various sensors such as piezoelectric sensors. In particular, application to flexible devices taking advantage of flexibility is expected.

Explanation of Reference Numerals

[0107] 100, 101, 103, 104, 108 to 111 Thin film transistor 0 Insulating substrate 1 Gate electrode 2 First gate insulating layer 3 Second gate insulating layer 4 Inorganic semiconductor layer 5 Source electrode 6 Drain electrode 7 Gate insulating layer 10 Insulating substrate 11 Gate electrode 12 First gate insulating layer 13 Second gate insulating layer 14 Inorganic semiconductor layer 15 Source electrode 16 Drain electrode 21 Gate wiring 22 Source wiring 23 Interlayer insulating layer 24 Interlayer insulating layer opening 25 Upper electrode 31 Electrophoretic medium 32 Counter electrode 41 Pressure-sensitive layer 42 Counter electrode

Claims

1. An insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed of one or more layers of films formed on the gate electrode, an inorganic semiconductor layer formed on the gate insulating layer, and a source / drain electrode formed on the inorganic semiconductor layer, The gate insulating layer, A first gate insulating layer formed using an organic material, And a second gate insulating layer formed using an inorganic material, The second gate insulating layer is formed on a part of the first gate insulating layer, The first gate insulating layer is not in contact with the inorganic semiconductor, The second gate insulating layer has a film thickness of 2 nm or more and 50 nm or less, and at least a part thereof is in contact with the inorganic semiconductor layer, A thin film transistor in which the area of the second region where the second gate insulating layer is formed is 5% or less of the area of the first region where the first gate insulating layer is formed.

2. The thin film transistor according to claim 1, wherein the area of the second region where the second gate insulating layer is formed is 2% or more of the area of the first region where the first gate insulating layer is formed.

3. The thin film transistor according to claim 1 or 2, wherein the second gate insulating layer contains any one of oxides, nitrides, and oxynitrides selected from silicon and aluminum.

4. The thin film transistor according to any one of claims 1 to 3, wherein the inorganic semiconductor layer is an oxide containing at least one of indium, gallium, zinc, and tin.

5. A flexible display and a planar sensor using the thin film transistor according to claims 1 to 4.

Images