Semiconductor Chip, Test Method, Test Apparatus, Memory Medium, and Program Product

Abstract

The present application relates to a semiconductor testing method, a testing apparatus, a chip, a storage medium and a program product, particularly to the field of semiconductor devices. The method includes the steps of: upon receiving target addressing information corresponding to a target circuit module in a semiconductor chip, determining a target pin corresponding to the target circuit module inside the semiconductor chip according to the target addressing information; turning on the target pin and an external test pin of the semiconductor chip through a target non-volatile memory; and in response to receiving a test signal transmitted by a test instrument connected to the external test pin, generating an output signal and transmitting it to the test instrument, and the test instrument generates a test result of the target circuit module according to the output signal. The above solution proposes a method for testing an internal module of a semiconductor from the outside of a semiconductor chip without exposing a wafer, so as to test the circuit module in the semiconductor chip and avoid damaging the wafer.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on September 6, 2021, with the application number 202111035542.9 and the title "Semiconductor Testing Method and Testing Apparatus", the entire content of which is incorporated herein by reference.

[0002] This application relates to the field of semiconductor devices, and specifically to semiconductor testing methods, testing apparatuses, chips, storage media, and program products.

Background Art

[0003] In the production process of semiconductor chips, in order to ensure the production quality of semiconductor chips, it is necessary to perform processes such as the design, simulation, and testing of semiconductor chips.

[0004] In the prior art, when testing semiconductor chips, it is usually divided into two inspection steps: wafer inspection and finished product testing. Wafer inspection refers to performing a functional inspection and an electrical parameter test on bare chips on a wafer through the cooperation of a probe station and a tester. Finished product testing refers to performing an overall function and electrical parameter test on packaged chips through the cooperation of a sorter and a tester.

[0005] In the above solution, it is common to damage bare chips during wafer inspection, and package inspection cannot test circuit modules in semiconductor chips individually.

Summary of the Invention

Means for Solving the Problems

[0006] This application provides a semiconductor testing method, testing apparatus, chip, storage medium, and program product that can test circuit modules in a semiconductor chip and prevent damage to the wafer. The solution is as follows.

[0007] In a first aspect, when receiving target address specification information corresponding to a target circuit module in the semiconductor chip and executed by the semiconductor chip, based on the target address specification information, determining a target pin corresponding to the target circuit module inside the semiconductor chip, wherein the target pin is connected to an external test pin of the semiconductor chip via a target non-volatile memory; turning on the target pin and the external test pin of the semiconductor chip via the target non-volatile memory; in response to receiving a test signal transmitted by a test device connected to the external test pin, generating an output signal and transmitting the output signal to the test device, and the test device generating a test result of the target circuit module based on the output signal. A semiconductor test method is provided that includes these steps.

[0008] In one possible embodiment, the step of turning on the target pin and the external test pin of the semiconductor chip via the target non-volatile memory includes the test address specification module in the semiconductor chip transmitting a control signal to the target non-volatile memory to set the target non-volatile memory to an on state, and turning on the target pin and the external test pin of the semiconductor chip.

[0009] In another aspect, a chip test apparatus based on the reconstruction of the internal circuit structure of the chip is provided. The semiconductor test apparatus is applied to a semiconductor chip. When the apparatus receives target address specification information corresponding to a target circuit module in the semiconductor chip, based on the target address specification information, it is a pin determination unit for determining a target pin corresponding to the target circuit module, and the target pin is connected to an external test pin of the semiconductor chip via a target non-volatile memory. A pin connection unit for connecting the target pin and the external test pin of the semiconductor chip via the target non-volatile memory, and in response to receiving a test signal transmitted by a test device connected to the external test pin, transmitting an output signal to the test device, and a test data output unit for generating a test result of the target circuit module based on the output signal by the test device.

[0010] In one possible embodiment, the pin connection unit is used to instruct a test address specification module in the semiconductor chip to transmit a control signal to the target non-volatile memory, set the target non-volatile memory to an on state, and connect the target pin and the external test pin of the semiconductor chip.

[0011] In one possible embodiment, the apparatus further includes a memory off unit for instructing a test address specification module in the semiconductor chip to transmit a control signal to another non-volatile memory in the semiconductor chip except the target non-volatile memory and set the other non-volatile memory to an off state.

[0012] In one possible embodiment, when the apparatus receives address specification recovery information corresponding to the target circuit module by a test address specification module in the semiconductor chip, based on the address specification recovery information, the apparatus further includes a connection recovery unit for recovering the connection state between the target pin and the external test pin of the semiconductor chip to a default state.

[0013] In one possible embodiment, when the adjustment addressing module in the semiconductor chip receives adjustment information corresponding to the target circuit module, the circuit adjustment unit further includes a circuit adjustment unit for changing the structure of the target circuit module by adjusting the adjustment module corresponding to the target circuit module based on the adjustment information.

[0014] In one possible embodiment, the circuit adjustment unit is further used for connecting or disconnecting a capacitor corresponding to the adjustment information based on the adjustment information, or for connecting or disconnecting a resistor corresponding to the adjustment information based on the adjustment information.

[0015] In one possible embodiment, after the structure of the target circuit module is changed based on the adjustment information, the test data output unit further transmits an output signal to the test equipment in response to receiving a test signal transmitted by the test equipment, and the test equipment is used for generating a test result of the target circuit module after being updated based on the output signal.

[0016] In a further aspect, a semiconductor chip is provided, which includes a test addressing module, a target circuit module and a target non-volatile memory. When the test addressing module in the semiconductor chip receives target addressing information corresponding to the target circuit module, it is used for determining a target pin corresponding to the target circuit module based on the target addressing information. The target non-volatile memory is used for turning on the target pin and an external test pin of the semiconductor chip. The target circuit module generates an output signal and transmits it to the test equipment in response to receiving a test signal transmitted by the test equipment connected to the external test pin, and the test equipment is used for generating a test result of the target circuit module based on the output signal.

[0017] In one possible embodiment, the test address specifying module further transmits a control signal to the target non-volatile memory to set the target non-volatile memory to an on state, and is used to turn on the target pin and the external test pin of the semiconductor chip.

[0018] In another aspect, there is provided a computer-readable storage medium that is uploaded to and executed on a semiconductor chip and stores at least one instruction or information for implementing the method according to any of the above aspects.

[0019] In a further aspect, there is provided a computer program product including computer instructions that, when executed on an electronic device, cause the electronic device to implement a method for testing a chip based on the reconstruction of the internal circuit structure of the chip according to any of the above aspects.

Advantages of the Invention

[0020] The technical solution provided by the present application can include the following beneficial effects. When it is necessary to test a circuit module inside a semiconductor chip, first, determine the target pin corresponding to the circuit module inside the semiconductor chip, and then, through the target non-volatile memory, turn on the pins inside the semiconductor chip and the external test pins of the semiconductor chip, and turn on the test device and the external test pins, so that a test signal can be input into the target pin corresponding to the target circuit module, thereby realizing the testing of the target circuit module. Therefore, the above solution proposes a method for testing the internal module of a semiconductor from the outside of the semiconductor chip without exposing the wafer, and tests the circuit module inside the semiconductor chip while not damaging the wafer.

Brief Description of the Drawings

[0021] To more clearly explain the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used for describing the specific embodiments or the prior art will be briefly described below. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

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Best Mode for Carrying Out the Invention

[0022] Hereinafter, with reference to the drawings, the technical solution of the present application will be clearly and completely described. It is clear that the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the present application.

[0023] It should be understood that the "instruction" referred to in the embodiments of the present application may be a direct instruction, an indirect instruction, or may mean having a relevant relationship. For example, A instructing B may mean that A directly instructs B, for example, B can be obtained by A, or A indirectly instructs B, for example, A instructs C and B is obtained by C, or it may mean that there is a relevant relationship between A and B.

[0024] In the description of the embodiments of the present application, the term "corresponding" may mean that there is a direct corresponding relationship or an indirect correspondence between the two, may mean that there is a relevant relationship between the two, or may be a relationship such as instruction and being instructed, arrangement and being arranged, etc.

[0025] In the embodiments of the present application, "predefinition" can be realized by pre-saving codes, tables, or other methods that can instruct information corresponding to devices (including, for example, terminal devices and network devices), and the present application does not limit its specific implementation method.

[0026] FIG. 1 is a schematic structural diagram of a semiconductor chip shown in one exemplary embodiment. The semiconductor chip includes a test address designating module 101, a target circuit module 102, and a target non-volatile memory 103. When the test address specifying module receives the target address specifying information corresponding to the target circuit module in the semiconductor chip, it is used to determine the target pin corresponding to the target circuit module based on the target address specifying information, and the target pin is connected to the external test pin of the semiconductor chip through the target non-volatile memory.

[0027] The target non-volatile memory is used to turn on the target pin and the external test pin of the semiconductor chip.

[0028] In response to receiving the test signal transmitted by the test equipment connected to the external test pin, the target circuit module generates an output signal and transmits it to the test equipment, and the test equipment is used to generate the test result of the target circuit module based on the output signal.

[0029] In the semiconductor chip according to the embodiment of the present application, the access pins of each module that needs to be tested in the semiconductor chip are connected to the external test pins of the semiconductor chip through the non-volatile memory. When it is necessary to test a specific circuit module in the semiconductor chip, the test address specifying module in the semiconductor chip determines the pin corresponding to the circuit module and turns on the pin corresponding to the circuit module and the external test pin. At this time, the test equipment connected to the external test pin can test the circuit module inside the semiconductor chip through the external test pin.

[0030] Referring to FIG. 2, a structural schematic diagram of the non-volatile memory according to the embodiment of the present application is shown. As shown in FIG. 2, M1 is a tunnel diode, C1 is a MOS (MOSFET, metal-oxide-semiconductor field-effect transistor) capacitor, and M2 is a switch transistor.

[0031] M1 is a PMOS (P-channel metal-oxide-semiconductor field-effect transistor) transistor, and the drain electrode and source electrode of M1 are connected to the substrate.

[0032] M2 is a P-LDMOS (lateral-diffused metal-oxide semiconductor) transistor in which the source electrode and the gate electrode are not connected, and the source electrode and the drain electrode of M2 are connected to the pins of the circuit module and the external test pins, respectively.

[0033] The reasons for designing M2 as a P-LDMOS transistor in which the source electrode and the gate electrode are not connected mainly include the following. (1) Test pins are connected to both ends of M2 in this application. Certain test pins inevitably need to use high voltages. However, all the switch transistors in a normal non-volatile memory are low-voltage MOS transistors and cannot withstand the high voltages of analog circuits. Therefore, it is necessary to select and use an LDMOS transistor. (2) Since both ends of M2 need to be connected to high-voltage test pins, it is necessary to ensure that the source electrode and the gate electrode are not connected so that the voltage difference between the gate electrode and the substrate can be individually controlled. This voltage difference is not affected by the voltage of the source electrode, and the on and off of the switch transistor are realized. (3) When the source electrode and the gate electrode of M2 are connected, both the direction of the current flowing through M2 and the voltage directions of the drain electrode and the source electrode are constant. Test pins are connected to both ends of M2, and the voltage and current directions between the two test pins change according to whether the pins are used as inputs or outputs, that is, the directions are indefinite. Therefore, at this time, it is necessary to design M2 so that the source electrode and the gate electrode are not connected, and M2 forms a completely symmetric structure. Thereby, when the voltage difference between the gate electrode and the substrate meets the requirements, the current can flow from the drain electrode to the source electrode or from the source electrode to the drain electrode.

[0034] The operation modes of the non-volatile memory shown in Figure 2 are as follows.

[0035] ON mode: The CG terminal is connected to the high voltage VP, and the TG terminal is connected to 0V. At this time, a very large forward voltage drop occurs across the tunnel diode M1. Electrons tunnel through the gate oxide layer from the channel below the gate oxide layer of M1 and are accumulated in the polysilicon gate. The FG terminal is accumulated as "1". During this process, the potential on FG continues to decrease. Therefore, the forward voltage across M1 continues to decrease. Eventually, it becomes insufficient to cause tunneling, and the accumulation of the FG terminal remains "1". At this time, there are multiple electrons in the polysilicon gate. Due to these multiple electrons, the electrons near the gate electrode in the N-type substrate of the PMOS transistor are repelled, and holes are attracted. Due to the attracted holes, the drain electrode and source electrode of M2 are turned on, that is, M2 is turned on, and the pin of the circuit module is integrally connected to the external test pin.

[0036] OFF mode: The TG terminal is connected to the high voltage VP, and the CG terminal is connected to 0V. At this time, a very large reverse voltage drop occurs across the tunnel diode M1. Electrons tunnel through the gate oxide layer from the polysilicon gate and are extracted into the well region of M1. The node FG is accumulated as "0". During this process, the potential on FG continues to increase. Therefore, the reverse voltage across M1 continues to decrease. Eventually, it becomes insufficient to cause tunneling, and the accumulation of the FG terminal remains "0". At this time, no electrons are accumulated in the polysilicon gate, no conductive holes can be formed between the drain electrode and source electrode of M2, and the drain electrode and source electrode of M2 are disconnected, that is, M2 is turned off, and the pin of the circuit module is not integrally connected to the external test pin.

[0037] Therefore, at this time, the test address specifying module outputs a control signal based on the address specifying information, and is designed to connect the adjustment signal of the CG terminal of the memory that needs to be turned on to the high voltage VP, and the adjustment signal of the TG terminal to 0V, and is designed to connect the adjustment signal of the TG terminal of other memories to the high voltage VP, and the adjustment signal of the CG terminal to 0V.

[0038] Referring to FIG. 3, a structural schematic diagram of the non-volatile memory according to the embodiment of the present application is shown. As shown in FIG. 3, M3 is a tunnel diode, C2 is a MOS capacitor, and J1 is a switch transistor.

[0039] M3 is a PMOS transistor, and the drain electrode and source electrode of M3 are connected to the substrate.

[0040] J1 is an N-JFET (Junction Field-Effect Transistor) transistor, and the source electrode and drain electrode of J1 are connected to the pin of the circuit module and the external test pin, respectively.

[0041] The reasons for designing J1 as an N-JFET transistor mainly include the following. (1) Test pins are connected to both ends of J1 in the present application. A specific test pin inevitably needs to use a high voltage. However, all the switch transistors in a normal non-volatile memory are low-voltage MOS transistors and cannot withstand the high voltage of the analog circuit. Therefore, it is necessary to select and use an N-JFET transistor. (2) Both ends of J1 need to be connected to high-voltage test pins. Since the source electrode and gate electrode of the N-JFET transistor are not connected, the voltage difference between the gate electrode and the substrate can be controlled individually. This voltage difference is not affected by the voltage of the source electrode, and the on and off of the switch transistor are realized. At the same time, the source electrode and drain electrode of the N-JFET transistor are N regions, and the gate electrode is a P region. Therefore, no matter how high the voltage connected to the source electrode and drain electrode is, no path is formed between the drain electrode or source electrode and the gate electrode. (3) The N-JFET transistor has a completely symmetrical structure, and its current can flow from the drain electrode to the source electrode or from the source electrode to the drain electrode.

[0042] The operation mode is as follows.

[0043] ON mode: The TG terminal is connected to the high voltage VP, and the CG terminal is connected to 0V. At this time, a very large reverse voltage drop occurs across the tunnel diode M3. Electrons tunnel from the polysilicon gate through the gate oxide layer and are extracted into the well region of M3. The node FG is accumulated as "0". During this process, the potential on FG continues to increase. Therefore, the reverse voltage across M3 continues to decrease. Eventually, it becomes insufficient to cause tunneling, and the accumulation of the FG terminal remains "0". At this time, no electrons are accumulated in the polysilicon gate. Since both the drain electrode and the source electrode of J1 are N-type regions, the drain electrode and the source electrode of J1 are connected through the N-type conductive channel between the drain electrode and the source electrode. That is, J1 is turned on, and the pin of the circuit module and the external test pin are integrally connected.

[0044] OFF mode: The CG terminal is connected to the high voltage VP, and the TG terminal is connected to 0V. At this time, a very large forward voltage drop occurs across the tunnel diode M3. Electrons tunnel from the channel below the gate oxide layer of M3 through the gate oxide layer and are accumulated in the polysilicon gate. The FG terminal is accumulated as "1". During this process, the potential on FG continues to decrease. Therefore, the forward voltage across M3 continues to decrease. Eventually, it becomes insufficient to cause tunneling, and the accumulation of the FG terminal remains "1". At this time, there are multiple electrons in the polysilicon gate. Due to these multiple electrons, the electrons near the gate electrode in the N-type conductive channel of J1 are repelled, and holes are attracted. Due to the attracted holes, the N-type conductive channel is blocked, and the N-type conductive channel cannot conduct electrons. The drain electrode and the source electrode of J1 are disconnected. That is, J1 is turned off, and the pin of the circuit module and the external test pin are not integrally connected.

[0045] Therefore, at this time, the test address specifying module outputs a control signal based on the address specifying information, and is designed to connect the adjustment signal of the TG terminal of the memory that needs to be turned on to the high voltage VP, design to connect the adjustment signal of the CG sub to 0V, and design to connect the adjustment signals of the CG terminals of other memories to the high voltage VP and connect the adjustment signal of the TG terminal to 0V.

[0046] Using the structure of the non-volatile memory described above, designing the switch transistor of the memory as a switch transistor that can withstand high voltages, and controlling the memory in combination with the corresponding control method, the internal circuit structure of the chip can be arbitrarily reconstructed, and there is no need to consider problems such as withstand voltage, current, and voltage direction.

[0047] However, after the non-volatile memory connects the pins of the circuit module to the external test pins, it is necessary to consider the method of determining the connection relationship between the circuit module and the external test pins in the test state, that is, when testing each circuit module, the method of determining the non-volatile memory that needs to be turned on.

[0048] FIG. 4 shows a schematic configuration diagram of a circuit module of a semiconductor chip according to an embodiment of the present application.

[0049] Optionally, the inside of the semiconductor chip is composed of a plurality of circuit modules. As shown in FIG. 4, the plurality of circuit modules are, for example, a 5V reference voltage source module (5V REFERENCE), an error amplifier module, a first current comparator module, a second current comparator module, an oscillator module (OSCILLATOR), a PWM latch module (PWM Latch), an RS latch module, a PWM comparator module (PWM Comparator), a low voltage lockout module (UV LOCKOUT), a blanking module (BLANKING), and a gate circuit output module, etc. The plurality of circuit modules are interconnected to form the internal circuit structure of the semiconductor chip.

[0050] The method for obtaining the address specification information will be described below by taking some of the circuit modules inside the above chip as an example. (1) When the low-voltage lockout module (UV LOCKOUT) is below the threshold voltage, the module generates a signal to turn off the reference voltage module and the output module. That is, the module has two inputs and two outputs, and the two inputs are respectively connected to the output of the 5V reference voltage source module and the input voltage VIN pin. (2) The error amplifier module has two inputs and one output, and the two inputs are the VFB pin and the 2.5V power supply respectively. (3) The frequency of the oscillator module (OSCILLATOR) is set by selecting different RT and CT. That is, the module has two inputs and one output, and the two inputs are the output of the 5V reference voltage source module and the RT / CT pin respectively. (4) The PWM latch module (PWM Latch) has four inputs and two outputs, and the four inputs are the output of the 5V reference voltage source module, the output of the oscillator module, the periodic signal, and the output of the RS latch module respectively.

[0051] The semiconductor chip itself shown in Figure 4 has eight external pins. First, when testing the chip, most modules need to be powered by VIN or by the reference voltage generated by VIN. Therefore, the VIN pin and the GND pin cannot be multiplexed as test pins.

[0052] Next, when testing the chip, it is necessary to communicate with the upper computer. Therefore, this solution uses the OUTPUT pin individually as a communication pin, and the pin is connected to the test address specification module and the adjustment address specification module inside the semiconductor chip. At the same time, within 30 ms after the chip is powered on, when a high level exceeding 15V is connected to the OUTPUT pin of the chip, the chip enters the test / adjustment mode, and the OUTPUT pin is used as a communication pin. If the chip does not recognize the high level exceeding 15V, the chip enters the normal operation mode.

[0053] Therefore, in the embodiments of the present application, five pins of RT / CT, COMP, VFB, ISENCE, and VREF are used as test multiplexing pins. When the number of test multiplexing pins is designed to be five, the test needs of all circuit modules can basically be satisfied. This is basically because the total number of other input / output pins of all circuit modules except the input power supply pins is five or less.

[0054] Referring to FIG. 5, a test netlist diagram of a circuit module according to an embodiment of the present application is shown.

[0055] In FIG. 5, the vertical axis represents each circuit module that needs to be tested, and the horizontal axis represents the external pins or internal voltages to which the pins of each circuit module need to be connected. Although only four modules are shown on the vertical axis, actually there are more than four modules. The horizontal axis further shows the VIN pin, 5V, 2.5V, and 1V voltages in addition to the five multiplexing pins. And actually, there may be more than three types of voltages of 5V, 2.5V, and 1V.

[0056] Referring to FIG. 6, a test management diagram of a circuit module according to an embodiment of the present application is shown. (1) The 5V voltage, 2.5V voltage, and 1V voltage are respectively connected to the COMP pin in sequence. (2) Two inputs of the low voltage lockout module (UV LOCKOUT) are respectively connected to the 5V voltage and the VIN pin, and two outputs are respectively connected to the VREF pin and the ISENCE pin. (3) Two inputs of the error amplifier module are respectively the VFB pin and the 2.5V voltage, and the output is connected to the COMP pin. (4) Two inputs of the oscillator module (OSCILLATOR) are respectively connected to the 5V voltage and the RT / CT pin, and the output is connected to the COMP pin. (5) Four inputs of the PWM latch module are respectively the 5V voltage, the RT / CT pin, the COMP pin, and the VFB pin, and two outputs are respectively connected to the ISENCE pin and the VREF pin.

[0057] What needs to be explained is as follows. (1) Voltages such as 5V, 2.5V, and 1V in FIG. 6 are voltage values naturally generated by each voltage generation circuit module inside the chip after VIN is input to the chip, and each voltage is connected integrally in a one-to-one correspondence with each module, that is, these voltages do not need to be additionally input by external pins. (2) One non-volatile memory is installed on both sides of the connection line between each input pin and output pin of each circuit module. Therefore, at this time, between each input pin or output pin of each circuit module and the external pin naturally connected thereto, and between each circuit module, all are connected by non-volatile memory. At the same time, based on the test management diagram of the above circuit module, when a specific input pin or output pin of the circuit module is naturally connected to the pin in the management diagram, during the test, it is only necessary to turn on the non-volatile memory between the input pin or output pin and the pin naturally connected thereto. When a specific input pin or output pin of the circuit module is not naturally connected to the pin in the management diagram, the input pin or output pin is connected to the corresponding pin inside the chip through the non-volatile memory. And when testing a specific circuit module, if the module needs to use voltages such as 5V, 2.5V, and 1V as inputs, it is also necessary to turn on the memory between VIN and the input pin of the corresponding voltage generation circuit module. For example, in the low voltage lockout module, VIN is naturally connected to the input pin of the 5V voltage generation circuit module inside the chip through non-volatile memory, input 1 is directly and naturally connected to the 5V voltage inside the chip through non-volatile memory, input 2 is naturally input from the VIN pin through non-volatile memory, output 1 is naturally output from the VREF pin through non-volatile memory, output 2 is connected to the ISENCE pin through non-volatile memory, and after turning off other non-volatile memories inside the chip, the measuring device is connected to the VREF pin and ISENCE pin, thereby obtaining the output value during the test, and other modules are analogized in sequence. (3) When it is necessary to test voltage generation circuit modules such as 5V, 2.5V, and 1V, connect the input terminals of the voltage generation circuit modules such as 5V voltage, 2.5V voltage, and 1V to the VIN pin via a non-volatile memory respectively, connect the output terminals to the COMP pin via a non-volatile memory respectively, and turn off other non-volatile memories inside the chip. At this time, connect a measuring device to the COMP pin outside the chip to test each voltage generation circuit module accordingly. (4) The test management diagram of the circuit module is preset based on the operating principle of the circuit module inside the chip. At the same time, each non-volatile memory and its address information are also installed and set in advance, and different chips correspond to different test management diagrams of the circuit module. When testing the semiconductor chip, the tester connects the corresponding external pins (five test multiplexing pins, VIN pin, and GND pin) to an external input power supply or a measuring device according to the preset test management diagram of the circuit module in FIG. 6. (5) According to the above analysis, when inputting the low voltage lockout module to the host computer, the system automatically searches for the address information of the memory connected to the input pin of the VIN and 5V voltage generation circuit module, the address information of the memory connected to the output pin of the input 1 and 5V voltage generation circuit module, the address information of the memory connected to the input 2 and VIN pin, the address information of the memory connected to the output 1 and VREF pin, and the address information of the memory connected to the output 2 and ISENCE pin, and blocks the address information of other memories. The above address information becomes the address designation information of the low voltage lockout module, and the address designation information of other modules can be obtained by the above analysis. (6) Figure 6 only shows the connection between voltages such as 5V, 2.5V, and 1V described in Figure 1 and the circuit modules, and the connection between some circuit modules and the voltage generation module is not described in Figure 1. Therefore, Figure 6 does not show the connection between these circuit modules and the voltage generation module either. During the test process, these circuit modules and the voltage generation module need to be naturally and integrally connected through the non-volatile memory. At this time, since there is no special control for the non-volatile memory, it does not affect the understanding of the test management diagram of the circuit module.

[0058] As is clear from the above Figures 4 to 6 and their corresponding contents, during the design of the semiconductor chip shown in the embodiments of the present application, the external test pins used when testing the internal circuit modules of the semiconductor chip can be determined. Moreover, the pins of each circuit module in the semiconductor chip and the non-volatile memory that needs to be turned on when testing each circuit module can be further determined in advance, and the corresponding address information of the non-volatile memory can be stored in the test address designation module.

[0059] At this time, when the test address designation module receives the target circuit module information that needs to be tested sent by the host computer, based on the target circuit module information, it can determine the pins corresponding to the target circuit module and the target non-volatile memory that needs to be turned on, and send a command to the target non-volatile memory to turn on the target non-volatile memory.

[0060] That is, even after the above semiconductor chip is packaged, the test address designation module can realize the reconstruction of the internal structure of the semiconductor chip, whereby one or more internal circuit modules of the semiconductor can be directly tested from the external test pins of the semiconductor.

[0061] FIG. 7 is a flowchart of a semiconductor test method shown in one exemplary embodiment. The method is executed by a semiconductor chip, which may be the semiconductor chip of the embodiment shown in FIG. 1. As shown in FIG. 7, the semiconductor test method may include steps 701 to 703.

[0062] In step 701, when receiving target address specification information corresponding to a target circuit module in the semiconductor chip, based on the target address specification information, a target pin corresponding to the target circuit module inside the semiconductor chip is determined.

[0063] The target pin is connected to an external test pin of the semiconductor chip via a target non-volatile memory.

[0064] In one possible implementation, when it is necessary to test a target circuit module in the semiconductor chip, the host computer can input information corresponding to the target circuit module that needs to be tested into the semiconductor chip. At this time, the test address specification module in the semiconductor chip can determine the target pin corresponding to the input target circuit module based on the input information corresponding to the target circuit module.

[0065] In step 702, the target pin and the external test pin of the semiconductor chip are turned on via the target non-volatile memory.

[0066] When the target pin corresponding to the target circuit module is determined, the test address specification module can send an instruction signal to the corresponding target non-volatile memory of the target pin, switch the target non-volatile memory to the on state, and turn on the target pin and the external test pin of the semiconductor chip.

[0067] In step 703, in response to receiving a test signal transmitted by a test device connected to the external test pin, an output signal is generated and transmitted to the test device, and the test device generates a test result of the target circuit module based on the output signal.

[0068] After the target pin and the external test pin of the semiconductor are turned on, and since the target pin and the external test pin of the semiconductor are turned on via the target non-volatile memory, even in the case of a power outage, the target non-volatile memory remains in the on state. Therefore, the process of turning on in step 702 can actually correspond to the process of reconstructing the internal structure of the semiconductor chip circuit. In the semiconductor chip after reconstruction, the external test pin can be directly connected to the internal target circuit module, whereby a test device connected to the external test pin can directly test the target circuit module.

[0069] As described above, when it is necessary to test a circuit module inside a semiconductor chip, first, a target pin corresponding to the circuit module inside the semiconductor chip is determined. Next, the pins inside the semiconductor chip and the external test pins of the semiconductor chip are turned on via the target non-volatile memory, and the test device and the external test pin are turned on. By doing so, a test signal can be input into the target pin corresponding to the target circuit module, thereby realizing the testing of the target circuit module. Therefore, the above solution proposes a method for testing an internal module of a semiconductor from the outside of the semiconductor chip without exposing the wafer, testing the circuit module inside the semiconductor chip, and preventing damage to the wafer.

[0070] FIG. 8 is a flowchart of a semiconductor test method shown in one exemplary embodiment. The method is executed by a semiconductor chip, and the semiconductor chip may be the semiconductor chip of the embodiment shown in FIG. 1. As shown in FIG. 8, the semiconductor test method may include steps 801 to 805.

[0071] In step 801, when the host computer receives a test instruction corresponding to a target circuit module in the semiconductor chip, it generates target address specification information and transmits the target address specification information to the semiconductor chip.

[0072] In one possible implementation, when it is necessary to test a target circuit module in the semiconductor chip, the tester can input a test instruction corresponding to the target circuit module to the host computer. At this time, when the host computer determines the target circuit module that needs to be tested based on the test instruction, it generates corresponding target address specification information.

[0073] Moreover, in the design process, since each target circuit module inside the semiconductor chip and the corresponding circuit information have already been determined, the target address specification information corresponding to each target circuit module may also be determined in advance. The specific determination process of the target address specification information can refer to FIGS. 4 to 6, and detailed description is omitted here.

[0074] In the embodiment of the present application, when the first input module of the host computer receives a test instruction corresponding to a target circuit module, it determines the target circuit module that needs to be tested, generates corresponding target address specification information, and can transmit it to the OUTPUT pin (communication interface) of the semiconductor chip through the transmission module of the host computer.

[0075] Moreover, in the semiconductor chip shown in the corresponding embodiment of FIG. 1, since the OUTPUT pin is connected to the test address specification module, the target address specification information can be transmitted to the test address specification module inside the semiconductor chip through the OUTPUT pin.

[0076] In step 802, when the semiconductor chip receives target address specifying information corresponding to the target circuit module, based on the target address specifying information, the target pins corresponding to the target circuit module inside the semiconductor chip are determined.

[0077] In one possible embodiment, when the semiconductor enters the test module and the test address specifying module in the semiconductor chip receives the target address specifying information, the test address specifying module can determine the target pins of the target circuit in the semiconductor chip based on the target address specifying information.

[0078] The test address specifying module can be used to determine the address corresponding to the target address specifying information in the semiconductor chip based on the target address specifying information transmitted by the host computer. For example, after the transmission module generates an address specifying signal identifiable by the corresponding test address specifying module based on the address specifying information and the related transmission protocol and transmits it to the test address specifying module inside the semiconductor chip, the test address specifying module includes a row and column decoding module, decodes the target address specifying information based on the transmission protocol, determines the row address and column address corresponding to the target address specifying information, and determines the target pins inside the semiconductor chip.

[0079] In step 803, the test address specifying module in the semiconductor chip transmits a control signal to the target non-volatile memory to set the target non-volatile memory to the on state, and turn on the target pins and the external test pins of the semiconductor chip.

[0080] In a semiconductor chip, the pins of each circuit module and the external pins are connected via a non-volatile memory. That is, the structure among the pins of each circuit module, the external test pins, and the non-volatile memory used for the connection is determined during circuit design. Therefore, after determining the target pins corresponding to the target circuit module, the target non-volatile memory for connecting the target pins and the external test pins can actually be determined.

[0081] Therefore, the test address specifying module in the semiconductor chip can send a control signal to the target non-volatile memory to set the target non-volatile memory to the on state and turn on the target pins and the external test pins of the semiconductor chip. At this time, the external test pins of the semiconductor chip and the pins of the target test module inside the semiconductor chip are turned on, so that the target test module inside the semiconductor can be directly tested by the external test pins.

[0082] In one possible embodiment, the test address specifying module in the semiconductor chip sends a control signal to other non-volatile memories in the semiconductor chip except the target non-volatile memory and sets the other non-volatile memories to the off state.

[0083] When the test address specifying module inside the semiconductor sends a control signal to the target non-volatile memory in the semiconductor chip, turns on the target non-volatile memory, and integrally connects the external test pins and the target pins, the semiconductor chip can further send a control signal to other non-volatile memories except the target non-volatile memory and set the other non-volatile memories to the off state.

[0084] Since the target non-volatile memory is used to connect the external test pins and the pins of the target circuit module, setting only the target non-volatile memory to the on state can reduce the influence of other circuit modules on the test of the target circuit module, thereby improving the test accuracy of the target circuit module.

[0085] In one possible implementation, the target non-volatile memory further includes a non-volatile memory that needs to be turned on when the target circuit module is operating normally.

[0086] In order to ensure that the test results obtained from the test of the circuit module can accurately indicate the actual performance of the circuit module, when testing the target circuit module, the non-volatile memory that needs to be turned on during the normal operation of the target circuit module can also be turned on as the target non-volatile memory, thereby ensuring that the target circuit module has the same operating state as during normal operation during the test and ensuring the accuracy of the test results.

[0087] Optionally, the non-volatile memory that needs to be turned on when the target circuit module is operating normally may be a non-volatile memory that needs to be turned on to realize the expected function of the target circuit module.

[0088] Exemplarily, when there are non-volatile memories 1 to 10 in the target circuit module, if it is necessary to test the expected function of the target circuit module, it is necessary to turn on non-volatile memories 1, 2, and 5 correspondingly, so that the target circuit module can logically realize the expected function, and the non-volatile memories that have nothing to do with the expected function of the target circuit module (for example, sending signals to other modules to control other modules) may not be turned on.

[0089] Optionally, the non-volatile memory that needs to be turned on to realize the expected function of the target circuit module may include a non-volatile memory for connecting the target circuit module and a predetermined voltage generation module.

[0090] For example, when testing a target circuit module, the target circuit module needs to receive at least one voltage signal among 5V, 2.5V, and 1V as input to ensure that it can realize the functions expected when the target circuit module is being tested.

[0091] Moreover, since the voltages of 5V, 2.5V, and 1V are generated by the semiconductor chip through the internal voltage generation module of the chip after the semiconductor chip accesses the power supply, in order to ensure the test accuracy of the circuit module, further, the target circuit module that requires the test and the corresponding voltage generation module need to be turned on via a non-volatile memory so that the target circuit module can access the required voltage signal. Therefore, these non-volatile memories (i.e., the non-volatile memories for connecting the target circuit module and the corresponding voltage generation module) need to function as target non-volatile memories and be set to the on state during the test of the target circuit.

[0092] Optionally, the address of the target non-volatile memory may be determined by target address specification information transmitted by the upper computer.

[0093] In step 804, in response to receiving a test signal transmitted by a test device connected to the external test pin, the semiconductor chip generates an output signal and transmits it to the test device, and the test device generates a test result of the target circuit module based on the output signal.

[0094] When a test address designation module in a semiconductor chip controls a non-volatile memory in the semiconductor chip, the internal circuit connections within the semiconductor chip actually change, thereby realizing the reconstruction of the internal circuit structure of the semiconductor chip. With the reconstructed circuit structure, it becomes possible for a test device to test a target circuit module inside the semiconductor chip via an external test pin, and the semiconductor chip generates a corresponding output signal based on the test signal transmitted by the test device. The test device can obtain the test result corresponding to the target circuit module based on the output signal generated by the reconstructed chip.

[0095] Moreover, in the process of reconstructing the semiconductor chip, it is necessary to connect the semiconductor chip to a host computer, and in the process of testing the semiconductor chip, it is necessary to connect the semiconductor chip to a test device. Since a non-volatile memory is used, after disconnecting the connection between the semiconductor chip and the host computer and powering off, the state of the memory does not change. That is, after power-off, the circuit structure inside the semiconductor chip is not changed and always remains in the reconstructed test structure set by the host computer.

[0096] In one possible embodiment, regarding the test process of the semiconductor, connect a high level to the OUTPUT pin, set the chip to the test / debug mode, and according to the test management diagram of the circuit module in FIG. 6, connect the corresponding external pins (five test multiplexing pins, VIN pin, and GND pin) to an external input power source or a measuring device. After inputting the voltage or current corresponding to the input pin, directly obtain the output signal of the circuit module being tested by a measuring device. The output signal of the circuit module may include data or waveforms, and based on the output signal, the test result of the target circuit module inside the semiconductor chip can be obtained quickly and conveniently.

[0097] In step 805, when the test address designation module in the semiconductor chip receives the address designation recovery information corresponding to the target circuit module, based on the address designation recovery information, the on state between the target pin and the external test pin of the semiconductor chip is restored to the default state.

[0098] If the target circuit module is tested in the above step and the test result is as expected, the semiconductor and the host computer can be connected. At this time, the host computer can send address specification recovery information to the semiconductor chip through the first input module of the host computer. At this time, when the test address specification module in the semiconductor chip receives the address specification recovery information, the on-state between the target pin and the external test pin of the semiconductor chip can be restored to the default state. That is, based on the address specification recovery information sent by the host computer, the test address specification module can restore the semiconductor chip from the circuit structure reconstructed for testing the target circuit module to the circuit structure before testing, avoiding the adverse effects caused by the testing of other circuits later or the change of the circuit module when applying the chip.

[0099] In one possible implementation, since the test address specification module also changes the on-state of the non-volatile memory in the semiconductor chip except for the target non-volatile memory based on the target address specification information, the test address specification module can control the on-state of each non-volatile memory in the semiconductor chip based on the address specification recovery information. For example, there may be address information of the non-volatile memory that needs to be turned on by default in the test address specification information. At this time, the test address specification module sets the non-volatile memory that needs to be turned on to the on-state based on the address information, sets other non-volatile memories that do not need to be turned on to the off-state, and resets the semiconductor chip to the state before the structure is reconstructed.

[0100] As described above, when it is necessary to test the circuit modules inside the semiconductor chip, first, determine the target pins corresponding to the circuit modules inside the semiconductor chip. Next, turn on the pins inside the semiconductor chip and the external test pins of the semiconductor chip via the target non-volatile memory, and turn on the test equipment and the external test pins. In this way, the test signal can be input into the target pins corresponding to the target circuit modules, thereby realizing the testing of the target circuit modules. Therefore, the above solution proposes a method for testing the internal modules of a semiconductor without exposing the wafer, testing the circuit modules inside the semiconductor chip, and preventing damage to the wafer.

[0101] By the solution shown in the embodiments of the present application, it is possible to individually test each circuit module inside the semiconductor chip outside the semiconductor chip. Therefore, it is possible to avoid the wafer being completely exposed outside during the test, improving the safety of the test. The solution shown in the embodiments of the present application further realizes the multiplexing of the external pins of the semiconductor chip during the test and normal use by using a non-volatile memory. After a power outage, the circuit structure inside the semiconductor chip remains unchanged and is always maintained in the test structure set by the host computer. Thereby, after the packaging of the chip is completed, it is also possible to realize the reconstruction of the internal circuit structure of the chip. Therefore, after the chip is detached from the host computer, any module can be tested.

[0102] Moreover, when the semiconductor chip reconstructs and tests its internal structure based on the target address specification information by the solution means shown in the embodiments of the present application, and the test result indicates that there is no error in the target circuit module, it means that the target circuit module in the semiconductor chip has been tested. At this time, in order to avoid the on-state between the target pin and the external test pin of the semiconductor chip from affecting the test results of other circuit modules subsequently, the on-state between the target pin and the external test pin of the semiconductor chip is restored to the default state, so as to ensure that each circuit module is not interfered by other circuit modules when testing each circuit module by the solution means shown in the embodiments of the present application, and improve the test accuracy of the circuit module.

[0103] FIG. 9 is a flowchart of a semiconductor test method shown in one exemplary embodiment. The method is executed by a semiconductor chip, which may be the semiconductor chip shown in the embodiment of FIG. 1. As shown in FIG. 7, the semiconductor test method may include steps 901 to 904.

[0104] In step 901, when receiving the target address specification information corresponding to the target circuit module in the semiconductor chip, based on the target address specification information, determine the target pin corresponding to the target circuit module inside the semiconductor chip.

[0105] This step 901 is the same as step 802 of the embodiment shown in FIG. 8 above, and detailed description is omitted here.

[0106] In step 902, the test address specification module in the semiconductor chip transmits a control signal to the target non-volatile memory to set the target non-volatile memory to the on-state, and turn on the target pin and the external test pin of the semiconductor chip.

[0107] This step 902 is the same as step 803 of the embodiment shown in FIG. 8 above, and detailed description is omitted here.

[0108] In step 903, in response to receiving a test signal transmitted by test equipment connected to the external test pins, an output signal is generated and transmitted to the test equipment, and the test equipment generates a test result of the target circuit module based on the output signal.

[0109] This step 903 is the same as step 804 of the embodiment shown in FIG. 8 above, and detailed description is omitted here.

[0110] In step 904, when an adjustment address specifying module in the semiconductor chip receives adjustment information corresponding to the target circuit module, based on the adjustment information, by adjusting an adjustment module corresponding to the target circuit module, the structure of the target circuit module is changed.

[0111] In one possible embodiment, if the test result does not meet the design requirements, the OUTPUT communication interface and the host computer are reconnected, and corresponding adjustment information is input to the second input module of the host computer for the circuit module that needs to be adjusted.

[0112] In one possible embodiment, if there are voltages such as 5V, 2.5V, and 1V in the circuit module that needs to be adjusted, first, the voltage generation module that generated the voltage value is tested, and it is necessary to determine whether the cause of the test not meeting the requirements is an input voltage error. When the test results of voltage generation circuit modules such as 5V, 2.5V, and 1V meet the design requirements, adjustment is performed by an adjustment resistor network or an adjustment capacitor network integrated in the circuit module.

[0113] In one possible embodiment, based on the adjustment information, a capacitor corresponding to the adjustment information is connected or disconnected, or, Based on the adjustment information, a resistor corresponding to the adjustment information is connected or disconnected.

[0114] To maintain and debug a semiconductor chip, a trimming resistor network or a trimming capacitor network is preset at a plurality of positions where maintenance and debugging of the semiconductor chip are required. By connecting or disconnecting each trimming resistor or trimming capacitor, adjustment of chip parameters can be achieved.

[0115] Referring to FIG. 10, a schematic diagram of a parallel connection network of trimming resistors according to an embodiment of the present application is shown.

[0116] The adjustment module in FIG. 10 may be the non-volatile memory shown in FIG. 5 or FIG. 6. That is, the on-state of each non-volatile memory can be controlled to control any one of the resistors R1, R2, and R3, and it can be determined whether it is connected to the parallel connection network of the trimming resistors.

[0117] Optionally, at least one of R1, R2, and R3 can also be replaced with a capacitor.

[0118] Referring to FIG. 11, a schematic diagram of a series connection network of an adjustment circuit according to an embodiment of the present application is shown.

[0119] The adjustment module in FIG. 11 may be the non-volatile memory shown in FIG. 2 or FIG. 3. That is, the on-state of each non-volatile memory can be controlled to control any one of the resistors R4, R5, and R6, and it can be determined whether it is connected to the series connection network of the trimming resistors.

[0120] Optionally, at least one of R4, R5, and R6 can also be replaced with a capacitor.

[0121] Referring to FIG. 12, a schematic diagram of an adjustment module according to an embodiment of the present application is shown. When adjusting the adjustment module of the series connection network of the adjustment circuit shown in FIG. 11, it can be adjusted by the adjustment module shown in FIG. 12. When the switch transistor M5 of the adjustment module in FIG. 12 is turned on, pins 1 and 2 of the adjustment resistor are turned on, that is, it means that the adjustment resistor is short-circuited. At this time, the adjustment resistor is not connected to the circuit network. When the adjustment module M5 is turned off, it means that pins 1 and 2 of the adjustment resistor are not short-circuited. At this time, the adjustment circuit is connected to the circuit network. The adjustment module M5 in FIG. 12 can use an N-type JFET in addition to the P-type LDMOS. The corresponding content in FIG. 12 is the same as that in FIGS. 2 and 3. Moreover, the adjustment module shown in FIG. 12 can be further applied to the parallel connection network of the adjustment resistor shown in FIG. 10, that is, by controlling the switch transistor M5 in the adjustment module, any one of the resistors R1, R2, and R3 is controlled to determine whether it is connected to the parallel connection network of the adjustment resistor.

[0122] In step 905, after the structure of the target circuit module is changed based on the adjustment information, in response to receiving a test signal transmitted by the test device, an output signal is transmitted to the test device, and the test device generates a test result of the target circuit module after being updated based on the output signal.

[0123] After the structure of the target circuit module is changed based on the adjustment information, the test device tests the adjusted target circuit module to determine whether the adjusted target circuit module meets the expectations. If the test result of the adjusted target circuit module does not meet the expectations, the upper computer continues to adjust the target circuit module in the semiconductor chip. If the test result of the adjusted target circuit module meets the expectations, it means that the adjusted target circuit module is a target circuit module that meets the design expectations.

[0124] Note that the above adjustment module is adjusted through the control instructions sent by the adjustment address specifying module, and during the adjustment process of the above adjustment module, the circuit is reconstructed through the non-volatile memory, and the test address specifying module does not affect the adjustment module. Therefore, after the circuit is reconstructed in the target circuit module part by the adjustment address specifying module controlling the adjustment module, the adjustment module of the target circuit module is always maintained in the adjusted state. Thereby, all subsequent semiconductor chip testing and application processes can be completed based on the adjusted target circuit module, and the accuracy of semiconductor chip testing and semiconductor chip application is improved.

[0125] As described above, when it is necessary to test the circuit module inside the semiconductor chip, first, determine the target pins corresponding to the circuit module inside the semiconductor chip. Next, turn on the pins inside the semiconductor chip and the external test pins of the semiconductor chip through the target non-volatile memory, and turn on the test equipment and the external test pins. In this way, the test signal can be input into the target pins corresponding to the target circuit module, thereby realizing the testing of the target circuit module. Therefore, the above solution proposes a method for testing the internal module of the semiconductor from the outside of the semiconductor chip without exposing the wafer, testing the circuit module inside the semiconductor chip, and preventing damage to the wafer.

[0126] And if there is a problem with the test result, at this time, it means that there is an error in the circuit part of the target circuit module. In the embodiments of the present application, in order to repair and debug the chip, a plurality of positions that need to be repaired and debugged of the chip are preset with an adjustment resistor network or an adjustment capacitor network. By connecting or disconnecting each adjustment resistor or adjustment capacitor, the adjustment of the chip parameters is realized. After disconnecting the communication connection between the semiconductor chip and the upper computer, test the finely adjusted circuit module inside the semiconductor chip.

[0127] Since a non-volatile memory is used, after the connection between the semiconductor chip and the host computer is disconnected and a power failure occurs, the state of the memory does not change. That is, after the power failure, the circuit structure in the semiconductor chip is not changed and is always maintained in the adjusted test structure set by the host computer. At this time, the output signal of the circuit module being tested by the measuring device can be directly obtained. The output signal includes data or waveforms, and the test results of the circuit module in the semiconductor chip after being updated can be obtained quickly and conveniently. After the test is completed, if the test results meet the design requirements, the test of the target circuit module in the semiconductor chip is completed, and other circuit modules of the semiconductor chip can continue to be tested.

[0128] FIG. 13 is a structural block diagram of a semiconductor test device shown in one exemplary embodiment. The semiconductor test device is applied to a semiconductor chip, and the device includes: a pin determination unit 1301 that determines a target pin corresponding to a target circuit module based on target address specification information received for the target circuit module in the semiconductor chip. The target pin is connected to an external test pin of the semiconductor chip through a target non-volatile memory. a pin connection unit 1302 that connects the target pin and the external test pin of the semiconductor chip through the target non-volatile memory. a test data output unit 1303 that transmits an output signal to the test device in response to receiving a test signal transmitted by the test device connected to the external test pin, and the test device generates a test result of the target circuit module based on the output signal.

[0129] In one possible implementation, the pin connection unit is used to instruct the test address specification module in the semiconductor chip to send a control signal to the target non-volatile memory, set the target non-volatile memory to the on state, and connect the target pin and the external test pin of the semiconductor chip.

[0130] In one possible embodiment, the device further includes a memory off unit for instructing a test address designation module in the semiconductor chip to send a control signal to other non-volatile memories in the semiconductor chip excluding the target non-volatile memory and setting the other non-volatile memories to an off state.

[0131] In one possible embodiment, the device further includes a connection recovery unit for recovering a connection state between the target pin and an external test pin of the semiconductor chip to a default state based on address designation recovery information when the test address designation module in the semiconductor chip receives the address designation recovery information corresponding to the target circuit module.

[0132] In one possible embodiment, the device further includes a circuit adjustment unit for changing a structure of the target circuit module by adjusting an adjustment module corresponding to the target circuit module based on adjustment information when an adjustment address designation module in the semiconductor chip receives the adjustment information corresponding to the target circuit module.

[0133] In one possible embodiment, the circuit adjustment unit further is used to connect or disconnect a capacitor corresponding to the adjustment information based on the adjustment information, or is used to connect or disconnect a resistor corresponding to the adjustment information based on the adjustment information.

[0134] In one possible embodiment, the test data output unit further After the structure of the target circuit module is changed based on the adjustment information, in response to receiving a test signal transmitted by the test equipment, an output signal is transmitted to the test equipment, and the test equipment uses the output signal to generate a test result of the target circuit module after the update.

[0135] As described above, when it is necessary to test a circuit module inside a semiconductor chip, first, a target pin corresponding to the circuit module inside the semiconductor chip is determined. Next, by turning on the pins inside the semiconductor chip and the external test pins of the semiconductor chip via the target non-volatile memory, and turning on the test equipment and the external test pins, a test signal can be input into the target pin corresponding to the target circuit module, thereby realizing the testing of the target circuit module. Therefore, the above solution proposes a method for testing an internal module of a semiconductor from outside the semiconductor chip without exposing the wafer, testing the circuit module inside the semiconductor chip, and preventing damage to the wafer.

[0136] FIG. 14 shows a structural block diagram of a computer device 1400 shown in one exemplary embodiment of the present application. The computer device is realized as the upper computer or test equipment in the above solution of the present application. The computer device 1400 includes a central processing unit (CPU) 1401, a system memory 1404 including a random access memory (RAM) 1402 and a read-only memory (ROM) 1403, and a system bus 1405 connecting the system memory 1404 and the central processing unit 1401. The computer device 1400 further includes a mass storage device 1406 for storing an operating system 1409, an application program 1410, and other program modules 1411.

[0137] The large-capacity storage device 1406 is connected to the central processing unit 1401 via a large-capacity storage controller (not shown) connected to the system bus 1405. The large-capacity storage device 1406 and its associated computer-readable medium provide non-volatile storage for the computer device 1400. That is, the large-capacity storage device 1406 may include a computer-readable medium (not shown) such as a hard disk or a read-only optical disc (Compact Disc Read-Only Memory, CD-ROM) driver, etc.

[0138] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes RAM, ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other solid-state memory technologies, CD-ROM, digital versatile disc (DVD) or other optical storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices or other magnetic storage devices. Of course, those skilled in the art will understand that the computer storage media is not limited to some of the above. The above system memory 1404 and large-capacity storage device 1406 can be collectively referred to as memory.

[0139] According to various embodiments of the present disclosure, the computer device 1400 may be further connected to and executed on a remote computer on a network via a network such as the Internet. That is, the computer device 1400 can be connected to the network 1408 via the network interface unit 1407 connected to the system bus 1405, or may be connected to other types of networks or remote computer systems (not shown) using the network interface unit 1407.

[0140] The memory further includes at least one computer program, the at least one computer program is stored in the memory, and the central processor 1401 realizes all or part of the steps of the methods shown in the above embodiments by executing the at least one computer program.

[0141] In one exemplary embodiment, there is further provided a computer-readable storage medium storing at least one computer program that is uploaded to and executed by a processor to realize all or part of the steps of the above method. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0142] In one exemplary embodiment, there is further provided a computer-readable storage medium storing at least one instruction that is uploaded to and executed by a semiconductor chip to realize the above semiconductor test method.

[0143] In one exemplary embodiment, there is further provided a computer program product or a computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform all or part of the steps of the method shown in any of the above embodiments.

[0144] Those skilled in the art can easily conceive of other embodiments of this application after referring to the specification and practicing the invention disclosed herein. This application is intended to cover any modifications, uses, or adaptations of this application that follow the general principles of this application and include known general knowledge or conventional technical means in the technical field not disclosed in this application. The specification and examples are regarded as illustrative, and the true scope and spirit of this application are pointed out from the following claims.

[0145] This application is not limited to the structure described above and precisely shown in the drawings, and various modifications and changes can be made without departing from its scope. It should be understood that the scope of this application is limited only by the appended claims.

Claims

1. A semiconductor testing method, which is executed by a semiconductor chip, connecting the semiconductor chip and a host computer, when receiving target address specification information corresponding to a target circuit module in the semiconductor chip from the host computer, a test address specification module in the semiconductor chip determines a target pin corresponding to the target circuit module in the semiconductor chip based on the target address specification information, wherein the target pin is connected to an external test pin of the semiconductor chip via a target non-volatile memory, the test address specification module in the semiconductor chip transmits a control signal to the target non-volatile memory to set the target non-volatile memory to an on state and set the target pin and the external test pin of the semiconductor chip to an on state, disconnecting the connection between the semiconductor chip and the host computer and connecting the semiconductor chip and a test device, in response to the target circuit module receiving a test signal transmitted by the test device connected to the external test pin, generating an output signal and transmitting the output signal to the test device, and the test device generating a test result of the target circuit module based on the output signal, characterized by including the above steps, a semiconductor testing method.

2. The target non-volatile memory further includes a non-volatile memory that needs to be turned on when the target circuit module is operating normally, and the non-volatile memory that needs to be turned on when the target circuit module is operating normally includes a non-volatile memory for connecting the target circuit module and a predetermined voltage generation module, the method according to claim 1.

3. The test address specifying module in the semiconductor chip further includes a step of transmitting a control signal to other non-volatile memories in the semiconductor chip excluding the target non-volatile memory and setting the other non-volatile memories to an off state. The method according to claim 2 is characterized by this.

4. When the test address specifying module in the semiconductor chip receives address specifying recovery information corresponding to the target circuit module, the method further includes a step of restoring the connection state between the target pin and the external test pin of the semiconductor chip to a default state based on the address specifying recovery information. The method according to any one of claims 1 to 3 is characterized by this.

5. When the adjustment address specifying module in the semiconductor chip receives adjustment information corresponding to the target circuit module, the method further includes a step of changing the structure of the target circuit module by adjusting the adjustment module corresponding to the target circuit module based on the adjustment information. The method according to any one of claims 1 to 3 is characterized by this.

6. The step of adjusting the adjustment module corresponding to the target circuit module based on the adjustment information is a step of connecting or disconnecting a capacitor corresponding to the adjustment information based on the adjustment information, or The method according to claim 5 is characterized by including a step of connecting or disconnecting a resistor corresponding to the adjustment information based on the adjustment information.

7. After the structure of the target circuit module is changed based on the adjustment information, in response to receiving a test signal transmitted by the test equipment, the method further includes a step of transmitting an output signal to the test equipment, and the test equipment generates a test result of the target circuit module after being updated based on the output signal. The method according to claim 6 is characterized by this.

8. A semiconductor test device, which is applied to a semiconductor chip After connecting the semiconductor chip and the host computer, when receiving target address specification information corresponding to a target circuit module in the semiconductor chip from the host computer, a pin determination unit for determining a target pin corresponding to the target circuit module based on the target address specification information, wherein the target pin is connected to an external test pin of the semiconductor chip via a target non-volatile memory, and the pin determination unit; A pin connection unit that transmits a control signal to a target non-volatile memory to set the target non-volatile memory to an on state and turn on the target pin and the external test pin of the semiconductor chip; After disconnecting the connection between the semiconductor chip and the host computer and connecting the semiconductor chip and a test device, in response to receiving a test signal transmitted by the test device connected to the external test pin, an output signal is transmitted to the test device, and a test data output unit for generating a test result of the target circuit module based on the output signal by the test device. A semiconductor test device, characterized by including:

9. A chip test device according to claim 8, wherein the target non-volatile memory further includes a non-volatile memory that needs to be turned on when the target circuit module is operating normally, and the non-volatile memory that needs to be turned on when the target circuit module is operating normally includes a non-volatile memory for connecting the target circuit module and a predetermined voltage generation module. A chip test device, characterized by:

10. A semiconductor chip, The semiconductor chip includes a test address specification module, a target circuit module, and a target non-volatile memory, After connecting the semiconductor chip and the host computer, when the test address designating module receives target address designating information corresponding to the target circuit module in the semiconductor chip from the host computer, it is used to determine a target pin corresponding to the target circuit module based on the target address designating information. The target non-volatile memory is used to connect the target pin and an external test pin of the semiconductor chip. The test address designating module is further used to transmit a control signal to the target non-volatile memory to set the target non-volatile memory to an on state and to turn on the target pin and the external test pin of the semiconductor chip. After disconnecting the connection between the semiconductor chip and the host computer and connecting the semiconductor chip and a test device, in response to receiving a test signal transmitted by the test device connected to the external test pin, the target circuit module generates an output signal and transmits it to the test device, and the test device is used to generate a test result of the target circuit module based on the output signal. A semiconductor chip characterized by the above.

11. The target non-volatile memory further includes a non-volatile memory that needs to be turned on when the target circuit module is operating normally. The non-volatile memory that needs to be turned on when the target circuit module is operating normally includes a non-volatile memory for connecting the target circuit module and a predetermined voltage generation module. The semiconductor chip according to claim 10, characterized by the above.

12. A computer-readable storage medium, on which at least one instruction or information for realizing the method according to any one of claims 1 to 3 is stored and is uploaded and executed on a semiconductor chip.

13. A computer program product, which includes computer instructions for realizing the method according to any one of claims 1 to 3 when executed on an electronic device.

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