Nitrogen-rich silicon nitride film for thin film transistors

Abstract

To provide nitrogen-rich silicon nitride, methods for depositing the nitrogen-rich silicon nitride, and transistors and other devices containing the nitrogen-rich silicon nitride.SOLUTION: In a thin-film transistor (TFT) 800, a passivation film stack 156 comprises a silicon oxide layer 160 disposed on a workpiece, and a nitrogen-rich silicon nitride layer 170 disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percent (at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%. In one or more examples, the passivation film stack comprises the silicon oxide layer, the nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride, such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to deposition processes, and more particularly to vapor deposition processes for depositing silicon nitride and other materials onto a workpiece.

Background Art

[0002] Liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), and micro-LED panels are often used in flat panel displays. Typically, an LCD generally includes two glass substrates joined with a layer of liquid crystal material sandwiched therebetween. The glass substrate may be a semiconductor substrate or a transparent substrate such as glass, quartz, sapphire, or a transparent plastic film. An LCD may also contain light-emitting diodes for a backlight.

[0003] As the resolution requirements of LCDs increase, it has become desirable to control a large number of individual regions of liquid crystal cells called pixels. Modern display panels can have about 8 million pixels (4K resolution), about 33 million pixels (8K resolution), or more pixels. At least the same number of transistors are formed on the glass substrate, thereby enabling each pixel to be switched between an energized state and a non-energized state with respect to other pixels arranged on the substrate.

[0004] Silicon-containing materials are the basic elements of most TFTs. Silicon-containing materials have been used to form channel materials such as polysilicon for low-temperature polysilicon (LTPS) TFTs, and have also been used as components utilized in forming the gate dielectric layer, interface layer, passivation layer, and / or etch stop layer of a TFT.

[0005] In a metal oxide channel-based TFT, a silicon-containing passivation layer cannot protect the device against humidity and gas diffusion, especially in the case of an In-Ga-Zn oxide (IGZO) channel semiconductor. When moisture (H2O) and / or gas (e.g., H2, O2, and / or N2) diffuses into the IGZO channel semiconductor as well as other layers, the entire device becomes unstable. Typically, moisture and gas can diffuse through or from a passivation layer containing hydrogen-rich silicon oxide and / or hydrogen-rich silicon nitride, which is generated by various underlying layers.

[0006] Therefore, there is a need for a passivation material to reduce or eliminate the diffusion of moisture and / or gas in a TFT or other types of devices. SUMMARY OF THE INVENTION

[0007] Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride, a method of depositing nitrogen-rich silicon nitride, and transistors and other devices containing nitrogen-rich silicon nitride. In one or more embodiments, a passivation film stack contains a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percent (at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%. In one or more examples, the passivation film stack contains a silicon oxide layer, a nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.

[0008] In other embodiments, the passivation film stack includes a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, and the nitrogen-rich silicon nitride layer has a water resistance of about 1×10 -8 g / m 2 / day to about 1×10-4 g / m 2 per day, the silicon-hydrogen bond concentration is from about 0.1% to about 10%, and the nitrogen-rich silicon nitride layer has a nitrogen-to-silicon ratio greater than 1.03 to about 2. In some examples, the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration from about 0.5% to about 6% and a total hydrogen bond concentration (including the nitrogen-hydrogen bond concentration) of less than 30%.

[0009] In some embodiments, a method of depositing a silicon nitride material includes heating a workpiece to a temperature of about 200 °C to about 250 °C, exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition (PE-CVD) process, and depositing a nitrogen-rich silicon nitride layer on the workpiece. The deposition gas contains a silicon precursor, a nitrogen precursor, and a carrier gas, and the deposition gas has a molar ratio of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas in the ranges of about 1: about 4 to about 8: about 20 to about 80, respectively. In some examples, the deposition gas has a molar ratio of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas in the ranges of about 1: about 5 to about 7: about 30 to about 50, respectively. In one or more examples, the silicon precursor is or contains silane, the nitrogen precursor is or contains ammonia, and the carrier gas is or contains nitrogen (N2).

[0010] To enable a more detailed understanding of the above-listed features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, can be obtained by referring to the embodiments shown in part in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered as limiting the scope of the present invention, and other equally effective embodiments may be recognized. BRIEF DESCRIPTION OF THE DRAWINGS

[0011]

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DETAILED DESCRIPTION OF THE INVENTION

[0012] For ease of understanding, the same reference numerals are used, where possible, to indicate the same elements common to each drawing. It is contemplated that the elements and features of one or more embodiments may be advantageously incorporated into other embodiments.

[0013] Embodiments of the present disclosure generally relate to a passivation film stack containing nitrogen-rich silicon nitride, a method of depositing the passivation film stack, and transistors and other devices containing the passivation film stack. In one or more embodiments, the passivation film stack includes a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. In some examples, the passivation film stack is disposed on a workpiece and contains a silicon oxide layer, a nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride such as nitrogen-rich silicon nitride and / or hydrogen-rich silicon nitride.

[0014] The nitrogen-rich silicon nitride layer contains more nitrogen and / or less hydrogen than conventional silicon nitride. Conventional silicon nitride is typically nitrogen-poor silicon nitride and / or hydrogen-rich silicon nitride. Thus, the hydrogen-rich silicon nitride layer has a higher hydrogen concentration than the nitrogen-rich silicon nitride layer described and discussed herein. Also, the nitrogen-rich silicon nitride layer has a higher water resistance than nitrogen-poor silicon nitride and / or hydrogen-rich silicon nitride.

[0015] In one or more embodiments, the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percent (at%), about 22 at%, about 24 at%, about 25 at%, about 26 at%, about 27 at%, about 28 at%, about 29 at%, about 30 at%, or about 31 at% to about 32 at%, about 33 at%, about 34 at%, about 35 at%, about 36 at%, about 37 at%, or about 38 at% or more. For example, the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at% to about 38 at%, about 22 at% to about 38 at%, about 25 at% to about 38 at%, about 27 at% to about 38 at%, about 28 at% to about 38 at%, about 30 at% to about 38 at%, about 31 at% to about 38 at%, about 32 at% to about 38 at%, about 33 at% to about 38 at%, about 35 at% to about 38 at%, about 36 at% to about 38 at%, about 20 at% to about 35 at%, about 22 at% to about 35 at%, about 25 at% to about 35 at%, about 27 at% to about 35 at%, about 28 at% to about 35 at%, about 30 at% to about 35 at%, about 31 at% to about 35 at%, about 32 at% to about 35 at%, about 33 at% to about 35 at%, about 20 at% to about 34 at%, about 22 at% to about 34 at%, about 25 at% to about 34 at%, about 27 at% to about 34 at%, about 28 at% to about 34 at%, about 30 at% to about 34 at%, about 31 at% to about 34 at%, about 32 at% to about 34 at%, about 33 at% to about 34 at%, about 20 at% to about 33 at%, about 22 at% to about 33 at%, about 25 at% to about 33 at%, about 27 at% to about 33 at%, about 28 at% to about 33 at%, about 30 at% to about 33 at%, about 31 at% to about 33 at%, or about 32 at% to about 33 at%.

[0016] In some embodiments, the nitrogen-rich silicon nitride layer has a nitrogen concentration of about 40 at%, about 42 at%, about 43 at%, about 44 at%, about 45 at%, about 46 at%, about 48 at%, about 50 at%, or about 52 at% to about 54 at%, about 55 at%, about 58 at%, about 60 at%, about 65 at%, about 70 at%, about 72 at%, or about 75 at% or more. For example, the nitrogen-rich silicon nitride layer has a nitrogen concentration of about 40 at% to about 75 at%, about 42 at% to about 75 at%, about 43 at% to about 75 at%, about 44 at% to about 75 at%, about 45 at% to about 75 at%, about 48 at% to about 75 at%, about 50 at% to about 75 at%, about 55 at% to about 75 at%, about 60 at% to about 75 at%, about 65 at% to about 75 at%, about 70 at% to about 75 at%, about 40 at% to about 65 at%, about 42 at% to about 65 at%, about 43 at% to about 65 at%, about 44 at% to about 65 at%, about 45 at% to about 65 at%, about 48 at% to about 65 at%, about 50 at% to about 65 at%, about 55 at% to about 65 at%, about 60 at% to about 65 at%, about 62 at% to about 65 at%, about 40 at% to about 58 at%, about 42 at% to about 58 at%, about 43 at% to about 58 at%, about 44 at% to 58 at%, about 45 at% to 58 at%, about 48 at% to about 58 at%, about 50 at% to about 58 at%, about 55 at% to about 58 at%, about 40 at% to about 55 at%, about 42 at% to about 55 at%, about 43 at% to about 55 at%, about 44 at% to about 55 at%, about 45 at% to about 55 at%, about 48 at% to about 55 at%, about 50 at% to about 55 at%, or about 52 at% to about 55 at%.

[0017] In one or more embodiments, the nitrogen-rich silicon nitride layer has a hydrogen concentration of about 10 at%, about 12 at%, about 15 at%, about 18 at%, or about 20 at% to about 21 at%, about 22 at%, about 23 at%, about 25 at%, about 27 at%, about 30 at%, about 32 at%, or about 35 at% or more. For example, the nitrogen-rich silicon nitride layer has a hydrogen concentration of about 10 at% to about 35 at%, about 12 at% to about 35 at%, about 15 at% to about 35 at%, about 18 at% to about 35 at%, about 19 at% to about 35 at%, about 20 at% to about 35 at%, about 21 at% to about 35 at%, about 22 at% to about 35 at%, about 23 at% to about 35 at%, about 24 at% to about 35 at%, about 25 at% to about 35 at%, about 28 at% to about 35 at%, about 30 at% to about 35 at%, about 10 at% to about 25 at%, about 12 at% to about 25 at%, about 15 at% to about 25 at%, about 18 at% to about 25 at%, about 19 at% to about 25 at%, about 20 at% to 25 at%, about 21 at% to 25 at%, about 22 at% to 25 at%, about 23 at% to 25 at%, about 24 at% to 25 at%, about 10 at% to about 23 at%, about 12 at% to about 23 at%, about 15 at% to about 23 at%, about 18 at% to about 23 at%, about 19 at% to about 23 at%, about 20 at% to about 23 at%, about 21 at% to about 23 at%, or about 22 at% to about 23 at%.

[0018] In one or more examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at% to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%. In other examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 27 at% to about 34 at%, a nitrogen concentration of about 42 at% to about 65 at%, and a hydrogen concentration of about 18 at% to about 25 at%. In some examples, the nitrogen-rich silicon nitride layer has a silicon concentration of about 28 at% to about 33 at%, a nitrogen concentration of about 43 at% to about 58 at%, and a hydrogen concentration of about 19 at% to about 23 at%.

[0019] In one or more embodiments, the nitrogen-rich silicon nitride layer has a ratio of nitrogen to silicon that is greater than 1, greater than 1.02, greater than 1.03, or greater than 1.05, such as about 1.06, about 1.08, about 1.10, about 1.12, about 1.15, about 1.18, about 1.20, about 1.22, or about 1.25 to about 1.28, about 1.30, about 1.35, about 1.38, about 1.40, about 1.45, about 1.50, about 1.55, about 1.60, about 1.80, about 1.90, or about 2 or more. For example, the nitrogen-rich silicon nitride layer has a ratio of nitrogen to silicon that is greater than 1.03 to about 2, greater than 1.03 to about 1.9, greater than 1.03 to about 1.8, greater than 1.03 to about 1.7, greater than 1.03 to about 1.6, greater than 1.03 to about 1.5, greater than 1.03 to about 1.45, greater than 1.03 to about 1.4, greater than 1.03 to about 1.39, greater than 1.03 to about 1.38, 1.03 to about 1.36, greater than 1.03 to about 1.35, greater than 1.03 to about 1.3, greater than 1.03 to about 1.25, greater than 1.03 to about 1.2, greater than 1.03 to about 1.15, greater than 1.03 to about 1.1, about 1.05 to about 2, about 1.05 to about 1.9, about 1.05 to about 1.8, about 1.05 to about 1.7, about 1.05 to about 1.6, about 1.05 to about 1.5, about 1.05 to about 1.45, about 1.05 to about 1.4, about 1.05 to about 1.39, about 1.05 to about 1.38, about 1.05 to about 1.36, about 1.05 to about 1.35, about 1.05 to about 1.3, about 1.05 to about 1.25, about 1.05 to about 1.2, about 1.05 to about 1.15, about 1.05 to about 1.1, about 1.1 to about 2, about 1.1 to about 1.9, about 1.1 to about 1.8, about 1.1 to about 1.7, about 1.1 to about 1.6, about 1.1 to about 1.5, about 1.1 to about 1.45, about 1.1 to about 1.4, about 1.1 to about 1.39, about 1.1 to about 1.38, about 1.1 to about 1.36, about 1.1 to about 1.35, about 1.1 to about 1.3, about 1.1 to about 1.25, about 1.1 to about 1.2, about 1.1 to about 1.15, about 1.2 to about 2, about 1.2 to about 1.9, about 1.2 to about 1.8, about 1.2 to about 1.7, about 1.2 to about 1.6, about 1.2 to about 1.5, about 1.2 to about 1.45, about 1.2 to about 1.4, about 1.2 to about 1.39, about 1.2 to about 1.38, about 1.2 to about 1.36, about 1.2 to about 1.35, about 1.2 to about 1.3 or about 1.2 to about 1.25.

[0020] In some embodiments, the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration, as determined by Fourier transform infrared (FT-IR) spectroscopy, of less than about 0.05%, about 0.1%, about 0.2%, about 0.5%, about 0.8%, about 1%, about 1.2%, about 1.5%, about 1.8%, or about 2% to about 2.2%, about 2.5%, about 2.8%, about 3%, about 3.5%, about 4%, about 5%, about 6%, about 8%, about 10%, about 12%, about 14%, about 15%, about 16%, about 17%, or 18%. For example, the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration, as determined by FT-IR spectroscopy, of from about 0.1% to less than about 18%, from about 0.1% to about 17%, from about 0.1% to about 15%, from about 0.1% to about 12%, from about 0.1% to about 10%, from about 0.1% to about 8%, from about 0.1% to about 6%, from about 0.1% to about 5%, from about 0.1% to about 4%, from about 0.1% to about 3%, from about 0.1% to about 2%, from about 0.1% to about 1%, from about 0.5% to less than 18%, from about 0.5% to about 17%, from about 0.5% to about 15%, from about 0.5% to about 12%, from about 0.5% to about 10%, from about 0.5% to about 8%, from about 0.5% to about 6%, from about 0.5% to about 5%, from about 0.5% to about 4%, from about 0.5% to about 3%, from about 0.5% to about 2%, from about 0.5% to 1%, from about 1% to less than about 18%, from about 1% to about 17%, from about 1% to about 15%, from about 1% to about 12%, from about 1% to about 10%, from about 1% to about 8%, from about 1% to about 6%, from about 1% to about 5%, from about 1% to about 4%, from about 1% to about 3%, from about 1% to about 2%, or from about 1% to about 1.5%.

[0021] In one or more embodiments, the nitrogen-rich silicon nitride layer has a nitrogen-hydrogen bond concentration, as determined by FT-IR spectroscopy, of about 1%, about 3%, about 5%, about 6%, about 8%, about 10%, about 12%, about 15%, or about 18% to about 20%, about 22%, about 25%, about 26%, about 27%, about 28%, about 28%, or about 30%. For example, the nitrogen-rich silicon nitride layer has a nitrogen-hydrogen bond concentration, as determined by FT-IR spectroscopy, of about 1% to about 30%, about 3% to about 30%, about 5% to about 30%, about 8% to about 30%, about 10% to about 30%, about 12% to about 30%, about 15% to about 30%, about 18% to about 30%, about 20% to about 30%, about 25% to about 30%, about 1% to about 25%, about 3% to about 25%, about 5% to about 25%, about 8% to about 25%, about 10% to about 25%, about 12% to about 25%, about 15% to about 25%, about 18% to about 25%, about 20% to about 25%, about 1% to about 22%, about 3% to about 22%, about 5% to about 22%, about 8% to about 22%, about 10% to about 22%, about 12% to about 22%, about 15% to about 22%, about 18% to about 22%, or about 20% to about 22%.

[0022] The total hydrogen bond concentration of the nitrogen-rich silicon nitride layer is the sum of the silicon-hydrogen bond concentration and the nitrogen-hydrogen bond concentration. In one or more embodiments, the nitrogen-rich silicon nitride layer has a total hydrogen bond concentration of less than 30% as determined by FT-IR spectroscopy, such as about 1%, about 2%, about 3%, about 5%, about 6%, about 8%, about 10%, about 12%, about 15%, about 16%, or about 18% to about 20%, about 22%, about 23%, about 24%, about 25%, about 26%, about 27%, about 28%, about 28%, about 29%, or less than 30%. For example, the nitrogen-rich silicon nitride layer has a nitrogen-hydrogen bond concentration of from about 1% to less than 30%, from about 3% to less than 30%, from about 5% to less than 30%, from about 8% to less than 30%, from about 10% to less than 30%, from about 12% to less than 30%, from about 15% to less than 30%, from about 18% to less than 30%, from about 20% to less than 30%, from about 25% to less than 30%, from about 1% to about 28%, from about 3% to about 28%, from about 5% to about 28%, from about 8% to about 28%, from about 10% to about 28%, from about 12% to about 28%, from about 15% to about 28%, from about 18% to about 28%, from about 20% to about 28%, from about 1% to about 24%, from about 3% to about 24%, from about 5% to about 24%, from about 8% to about 24%, from about 10% to about 24%, from about 12% to about 24%, from about 15% to about 24%, from about 18% to about 24%, from about 20% to about 24%, from about 1% to about 23%, from about 3% to about 23%, from about 5% to about 23%, from about 8% to about 23%, from about 10% to about 23%, from about 12% to about 23%, from about 15% to about 23%, from about 16% to about 23%, from about 18% to about 23%, or from about 20% to about 23% as determined by FT-IR spectroscopy.

[0023] The nitrogen-rich silicon nitride layer has a relatively high water resistance compared to conventional silicon nitride. In one or more embodiments, the nitrogen-rich silicon nitride layer has a water resistance of about 1×10 -8 g / m 2 / day or more as determined by a water vapor transmission rate (WVTR) standard test conducted at 85% relative humidity and 85 °C, such as, for example, about 2×10 -8 g / m 2 / day, about 5×10 -8 g / m 2 / day, about 1×10 -7 g / m 2 / day, about 5×10 -7 g / m2 / day, about 1×10 -6 g / m 2 / day, or about 5×10 -6 g / m 2 / day to about 1×10 -5 g / m 2 / day, about 5×10 -5 g / m 2 / day, about 1×10 -4 g / m 2 / day, about 5×10 -4 g / m 2 / day, or about 1×10 -3 g / m 2 / day. For example, a nitrogen-rich silicon nitride layer has a water vapor transmission rate of about 1×10 -8 g / m 2 / day to about 1×10 -4 g / m 2 / day, about 1×10 -7 g / m 2 / day to about 5×10 -4 g / m 2 / day, or about 5×10 -6 g / m 2 / day to about 1×10 -5 g / m 2 / day. In one or more examples, a nitrogen-rich silicon nitride layer having a thickness of about 2000 Å has a water vapor transmission rate of about 2.8×10 -4 g / m 2 / day to about 4×10 -4 g / m 2 / day.

[0024] In one or more embodiments, a method of depositing a nitrogen-rich silicon nitride material or layer includes heating a workpiece to a processing temperature, exposing the workpiece to a deposition gas during a plasma-enhanced chemical vapor deposition (PE-CVD) process, and depositing a nitrogen-rich silicon nitride material or layer on the workpiece. In other embodiments, a method of depositing a nitrogen-rich silicon nitride material or layer includes heating a workpiece to a processing temperature, successively exposing the workpiece to a silicon precursor and a nitrogen precursor during a thermal atomic layer deposition (ALD) process or a plasma-enhanced ALD (PE-ALD) process, and depositing a nitrogen-rich silicon nitride material or layer on the workpiece. In the embodiments described and discussed herein, the workpiece may be, include, or be a substrate, a thin film transistor (TFT) structure or a portion thereof, a gate structure or a portion thereof, or any other type of electronic device or a portion thereof related to displays, semiconductors, photovoltaic cells, microelectronics, and / or other fields. In some examples, the workpiece includes one or more layers containing silicon oxide. In one or more examples, the method includes depositing a silicon oxide layer on the workpiece and then depositing a nitrogen-rich silicon nitride layer on the silicon oxide layer.

[0025] During PE-CVD or other deposition processes, the substrate or workpiece can be heated to the processing temperature or maintained at the processing temperature. The processing temperature can be about 25°C, about 50°C, about 80°C, about 100°C, about 150°C, or about 200°C to about 220°C, about 235°C, about 250°C, about 280°C, about 300°C, about 350°C, or about 400°C or higher. For example, the processing temperature can be about 25°C to about 400°C, about 25°C to about 300°C, about 25°C to about 280°C, about 25°C to about 265°C, about 25°C to about 250°C, about 25°C to about 235°C, about 25°C to about 220°C, about 25°C to about 200°C, about 25°C to about 180°C, about 25°C to about 150°C, about 25°C to about 125°C, about 25°C to about 100°C, about 25°C to about 80°C, about 25°C to about 50°C, about 100°C to about 400°C, about 100°C to about 300°C, about 100°C to about 280°C, about 100°C to about 265°C, about 100°C to about 250°C, about 100°C to about 235°C, about 100°C to about 220°C, about 100°C to about 200°C, about 100°C to about 180°C, about 100°C to about 150°C, about 100°C to about 125°C, about 200°C to about 400°C, about 200°C to about 300°C, about 200°C to about 280°C, about 200°C to about 265°C, about 200°C to about 250°C, about 200°C to about 235°C, about 200°C to about 220°C, about 220°C to about 250°C, about 230°C to about 250°C, or about 235°C to about 250°C. In one or more examples, the processing temperature is less than 350°C, less than 300°C, less than 280°C, less than 265°C, less than 250°C, less than 235°C, or less than 200°C.

[0026] In one or more embodiments, during PE-CVD or other deposition processes, the deposition gas may include one or more silicon precursors, one or more nitrogen precursors, and one or more carrier gases. The silicon precursor may be one or more of silane, disilane, trisilane, tetrasilane, silicon tetrafluoride, or any combination thereof, or may include these. The nitrogen precursor may be ammonia, hydrazine, methylamine, dimethylamine, nitrogen (N2), one or more of their plasmas, or any combination thereof, or may include these. The carrier gas may be one or more of nitrogen (N2), hydrogen (H2), argon, helium, neon, xenon, krypton, or any combination thereof, or may include these. In one or more examples, the silicon precursor is or contains silane, the nitrogen precursor is or contains ammonia, and the carrier gas is or contains nitrogen.

[0027] The flow rate of the silicon precursor in the deposition gas can be about 100 sccm (standard cubic centimeters per minute), about 150 sccm, about 180 sccm, about 200 sccm, about 220 sccm, or about 250 sccm to about 280 sccm, about 300 sccm, about 320 sccm, about 350 sccm, about 400 sccm, about 450 sccm, about 500 sccm, about 650 sccm, about 800 sccm, or about 1000 sccm. For example, the flow rate of the silicon precursor can be about 100 sccm to about 1,000 sccm, about 100 sccm to about 800 sccm, about 100 sccm to about 500 sccm, about 100 sccm to about 400 sccm, about 100 sccm to about 350 sccm, about 100 sccm to about 300 sccm, about 100 sccm to about 250 sccm, about 100 sccm to about 200 sccm, about 200 sccm to about 1,000 sccm, about 200 sccm to about 800 sccm, about 200 sccm to about 500 sccm, about 200 sccm to about 400 sccm, about 200 sccm to about 350 sccm, about 200 sccm to about 300 sccm, about 200 sccm to about 250 sccm, about 200 sccm to about 225 sccm, about 250 sccm to about 1,000 sccm, about 250 sccm to about 800 sccm, about 250 sccm to about 500 sccm, about 250 sccm to about 400 sccm, about 250 sccm to about 350 sccm, about 250 sccm to about 300 sccm, about 250 sccm to about 280 sccm, about 270 sccm to about 300 sccm, about 285 sccm to about 300 sccm, about 270 sccm to about 320 sccm, or about 285 sccm to about 320 sccm.

[0028] The flow rate of the nitrogen precursor in the deposition gas can be about 800 sccm, about 1000 sccm, about 1200 sccm, about 1350 sccm, about 1500 sccm, or about 1600 sccm to about 1650 sccm, about 1700 sccm, about 1800 sccm, about 2000 sccm, about 2200 sccm, about 2500 sccm, about 3000 sccm, about 3500 sccm, about 4000 sccm, or about 5000 sccm. For example, the flow rate of the nitrogen precursor can be about 1000 sccm to about 5000 sccm, about 1000 sccm to about 4000 sccm, about 1000 sccm to about 3000 sccm, about 1000 sccm to about 2500 sccm, about 1000 sccm to about 2000 sccm, about 1000 sccm to about 1800 sccm, about 1000 sccm to about 1500 sccm, about 1500 sccm to about 5000 sccm, about 1500 sccm to about 4000 sccm, about 1500 sccm to about 3000 sccm, about 1500 sccm to about 2500 sccm, about 1500 sccm to about 2000 sccm, about 1500 sccm to about 1800 sccm, about 1800 sccm to about 5000 sccm, about 1800 sccm to about 4000 sccm, about 1800 sccm to about 3000 sccm, about 1800 sccm to about 2500 sccm, or about 1800 sccm to about 2000 sccm.

[0029] The flow rate of the carrier gas in the deposition gas can be about 1 SLM (standard liters per second), about 3 SLM, about 4 SLM, about 5 SLM, about 6 SLM, or about 8 SLM to about 9 SLM, about 10 SLM, about 12 SLM, about 15 SLM, about 18 SLM, about 20 SLM, about 22 SLM, about 25 SLM, or about 30 SLM. For example, the flow rate of the carrier gas can be about 1 SLM to about 30 SLM, about 5 SLM to about 30 SLM, about 8 SLM to about 30 SLM, about 10 SLM to about 30 SLM, about 12 SLM to about 30 SLM, about 15 SLM to about 30 SLM, about 20 SLM to about 30 SLM, about 1 SLM to about 20 SLM, about 5 SLM to about 20 SLM, about 8 SLM to about 20 SLM, about 10 SLM to about 20 SLM, about 12 SLM to about 20 SLM, about 15 SLM to about 20 SLM, about 18 SLM to about 20 SLM, about 1 SLM to about 15 SLM, about 5 SLM to about 15 SLM, about 8 SLM to about 15 SLM, about 10 SLM to about 15 SLM, about 12 SLM to about 15 SLM, or about 13 SLM to about 15 SLM.

[0030] In one or more examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas of about 1 silicon precursor, i.e., a molar ratio in which the nitrogen precursor is in the range of about 4 to about 8 and the carrier gas is in the range of about 20 to about 80, respectively. In other examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas of about 1 silicon precursor, i.e., a molar ratio in which the nitrogen precursor is in the range of about 5 to about 7 and the carrier gas is in the range of about 30 to about 50, respectively. In some examples, the deposition gas has a molar ratio of silicon precursor to nitrogen precursor to carrier gas of about 1 silicon precursor, i.e., a molar ratio in which the nitrogen precursor is in the range of about 5.5 to about 6.5 and the carrier gas is in the range of about 35 to about 45, respectively.

[0031] PE-CVD or other deposition processes can be carried out in various plasma systems such as capacitively coupled plasma (CCP) systems, inductively coupled plasma (ICP) systems having high density plasma (HDP), or remote plasma systems (RPS), or in other PE-CVD or PE-ALD process chambers or systems. During the PE-CVD or other deposition process, the plasma can have an RF power of less than 2400 watts (W), for example, about 800W, about 1000W, about 1200W, about 1500W, about 1700W, or about 1800W to about 1900W, about 2000W, about 2100W, about 2200W, or about 2300W, etc. For example, the plasma can have an RF power of about 800W to less than 2400W, about 800W to about 2200W, about 800W to about 2000W, about 800W to about 1900W, about 800W to about 1800W, about 800W to about 1600W, about 800W to about 1200W, about 1200W to less than 2400W, about 1200W to about 2200W, about 1200W to about 2000W, about 1200W to about 1900W, about 1200W to about 1800W, about 1200W to about 1600W, about 1200W to about 1500W, about 1500W to less than 2400W, about 1500W to about 2200W, about 1500W to about 2000W, about 1500W to about 1900W, or about 1500W to about 1800W.

[0032] In one or more embodiments, the nitrogen-rich silicon nitride layer is part of a passivation film stack that includes a silicon oxide layer and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. In some examples, the passivation film stack also includes a third layer containing silicon nitride disposed on the nitrogen-rich silicon nitride layer. The third layer can be any type of silicon nitride, such as nitrogen-rich silicon nitride, nitrogen-poor silicon nitride, and / or hydrogen-rich silicon nitride, and can include these. In other embodiments, the nitrogen-rich silicon nitride layer is part of an oxide buffer film stack that includes an oxide buffer layer containing silicon oxide and an oxide buffer layer containing nitrogen-rich silicon nitride disposed on the oxide buffer layer containing silicon oxide.

[0033] In some embodiments, the silicon oxide layer and / or the oxide buffer layer containing silicon oxide can be deposited or formed by other means during a PE-CVD process. The PE-CVD process includes exposing the workpiece to an oxide deposition gas and depositing the silicon oxide layer and / or the oxide buffer layer containing silicon oxide on the workpiece. The oxide deposition gas can include one or more silicon precursors, one or more oxidants, and optionally one or more carrier gases. The silicon precursor can be one or more of silane, disilane, trisilane, tetrasilane, silicon tetrafluoride, or any combination or inclusion thereof. The oxidant can be nitrous oxide, oxygen, ozone, water, one or more peroxides, one or more of their plasmas, or any combination or inclusion thereof. The carrier gas, if included, can be one or more of nitrogen (N2), hydrogen (H2), argon, helium, neon, krypton, or any combination or inclusion thereof. In one or more examples, the silicon precursor is or contains silane, and the oxidant is or contains nitrous oxide.

[0034] The flow rate of the silicon precursor in the oxide deposition gas can be about 20 sccm, about 35 sccm, about 50 sccm, about 60 sccm, about 80 sccm, or about 100 sccm to about 120 sccm, about 135 sccm, about 150 sccm, about 165 sccm, about 180 sccm, about 200 sccm, about 250 sccm, about 280 sccm, about 300 sccm, about 350 sccm, about 400 sccm, or about 500 sccm. For example, the flow rate of the silicon precursor can be about 20 sccm to about 500 sccm, about 20 sccm to about 400 sccm, about 20 sccm to about 350 sccm, about 20 sccm to about 300 sccm, about 20 sccm to about 250 sccm, about 20 sccm to about 220 sccm, about 20 sccm to about 200 sccm, about 20 sccm to about 180 sccm, about 20 sccm to about 165 sccm, about 20 sccm to about 150 sccm, about 20 sccm to about 135 sccm, about 20 sccm to about 120 sccm, about 20 sccm to about 100 sccm, about 20 sccm to about 80 sccm, about 20 sccm to about 50 sccm, about 100 sccm to about 500 sccm, about 100 sccm to about 400 sccm, about 100 sccm to about 350 sccm, about 100 sccm to about 300 sccm, about 100 sccm to about 250 sccm, about 100 sccm to about 220 sccm, about 100 sccm to about 200 sccm, about 100 sccm to about 180 sccm, about 100 sccm to about 165 sccm, about 100 sccm to about 150 sccm, about 100 sccm to about 135 sccm, about 100 sccm to about 120 sccm, about 140 sccm to about 500 sccm, about 140 sccm to about 400 sccm, about 140 sccm to about 350 sccm, about 140 sccm to about 300 sccm, about 140 sccm to about 250 sccm, about 140 sccm to about 220 sccm, about 140 sccm to about 200 sccm, about 140 sccm to about 180 sccm, about 140 sccm to about 165 sccm, or about 140 sccm to about 150 sccm.

[0035] The flow rate of the oxidant in the oxide deposition gas can be about 1 SLM, about 2 SLM, about 3 SLM, about 4 SLM, about 5 SLM, or about 6 SLM to about 7 SLM, about 8 SLM, about 9 SLM, about 10 SLM, about 11 SLM, about 12 SLM, about 14 SLM, about 16 SLM, about 18 SLM, or about 20 SLM. For example, the flow rate of the oxidant in the oxide deposition gas can be about 1 SLM to about 20 SLM, about 1 SLM to about 18 SLM, about 1 SLM to about 15 SLM, about 1 SLM to about 12 SLM, about 1 SLM to about 10 SLM, about 1 SLM to about 8 SLM, about 1 SLM to about 6 SLM, about 1 SLM to about 5 SLM, about 4 SLM to about 20 SLM, about 4 SLM to about 18 SLM, about 4 SLM to about 15 SLM, about 4 SLM to about 12 SLM, about 4 SLM to about 10 SLM, about 4 SLM to about 8 SLM, about 4 SLM to about 6 SLM, about 8 SLM to about 20 SLM, about 8 SLM to about 18 SLM, about 8 SLM to about 15 SLM, about 8 SLM to about 12 SLM, or about 8 SLM to about 10 SLM.

[0036] In some examples, during the PE-CVD process, the oxide deposition gas is exposed to a plasma with an RF power of about 800 W, about 1000 W, about 1500 W, about 1800 W, or about 2000 W to about 2200 W, about 2500 W, about 2800 W, about 3000 W, about 3500 W, about 4000 W, about 4500 W, or about 5000 W or more. For example, during the PE-CVD process, the oxide deposition gas is exposed to a plasma with an RF power of about 800 W to 5000 W, about 1000 W to about 4000 W, about 1000 W to about 3500 W, about 1000 W to about 3000 W, about 1000 W to about 2500 W, about 1000 W to about 2000 W, about 2000 W to about 4000 W, about 2000 W to about 3500 W, about 2000 W to about 3000 W, about 2000 W to about 2500 W, about 2000 W to about 2200 W, or about 2800 W to about 3200 W.

[0037] FIG. 1 is a schematic diagram of a thin film transistor (TFT) structure 100 containing a passivation film stack 156 including a silicon oxide layer 160 and a nitrogen-rich silicon nitride layer 170, according to one or more embodiments described and discussed herein. The TFT structure 100 contains a buffer layer 110 disposed on a substrate 102 and a first metal layer 120 disposed on the buffer layer 110. The buffer layer 110 is disposed between the substrate 102 and the first metal layer 120.

[0038] The substrate 102 can be a semiconductor substrate, a display substrate, or any other type of substrate. In some examples, the substrate 102 can be transparent. The substrate 102 can be glass, quartz, sapphire, plastic or polymer (e.g., a transparent plastic film), silicon, silicon oxide, gallium, gallium arsenide, doped variants thereof, or any combination or inclusion thereof. The buffer layer 110 can be silicon oxide, silicon nitride, silicon oxynitride, dopants thereof, or any combination or inclusion thereof. The buffer layer 110 can include one, two, three, or four or more layers of the same material and / or different materials. In some examples, the buffer layer 110 can be or include a silicon oxide stack and a silicon nitride stack. For example, the buffer layer 110 can include a first silicon oxide layer, a first silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the first silicon nitride layer. The buffer layer 110 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the buffer layer 110 can have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0039] The first metal layer 120 can be, or can include, chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, their alloys, their dopants, or any combination thereof. The first metal layer 120 can have a thickness of about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the first metal layer 120 can have a thickness of about 500 Å to about 10000 Å, about 1000 Å to about 10000 Å, or about 1500 Å to about 8000 Å.

[0040] The TFT structure 100 contains a gate insulator layer 130 disposed on and / or covering the first metal layer 120 and disposed on the buffer layer 110. The metal oxide layer 140 is disposed on the gate insulator layer 130. The second metal layer, i.e., the contact metal layer 150, is disposed on and / or covering the metal oxide layer 140 and is disposed on the gate insulator layer 130 to form a gate structure.

[0041] The gate insulator layer 130 can be, or can include, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, their silicates, their nitrides, their dopants, or any combination thereof. The gate insulator layer 130 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the gate insulator layer 130 can have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0042] The metal oxide layer 140 may be, or may contain, molybdenum oxide, copper oxide, aluminum oxide, titanium oxide, indium oxide, tin oxide, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), alloys thereof, dopants thereof, or any combination thereof. The metal oxide layer 140 can have a thickness of about 50 Å, about 100 Å, about 250 Å, or about 500 Å to about 800 Å, about 1000 Å, about 1200 Å, about 1500 Å, about 1800 Å, or about 2000 Å. For example, the metal oxide layer 140 can have a thickness of about 50 Å to about 2000 Å, about 100 Å to about 2000 Å, or about 500 Å to about 1500 Å.

[0043] The second metal layer, i.e., the contact metal layer 150, may be, or may contain, chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium - molybdenum, copper - molybdenum, alloys thereof, dopants thereof, or any combination thereof. The second metal layer, i.e., the contact metal layer 150, can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the second metal layer, i.e., the contact metal layer 150, can have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0044] The passivation film stack 156 is disposed on the gate structure so that the silicon oxide layer 160 is disposed on at least one, or two or more, of the contact metal layer 150, the metal oxide layer 140, the gate insulator layer 130, or any combination thereof, covering these. In one or more examples, the silicon oxide layer 160 is disposed on the contact metal layer 150, the metal oxide layer 140, and the gate dielectric layer 130. The nitrogen - rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0045] The silicon oxide layer 160 may be silicon dioxide or silica, or may contain these. The silicon oxide layer 160 can have a thickness of about 50 nm, about 100 nm, or about 200 nm to about 300 nm, about 500 nm, about 800 nm, or about 1,000 nm or more. For example, the silicon oxide layer 160 can have a thickness of about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 200 nm, about 50 nm to about 100 nm, about 100 nm to about 1,000 nm, about 100 nm to about 800 nm, about 100 nm to about 500 nm, about 100 nm to about 300 nm, or about 100 nm to about 200 nm.

[0046] The nitrogen-rich silicon nitride layer 170 contains the compositions described and discussed herein. The nitrogen-rich silicon nitride layer 170 can have a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, or about 1000 nm or more. For example, the nitrogen-rich silicon nitride layer 170 can have a thickness of about 1 nm to about 1000 nm, about 1 nm to about 800 nm, about 1 nm to about 500 nm, about 1 nm to about 300 nm, about 1 nm to about 250 nm, about 1 nm to about 200 nm, about 1 nm to about 150 nm, about 1 nm to about 100 nm, about 1 nm to about 80 nm, about 1 nm to about 50 nm, about 1 nm to about 25 nm, about 1 nm to about 15 nm, about 1 nm to about 10 nm, about 1 nm to about 5 nm, about 20 nm to about 1000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, about 50 nm to about 100 nm, or about 50 nm to about 80 nm.

[0047] In one or more examples, the silicon oxide layer 160 has a thickness of about 50 nm to about 500 nm, and the nitrogen-rich silicon nitride layer 170 has a thickness of about 1 nm to about 200 nm.

[0048] FIG. 2 is a schematic diagram of a TFT structure 200 according to one or more embodiments described and discussed herein. The TFT structure 200 includes a passivation film stack 158 including a silicon oxide layer 160, a nitrogen-rich silicon nitride layer 170, and a third layer 180 containing silicon nitride disposed on the nitrogen-rich silicon nitride layer 170. The third layer 180 can be any type of silicon nitride, including, but not limited to, nitrogen-rich silicon nitride, nitrogen-poor silicon nitride, and / or hydrogen-rich silicon nitride. The silicon and nitrogen in the third layer 180 can have a stoichiometric ratio or Si:N ratio of about 1:1, about 1:1.1, about 1:1.2, about 1:1.3, or about 3:4. In some examples, the third layer 180 is or contains a hydrogen-rich silicon nitride layer having a higher hydrogen concentration than the nitrogen-rich silicon nitride layer 170. In other examples, the third layer 180 is or contains a nitrogen-rich silicon nitride layer having the same or substantially the same nitrogen concentration as the nitrogen-rich silicon nitride layer 170.

[0049] The third layer 180 containing silicon nitride can be deposited by any deposition process, such as one or more thermal vapor deposition processes and / or plasma vapor deposition processes. Exemplary deposition processes can be, but are not limited to, chemical vapor deposition (CVD), plasma enhanced CVD (PE-CVD), sputtering or physical vapor deposition (PVD), or any combination thereof. In some examples, the third layer 180 containing silicon nitride is deposited by a plasma system, such as a capacitively coupled plasma (CCP) system or an inductively coupled plasma (ICP) system using a high density plasma (HDP).

[0050] The third layer 180 containing silicon nitride contains the compositions described and discussed herein. The nitrogen-rich silicon nitride layer 170 can have a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, or about 1,000 nm or more. For example, the third layer 180 containing silicon nitride can have a thickness of about 1 nm to about 1,000 nm, about 5 nm to about 1,000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1,000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1,000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0051] In one or more examples, the silicon oxide layer 160 has a thickness of about 50 nm to about 500 nm, the nitrogen-rich silicon nitride layer 170 has a thickness of about 1 nm to about 200 nm, and the third layer 180 containing silicon nitride has a thickness of about 5 nm to about 500 nm.

[0052] FIG. 3 is a schematic diagram of a TFT structure 300 according to one or more embodiments described and discussed herein. The TFT structure 300 includes a buffer layer 110 disposed on a substrate 102, a first metal layer 120 disposed on the buffer layer 110, and a gate insulator layer 130 disposed on the first metal layer 120 and the buffer layer 110.

[0053] The TFT assembly 300 further includes a metal oxide layer 140 disposed on the gate insulator layer 130, and an etching stop layer (ESL) 320 disposed on and covering the metal oxide layer 140 and also disposed on the gate insulator layer 130. The TFT assembly 300 also includes a second metal layer, i.e., a contact metal layer 150, disposed on the etching stop layer 320 and the metal oxide layer 140. The second metal layer, i.e., the contact metal layer 150, passes through or extends through the etching stop layer 320 and contacts the metal oxide layer 140 by means of a via or a contact via.

[0054] The etching stop layer 320 may be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, their silicates, their nitrides, their dopants, or any combination or inclusion thereof. The etching stop layer 320 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, or about 1500 Å to about 2000 Å, about 2500 Å, about 3000 Å, about 3500 Å, about 4000 Å, or about 5000 Å. For example, the etching stop layer 320 can have a thickness of about 50 Å to about 5000 Å, about 100 Å to about 5000 Å, or about 1000 Å to about 5000 Å.

[0055] The silicon oxide layer 160 is disposed on and / or covers at least one or both of the second metal layer or the contact metal layer 150 and the etching stop layer 320. For example, the silicon oxide layer 160 of the passivation film stack 156 is disposed on and covers the second metal layer, i.e., the contact metal layer 150, and is also disposed on the etching stop layer 320. The nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0056] FIG. 4 is a schematic diagram of a TFT structure 400 according to one or more embodiments described and discussed herein. The TFT 400 includes a passivation film stack 158 including a silicon oxide layer 160, a nitrogen-rich silicon nitride layer 170, and a third layer 180 containing silicon nitride disposed on the nitrogen-rich silicon nitride layer 170.

[0057] FIG. 5 is a schematic diagram of a TFT structure 500 according to one or more embodiments described and discussed herein. The system of the TFT 500 includes a buffer layer 110 disposed on a substrate 102, a metal oxide layer 140 disposed on the buffer layer 110, a gate insulator layer 520 disposed on the metal oxide layer 140, and a first metal layer, i.e., a gate metal layer 530, disposed on the gate insulator layer 520. The gate insulator layer 520 is disposed between the metal oxide layer 140 and the first metal layer, i.e., the gate metal layer 530.

[0058] The gate insulator layer 520 may be or include silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, silicates thereof, nitrides thereof, dopants thereof, or any combination thereof. The gate insulator layer 520 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, or about 1500 Å to about 2000 Å, about 2500 Å, about 3000 Å, about 3500 Å, about 4000 Å, or about 5000 Å. For example, the gate insulator layer 520 can have a thickness of about 50 Å to about 5000 Å, about 100 Å to about 5000 Å, or about 1000 Å to about 5000 Å.

[0059] The first metal layer, i.e., the gate metal layer 530, can be chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, their alloys, their dopants, or any combination thereof, and may contain these. The first metal layer, i.e., the gate metal layer 530, can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the first metal layer, i.e., the gate metal layer 530, can have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0060] TFT 500 also contains an interlayer dielectric (ILD) layer 540 disposed on and / or covering at least one of the buffer layer 110, the metal oxide layer 140, the gate insulator layer 520, and / or the gate metal layer 530. In one or more examples, the interlayer dielectric layer 540 disposed on at least one buffer layer 110 is disposed on and covers the metal oxide layer 140, the gate dielectric layer 520, and the gate metal layer 530.

[0061] The interlayer dielectric layer 540 may be one or more layers consisting of, including, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, their silicates, their nitrides, their dopants, or any combination thereof. In one or more examples, the interlayer dielectric layer 540 may include a double layer of silicon nitride disposed on silicon oxide. In other examples, the interlayer dielectric layer 540 may include a double layer of silicon oxide disposed on silicon nitride. The interlayer dielectric layer 540 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the interlayer dielectric layer 540 may have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0062] The second metal layer, i.e., the contact metal layer 150, is disposed on the ILD layer 540 and the metal oxide layer 140. The second metal layer, i.e., the contact metal layer 150, passes through or extends through the interlayer dielectric layer 540 and contacts the metal oxide layer 140 via a via or contact via.

[0063] The silicon oxide layer 160 of the passivation film stack 156 is disposed on at least one or both of the ILD layer 540 and the contact metal layer 150. For example, the silicon oxide layer 160 is disposed on and covers the ILD layer 540 and the contact metal layer 150. The nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0064] FIG. 6 is a schematic diagram of a TFT structure 600 according to one or more embodiments described and discussed herein. The TFT system 600 has all of the layers or components as the TFT system 500, but also includes a third metal layer 550 disposed on the substrate 102. The buffer layer 110 is disposed on and / or covers the third metal layer 550 and is disposed on the substrate 102.

[0065] The third metal layer 550 can be, or include, chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium-molybdenum, copper-molybdenum, alloys thereof, dopants thereof, or any combination thereof. The third metal layer 550 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, or about 1500 Å to about 2000 Å, about 2500 Å, about 3000 Å, about 3500 Å, about 4000 Å, or about 5000 Å. For example, the third metal layer 550 can have a thickness of about 50 Å to about 5000 Å, about 100 Å to about 5000 Å, or about 1000 Å to about 5000 Å.

[0066] FIG. 7 is a schematic diagram of a TFT 700 according to one or more embodiments described and discussed herein. FIG. 8 is a schematic diagram of a TFT 800 according to the embodiments described and discussed herein. Each of the TFTs 700, 800 contains at least two nitrogen-rich silicon nitride layers, such as a nitrogen-rich silicon nitride layer 170 and a first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material.

[0067] TFT700 and 800 contain a buffer layer 710 disposed on a substrate 102, and the buffer layer 710 contains one or more low-temperature polysilicon (LTPS) materials. The LTPS material may be or may include one or more polysilicon materials, amorphous silicon (α-Si) materials, microcrystalline silicon materials, their dopants, or any combination thereof. The buffer layer 710 can have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the buffer layer 710 can have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0068] TFT700 and 800 contain a polysilicon layer 720 disposed on the buffer layer 710, a first gate insulator layer 730 disposed on the polysilicon layer 720 and the buffer layer 710, a first metal layer 732 disposed on the first gate insulator layer 730, and a first interlayer dielectric (ILD) layer 740 disposed on at least one of the first metal layer 732 and the first gate insulator layer 730. The polysilicon layer 720 may be or may include one or more polysilicon materials, amorphous silicon (α-Si) materials, microcrystalline silicon materials, their dopants, or any combination thereof. The polysilicon layer 720 can have a thickness of about 50 Å, about 100 Å, about 250 Å, or about 500 Å to about 600 Å, about 800 Å, about 1000 Å, about 1500 Å, about 1800 Å, or about 2000 Å. For example, the polysilicon layer 720 can have a thickness of about 50 Å to about 2000 Å, about 100 Å to about 2000 Å, or about 500 Å to about 1500 Å.

[0069] The first gate insulator layer 730 may be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, their silicates, nitrides thereof, dopants thereof, or any combination of these, and may contain these. The first gate insulator layer 730 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, or about 1500 Å to about 2000 Å, about 2500 Å, about 3000 Å, about 3500 Å, about 4000 Å, or about 5000 Å. For example, the first gate insulator layer 730 may have a thickness of about 50 Å to about 5000 Å, about 100 Å to about 5000 Å, or about 1000 Å to about 5000 Å.

[0070] The first metal layer 732 may be chromium, molybdenum, copper, titanium, tantalum, aluminum, chromium - molybdenum, copper - molybdenum, alloys thereof, dopants thereof, or any combination of these, and may contain these. The first metal layer 732 may have a thickness of about 100 Å, about 150 Å, about 200 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the first metal layer 732 may have a thickness of about 100 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0071] The first ILD layer 740 may be one or more layers consisting of, including, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, their silicates, their nitrides, their dopants, or any combination thereof. In one or more examples, the interlayer dielectric 740 may include a double layer of silicon nitride disposed on silicon oxide. In other examples, the first ILD layer 740 may include a double layer of silicon oxide disposed on silicon nitride. The first ILD layer 740 may have a thickness of about 50 Å, about 100 Å, about 250 Å, about 500 Å, about 800 Å, about 1000 Å, about 1500 Å, or about 2000 Å to about 2500 Å, about 3000 Å, about 4000 Å, about 5000 Å, about 8000 Å, or about 10000 Å. For example, the first ILD layer 740 may have a thickness of about 50 Å to about 10000 Å, about 500 Å to about 10000 Å, or about 1000 Å to about 8000 Å.

[0072] In one or more embodiments, the TFTs 700, 800 include an oxide buffer film 756 containing one or more first oxide buffer layers 760 and one or more second oxide buffer layers 770. The first oxide buffer layer 760 contains a nitrogen-rich silicon nitride material and is disposed on the first ILD layer 740. The second oxide buffer layer 770 contains a silicon oxide material and is disposed on the first oxide buffer layer 760.

[0073] The first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material has a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, or about 1000 nm or more. For example, the first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material can have a thickness of about 1 nm to about 1000 nm, about 5 nm to about 1000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0074] The second oxide buffer layer 770 containing a silicon oxide material has a thickness of about 1 nm, about 5 nm, about 10 nm, about 20 nm, about 30 nm, about 50 nm, about 80 nm, or about 100 nm to about 120 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 400 nm, about 500 nm, about 800 nm, or about 1000 nm or more. For example, the second oxide buffer layer 770 containing a silicon oxide material can have a thickness of about 1 nm to about 1000 nm, about 5 nm to about 1000 nm, about 5 nm to about 800 nm, about 5 nm to about 500 nm, about 5 nm to about 300 nm, about 5 nm to about 250 nm, about 5 nm to about 200 nm, about 5 nm to about 150 nm, about 5 nm to about 100 nm, about 5 nm to about 80 nm, about 5 nm to about 50 nm, about 5 nm to about 25 nm, about 5 nm to about 15 nm, about 5 nm to about 10 nm, about 20 nm to about 1000 nm, about 20 nm to about 800 nm, about 20 nm to about 500 nm, about 20 nm to about 300 nm, about 20 nm to about 250 nm, about 20 nm to about 200 nm, about 20 nm to about 150 nm, about 20 nm to about 100 nm, about 20 nm to about 80 nm, about 20 nm to about 50 nm, about 20 nm to about 25 nm, about 50 nm to about 1000 nm, about 50 nm to about 800 nm, about 50 nm to about 500 nm, about 50 nm to about 300 nm, about 50 nm to about 250 nm, about 50 nm to about 200 nm, about 50 nm to about 150 nm, or about 50 nm to about 100 nm.

[0075] In one or more examples, the first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material has a thickness of about 50 nm to about 500 nm, and the second oxide buffer layer 770 containing a silicon oxide material has a thickness of about 5 nm to about 500 nm.

[0076] The second metal layer 750 is in contact with both the first oxide buffer layer 760 and the polysilicon layer 720 in both TFTs 700 and 800. In one or more embodiments of the TFT 700, as shown in FIG. 7, the second metal layer 750 is further in contact with the first ILD layer 740. For example, the second metal layer 750 is disposed on the first ILD layer 740, and the first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material is disposed on and / or covers the second metal layer 750. In one or more embodiments of the TFT 800, the second metal layer 750 is further in contact with a second oxide buffer layer 770, as shown in FIG. 8. For example, the second metal layer 750 is disposed on the first oxide buffer layer 760 containing a nitrogen-rich silicon nitride material, and the second oxide buffer layer 770 is disposed on and / or covers the second metal layer 750.

[0077] The TFTs 700 and 800 also contain a third metal gate layer such as a metal oxide layer 140 disposed on the second oxide buffer layer 770, a second gate insulator layer 520 disposed on the metal oxide layer 140, and a gate metal layer 530 disposed on the second gate insulator layer 520. The TFTs 700 and 800 further contain a second ILD layer such as an ILD layer 540 disposed on at least one of the second oxide buffer layer 770, the metal oxide layer 140, the second gate insulator layer 520, and the gate metal layer 530.

[0078] As further shown in FIGS. 7 and 8, the TFTs 700 and 800 contain a fourth contact metal layer such as a contact metal layer 150 disposed on the second ILD layer 540 and in contact with the metal oxide layer 140 or the second metal layer 750, or both. The silicon oxide layer 160 of the passivation film stack 156 is disposed on at least one second ILD layer 540, on and / or covering the contact metal layer 150. The nitrogen-rich silicon nitride layer 170 is disposed on the silicon oxide layer 160.

[0079] Embodiments of the present disclosure are further related to any one or more of the following Items 1 to 23.

[0080] 1. A passivation film stack including a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 20 atomic percentage (at%) to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%.

[0081] 2. A thin film transistor including the passivation film stack according to Item 1, comprising a buffer layer disposed on a substrate, a first metal layer disposed on the buffer layer, a gate insulator layer disposed on the first metal layer and the buffer layer, a metal oxide layer disposed on the gate insulator layer, and a second metal layer disposed on the metal oxide layer and the gate insulator layer, wherein the silicon oxide layer of the passivation film stack is disposed on at least one of the second metal layer, the metal oxide layer, and the gate insulator layer.

[0082] 3. The thin film transistor according to Item 2, wherein the passivation film stack further includes a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, and the hydrogen concentration of the hydrogen-rich silicon nitride layer is higher than that of the nitrogen-rich silicon nitride layer.

[0083] 4. A thin film transistor including the passivation film stack according to Item 1, comprising a buffer layer disposed on a substrate, a first metal layer disposed on the buffer layer, a gate insulator layer disposed on the first metal layer and the buffer layer, a metal oxide layer disposed on the gate insulator layer, an etching stop layer disposed on the metal oxide layer and the gate insulator layer, and a second metal layer disposed on the etching stop layer and the metal oxide layer, wherein the silicon oxide layer of the passivation film stack is disposed on at least one of the second metal layer and the etching stop layer.

[0084] 5. The passivation film stack further includes a hydrogen-rich silicon nitride layer disposed on a nitrogen-rich silicon nitride layer, and the hydrogen-rich silicon nitride layer has a higher hydrogen concentration than the nitrogen-rich silicon nitride layer. The thin film transistor according to item 4.

[0085] 6. A thin film transistor including the passivation film stack according to item 1, comprising a buffer layer disposed on a substrate, a metal oxide layer disposed on the buffer layer, a gate insulator layer disposed on the metal oxide layer, a first metal layer disposed on the gate insulator layer, an interlayer dielectric layer disposed on at least one of the buffer layer, the metal oxide layer, the gate insulator layer, and the first metal layer, and a second metal layer disposed on the interlayer dielectric layer and the metal oxide layer, wherein the silicon oxide layer of the passivation film stack is disposed on at least one of the interlayer dielectric layer and the second metal layer.

[0086] 7. The thin film transistor according to item 6, further comprising a third metal layer disposed on the substrate, and the buffer layer is disposed on the third metal layer and the substrate.

[0087] 8. A thin film transistor including the passivation film stack according to claim 1, comprising: a buffer layer containing low-temperature polysilicon disposed on a substrate; a polysilicon layer disposed on the buffer layer; a first gate insulator layer disposed on the polysilicon layer and the buffer layer; a first metal layer disposed on the first gate insulator layer; a first interlayer dielectric layer disposed on at least one of the first metal layer and the first gate insulator layer; a first oxide buffer layer containing nitrogen-rich silicon nitride disposed on the first interlayer dielectric; a second oxide buffer layer containing silicon oxide disposed on the first oxide buffer layer; a second metal layer in contact with the first oxide buffer layer and the polysilicon layer; a metal oxide layer disposed on the second oxide buffer layer; a second gate insulator layer disposed on the metal oxide layer; a third metal layer disposed on the second gate insulator layer; a second interlayer dielectric layer disposed on at least one of the second oxide buffer layer, the metal oxide layer, the second gate insulator layer, and the third metal layer; and a fourth metal layer disposed on the second interlayer dielectric and in contact with the metal oxide layer or the second metal layer or both, wherein the silicon oxide layer of the passivation film stack is disposed on at least one of the second interlayer dielectric layer and the fourth metal layer.

[0088] 9. The thin film transistor according to claim 8, wherein the second metal layer is further in contact with the first interlayer dielectric layer or the second oxide buffer layer.

[0089] 10. A passivation film stack including a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, wherein the nitrogen-rich silicon nitride layer has a water resistance of about 1×10 -8 g / m 2 / day to about 1×10 -4 g / m 2 / day, a silicon-hydrogen bond concentration of about 0.1% to about 10%, and a ratio of nitrogen to silicon in the nitrogen-rich silicon nitride layer of greater than 1.03 to about 2.

[0090] 11. A method of depositing a silicon nitride material, comprising heating a workpiece to a temperature of about 200 °C to about 250 °C, exposing the workpiece to a deposition gas during a plasma enhanced chemical vapor deposition process, and depositing a nitrogen-rich silicon nitride layer on the workpiece, wherein the deposition gas includes a silicon precursor, a nitrogen precursor, and a carrier gas, and the molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are in the ranges of about 1: about 4 to about 8: about 20 to about 80, respectively.

[0091] 12. The method according to claim 11, wherein the molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are in the ranges of about 1: about 5 to about 7: about 30 to about 50, respectively, the silicon precursor includes silane, the nitrogen precursor includes ammonia, and the carrier gas includes nitrogen (N2).

[0092] 13. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at% to about 35 at%, a nitrogen concentration of about 40 at% to about 75 at%, and a hydrogen concentration of about 10 at% to about 35 at%, and the ratio of nitrogen to silicon in the nitrogen-rich silicon nitride layer is greater than 1.03 to about 2. The method according to claim 11.

[0093] 14. The passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 13, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of about 27 at% to about 34 at%.

[0094] 15. The passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 14, wherein the nitrogen-rich silicon nitride layer has a nitrogen concentration of about 42 at% to about 65 at%.

[0095] 16. The passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 15, wherein the nitrogen-rich silicon nitride layer has a hydrogen concentration of about 18 at% to about 25 at%.

[0096] 17. The nitrogen-rich silicon nitride layer has a ratio of nitrogen to silicon greater than 1.03 to about 2, and is the passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 16.

[0097] 18. The nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of about 0.5% to about 6%, and is the passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 17.

[0098] 19. The nitrogen-rich silicon nitride layer has a total hydrogen bond concentration of less than 30%, and is the passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 18.

[0099] 20. The nitrogen-rich silicon nitride layer has a water resistance of about 1×10 -8 g / m 2 / day to about 1×10 -4 g / m 2 / day, and is the passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 19.

[0100] 21. The nitrogen-rich silicon nitride layer has a thickness of about 1 nm to about 500 nm, and is the passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 20.

[0101] 22. The silicon oxide layer has a thickness of about 50 nm to about 1000 nm, and is the passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 21.

[0102] 23. Further includes a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, and the hydrogen-rich silicon nitride layer has a higher hydrogen concentration than the nitrogen-rich silicon nitride layer, and is the passivation film stack, thin film transistor, and / or method according to any one of claims 1 to 22.

[0103] The foregoing is directed to embodiments of the present disclosure, but other additional embodiments can be devised without departing from the basic scope of the present disclosure, and the scope of the invention is determined by the appended claims. All documents described herein are incorporated herein by reference, including any priority documents and / or test procedures, to the extent they do not conflict with this specification. As is apparent from the foregoing general description and the specific embodiments, embodiments of the present disclosure have been illustrated and described, but various changes can be made without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not limited by the foregoing general description and specific embodiments. Similarly, the term "comprising" is considered to be synonymous with the term "including" for the purposes of U.S. law. Similarly, whenever the transitional phrase "comprising" precedes a composition, element, or group of elements, a description of the composition, element, or element with the transitional phrases "consisting essentially of", "consisting of", "selected from the group consisting of", or "is" preceding is also contemplated for the same composition or group of elements, and vice versa should be understood.

[0104] Some embodiments and features have been described using a set of numerical upper limits and a set of numerical lower limits. It should be understood that ranges including any combination of any two values, e.g., any combination of any lower value and any upper value, any combination of any two lower values, and / or any combination of any two upper values, are contemplated unless otherwise indicated. Specific lower values, upper values, and ranges appear in one or more of the appended claims.

Claims

1. A passivation film stack including a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, wherein the nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of 0.5% to 6% and a total hydrogen bond concentration of less than 30%.

2. The passivation film stack according to claim 1, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of 20 atomic percentage (at%) to 35 at%, a nitrogen concentration of 40 at% to 75 at%, and a hydrogen concentration of 10 at% to 35 at%, and a ratio of nitrogen to silicon is more than 1.03 to 2.

3. The passivation film stack according to claim 1, wherein the nitrogen-rich silicon nitride layer has a silicon concentration of 27 at% to 34 at%, a nitrogen concentration of 42 at% to 65 at%, and a hydrogen concentration of 18 at% to 25 at%, and a ratio of nitrogen to silicon is more than 1.03 to 2.

4. The nitrogen-rich silicon nitride layer of the passivation film stack according to claim 1 has a water resistance of 1×10 －８ g / m ２ / day to 1×10 －４ g / m ２ / day.

5. The passivation film stack according to claim 1, wherein the nitrogen-rich silicon nitride layer has a thickness of 1 nm to 500 nm.

6. The passivation film stack according to claim 1, further including a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, wherein the hydrogen concentration of the hydrogen-rich silicon nitride layer is higher than that of the nitrogen-rich silicon nitride layer.

7. The nitrogen-rich silicon nitride layer is deposited from a deposition gas containing a silicon precursor, a nitrogen precursor, and a carrier gas by plasma-enhanced chemical vapor deposition, and the molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are in the ranges of 1:4 to 8, 20 to 80, respectively. The passivation film stack according to claim 1.

8. The molar ratios of the silicon precursor, the nitrogen precursor, and the carrier gas in the deposition gas are in the ranges of 1:5 to 7, 30 to 50, respectively. The silicon precursor contains silane, the nitrogen precursor contains ammonia, and the carrier gas contains nitrogen (N2). The passivation film stack according to claim 7.

9. A silicon oxide layer disposed on a workpiece, A nitrogen-rich silicon nitride layer disposed on the silicon oxide layer A passivation film stack comprising: The nitrogen-rich silicon nitride layer has a water resistance of 1×10 －８ g / m ２ / day to 1×10 －４ g / m ２ / day, and a silicon-hydrogen bond concentration of 0.1% to 10%. The passivation film stack.

10. The nitrogen-rich silicon nitride layer has a silicon concentration of 20 at% to 35 at%, a nitrogen concentration of 40 at% to 75 at%, and a hydrogen concentration of 10 at% to 35 at%. The ratio of nitrogen to silicon in the nitrogen-rich silicon nitride layer is greater than 1.03 to 2. The passivation film stack according to claim 9.

11. The nitrogen-rich silicon nitride layer has a silicon concentration of 27 at% to 34 at%, a nitrogen concentration of 42 at% to 65 at%, and a hydrogen concentration of 18 at% to 25 at%. The ratio of nitrogen to silicon in the nitrogen-rich silicon nitride layer is greater than 1.03 to 2. The passivation film stack according to claim 9.

12. The nitrogen-rich silicon nitride layer has a silicon-hydrogen bond concentration of 0.5% to 6%, and the passivation film stack according to claim 9.

13. The nitrogen-rich silicon nitride layer has a total hydrogen bond concentration of less than 30%, and the passivation film stack according to claim 9.

14. The nitrogen-rich silicon nitride layer has a thickness of 1 nm to 500 nm, and the passivation film stack according to claim 9.

15. The silicon oxide layer has a thickness of 50 nm to 1,000 nm, and the passivation film stack according to claim 9.

16. The passivation film stack further includes a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, and the hydrogen-rich silicon nitride layer has a higher hydrogen concentration than the nitrogen-rich silicon nitride layer, and the passivation film stack according to claim 9.

17. A silicon oxide layer disposed on a workpiece, A nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, and A passivation film stack including the above, The nitrogen-rich silicon nitride layer has a ratio of nitrogen to silicon of more than 1.03 to 2, and a silicon-hydrogen bond concentration of 0.5% to 6%, and the passivation film stack.

18. The nitrogen-rich silicon nitride layer has a total hydrogen bond concentration of less than 30%, and the passivation film stack according to claim 17.

19. The nitrogen-rich silicon nitride layer has a thickness of 1 nm to 500 nm, and the silicon oxide layer has a thickness of 50 nm to 1,000 nm, and the passivation film stack according to claim 17.

20. Further including a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer, wherein the hydrogen-rich silicon nitride layer has a higher hydrogen concentration than the nitrogen-rich silicon nitride layer, the passivation film stack according to claim 17.

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