Semiconductor device

Abstract

To provide a semiconductor device that achieves better operation.SOLUTION: A semiconductor device comprises a first transistor and a second transistor electrically connected to a gate of the first transistor. The first transistor has a first terminal electrically connected to a first wire, a second terminal electrically connected to a second wire, and a gate electrically connected to a first terminal or a second terminal of the second transistor. Each of the first and second transistors has an oxide semiconductor in at least a channel region, and has a small off current.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] One aspect of the present invention relates to a display device. For example, a liquid crystal display device is exemplified. A display device in which pixels are selected by a pixel signal line and a source signal line to display an image is classified into a technical category. Also, semiconductor devices such as driver circuits used in display devices, display devices, etc. Electronic devices using this technology are also included as part of the technical field. [Background technology]

[0002] A gate made of amorphous silicon transistors (also called a-Si TFTs) Development of a driver circuit is underway (for example, Patent Documents 1 and 2). A gate driver is a transistor that controls the timing of outputting a high voltage to the gate line. A pull-up transistor has a source and a drain. One of the inputs is connected to a clock signal line, and the other of the source and drain is connected to a gate signal line. The gate potential of the pull-up transistor is connected to the clock by capacitive coupling. A driving method is used in which the potential of the signal is increased to a value higher than the H level. In order to achieve this, the gate of the pull-up transistor must be left floating. All transistors connected to the gate of the pull-up transistor must be in the off state. be. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-207413 A [Patent Document 2] JP 2008-009393 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology, all transistors connected to the gate of the pull-up transistor Even if the transistor is in the off state, the pull-up transistor The charge held by the gate of the transistor was lost over time. It has been difficult to lower the driving frequency of a semiconductor device such as a circuit. As a result, the driving performance of the semiconductor device is reduced. There was a limit to how much power could be increased.

[0005] In view of the above problems, one aspect of the present invention is to provide a method for outputting a predetermined voltage to a downstream circuit. In a semiconductor device having a transistor (pull-up transistor) that controls Another object of the present invention is to realize a device that operates better. A transistor (pull-up transistor) that controls the timing of outputting a specified voltage to the circuit. One of the objectives of the present invention is to improve the driving capability of a semiconductor device having a semiconductor device having a transistor. Let us assume that. [Means for solving the problem]

[0006] One embodiment of the present invention includes a first transistor and a gate of the first transistor. and a second transistor connected to the first terminal of the first transistor, the first terminal of the first transistor being connected to the first wiring. a second terminal of the first transistor electrically connected to a second wiring; The gate of the first transistor is electrically connected to the first terminal or the second terminal of the second transistor. A semiconductor device is formed by being connected. In the above, the first to second transistors can have an oxide semiconductor in at least the channel region and have a small off-current and can be used. Alternatively, in the above, at least the second transistor can have an oxide semiconductor in at least the channel region and have a small off-current and can be used . Specifically, those with an off-current of 1 aA / μm or less at room temperature (here, 20 °C is assumed.) per 1 μm channel width can be used. In the above, one or more second transistors can be provided. When there are a plurality of second transistors, it is preferable that all of those transistors have an oxide semiconductor in at least the channel region and have a small off-current. In the above, the second wiring can be electrically connected to the subsequent-stage circuit. Thereby, the first transistor can function as a transistor ( pull-up transistor) that controls the timing of outputting a predetermined voltage to the subsequent-stage circuit.

[0007] Another aspect of the present invention has a first transistor, a second transistor, and a third transistor. The first terminal of the first transistor is electrically connected to the first wiring, the second terminal of the first transistor is electrically connected to the second wiring, the first terminal of the second transistor is electrically connected to the second wiring, the second terminal of the second transistor is electrically connected to the gate of the first transistor, the gate of the second transistor is electrically connected to the first wiring, and the first terminal of the third transistor is electrically connected to the third wiring. is connected, and the second terminal of the third transistor is electrically connected to the gate of the first transistor is connected, and the gate of the third transistor is electrically connected to the third wiring, whereby a semiconductor device is configured. In the above, for the first transistor to the third transistors, those in which at least the channel regions are formed of an oxide semiconductor can be used and the off-current of the first transistor to the third transistor can be 1 aA / μm or less Alternatively, in the above, at least the second transistor to the third transistors can be those in which at least the channel regions are formed of an oxide semiconductor and the off-current of at least the second transistor to the third transistor can be 1 aA / μm or less .

[0008] Another aspect of the present invention has a first transistor, a second transistor, and a third transistor , wherein the first terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is electrically connected to the second wiring, the first terminal of the second transistor is electrically connected to the third wiring, the second terminal of the second transistor is electrically connected to the second wiring, the first terminal of the third transistor is electrically connected to the fourth wiring , the second terminal of the third transistor is electrically connected to the gate of the first transistor , and the gate of the third transistor is electrically connected to the fourth wiring, whereby a semiconductor device is configured. In the above, for the first transistor to the third transistors, those in which at least the channel regions are formed of an oxide semiconductor can be used The off-state current of the first to third transistors can be 1 aA / μm The following can be used. Or, in the above, at least the third transistor The capacitor may have at least a channel region made of an oxide semiconductor. At least the third transistor may have an off-state current of 1 aA / μm or less. Cut.

[0009] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor and a fourth transistor, and a second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the third wiring. The second terminal of the third transistor is electrically connected to the second wiring, and the first terminal of the third transistor is electrically connected to the second wiring. The second terminal of the third transistor is electrically connected to the third wiring, and the second terminal of the third transistor is electrically connected to the first wiring. The gate of the third transistor is electrically connected to the gate of the second transistor. The first terminal of the fourth transistor is electrically connected to the gate of the fourth transistor and the fourth wiring. The second terminal of the fourth transistor is electrically connected to the gate of the first transistor. The gate of the fourth transistor is electrically connected to the fourth wiring. In the above, the first transistor to the second transistor The fourth transistor has at least a channel region formed of an oxide semiconductor. The off-state current of the first to fourth transistors can be 1 aA. / μm or less. Alternatively, in the above, at least the second transistor At least a channel region of each of the first to fourth transistors is formed using an oxide semiconductor. At least the second transistor to the fourth transistor The off-current of the transistor can be 1 aA / μm or less.

[0010] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor and a fourth transistor, and a second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the third wiring. The second terminal of the third transistor is electrically connected to the second wiring, and the first terminal of the third transistor is electrically connected to the second wiring. The second terminal of the third transistor is electrically connected to the fourth wiring, and the second terminal of the third transistor is electrically connected to the fourth wiring. The gate of the third transistor is electrically connected to the fourth wiring and the a first terminal of the fourth transistor is electrically connected to the third wiring; and a second terminal of the fourth transistor electrically connected to the gate of the first transistor; The gate of the fourth transistor is electrically connected to the fifth wiring. In the above, the first transistor to the fourth transistor The capacitor may have at least a channel region made of an oxide semiconductor. The off-state current of the first to fourth transistors is 1 aA / μm or less. Alternatively, in the above, at least the second transistor to the fourth transistor The transistor has at least a channel region formed of an oxide semiconductor. It is possible, and at least the off-currents of the second to fourth transistors can be 1 aA / μm or less can be used.

[0011] Another aspect of the present invention is a display device having a gate driver circuit, wherein the semiconductor device is used as the gate driver circuit.

[0012] In the present specification and the like, when it is explicitly described that X and Y are connected, it shall include the case where X and Y are electrically connected. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). An example of the case where X and Y are electrically connected is a configuration in which one or more elements (e.g., switches, transistors, capacitive elements, inductors, resistive elements, diodes etc.) that enable the electrical connection between X and Y are connected between X and Y.

Advantages of the Invention

[0013] One aspect of the present invention is a semiconductor device having a transistor ( pull-up transistor) that controls the timing of outputting a high voltage to a subsequent-stage circuit. In this semiconductor device, the charge stored in the gate of the pull-up transistor can be held for a long period. As a result, the driving frequency of the semiconductor device can be lowered. In addition, the range of driving frequencies at which the semiconductor device can operate can be widened. Thereby, better operation of the semiconductor device can be realized or the driving ability of the semiconductor device can be improved.

Brief Description of the Drawings

[0014]

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Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope thereof. Therefore, this embodiment It should not be construed as being limited to the described content. In the configurations described below, the same part or parts having similar functions are denoted by common reference numerals in different drawings, and detailed descriptions of the same part or parts having similar functions are omitted. In the drawings for reference, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0016] (Embodiment 1) In this embodiment, a circuit related to a display device which is one aspect of the present invention will be described.

[0017] FIG. 1(A) shows a configuration example of a circuit having transistors 101, 102, 103, 104, 105 and a circuit 200. The transistors constituting the circuit shown in FIG. 1( A) are of N-channel type. An N-channel type transistor is a transistor that turns on when the potential difference between the gate and the source is greater than the threshold voltage.

[0018] Note that, in the semiconductor layer of the transistors constituting the circuit shown in FIG. 1(A), an oxide semiconductor with a sufficiently reduced hydrogen concentration and high purity, and a sufficiently small carrier concentration, which is intrinsic (i-type) or substantially intrinsic (i-type), can be used. Thereby, the S value of the transistor can be improved. The off-current of the transistor can be reduced. The breakdown voltage of the transistor can be improved. The temperature characteristics of the transistor can be improved.

[0019] Note that the above oxide semiconductor is used as the semiconductor layer of some transistors, and the other transistors As the semiconductor layer of the transistor, semiconductors other than the above oxide semiconductor (for example, silicon (amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc.), organic semiconductors, etc.) can be used. However, as the semiconductor layer of the transistor in which at least the source or the drain is electrically connected to the gate of the transistor 101, the above oxide semiconductor is used.

[0020] Next, the connection relationship of the circuit shown in FIG. 1(A) will be described. The first terminal (one of the source and the drain) of the transistor 101 is connected to the wiring 111, and the second terminal (the other of the source and the drain) of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 102 is connected to the wiring 113, the second terminal of the transistor 102 is connected to the wiring 1 12, and the gate of the transistor 102 is connected to the circuit 200. The first terminal of the transistor 103 is connected to the wiring 112, the second terminal of the transistor 103 is connected to the gate of the transistor 101, and the gate of the transistor 103 is connected to the wiring 111. The first terminal of the transistor 104 is connected to the wiring 114, the second terminal of the transistor 1 04 is connected to the gate of the transistor 101, and the gate of the transistor 104 is connected to the wiring 114. The first terminal of the transistor 105 is connected to the wiring 113, the second terminal of the transistor 105 is connected to the gate of the transistor 101, and the gate of the transistor 105 is connected to the wiring 115. Note that the connection point between the gate of the transistor 101, the second terminal of the transistor 103, the second terminal of the transistor 104, and the second terminal of the transistor 105 is shown as the node 11. The connection point between the gate of the transistor 102 and the circuit 200 is shown as the node 12.

[0021] Note that the circuit related to the display device according to one aspect of the present invention is not limited to the configuration shown in FIG. 1(A). For example, as shown in FIG. 1(B), the gate of transistor 103 can be connected to the gate of transistor 102. As another example, as shown in FIG. 1(C), the first terminal of transistor 103 is connected to wiring 113, and the gate of transistor 103 can be connected to the gate of transistor 102. As another example, as shown in FIG. 1 (D), the second terminal of transistor 105 can be connected to wiring 112. As another example, as shown in FIG. 1(E), the first terminal of transistor 104 can be connected to wiring 116. As another example, as shown in FIG. 1(F), the gate of transistor 104 can be connected to wiring 116. Note that it is possible to combine at least two or more of the configurations shown in FIGS. 1(B) to (F). For example by combining FIG. 1(C) and FIG. 1(E), the first terminal of transistor 103 is connected to wiring 113, and the first terminal of transistor 104 is connected to wiring 116 is possible.

[0022] Note that circuit 200 can be connected to any wiring or any node according to its configuration is possible. For example, circuit 200 can be connected to at least one of wiring 111, wiring 112, wiring 113, wiring 11 4 and node 11.

[0023] A clock signal is input to wiring 111. The output signal of the circuit of the present embodiment is supplied to wiring 112. A voltage V2 is supplied to wiring 113. A star is supplied to wiring 114 A top pulse is input. A reset signal is input to wiring 115. Here, for the sake of convenience, the H-level potential of the signals input to wiring 11 1, wiring 112, wiring 114, and wiring 115 is defined as potential V1, and the L-level potential of the signals input to wiring 111, wiring 112, wiring 114, and wiring 115 is defined as potential V2 for the sake of convenience.

[0024] Wiring 111 is a wiring for transmitting signals such as a clock signal from an external circuit such as a controller to the circuit of the present embodiment, and has a function as a signal line or a clock signal line. The wiring 112 is a wiring for transmitting the output signal of the circuit of the present embodiment to a circuit such as a pixel circuit or a demultiplexer, and has a function as a signal line or a gate signal line. Wiring 113 is a wiring for supplying a power supply voltage such as voltage V2 from an external circuit such as a power supply circuit to the circuit of the present embodiment, and has a function as a power supply line, a negative power supply line, or a ground line. Wiring 114 is a wiring for transmitting a start signal from an external circuit such as a timing controller or another circuit to the circuit of the present embodiment, and has a function as a signal line. Wiring 115 is a wiring for transmitting a reset signal from an external circuit such as a timing controller or another circuit to the circuit of the present embodiment, and has a function as a signal line.

[0025] Transistor 101 has a function as a switch for controlling the conduction state between wiring 111 and wiring 112. Further, transistor 101 has a function of controlling the timing for raising the potential of node 11 by capacitive coupling between the second terminal and the gate. Transistor 10 2 has a function as a switch for controlling the conduction state between wiring 113 and wiring 112. It operates as follows. Transistor 103 functions as a switch that controls the conduction state between node 11 and wiring 112. Transistor 104 functions as a switch that controls the conduction state between wiring 114 and node 11. In addition, transistor 104 functions as a diode with its input terminal connected to wiring 114 and its output terminal connected to node 11. Transistor 105 functions as a switch that controls the conduction state between wiring 113 and node 11.

[0026] Next, an example of the operation of the circuit shown in FIGS. 1(A) to (F) will be described with reference to the timing chart shown in FIG. 2(A) and the schematic diagrams shown in FIGS. 2(B) to (E) and FIGS. 3(A) to (C). Here, the circuit shown in FIG. 1(A) will be described as an example.

[0027] FIG. 2(A) shows an example of the timing chart of the potentials of wiring 111, wiring 114, wiring 115, and wiring 112. Also shown are the potentials of node 11 and node 12. The timing chart shown in FIG. 2(A) has periods A, B, C, D, and E. The timing chart shown in FIG. 2(A) has a period in which periods A, B, and C are arranged in order, and a period in which periods D and E are arranged alternately.

[0028] First, period A will be described with reference to FIGS. 2(A), 2(B), and 2(C). In period A, the potential of wiring 111 (denoted as potential V111) becomes V2 (a potential at the L level). As a result, transistor 103 turns off, and wiring 112 and node 11 become non-conductive. The potential of wiring 114 (denoted as potential V114) is V1 (a potential at the H level). As a result, the transistor 104 turns on, and thus the wiring 114 and the node 1 1 are in a conductive state. The potential of the wiring 115 (denoted as the potential V115) becomes V2. Due to this, the transistor 105 turns off, and thus the wiring 113 and the node 11 are in a non-conductive state. Therefore, since the potential of the wiring 114 is supplied to the node 11, the potential of the node 1 1 (denoted as the potential V11) starts to rise. Eventually, the potential of the node 11 exceeds V2 + V th101 (Vth101 is the threshold voltage of the transistor 101). As a result, the transistor 101 turns on, and thus the wiring 112 becomes conductive with the wiring 111. The potential of the node 12 (denoted as the potential V12) becomes V2 or at least less than V2 + Vth102 (Vth102 is the threshold voltage of the transistor 102) due to the circuit 200. Due to this, the transistor 102 turns off, and thus the wiring 113 and the wiring 112 are in a non-conductive state. Therefore, since the potential of the wiring 111 is supplied to the wiring 112, the potential of the wiring 112 (denoted as the potential V112) becomes V2 (see Fig. 2(B)).

[0029] After that, the potential of the node 11 further rises. Eventually, the potential of the node 11 rises to V1 - V th104 (Vth104 is the threshold voltage of the transistor 104). Then, the transistor 104 turns off, and thus the wiring 114 and the node 11 are in a non-conductive state. Therefore, since the node 11 becomes floating, the potential of the node 11 is maintained at V1 - Vth1 04 (see Fig. 2(C)).

[0030] Regarding the period B, it will be described with reference to Figs. 2(A) and 2(D). In the period B, the node 12 The potential of remains less than V2 or V2 + Vth102 due to circuit 200. As a result, since transistor 102 remains off, wiring 113 and wiring 112 remain non-conductive. The potential of wiring 111 becomes V1. Then, since transistor 101 remains on, the potential of wiring 112 rises. At the same time, since transistor 103 turns on, wiring 112 and node 11 become conductive. However, when the potential of wiring 112 has risen to V1 - Vth103 (Vth103 is the threshold voltage of transistor 103), transistor 103 turns off. Therefore, wiring 112 and node 11 become non-conductive. The potential of wiring 114 becomes V2. As a result, since transistor 104 remains off, wiring 114 and node 11 remain non-conductive. The potential of wiring 115 remains V2. As a result, since transistor 105 remains off, wiring 113 and node 11 remain non-conductive. Therefore, node 11 becomes floating. At this time, the potential of wiring 112 continues to rise. Therefore, the potential of node 11 can rise to V1 + Vth101 + Va (Va is a positive number) due to the parasitic capacitance between the gate and the second terminal of transistor 101. This is the so-called bootstrap operation. Thus, the potential of wiring 112 can rise to a value equal to the potential V1 (see Fig. 2(D)). Regarding period C, it will be described with reference to Figs. 2(A), 2(E), and 3(A). In period C, the potential of wiring 111 becomes V2. As a result, since transistor 103 remains off, wiring 112 and node 11 remain non-conductive. The potential of wiring 114 is V The potential of node 11 becomes floating. At this time, the potential of wiring 112 continues to rise. Therefore, the potential of node 11 can rise to V1 + Vth101 + Va (Va is a positive number) due to the parasitic capacitance between the gate and the second terminal of transistor 101. This is the so-called bootstrap operation. Thus, the potential of wiring 112 can rise to a value equal to the potential V1 (see Fig. 2(D)). (See Fig. 2(D)).

[0031] Regarding period C, it will be described with reference to Figs. 2(A), 2(E), and 3(A). In period C, the potential of wiring 111 becomes V2. As a result, since transistor 103 remains off, wiring 112 and node 11 remain non-conductive. The potential of wiring 114 is V 2. It remains at 2. As a result, the transistor 104 remains off, so the wiring 1 14 and the node 11 remain in a non-conductive state. The potential of the wiring 115 becomes V1. Due to this , the transistor 105 turns on, so the wiring 113 and the node 11 become conductive . Therefore, the potential of the wiring 113 is supplied to the node 11. Since the potential of the wiring 113 is V2, the potential of the node 11 becomes V2. As a result, the transistor 101 turns off , so the wiring 111 and the wiring 112 become non-conductive. The potential of the node 12 remains less than V2 + Vth102 due to the circuit 200. As a result, the transistor 102 remains off, so the wiring 113 and the wiring 112 remain non-conductive (see Fig. 2(E)). However, the timing when the potential of the wiring 111 becomes V2 is often earlier than the timing when the transistor 101 turns off. Therefore, before the transistor 101 turns off, the potential of the wiring 111 is supplied to the wiring 112, so the potential of the wiring 1 12 becomes V2 (see Fig. 3(A)). For the period D, it will be described with reference to Figs. 2(A) and 3(B). In the period D, the potential of the wiring 111 is V1. As a result, the transistor 103 turns on, so the wiring 11

[0032] 2 and the node 11 become conductive. The potential of the wiring 114 remains V2. Due to this , the transistor 104 remains off, so the wiring 114 and the node 11 remain non-conductive . The potential of the wiring 115 becomes V2. As a result, the wiring 113 and the node 1 1 become non-conductive. The potential of the node 12 is V2 + Vth102 by the circuit 200 . and remains so. ​It becomes a value exceeding this. As a result, the transistor 102 is turned on, so that the wiring 113 and the wiring 112 are in a conductive state. Therefore, the potential of the wiring 113 is supplied to the node 11 so that the potential of the node 11 becomes V2. As a result, the transistor 101 is turned off so that the wiring 111 and the wiring 112 are in a non-conductive state. The potential of the wiring 113 is supplied to the wiring 11 2, so that the potential of the wiring 112 becomes V2 (see Fig. 3(B)).

[0033] Period E will be described with reference to Figs. 2(A) and 3(C). In period E, the potential of the wiring 111 becomes V2. As a result, the transistor 103 is turned off, so that the wiring 11 2 and the node 11 are in a non-conductive state. The potential of the wiring 114 remains V2. As a result the transistor 104 remains off, so that the wiring 114 and the node 11 remain in a non-conductive state. The potential of the wiring 115 remains V2. As a result, the wiring 113 and the node 11 are in a non-conductive state. The potential of the node 12 becomes V2 or less than V2 + Vth102 by the circuit 200. As a result, the transistor 102 is turned off, so that the wiring 113 and the wiring 112 are in a non-conductive state. Therefore, the node 11 becomes a floating state so that the potential of the node 11 remains V2. As a result, the transistor 101 remains off so that the wiring 111 and the wiring 112 remain in a non-conductive state. The wiring 112 becomes a floating state, so that the potential of the wiring 112 remains V2 (see Fig. 3(C)).

[0034] In the semiconductor device shown in Fig. 1(C), in period D, it is preferable that the potential of the node 12 exceeds V2 + Vth102 and exceeds a value exceeding V2 + Vth103. As a result Therefore, since the transistor 103 is turned on, the wiring 113 and the node 11 are in a conductive state. As a result, the potential of the wiring 113 is supplied to the node 11. Thus, since the potential of the wiring 113 is supplied to the node 11 via one transistor, the potential of the node 11 can be stabilized.

[0035] Note that in the circuit shown in Fig. 1(D), in period C, when the transistor 105 is turned on , the wiring 113 and the wiring 112 are in a conductive state. Therefore, the potential of the wiring 113 is supplied to the wiring 112. Thereby, the fall time of the potential of the wiring 112 can be shortened.

[0036] Note that in the circuit shown in Fig. 1(E), the potential of the wiring 116 may be V1 in period A. In periods B to E, the potential of the wiring 116 can be V1 or V2. Therefore, the voltage V1 can be supplied to the wiring 116. Alternatively, a clock signal with a phase shift from the clock signal input to the wiring 111, or an inverted signal of the clock signal input to the wiring 111, etc. can be input to the wiring 116. In the semiconductor device shown in Fig. 1(F), the potential of the wiring 116 may be V1 in period A and V2 in period B. In periods C to E, the potential of the wiring 11 6 can be V1 or V2. Therefore, a clock signal with a phase shift from the clock signal input to the wiring 111, or an inverted signal of the clock signal input to the wiring 111, etc. can be input to the wiring 116. .

[0037] ​​​As described above, by using the bootstrap operation, the circuit can make the potential of wiring 112 equal to the potential of wiring 111.

[0038] In the conventional technology, the S value of the transistor was high. Therefore, after the potential of wiring 114 reached V1, the time until transistor 104 turned off was long or it was difficult to increase the driving frequency because it was necessary to lengthen period A or the rising time of the potential of wiring 112 was long (the rising time of the output signal was long) or the load that could be connected to wiring 112 was small or the channel width of transistor 101 was large or the layout area was large.

[0039] In contrast, in this embodiment, the S value of the transistor is low. Therefore, the driving ability can be improved For example, since the S value of transistor 104 is low, the time from when the potential of wiring 114 reaches V1 until transistor 104 turns on can be shortened Therefore, the time of period A can be shortened. As a result, the driving frequency can be improved As another example, since the S value of transistor 101 is low the rising time of the potential of wiring 112 can be shortened. Or, even if a large load is connected to wiring 112, the load can be driven. Or, since the channel width of transistor 101 can be reduced, the layout area can be reduced.

[0040] In the conventional technology, the off-current of the transistor was large. Therefore, the time As time passed, a large amount of charge was lost from node 11. Or, the potential of node 11 was decreasing. Or, the time for which the transistor 101 could maintain the potential of node 11 at a value equal to or higher than the value at which it turns on was short. Or, it was difficult to lower the drive frequency . Or, the range of drive frequencies at which it could operate was narrow.

[0041] In contrast, in the present embodiment, the off-current of the transistor is small. Therefore, the driving ability can be improved. For example, since the off-currents of transistor 103, transistor 104, and transistor 105 are small, the amount of charge lost from node 11 can be reduced . Therefore, the decrease in the potential of node 11 can be suppressed. That is, the time for which the potential of node 11 can be maintained at a value equal to or higher than the value at which transistor 101 turns on can be lengthened. Thereby, the drive frequency can be lowered, so that the range of drive frequencies at which it can operate can be widened.

[0042] In the circuits shown in FIGS. 1(A) to (F), other elements such as transistors can be provided . An example thereof will be described.

[0043] FIG. 4(A) shows an example in which a transistor 121 is provided in the circuit shown in FIG. 1(A). Similarly, it is possible to provide a transistor 121 in the circuits shown in FIGS. 1(B) to (F). The first terminal of transistor 121 is connected to wiring 113, the second terminal of transistor 121 is connected to wiring 112, and the gate of transistor 121 is connected to wiring 116 . It is preferable that a clock signal is input to wiring 116. Thereby, during period E ​​When the transistor 121 is turned on, the potential of the wiring 113 can be supplied to the wiring 112. Therefore, the noise of the wiring 112 can be reduced.

[0044] FIG. 4(B) shows an example in which a transistor 122 is provided in the circuit shown in FIG. 1(A). Similarly, in the circuits shown in FIGS. 1(B) to (F) and FIG. 4(A), it is possible to provide the transistor 122. The first terminal of the transistor 122 is connected to the wiring 113, and the second terminal of the transistor 122 is connected to the wiring 112. The gate of the transistor 122 is connected to the wiring 115. As a result, during period C, when the transistor 122 is turned on, the potential of the wiring 113 can be supplied to the wiring 112. Therefore, the fall time of the potential of the wiring 112 can be shortened.

[0045] FIG. 4(C) shows an example in which a transistor 123 is provided in the circuit shown in FIG. 1(A). Similarly, in the circuits shown in FIGS. 1(B) to (F) and FIGS. 4(A) to (B), it is possible to provide the transistor 123. The first terminal of the transistor 123 is connected to the wiring 114, the second terminal of the transistor 123 is connected to the node 11, and the gate of the transistor 123 is connected to the wiring 116. As a result, also during period E, the potential of the wiring 114 can be supplied to the node 11. Therefore, the noise of the node 11 can be reduced.

[0046] FIG. 4(D) shows an example in which a transistor 124 is provided in the circuit shown in FIG. 1(A). Similarly, in the circuits shown in FIGS. 1(B) to (F) and FIGS. 4(A) to (C), it is possible to provide the transistor 12 It is possible to provide 4. The first terminal of the transistor 124 is connected to the wiring 111, the second terminal of the transistor 124 is connected to the wiring 117, and the gate of the transistor 124 is connected to the node 11. Thus, the potential of the wiring 117 can be changed at the timing equal to the potential of the wiring 112. In this case, one of the wiring 112 and the wiring 117 may be connected to a load, and the other may be connected to another circuit. Thereby, the other circuit can be driven without being affected by the potential fluctuation due to the load.

[0047] FIG. 4(E) is an example in which the transistors 124 and 125 are provided in the circuit shown in FIG. 1(A). Similarly, in the circuits shown in FIGS. 1(B) to (F) and FIGS. 4(A) to (C), it is possible to provide the transistors 124 and 125. The first terminal of the transistor 125 is connected to the wiring 113, the second terminal of the transistor 125 is connected to the wiring 117, and the gate of the transistor 125 is connected to the node 12. Thereby, the potential of the wiring 117 can be maintained at V2. Or, the noise of the wiring 117 can be reduced.

[0048] FIG. 4(F) is an example in which the capacitive element 126 is provided in the circuit shown in FIG. 1(A). Similarly, in the circuits shown in FIGS. 1(B) to (F) and FIGS. 4(A) to (E), it is possible to provide the capacitive element 126. The capacitive element 126 is provided between the gate and the second terminal of the transistor 101.

[0049] Note that, in the circuits shown in FIGS. 1(A) to (F), it is possible to provide two or more elements among the transistors 121 to 125 and the capacitive element 126.

[0050] In the circuit of this embodiment, not only the timing chart shown in Fig. 2(A) but also various other timing charts can be used. An example thereof will be described. For example, the potential of node 12 is preferably less than V2 + Vth102 at least during period B among periods A to E. Therefore, during periods A and C to E, the potential of node 12 can be less than V2 + Vth102 or can be a value exceeding V2 + Vth102. However, during one of periods D and E (particularly period D), the potential of node 12 is preferably a value exceeding V2 + Vth102. And during the other of periods D and E (particularly period E), the potential of node 12 is preferably less than V2 + Vth102. Thereby, the time during which transistor 102 is in the on state can be shortened, so that the shift of the threshold voltage of transistor 102 can be suppressed. In the circuit shown in Fig. 1(C), when the potential of node 12 exceeds V2 + Vth102 during period A, transistor 103 turns on and the potential of node 11 decreases. Therefore, during period A, the potential of node 12 is preferably less than V2 + Vth102. As another example, as shown in Fig. 5(A), the signal input to wiring 111 can be unbalanced. Thereby, during period C, the timing at which the potential of wiring 115 becomes V1 can be delayed compared to the timing at which the potential of wiring 111 becomes V2, so that the fall time of the potential of wiring 112 can be shortened. As another example, as shown in Fig. 5(B), the signal input to wiring 111 can be a multiphase clock signal. This makes it possible to reduce power consumption. FIG. 5(B) shows, as an example, a timing chart when a four-phase clock signal is input to wiring 111.

[0051] For example, the W / L (W: channel width, L: channel length) ratio of transistor 101 may be larger than the W / L ratios of all of transistors 102, 103, 104, 105, 121, 122, 123, 124, and 125. This can shorten the rise time and fall time of wiring 112. Specifically, the W / L ratio of transistor 101 is preferably more than twice and less than 20 times the W / L ratio of transistor 104. More preferably, it is more than three times and less than 15 times. Even more preferably, it is more than five times and less than 12 times. As another example, the W / L ratio of transistor 105 may be smaller than the W / L ratio of transistor 104. This can delay the timing at which transistor 101 enters the off state during period C, so that the fall time of the potential of wiring 112 can be shortened. Specifically, the W / L ratio of transistor 105 is preferably 0.3 times or more and less than 1 time the W / L ratio of transistor 104. More preferably, it is 0.4 times or more and 0.9 times or less. Even more preferably, it is 0.5 times or more and 0.8 times or less. As another example, the W / L ratio of transistor 103 may be smaller than the W / L ratio of transistor 104. This can prevent the potential of node 11 from decreasing too much during period B. Specifically, transistor 1 disters 102, transistors 103, transistors 104, transistors 105, trans disters 121, transistors 122, transistors 123, transistors 124 and tra isters 125. This can shorten the rise time and fall time of wiring 112. Specifically, the W / L ratio of transistor 101 is more than twice and less than 20 times the W / L ratio of transistor 104. Preferably, it is more than three times and less than 15 times. More preferably, it is more than five times and less than 1 is preferably more than twice and less than 20 times the W / L ratio of transistor 104. More preferably, it is more than three times and less than 15 times. Even more preferably, it is more than five times and less than 1 is preferably more than twice and less than 20 times the W / L ratio of transistor 104. More preferably, it is more than three times and less than 15 times. Even more preferably, it is more than five times and less than 1 is preferably more than twice and less than 20 times the W / L ratio of transistor 104. More preferably, it is more than three times and less than 15 times. Even more preferably, it is more than five times and less than 1 is preferably more than twice and less than 20 times the W / L ratio of transistor 104. More preferably, it is more than three times and less than 15 times. Even more preferably, it is more than five times and less than 1 is preferably more than twice and less than 20 times the W / L ratio of transistor 104. More preferably, it is more than three times and less than 15 times. Even more preferably, it is more than five times and less than 1 is preferably more than twice and less than 20 times the W / L ratio of transistor 104. More preferably, it is more than three times and less than 15 times. Even more preferably, it is more than five times and less than 1 is preferably 0.3 times or more and less than 1 time the W / L ratio of transistor 104. More preferably, it is is preferably 0.3 times or more and less than 1 time the W / L ratio of transistor 104. More preferably, it is is preferably 0.3 times or more and less than 1 time the W / L ratio of transistor 104. More preferably, it is is preferably 0.3 times or more and less than 1 time the W / L ratio of transistor 104. More preferably, it is is preferably 0.3 times or more and less than 1 time the W / L ratio of transistor 104. More preferably, it is The W / L ratio of 03 is 0.1 times or more and less than 1 time the W / L ratio of transistor 104. This is preferable. More preferably, it is 0.3 times or more and 0.9 times or less. Even more preferably, it is 0.4 times or more and 0.7 times or less.

[0052] For example, the W / L ratio of transistor 122 is preferably larger than the W / L ratio of transistor 102. Thereby, the fall time of the potential of wiring 112 can be shortened. Specifically, the W / L ratio of transistor 122 is preferably 2 times or more and less than 20 times the W / L ratio of transistor 102. More preferably, it is 3 times or more and 15 times or less. Even more preferably, it is 5 times or more and less than 10 times. As another example, the W / L ratio of transistor 124 is preferably smaller than the W / L ratio of transistor 101. This is because the load connected to wiring 117 is often smaller than the load connected to wiring 112. As another example, the W / L ratio of transistor 125 is preferably smaller than the W / L ratio of transistor 102. This is because the load connected to wiring 117 is often smaller than the load connected to wiring 112.

[0053] For example, the amplitude voltage of node 12 is preferably less than the amplitude voltage of at least one of node 11, wiring 111, wiring 112, wiring 114, wiring 115, wiring 116, and wiring 117. Thereby, power consumption can be reduced. Specifically, the amplitude voltage of node 12 is preferably 0.3 times or more and less than 1 time the amplitude voltage of wiring 111. More preferably, it is 0.5 times or more and less than 1 time. Even more preferably, it is 0.6 times or more and 0.9 times or less. As another example, the amplitude voltage of node 11 is that of node 12, wiring 111, wiring 111, wiring It is preferable that at least one of the amplitudes of wiring 112, wiring 114, wiring 115, wiring 116, and wiring 117 exceeds the voltage. Thereby, since the potential difference between the gate and the source of transistor 101 can be increased, the rise time and fall time of the potential of wiring 112 can be shortened. Specifically, the amplitude voltage of node 11 preferably exceeds 1 times and is 2 times or less of the amplitude voltage of wiring 111. More preferably, it is 1.2 times or more and 1.8 times or less. Even more preferably, it is 1.4 times or more and 1.6 times or less. For example, the time during which transistor 102 is in the off state is preferably longer than the time during which the potential of wiring 111 becomes the H level. In the technology using amorphous silicon, the mobility of the transistor was low. Furthermore, since transistor 101 drives a large load (for example, a gate signal line), it was necessary to increase the channel width of transistor 101. Therefore, the channel width of transistor 101 was larger than the wiring width of wiring 111. In contrast, the mobility of the transistors constituting the circuit of this embodiment is higher than the mobility of the transistors using amorphous silicon. Therefore, the channel width of transistor 101 can be reduced. Therefore, the channel width of transistor 101 is preferably smaller than at least a part of the wiring width of wiring 111. In particular, the channel width of transistor 101 is preferably 0.3 times or more and less than 1 times of at least a part of the wiring width of wiring 111. More preferably, it is 0.4 times or more and 0.9 times or less. Even more preferably, it is 0.5 times or more and 0.8 times or less.

[0054]

[0055]

[0056] ​

[0057] Next, a specific example of the circuit 200 will be described. FIG. 7(A) shows a configuration example of the circuit 200 having the capacitor element 201 and the transistor 202. One electrode of the capacitor element 201 is connected to the wiring 111, and the other electrode of the capacitor element 201 is connected to the node 12. The transistor 202 has its first terminal connected to the wiring 113, and its second terminal is connected to the node 12, and the gate of the transistor 202 is connected to the node 11. In addition , the gate of the transistor 202 can be connected to the wiring 112 or the wiring 114 .

[0058] Next, an example of the operation of the circuit 200 will be described with reference to FIGS. 7(B) to (F).

[0059] In periods A and B, the potential of the node 11 can be at a high potential (for example, a value exceeding V2 + Vth202 (Vth 202 is the threshold voltage of the transistor 202)). For example, the potential of the node 11 has a value of V1 - Vth104 in period A and a value of V1 + Vt h101 + Va in period B. As a result, the transistor 202 is turned on, and the wiring 113 and the node 12 are in a conductive state. Therefore, the potential of the wiring 113 is supplied to the node 1 2. Since the potential of the wiring 113 is V2, the potential of the node 12 becomes V2 (see FIG. 7 (B)).

[0060] In period C, the potential of the wiring 111 becomes V2. At this time, since the transistor 202 remains in the on state , the wiring 113 and the node 12 remain in a conductive state. Therefore, since the potential of the wiring 113 continues to be supplied to the node 12, the potential of the node 12 remains at V2 It becomes. The capacitor element 201 holds the difference between the potential of the wiring 111 and the potential of the node 12 at this time. After that, the potential of the node 11 becomes V2. As a result, the transistor 202 enters the off state, so the wiring 113 and the node 12 become non-conductive. Therefore, the node 12 becomes a floating state. However, the potential of the node 12 is maintained at V2 by the capacitor element 201 (see Fig. 7(C)).

[0061] During the period D, the potential of the node 11 remains at V2. As a result, the transistor 202 remains in the off state, so the wiring 113 and the node 12 remain non-conductive. At this time, the potential of the wiring 111 becomes V1. As a result, the potential of the node 12 rises due to the capacitive coupling of the capacitor element 201 (see Fig. 7(D)). During the period E, the potential of the node 11 remains at V2. As a result, the transistor 202 remains in the off state, so the wiring 113 and the node 12 remain non-conductive. At this time, the potential of the wiring 111 becomes V2. As a result, the potential of the node 12 decreases due to the capacitive coupling of the capacitor element 201 (see Fig. 7(E)).

[0062] As described above, a circuit that can control the potential of the node 12 can be configured with a small number of elements.

[0063] It is also possible to provide a transistor 203 as shown in Fig. 7(F), in which, in Fig. 7(A), the first terminal is connected to the wiring 113, the second terminal is connected to the node 12, and the gate is connected to the wiring 114. The transistor 203 is in the on state during the period A and in the off state during the periods B to E. Therefore, during the period A, the potential of the wiring 113...Since the potential is supplied to node 12, the fall time of the potential of node 12 in period A can be shortened. Also, if the gate of transistor 203 is connected to wiring 115, transistor 203 turns on in period C and turns off in periods A, B, D, and E. Therefore, in period C, since the potential of wiring 113 is supplied to node 12, the voltage necessary for the operation can be surely held in capacitor element 201. Alternatively, in period C, since the time for capacitor element 201 to hold the voltage can be lengthened, the capacitance value of capacitor element 201 can be increased. If the capacitance value of capacitor element 201 is large, the potential of node 12 in period D can be increased.

[0064] In this embodiment, for example, since the off-current of transistor 202 is small, the amount of charge lost from capacitor element 201 can be reduced. Therefore, the decrease in the potential on the H side of node 12 can be suppressed. The increase in the potential on the L side of node 12 can be suppressed. As a result, the time from the start time of period A to the start time of the next period A can be made long. That is, the drive frequency can be lowered. Therefore, the range of drive frequencies at which operation is possible can be widened.

[0065] As a circuit described in this embodiment, the following configuration is included as one aspect of the present invention. A semiconductor device having transistors 101, 103, and 104 (see FIG. 6( A)). A semiconductor device having transistors 101, 102, and 104 (see FIG. 6(B)). A semiconductor device having transistors 101, 102, and 104 A semiconductor device having a transistor 103 and a transistor 104 (see FIGS. 6(C) and 6(D)). The semiconductor device having transistors 101, 102, 104, and 105 (see FIG. 6(E)). The semiconductor device having transistors 101, 102, 103, 104, and 105 (see FIG. 6(F )). )

[0066] (Embodiment 2) In this embodiment, a shift register circuit related to a display device, which is one aspect of the present invention, will be described. The shift register circuit of this embodiment can include the circuit described in Embodiment 1 . Further, the shift register circuit of this embodiment can be used in a drive circuit of a display device, such as a gate driver circuit and / or a source driver circuit.

[0067] FIG. 8 is a configuration example of a shift register circuit having N circuits 301 (denoted as circuits 301_1 to 301_N). As the circuit 301, the circuit of Embodiment 1 can be used. FIG. 8 shows an example when the circuit shown in FIG. 1(A) is used as the circuit 301.

[0068] The connection relationship of the shift register circuit shown in FIG. 8 will be described. The connection relationship of the circuit 301_i (where i is any one of 2 to N-1) will be described as an example. The circuit 301_i is connected to wiring 311 _i, wiring 311_i-1, wiring 311_i+1, one of wiring 312 and wiring 313, and wiring 314. Specifically, in the circuit 301_i, wiring 112 is connected to wiring 3 11_i, wiring 114 is connected to wiring 311_i-1, wiring 115 is connected to wiring 311_i+ 1, wiring 111 is connected to one of wiring 312 and wiring 313, and wiring 113 is​ It is connected to wiring 314. In circuit 301_i, when wiring 111 is continued with wiring 312, in circuits 301_i+1 and 301_i-1, wiring 111 may be connected to wiring 313. In circuit 301_1, although wiring 114 is connected to wiring 315, it is different from circuit 301_i. Also, in circuit 301_N, where wiring 115 is connected to the output terminal of a dummy circuit (not shown), the wiring to which the reset signal is input (not shown), or wiring 315 etc. is different from circuit 301_i.

[0069] Next, the operation of the shift register circuit shown in FIG. 8 will be described with reference to the timing chart shown in FIG. 9.

[0070] The operation of circuit 301_i will be described as an example. First, the potential of wiring 311_i-1 (denoted as potential V311_i-1) becomes V1. Then, circuit 301_i performs the operation in period A, and the potential of wiring 311_i (denoted as potential V311_i) becomes V2. After that, the potential of wiring 312 (denoted as potential V312) and the potential of wiring 313 (denoted as potential V313) are inverted. Then, circuit 301_i performs the operation in period B, and the potential of wiring 311_i becomes V1. After that, the potential of wiring 312 and the potential of wiring 313 are inverted, and the potential of wiring 311_i+1 (denoted as potential V311_i+1) becomes V1. Then, circuit 301_i performs the operation in period C, and the potential of wiring 311_i becomes V2. After that, circuit 301_i repeats the operation in period D and the operation in period E in order until the potential of wiring 311_i-1 becomes V1 again, and the potential of wiring 311_i remains at V2. Note that ​​​​​​​​​​​​, when the potential of wiring 315 (denoted as potential V315) becomes V1, circuit 301_1 performs operations during period A , which is different from that of circuit 301_i.

[0071] As described above, the potential of wiring 311_1 (denoted as potential V311_1) to the potential of wiring 311_N (denoted as potential V311_N) can be sequentially set to V1.

[0072] The output signal of the shift register circuit is supplied to wiring 311. A clock signal is input to wiring 312. A clock signal with a phase different from the clock signal input to wiring 312, or the inverted signal of the clock signal input to wiring 312, is input to wiring 313 . Voltage V2 is supplied to wiring 314. A start signal is input to wiring 315 .

[0073] Wiring 311 is a wiring for transmitting the output signal of the shift register circuit to circuits such as pixel circuits or demultiplexers, and has the function as a signal line or a gate signal line. Wiring 31 2 and wiring 313 are wirings for transmitting signals such as clock signals from an external circuit such as a controller to the shift register circuit of the present embodiment, and have the function as a signal line or a clock signal line . Wiring 314 is a wiring for supplying a power supply voltage such as voltage V2 from an external circuit such as a power supply circuit to the shift register circuit of the present embodiment, and has the function as a power supply line, a negative power supply line, or a ground line. Wiring 315 is a wiring for transmitting a start signal from an external circuit such as a controller to the shift register circuit of the present embodiment, and has the function as a signal line .

[0074] By providing a transistor in the shift register circuit shown in FIG. 8, it is possible to provide a function of switching the scanning direction. That is, it is possible to switch between driving the potentials of wirings 311_1 to 311_N to V1 in order and driving the potentials of wirings 311_N to 311_1 to V1 in order. FIG. 10 shows an example of a shift register circuit provided with a switch for switching the scanning direction. In FIG. 10, circuits 301_i - 1 to 301_i + 1 are exemplified. The shift register circuit shown in FIG. 10 includes, in addition to N circuits 301, N transistors 302 (denoted as transistors 302_1 to 302_N), N transistors 303 (denoted as transistors 303_1 to 303_N), N transistors 304 (denoted as transistors 304_1 to 304_N), and N transistors 305 (denoted as transistors 305_1 to 305_N). For example, the first terminal of transistor 302_i is connected to wiring 311_i - 1, the second terminal of transistor 302_i is connected to wiring 114 of circuit 301_i, and the gate of transistor 302_i is connected to wiring 315. The first terminal of transistor 303_i is connected to wiring 311_i - 1, the second terminal of transistor 303_i is connected to wiring 115 of circuit 301_i, and the gate of transistor 303_i is connected to wiring 316. The first terminal of transistor 304_i is connected to wiring 311_i + 1, the second terminal of transistor 304_i is connected to wiring 114 of circuit 301_i, and the gate of transistor 304_i is connected to wiring 316. The first terminal of transistor 305_i is connected to wiring 311_i + 1, and the second terminal of transistor 305_i is connected to the wiring of circuit 301_i The potential from wiring 311_1 to wiring 311_N is sequentially set to V1, and the potential from wiring 311_N to wiring 311_1 can be sequentially set to V1. FIG. 10 shows an example of a shift register circuit provided with a switch for switching the scanning direction. In FIG. 10, circuits 301_i - 1 to 301_i + 1 are exemplified. The shift register circuit shown in FIG. 10 includes, in addition to N circuits 301, N transistors 302 (denoted as transistors 302_1 to 302_N), N transistors 303 (denoted as transistors 303_1 to 303_N), N transistors 304 (denoted as transistors 304_1 to 304_N), and N transistors 305 (denoted as transistors 305_1 to 305_N). For example, the first terminal of transistor 302_i is connected to wiring 311_i - 1, the second terminal of transistor 302_i is connected to wiring 114 of circuit 301_i, and the gate of transistor 302_i is connected to wiring 315. The first terminal of transistor 303_i is connected to wiring 311_i - 1, the second terminal of transistor 303_i is connected to wiring 115 of circuit 301_i, and the gate of transistor 303_i is connected to wiring 316. The first terminal of transistor 304_i is connected to wiring 311_i + 1, the second terminal of transistor 304_i is connected to wiring 114 of circuit 301_i, and the gate of transistor 304_i is connected to wiring 316. The first terminal of transistor 305_i is connected to wiring 311_i + 1, the second terminal of transistor 305_i is connected to wiring 114 of circuit 301_i, and the gate of transistor 305_i is connected to wiring 316. The first terminal of transistor 305_i is connected to wiring 311_i + 1, and the second terminal of transistor 305_i is connected to the wiring of circuit 301_i It is connected to 115, and the gate of transistor 305_i is connected to wiring 315.

[0075] An example of the operation of the shift register circuit shown in FIG. 10 will be described. When driving such that the potentials of the wirings from wiring 311_1 to wiring 311_N are sequentially set to V1, an H signal may be input to wiring 315 and an L signal may be input to wiring 316. Therefore, transistor 302_i turns on, transistor 303_i turns off, transistor 304_i turns off, and transistor 305_i turns on. As a result, the signal output from wiring 311_i is supplied to wiring 114 of circuit 301_i + 1 and wiring 115 of circuit 301_i - 1. On the other hand, when driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_1 to wiring 311_N are sequentially set to V1, an H signal may be input to wiring 315 and an L signal may be input to wiring 316. Therefore, transistor 302_i turns on, transistor 303_i turns off, transistor 304_i turns off, and transistor 305_i turns on. As a result, the signal output from wiring 311_i is supplied to wiring 114 of circuit 301_i + 1 and wiring 115 of circuit 301_i - 1. On the other hand, when driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_1 to wiring 311_N are sequentially set to V1, an H signal may be input to wiring 315 and an L signal may be input to wiring 316. Therefore, transistor 302_i turns on, transistor 303_i turns off, transistor 304_i turns off, and transistor 305_i turns on. As a result, the signal output from wiring 311_i is supplied to wiring 114 of circuit 301_i + 1 and wiring 115 of circuit 301_i - 1. On the other hand, when driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_1 to wiring 311_N are sequentially set to V1, an H signal may be input to wiring 315 and an L signal may be input to wiring 316. Therefore, transistor 302_i turns on, transistor 303_i turns off, transistor 304_i turns off, and transistor 305_i turns on. As a result, the signal output from wiring 311_i is supplied to wiring 114 of circuit 301_i + 1 and wiring 115 of circuit 301_i - 1. On the other hand, when driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_1 to wiring 311_N are sequentially set to V1, an H signal may be input to wiring 315 and an L signal may be input to wiring 316. Therefore, transistor 302_i turns on, transistor 303_i turns off, transistor 304_i turns off, and transistor 305_i turns on. As a result, the signal output from wiring 311_i is supplied to wiring 114 of circuit 301_i + 1 and wiring 115 of circuit 301_i - 1. On the other hand, when driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_1 to wiring 311_N are sequentially set to V1, an H signal may be input to wiring 315 and an L signal may be input to wiring 316. Therefore, transistor 302_i turns on, transistor 303_i turns off, transistor 304_i turns off, and transistor 305_i turns on. As a result, the signal output from wiring 311_i is supplied to wiring 114 of circuit 301_i + 1 and wiring 115 of circuit 301_i - 1. On the other hand, when driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_1 to wiring 311_N are sequentially set to V1, an H signal may be input to wiring 315 and an L signal may be input to wiring 316. Therefore, transistor 302_i turns on, transistor 303_i turns off, transistor 304_i turns off, and transistor 305_i turns on. As a result, the signal output from wiring 311_i is supplied to wiring 114 of circuit 301_i + 1 and wiring 115 of circuit 301_i - 1. On the other hand, when driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1. When driving such that the potentials of the wirings from wiring 311_N to wiring 311_1 are sequentially set to V1, an L signal may be input to wiring 315 and an H signal may be input to wiring 316. Therefore, transistor 302_i turns off, transistor 303_i turns on, transistor 304_i turns on, and transistor 305_i turns off. As a result, the signal output from wiring 311_i is supplied to wiring 115 of circuit 301_i + 1 and wiring 114 of circuit 301_i - 1.

[0076] Note that the amplitude voltage of the signal input to one or both of wiring 315 and wiring 316 is preferably larger than the amplitude voltage of the signal input to at least one of the N wirings 311, wiring 312, and wiring 313. Note that the amplitude voltage of the signal input to one or both of wiring 315 and wiring 316 is preferably larger than the amplitude voltage of the signal input to at least one of the N wirings 311, wiring 312, and wiring 313. Note that the amplitude voltage of the signal input to one or both of wiring 315 and wiring 316 is preferably larger than the amplitude voltage of the signal input to at least one of the N wirings 311, wiring 312, and wiring 313.

[0077] (Embodiment 3) In this embodiment, an example of a transistor that constitutes the circuit described in Embodiment 1 or 2 will be described. Specifically, an example of the structure and manufacturing process of a transistor in which at least the channel region is formed of an oxide semiconductor will be described. Here, an example of the structure and manufacturing process of a transistor in which at least the channel region is formed of an oxide semiconductor will be described.

[0078] As the oxide semiconductor, a quaternary metal oxide In-Sn-Ga-Zn-O-based oxide semiconductor, a ternary metal oxide In-Ga-Zn-O-based oxide semiconductor, In-Sn-Zn -O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based oxide semiconductor, Al-Ga-Zn-O-based oxide semiconductor, or Sn-Al-Zn-O-based oxide semiconductor, or a binary metal oxide In-Zn-O-based oxide semiconductor, Sn-Zn- O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, S n-Mg-O-based oxide semiconductor, In-Mg-O-based oxide semiconductor, In-O-based oxide semiconductor , Sn-O-based oxide semiconductor, or Zn-O-based oxide semiconductor, etc. can be used. Further, an oxide semiconductor obtained by adding SiO2 to the above oxide semiconductor may also be used. Further, an oxide semiconductor obtained by adding SiO2 to the above oxide semiconductor may also be used. Further, an oxide semiconductor obtained by adding SiO2 to the above oxide semiconductor may also be used.

[0079] m Further, a substance represented by InMO3(ZnO) (m>0 and m is not a natural number) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. Among the oxide semiconductors having a structure represented by InMO3(ZnO) (m>0 and m is not a natural number), an oxide semiconductor having a structure containing Ga as M is referred to as the above-described In-Ga-Zn-O oxide semiconductor, and its thin film is In-Ga-Z m (m>0 and m is a natural number) Among the oxide semiconductors having a structure represented by InMO3(ZnO) (m>0 and m is not a natural number), an oxide semiconductor having a structure containing Ga as M is referred to as the above-described In-Ga-Zn-O oxide semiconductor, and its thin film is In-Ga-Z -O oxide semiconductor, and It shall also be referred to as the n-O mesentery. Further, the oxide semiconductor material represented by In-Ga-Zn-O as used in this specification is InGaO3(ZnO) (m > 0, and m is not a natural number) m (m > 0, and m is not a natural number), and the fact that m is not a natural number can be confirmed by using ICP-MS analysis or RBS analysis (m > 0, and m is not a natural number), and the fact that m is not a natural number can be confirmed by using ICP-MS analysis or RBS analysis .

[0080] One embodiment of a method for manufacturing a transistor in which a channel region is formed of an oxide semiconductor will be described with reference to FIG 11.

[0081] FIGS. 11(A) to (D) are diagrams showing an example of the cross-sectional structure of a transistor. The transistor 410 shown in FIGS. 11(A ) to (D) is one of the bottom gate structures called the channel etch type .

[0082] Further, FIGS. 11(A) to (D) show a transistor with a single gate structure, but if necessary , it can be a transistor with a multi-gate structure having a plurality of channel regions .

[0083] Hereinafter, the process of manufacturing the transistor 410 on the substrate 400 will be described with reference to FIGS. 11(A) to (D .

[0084] First, after forming a conductive film on the substrate 400 having an insulating surface, a gate electrode layer 411 is formed by a first photolithography process.

[0085] There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance to withstand subsequent heat treatment. For example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used It is cut. Also, when the temperature of the subsequent heat treatment is high, it is advisable to use a glass substrate with a strain point of 730 °C or higher. It is good to use.

[0086] An insulating film serving as an underlayer film may be provided between the substrate 400 and the gate electrode layer 411. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 400, and is composed of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed by a laminated structure. It has a function of preventing the diffusion of impurity elements from the substrate 400, and is formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed by a laminated structure.

[0087] Also, the material of the gate electrode layer 411 can be formed by using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these, either in a single layer or by lamination. It can be formed by using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these, either in a single layer or by lamination. It can be formed either in a single layer or by lamination using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these.

[0088] Next, a gate insulating layer 402 is formed on the gate electrode layer 411.

[0089] The gate insulating layer 402 can be formed by using the plasma CVD method, the sputtering method, etc., either in a single layer or by lamination, as a silicon oxide layer, a silicon nitride layer, a silicon nitride oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. Also, it is possible to use a High-k material such as hafnium oxide (HfOx) or tantalum oxide (TaOx) as the gate insulating layer. The film thickness of the gate insulating layer 402 is set to be 100 nm or more and 500 nm or less. In the case of lamination, for example, it is a lamination of a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. It can be formed either in a single layer or by lamination as a silicon oxide layer, a silicon nitride layer, a silicon nitride oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. Also, it is possible to use a High-k material such as hafnium oxide (HfOx) or tantalum oxide (TaOx) as the gate insulating layer. It can be formed either in a single layer or by lamination as a silicon oxide layer, a silicon nitride layer, a silicon nitride oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. Also, it is possible to use a High-k material such as hafnium oxide (HfOx) or tantalum oxide (TaOx) as the gate insulating layer. It is also possible to use a High-k material such as hafnium oxide (HfOx) or tantalum oxide (TaOx) as the gate insulating layer. It is also possible to use a High-k material such as hafnium oxide (HfOx) or tantalum oxide (TaOx) as the gate insulating layer. The film thickness of the gate insulating layer 402 is set to be 100 nm or more and 500 nm or less. In the case of lamination, for example, it is a lamination of a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. It is a lamination of a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. It is a lamination of a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer.

[0090] In this embodiment, the gate insulating layer 402 is formed by the plasma CVD method with a film thickness of 100 nm or more. Form the underlying silicon oxynitride layer.

[0091] Also, as the gate insulating layer 402, a silicon oxynitride film may be formed using a high-density plasma device. Here, the high-density plasma device refers to a device capable of achieving a plasma density of 1×10 11 / cm 3 or higher. For example, microwave power of 3 kW to 6 kW is applied to generate plasma for forming the insulating film. The insulating film obtained by the high-density plasma device can form a film with a constant thickness, so it has excellent step coverage. Also, the insulating film obtained by the high-density plasma device can precisely control the thickness of a thin film. The insulating film obtained by the high-density plasma device is significantly different from the insulating film obtained by a conventional parallel-plate PCVD device. When comparing the etching rates using the same etchant the insulating film obtained by the high-density plasma device is 10% or more, or 20% or more

[0092] slower than the insulating film obtained by the parallel-plate PCVD device, and the insulating film obtained by the high-density plasma device can be said to be a dense film. Note that in a later process, an oxide semiconductor (a highly purified oxide semiconductor) that is or is substantially i-type is extremely sensitive to interface states and interface charges. Therefore, the interface with the gate insulating layer is important. Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor is required to have high quality. Therefore, high-density plasma CVD using microwaves (2.45 GHz) is preferable because it can form a high-quality insulating film that is dense and has high breakdown voltage. When the highly purified oxide semiconductor and the high-quality gate insulating layer are in close contact, the interface states are reduced and the interface characteristics are improved.

[0093] Note that in a later process, an oxide semiconductor (a highly purified oxide semiconductor) that is or is substantially i-type is extremely sensitive to interface states and interface charges. Therefore, the interface with the gate insulating layer is important. Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor is required to have high quality. Therefore, high-density plasma CVD using microwaves (2.45 GHz) is preferable because it can form a high-quality insulating film that is dense and has high breakdown voltage. When the highly purified oxide semiconductor and the high-quality gate insulating layer are in close contact, the interface states are reduced and the interface characteristics are improved. is preferable because it can form a high-quality insulating film that is dense and has high breakdown voltage. When the highly purified oxide semiconductor and the high-quality gate insulating layer are in close contact, the interface states are reduced and the interface characteristics are improved. is preferable because it can form a high-quality insulating film that is dense and has high breakdown voltage. When the highly purified oxide semiconductor and the high-quality gate insulating layer are in close contact, the interface states are reduced and the interface characteristics are improved. semiconductor and the high-quality gate insulating layer are in close contact, the interface states are reduced and the interface characteristics are improved. This is because it can be made into such a thing. Needless to say, the film quality as the gate insulating layer is good. It is important to reduce the interface state density with the oxide semiconductor and form a good interface.

[0094] Next, an oxide semiconductor film 430 with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 402. The oxide semiconductor film 430 can use any oxide semiconductor film such as an In-Ga-Zn-O system or an In-Zn-O system. In this embodiment, as the oxide semiconductor film 430, an In-Ga-Zn-O system oxide semiconductor target is used to form a film by sputtering. The cross-sectional view at this stage corresponds to Fig. 11(A). Also, the oxide semiconductor film 430 can be formed by sputtering in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. Here, a metal oxide target containing In, Ga, and Zn (In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio]) is used, with the distance between the substrate and the target being 100 mm, the pressure being 0.2 Pa, a DC power supply of 0.5 kW, and in an atmosphere of argon and oxygen (argon:oxygen = 30 sccm:20 sccm, oxygen flow ratio 40%) to form a film. Note that when using a pulsed DC power supply, the powdery substances generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. The film thickness of the In-Ga-Zn-O system film is 5 nm or more and 200 nm or less. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O system metal oxide target is used to form an In-Ga-Zn-O system film with a film thickness of 20 nm by sputtering. Next, the oxide semiconductor film 430 is formed into island-shaped acids by the second photolithography process.

[0095] ​​​​​​​​​​​​​​ Process the oxide semiconductor layer.

[0096] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or higher and 750°C or lower, preferably 400°C or higher and less than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without exposing it to the atmosphere, re - mixing of water or hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer 431 ( see Fig. 11(B)).

[0097] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal An neal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high - pressure sodium lamps, high - pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using a high - temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the object to be processed during heat treatment are used.

[0098] For example, as the first heat treatment, the substrate is moved and inserted into an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then the substrate is moved and placed in an inert gas heated to a high temperature and heated for several minutes, and then the substrate is moved and placed in an inert gas heated to a high temperature.​​​ GRTA may be performed to output from. When GRTA is used, high-temperature heat treatment in a short time becomes possible.

[0099] In the atmosphere of the first heat treatment, it is preferable that nitrogen, or noble gases such as helium, neon, argon, etc., dry air do not contain water, hydrogen, etc. For example, the purity of nitrogen, or noble gases such as helium, neon, argon, etc., introduced into the heat treatment device is 6N (99 .9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0100] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 430 before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device, and the second photolithography process is performed. When forming an opening in the gate insulating layer 402, the process may be performed before or after performing a dehydration or dehydrogenation treatment on the oxide semiconductor film 430.

[0101] Also, the etching of the oxide semiconductor film 430 here is not limited to wet etching, and

[0102] dry etching may be used. As the etching gas for the oxide semiconductor film 430 used for dry etching, a gas containing chlorine

[0103] (for example, chlorine (Cl2), boron trichloride (BCl3), etc.) is preferable.

[0104] As the etching solution for the oxide semiconductor film 430 used for wet etching, phosphoric acid and acetic acid A solution mixed with nitric acid, aqueous ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2), etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0105] Next, a metal conductive film is formed on the gate insulating layer 402 and the oxide semiconductor layer 431. The metal conductive film may be formed by sputtering or vacuum evaporation. As the material of the metal conductive film, a element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti) , molybdenum (Mo), tungsten (W), neodymium (Nd), scandium (Sc) , an alloy containing the above-mentioned elements as components, or an alloy combining the above-mentioned elements, etc. can be mentioned. Also, a nitride film of the above-mentioned elements may be used. Also, manganese (Mn ), magnesium (Mg), zirconium (Zr), beryllium (Be), yttrium (Y) or a material selected from any one or more of them may be used. Also, the metal conductive film may be a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which a titanium film is laminated on an aluminum film and then a titanium film is laminated on the aluminum film, etc. can be mentioned.

[0106] When heat treatment is performed after the metal conductive film, it is preferable to give the metal conductive film heat resistance to withstand this heat treatment.

[0107] A resist mask is formed on the metal conductive film by the third photolithography process, and selective etching is performed to form the source electrode layer 415a and the drain electrode layer 415b, and then the resist Remove the stencil mask (see Fig. 11(C)).

[0108] In this embodiment, a titanium film is used as the metal conductive film, and an In -Ga-Zn-O-based oxide is used for the oxide semiconductor layer 431, and aqueous ammonia peroxide (ammonia , water, and a mixed solution of hydrogen peroxide) is used as the etchant.

[0109] In the third photolithography process, only a part of the oxide semiconductor layer 431 may be etched to form an oxide semiconductor layer having a groove portion (recess).

[0110] In addition, in order to reduce the number of photomasks and processes used in the photolithography process, the resist mask formed by a multi-tone mask, which is an exposure mask in which the transmitted light has a plurality of intensities, may be used for the etching process. The resist mask formed using the multi-tone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing ashing so that it can be used for a plurality of etching processes for processing into different patterns . Therefore, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask . Therefore, the number of exposure masks can be reduced , and the corresponding photolithography process can also be reduced, so that the process can be simplified.

[0111] Next, plasma treatment is performed using a gas such as nitrous oxide (N2O), nitrogen (N2), or argon (Ar). By this plasma treatment, adsorbed water or the like attached to the surface of the exposed oxide semiconductor layer is removed. Plasma treatment may also be performed using a mixed gas of oxygen and argon .

[0112] After performing plasma treatment, without exposing to the atmosphere, an oxide insulating layer 416 serving as a protective insulating film is formed in contact with a part of the oxide semiconductor layer 431. An oxide insulating layer 416 serving as a protective insulating film is formed.

[0113] The oxide insulating layer 416 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the oxide insulating layer 416, such as sputtering. When hydrogen is contained in the oxide insulating layer 416, the hydrogen penetrates into the oxide semiconductor layer, causing the back channel of the oxide semiconductor layer 431 to have a lower resistance (become N-type) and a parasitic channel to be formed. Therefore, it is important not to use hydrogen in the film formation method so that the oxide insulating layer 416 becomes a film that contains as little hydrogen as possible. When hydrogen is contained in the oxide insulating layer 416, the hydrogen penetrates into the oxide semiconductor layer, causing the back channel of the oxide semiconductor layer 431 to have a lower resistance (become N-type) and a parasitic channel to be formed. Therefore, it is important not to use hydrogen in the film formation method so that the oxide insulating layer 416 becomes a film that contains as little hydrogen as possible. In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the oxide insulating layer 416 by sputtering. The substrate temperature during film formation may be from room temperature to 300 °C or less, and is set to 100 °C in this embodiment. The film formation of the silicon oxide film by sputtering can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by sputtering in an atmosphere of silicon, nitrogen, and oxygen using a silicon target. In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the oxide insulating layer 416 by sputtering.

[0114] In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the oxide insulating layer 416 by sputtering. The substrate temperature during film formation may be from room temperature to 300 °C or less, and is set to 100 °C in this embodiment. The film formation of the silicon oxide film by sputtering can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by sputtering in an atmosphere of silicon, nitrogen, and oxygen using a silicon target. For example, a silicon oxide film can be formed by sputtering in an atmosphere of silicon, nitrogen, and oxygen using a silicon target. For example, a silicon oxide film can be formed by sputtering in an atmosphere of silicon, nitrogen, and oxygen using a silicon target.

[0115] Next, a second heat treatment (preferably from 200 °C to 400 °C, for example, from 250 °C to 350 °C) is performed in an inert gas atmosphere, a dry air atmosphere, or an oxygen gas atmosphere. For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When this is done, a part (channel region) of the oxide semiconductor layer is heated while being in contact with the oxide insulating layer 416. As a result, oxygen is supplied to a part (channel region) of the oxide semiconductor layer. By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer, a part (channel region) of the oxide semiconductor layer is selectively brought into an oxygen-excessive state. The transistor 410 is formed through the above steps.

[0116] By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer, a part (channel region) of the oxide semiconductor layer is selectively brought into an oxygen-excessive state. The transistor 410 is formed through the above steps. By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer, a part (channel region) of the oxide semiconductor layer is selectively brought into an oxygen-excessive state. The transistor 410 is formed through the above steps. By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer, a part (channel region) of the oxide semiconductor layer is selectively brought into an oxygen-excessive state. The transistor 410 is formed through the above steps.

[0117] Furthermore, a heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or longer and 30 hours or shorter. In this embodiment, a heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating a temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C and a temperature decrease from the heating temperature to room temperature a plurality of times. Furthermore, a heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or longer and 30 hours or shorter. In this embodiment, a heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating a temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C and a temperature decrease from the heating temperature to room temperature a plurality of times. Furthermore, a heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or longer and 30 hours or shorter. In this embodiment, a heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating a temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C and a temperature decrease from the heating temperature to room temperature a plurality of times. Furthermore, a heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or longer and 30 hours or shorter. In this embodiment, a heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating a temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C and a temperature decrease from the heating temperature to room temperature a plurality of times.

[0118] A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. In this embodiment, the protective insulating layer 403 is formed as the protective insulating layer using a silicon nitride film (see Fig. 11(D)). A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. In this embodiment, the protective insulating layer 403 is formed as the protective insulating layer using a silicon nitride film (see Fig. 11(D)). A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. In this embodiment, the protective insulating layer 403 is formed as the protective insulating layer using a silicon nitride film (see Fig. 11(D)). - A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. In this embodiment, the protective insulating layer 403 is formed as the protective insulating layer using a silicon nitride film (see Fig. 11(D)). A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. In this embodiment, the protective insulating layer 403 is formed as the protective insulating layer using a silicon nitride film (see Fig. 11(D)). A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. In this embodiment, the protective insulating layer 403 is formed as the protective insulating layer using a silicon nitride film (see Fig. 11(D)). A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. In this embodiment, the protective insulating layer 403 is formed as the protective insulating layer using a silicon nitride film (see Fig. 11(D)). A protective insulating layer may be further formed on the oxide insulating layer 416. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. In this embodiment, the protective insulating layer 403 is formed as the protective insulating layer using a silicon nitride film (see Fig. 11(D)).

[0119] In this embodiment, in the oxide semiconductor layer of the transistor 410, hydrogen, which is an n-type impurity, is removed from the oxide semiconductor so that the oxide semiconductor contains as few impurities as possible other than the main components. In this embodiment, in the oxide semiconductor layer of the transistor 410, hydrogen, which is an n-type impurity, is removed from the oxide semiconductor so that the oxide semiconductor contains as few impurities as possible other than the main components. It is made to be true (type I) or substantially true type by purification. That is, instead of adding impurities to make it type I, impurities such as hydrogen and water are removed as much as possible, resulting in highly purified type I (intrinsic semiconductor) or approaching it. By doing so, the Fermi level (Ef) can be made to the same level as the true Fermi level (Ei).

[0120] The bandgap (Eg) of the oxide semiconductor is 3.15 eV, and the electron affinity (χ) is said to be 4. 3 eV. The work function of titanium (Ti) constituting the source electrode layer and the drain electrode layer is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons.

[0121] For example, even for an element with a channel width W of 1×10 4 μm and a channel length of 3 μm, at room temperature, the off-current is 10 A or less, and the S value can be 0.1 V / deca -13 de (gate insulating layer film thickness 100 nm).

[0122] By highly purifying the oxide semiconductor so that impurities other than the main component are not contained as much as possible, the operation of the transistor 410 can be made good.

[0123] The above-mentioned oxide semiconductor intentionally excludes impurities such as hydrogen, moisture, hydroxyl groups or hydrides (also called hydrogen compounds) that cause fluctuations in electrical characteristics, and is the main component material of the oxide semiconductor that is reduced simultaneously by the impurity Since the oxide semiconductor is supplied with the above-mentioned oxide semiconductor, it is highly purified and electrically i-type (intrinsic).

[0124] Therefore, the less hydrogen there is in the oxide semiconductor, the better. There are very few carriers in semiconductors (close to zero), with a carrier density of 1×10 12 / c m 3 Less than 1 x 10 11 / cm 3 That is, the carrier of the oxide semiconductor layer is less than 1000 nm. The carrier density is close to zero. Since there are very few carriers in the oxide semiconductor layer, The reverse bias characteristic of the transistor can reduce the off-state current. The smaller the better. A transistor has a current value of 1 μm per 1 μm of channel width (w). 00 aA / μm or less, preferably 10 zA (zeptoamperes) or less, and more preferably 1 z Furthermore, since there is no pn junction and no hot carrier degradation, The electrical characteristics of the transistor are not affected.

[0125] In this way, hydrogen contained in the oxide semiconductor layer is thoroughly removed, resulting in a highly purified oxide semiconductor layer. A transistor that uses an oxide semiconductor for the channel region has an extremely small off-state current. In other words, when the transistor is in a non-conducting state, the oxide semiconductor layer can be regarded as an insulator. On the other hand, the oxide semiconductor layer can be used to control the conduction state of a transistor. In this case, it is expected that the current supply capacity will be higher than that of a semiconductor layer formed of amorphous silicon. can be done.

[0126] In addition, thin film transistors having low-temperature polysilicon are manufactured using oxide semiconductors. It is estimated that the off-current is about 10,000 times larger than that of a conventional transistor, and thus the design is carried out accordingly. Therefore, in a transistor having an oxide semiconductor, when the holding capacitance is equivalent (about 0.1 pF) compared to a thin film transistor including low-temperature polysilicon, the holding period of the voltage can be extended by about 10,000 times. As an example, when video display is performed at 60 frames per second, the holding period by one signal writing can be set to about 160 seconds, which is 10,000 times longer. Then, even with a small number of write operations of image signals, a still image can be displayed on the display unit. In the present embodiment, an example of a display device according to an aspect of the present invention will be described. FIG. 12(A) shows an example of a display device in which the shift register circuit of Embodiment 2 is used. The display device shown in FIG. 12(A) includes a timing controller 5360, a source driver circuit 5362, a gate driver circuit 5363_1, a gate driver circuit 5363_2, and a drive circuit 5361 having these circuits, and a pixel portion 5364. A plurality of source signal lines 5371 extend from the source driver circuit 5362 and are arranged in the pixel portion 5364, and a plurality of gate signal lines 5372 extend from the gate driver circuit 5363_1 and the gate driver circuit 5363_2 and are arranged. Pixels 5367 are arranged in a matrix in the intersection region of the plurality of source signal lines 5371 and the plurality of gate signal lines 5372. Note that the display device can include a lighting device and its control circuit or the like. In this case, the pixel 5367 preferably has a liquid crystal element. (Embodiment 4) In this embodiment, an example of a display device according to an aspect of the present invention will be described.

[0127] (Embodiment 4) In this embodiment, an example of a display device according to an aspect of the present invention will be described.

[0128] FIG. 12(A) shows an example of a display device in which the shift register circuit of Embodiment 2 is used. The display device shown in FIG. 12(A) includes a timing controller 5360, a source driver circuit 5362, a gate driver circuit 5363_1, a gate driver circuit 5363_2, and a drive circuit 5361 having these circuits, and a pixel portion 5364. A plurality of source signal lines 5371 extend from the source driver circuit 5362 and are arranged in the pixel portion 5364, and a plurality of gate signal lines 5372 extend from the gate driver circuit 5363_1 and the gate driver circuit 5363_2 and are arranged. Pixels 5367 are arranged in a matrix in the intersection region of the plurality of source signal lines 5371 and the plurality of gate signal lines 5372. Note that the display device can include a lighting device and its control circuit or the like. In this case, the pixel 5367 preferably has a liquid crystal element. FIG. 12(A) shows an example of a display device in which the shift register circuit of Embodiment 2 is used. The display device shown in FIG. 12(A) includes a timing controller 5360, a source driver circuit 5362, a gate driver circuit 5363_1, a gate driver circuit 5363_2, and a drive circuit 5361 having these circuits, and a pixel portion 5364. A plurality of source signal lines 5371 extend from the source driver circuit 5362 and are arranged in the pixel portion 5364, and a plurality of gate signal lines 5372 extend from the gate driver circuit 5363_1 and the gate driver circuit 5363_2 and are arranged. Pixels 5367 are arranged in a matrix in the intersection region of the plurality of source signal lines 5371 and the plurality of gate signal lines 5372. Note that the display device can include a lighting device and its control circuit or the like. In this case, the pixel 5367 preferably has a liquid crystal element. FIG. 12(A) shows an example of a display device in which the shift register circuit of Embodiment 2 is used. The display device shown in FIG. 12(A) includes a timing controller 5360, a source driver circuit 5362, a gate driver circuit 5363_1, a gate driver circuit 5363_2, and a drive circuit 5361 having these circuits, and a pixel portion 5364. A plurality of source signal lines 5371 extend from the source driver circuit 5362 and are arranged in the pixel portion 5364, and a plurality of gate signal lines 5372 extend from the gate driver circuit 5363_1 and the gate driver circuit 5363_2 and are arranged. Pixels 5367 are arranged in a matrix in the intersection region of the plurality of source signal lines 5371 and the plurality of gate signal lines 5372.

[0129] Note that the display device can include a lighting device and its control circuit or the like. In this case, the pixel 5367 preferably has a liquid crystal element. FIG. 12(A) shows an example of a display device in which the shift register circuit of Embodiment 2 is used.

[0130] Note that one of the gate driver circuits 5363_1 and 5363_2 can be omitted. It can be omitted.

[0131] The timing controller 5360 is a circuit that controls the operation of the drive circuit 5361 by supplying a control signal to the drive circuit 5361. For example, the timing controller 5360 supplies control signals such as a start signal SSP, a clock signal SCK, an inverted clock signal SCKB, a video signal DATA, and a latch signal LAT to the source driver circuit 5362. Also, the timing controller 5360 supplies control signals such as a start signal GSP, a clock signal GCK, and a clock signal GCKB to the gate driver circuits 5363_1 and 5363_2. It is a circuit having a function of controlling the operation of the drive circuit 5361. For example, the timing controller 5360 supplies control signals such as a start signal SSP, a clock signal SCK, an inverted clock signal SCKB, a video signal DATA, and a latch signal LAT to the source driver circuit 5362. Also, the timing controller 5360 supplies control signals such as a start signal GSP, a clock signal GCK, and a clock signal GCKB to the gate driver circuits 5363_1 and 5363_2. The timing controller 5360 supplies control signals such as a start signal SSP, a clock signal SCK, an inverted clock signal SCKB, a video signal DATA, and a latch signal LAT to the source driver circuit 5362. Also, the timing controller 5360 supplies control signals such as a start signal GSP, a clock signal GCK, and a clock signal GCKB to the gate driver circuits 5363_1 and 5363_2. The timing controller 5360 supplies control signals such as a start signal GSP, a clock signal GCK, and a clock signal GCKB to the gate driver circuits 5363_1 and 5363_2. The source driver circuit 5362 is a circuit having a function of outputting video signals to a plurality of source signal lines 5371, and can be called a drive circuit or a signal line drive circuit. The video signal is input to the pixel 5367, and the display element constituting the pixel 5367 becomes a gradation corresponding to the video signal. The source driver circuit 5362 is a circuit having a function of outputting video signals to a plurality of source signal lines 5371, and can be called a drive circuit or a signal line drive circuit. The video signal is input to the pixel 5367, and the display element constituting the pixel 5367 becomes a gradation corresponding to the video signal.

[0132] The source driver circuit 5362 is a circuit having a function of outputting video signals to a plurality of source signal lines 5371, and can be called a drive circuit or a signal line drive circuit. The video signal is input to the pixel 5367, and the display element constituting the pixel 5367 becomes a gradation corresponding to the video signal. The video signal is input to the pixel 5367, and the display element constituting the pixel 5367 becomes a gradation corresponding to the video signal. The video signal is input to the pixel 5367, and the display element constituting the pixel 5367 becomes a gradation corresponding to the video signal. The video signal is input to the pixel 5367, and the display element constituting the pixel 5367 becomes a gradation corresponding to the video signal.

[0133] The gate driver circuits 5363_1 and 5363_2 are circuits having a function of sequentially selecting the pixels 5367 of each row, and can be called a drive circuit or a scanning line drive circuit. The control of the timing for selecting the pixel 5367 is performed by the gate driver circuits 5363_1 and 5363_2 outputting a gate signal to the gate signal line 5372. The gate driver circuits 5363_1 and 5363_2 are circuits having a function of sequentially selecting the pixels 5367 of each row, and can be called a drive circuit or a scanning line drive circuit. The control of the timing for selecting the pixel 5367 is performed by the gate driver circuits 5363_1 and 5363_2 outputting a gate signal to the gate signal line 5372. The gate driver circuits 5363_1 and 5363_2 are circuits having a function of sequentially selecting the pixels 5367 of each row, and can be called a drive circuit or a scanning line drive circuit. The control of the timing for selecting the pixel 5367 is performed by the gate driver circuits 5363_1 and 5363_2 outputting a gate signal to the gate signal line 5372. The gate driver circuits 5363_1 and 5363_2 are circuits having a function of sequentially selecting the pixels 5367 of each row, and can be called a drive circuit or a scanning line drive circuit. The control of the timing for selecting the pixel 5367 is performed by the gate driver circuits 5363_1 and 5363_2 outputting a gate signal to the gate signal line 5372. The control of the timing for selecting the pixel 5367 is performed by the gate driver circuits 5363_1 and 5363_2 outputting a gate signal to the gate signal line 5372.

[0134] In the display device shown in FIG. 12(A), the gate driver circuits 5363_1 and gate driver circuit 5363_2 can be formed on the same substrate as the pixel section 5364. FIG. 12(B) shows an example in which the gate driver circuits 5363_1 and gate driver circuit 5363_2 are formed on the same substrate (shown as substrate 5380) as the pixel section 5364. Note that the substrate 5380 and the external circuit are connected via the terminal 5381.

[0135] In the display device shown in FIG. 12(A), a part of the source driver circuit 5362 (for example, a switch, a multiplexer, a shift register circuit, a decoder circuit, an inverter circuit, a buffer circuit, and / or a level shifter circuit, etc.) can be formed on the same substrate as the pixel section 5364. FIG. 12(C) shows an example in which the gate driver circuits 5363_1 and gate driver circuit 5363_2 and a part of the source driver circuit 5362 (shown as 5362a) are formed on the same substrate (shown as substrate 5380), and another part of the source driver circuit 5362 (shown as 5362b) is formed on a substrate different from the substrate 5380.

[0136] As a driving circuit or a part of the driving circuit of the display device, the shift register circuit described in Embodiment 2 can be used. In particular, since the driving circuit of the display device is composed of the transistors described in Embodiment 3, it is possible to improve the driving ability of the driving circuit. Therefore, the size of the display device can be increased. Or, the resolution of the display device can be improved. Or, since the layout area of the driving circuit can be reduced, the frame of the display device can be made smaller. ​​​​

[0137] (Embodiment 5) In this embodiment, an example of an electronic device will be described.

[0138] FIGS. 13(A) to 13(H) and FIGS. 14(A) to 14(D) are diagrams showing an electronic device. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), connection terminals 5006, a sensor 5007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation,

[0139] FIG. 13(A) is a mobile computer, and in addition to the above-described components, it can have a switch 5009, an infrared port 5010, etc. FIG. 13(B) is a portable type image playback device (for example, a DVD playback device) provided with a recording medium, and in addition to the above-described components, it can have a second display unit 5002, a recording medium reading unit 5011, etc. FIG. 13(C) is a goggle type display, and in addition to the above-described components, it can have a second display unit 5002, a support unit 5012, earphones 5013, etc. FIG. 13(D) is a portable game machine, and in addition to the above described components, it can have a recording medium reading unit 5011, etc. FIG. 13(E) is a p rojector, and in addition to the above-described components, it can have a light source 5033, a projection lens 5034, etc. FIG. 13(F) is a portable game machine, and in addition to the above-described components, it can have a second 5002, a recording medium reading unit 5011, etc. can be included. FIG. 13(G) is a television receiver, and in addition to the above-described components, it can have a tuner, an image processing unit, etc. FIG. 13(H) is a portable television receiver, and in addition to the above-described components, it can have a charger 5017 capable of signal transmission and reception, etc. FIG. 14(A) is a display, and in addition to the above-described components, it can have a support base 5018, etc. FIG. 14(B) is a camera, and in addition to the above-described components, it can have an external connection port 5019, a shutter button 5015, an imaging unit 5016, etc. FIG. 14(C) is a computer, and in addition to the above-described components, it can have a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 14(D) is a mobile phone, and in addition to the above-described components, it can have an antenna, a tuner for one-seg (one-segment partial reception service for mobile phones and mobile terminals), etc. FIGS. 13(A) to 13(H) and FIGS. 14(A) to 14(D) show electronic devices that can have various functions. For example, functions such as displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, a function of reading a program or data recorded on a recording medium and displaying it on the display unit, etc. can be included. Furthermore, in an electronic device having a plurality of display units, one display unit mainly displays image information, and another one ...

[0140] The electronic devices shown in FIGS. 13(A) to 13(H) and FIGS. 14(A) to 14(D) can have various functions. For example, functions such as displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, a function of reading a program or data recorded on a recording medium and displaying it on the display unit, etc. can be included. Furthermore, in an electronic device having a plurality of display units, one display unit mainly displays image information, and another one display unit can be used mainly for other purposes such as displaying a touch panel operation screen or a menu screen. ... display unit can be used mainly for other purposes such as displaying a touch panel operation screen or a menu screen. It can have a function of mainly displaying character information on one display unit, or a function of displaying a three-dimensional image by displaying an image considering parallax on a plurality of display units, etc. Furthermore, In an electronic device having an image receiving unit, it can have a function of taking a still image, a function of taking a moving image, a function of automatically or manually correcting the taken image, a function of storing the taken image in a recording medium (external or built-in to the camera), a function of displaying the taken image on a display unit, etc. Note that the functions that the electronic devices shown in FIGS. 13(A) to 13(H) and FIGS. 14(A) to 14(D) can have are not limited to these, and can have various functions.

[0141] FIG. 14(E) shows an example in which a display device is provided integrally with a building. FIG. 14(E) includes a housing 5022, a display unit 5023, a remote control device 5024 which is an operation unit, a speaker 50 25, etc. The display device is wall-mounted and integrated with the building, and can be installed without requiring a large installation space.

[0142] FIG. 14(F) shows another example in which a display device is provided integrally with a building inside the building. The display panel 5026 is attached integrally with the unit bus 5027, and a bather can view the display panel 5026.

[0143] In this embodiment, a wall and a unit bus are taken as examples of the building, but this embodiment is not limited to this, and the display device can be installed in various buildings.

[0144] Next, an example in which a display device is provided integrally with a moving body is shown.

[0145] FIG. 14(G) is a diagram showing an example in which the display device is provided in an automobile. The display panel 5 028 is attached to the vehicle body 5029 of the automobile, and can display the operation of the vehicle body or information input from inside or outside the vehicle body on demand. Note that it may have a navigation function.

[0146] FIG. 14(H) is a diagram showing an example in which the display device is provided integrally with a passenger airplane. FIG. 14(H) is a diagram showing the shape during use when the display panel 5031 is provided on the ceiling 5030 above the seat of the passenger airplane. The display panel 5031 is integrally attached to the ceiling 503 0 via the hinge portion 5032, and the passenger can view the display panel 5031 by the expansion and contraction of the hinge portion 5032. The display panel 5031 has a function of displaying information by being operated by the passenger.

[0147] In the present embodiment, examples of the moving body are the vehicle body of an automobile and the airframe of an airplane, but the present invention is not limited to these, and it can be installed on various things such as motorcycles, four-wheeled vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, etc.

[0148] It is preferable to mount the shift register circuit of Embodiment 2 on the electronic device shown in the present embodiment. In particular, it is preferable to mount the shift register circuit of Embodiment 2 as a circuit for driving the display unit of the electronic device. By mounting the shift register circuit of Embodiment 2 as a circuit for driving the display unit of the electronic device, the area of the drive circuit can be reduced, the display unit can be enlarged, and the resolution of the display unit can be improved.

Explanation of reference numerals

[0149] 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 121 Transistor 122 Transistor 123 Transistor 124 Transistor 125 Transistor 126 Capacitor element 200 Circuit 201 Capacitor element 202 Transistor 203 Transistor 301 Circuit 302 Transistor 303 Transistor 304 Transistor 305 Transistor 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 316 Wiring 400 Substrate 402 Gate insulating layer 403 Protection insulating layer 410 Transistor 411 Gate electrode layer 415a Source electrode layer 415b Drain electrode layer 416 Oxide insulating layer 430 Oxide semiconductor film 431 Oxide semiconductor layer 5000 Housing 5001 Display unit 5002 Second display unit 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphone 5015 Shutter button 5016 Image receiving unit 5017 Charger 5018 Support stand 5019 External connection port 5020 Pointing device 5021 Reader / writer 5022 Housing 5023 Display unit 5024 Remote control device 5025 Speaker 5026 Display panel 5027 Unit bus 5028 Display panel 5029 Vehicle body 5030 Ceiling 5031 Display panel 5032 Hinge part 5360 Timing controller 5361 Circuit 5362 Circuit 5362a Circuit 5362b Circuit 5363_1 Circuit 5363_2 Circuit 5364 Pixel part 5367 Pixel 5371 Source signal line 5372 Gate signal line 5380 Substrate 5381 Terminal

Claims

1. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of a source and a drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the third wiring; one of a source and a drain of the third transistor is always electrically connected to the first wiring; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; the gate of the fourth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; one of a source and a drain of the sixth transistor is always electrically connected to the first wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the sixth wiring; the other of the source and the drain of the seventh transistor is always electrically connected to the second wiring; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the sixth wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; a gate of the eighth transistor is always electrically connected to a gate of the second transistor; an on state or an off state of the third transistor is controlled according to a potential of a gate of the third transistor; an on state or an off state of the fourth transistor is controlled according to a potential of a gate of the fourth transistor; an on state or an off state of the sixth transistor is controlled according to a potential of a gate of the sixth transistor; when the fourth wiring is electrically connected to the gate of the first transistor through at least a channel region of the fourth transistor, a potential of the fourth wiring is applied to the gate of the first transistor; the first wiring has a function as a first gate signal line, the fifth wiring functions as a second gate signal line; Semiconductor device.

2. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of a source and a drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the third wiring; one of a source and a drain of the third transistor is always electrically connected to the first wiring; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; the gate of the fourth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; one of a source and a drain of the sixth transistor is always electrically connected to the first wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the sixth wiring; the other of the source and the drain of the seventh transistor is always electrically connected to the second wiring; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the sixth wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; a gate of the eighth transistor is always electrically connected to a gate of the second transistor; an on state or an off state of the third transistor is controlled according to a potential of a gate of the third transistor; an on state or an off state of the fourth transistor is controlled according to a potential of a gate of the fourth transistor; an on state or an off state of the sixth transistor is controlled according to a potential of a gate of the sixth transistor; when the fourth wiring is electrically connected to the gate of the first transistor through at least a channel region of the fourth transistor, a potential of the fourth wiring is applied to the gate of the first transistor; the first wiring has a function as a first gate signal line, A clock signal is input to the second wiring, A power supply voltage is input to the third wiring, the fifth wiring has a function as a second gate signal line, The sixth wiring has a function of outputting a first signal. Semiconductor device.

3. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of a source and a drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the third wiring; one of a source and a drain of the third transistor is always electrically connected to the first wiring; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; the gate of the fourth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; one of a source and a drain of the sixth transistor is always electrically connected to the first wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the sixth wiring; the other of the source and the drain of the seventh transistor is always electrically connected to the second wiring; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the sixth wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; a gate of the eighth transistor is always electrically connected to a gate of the second transistor; an on state or an off state of the third transistor is controlled according to a potential of a gate of the third transistor; an on state or an off state of the fourth transistor is controlled according to a potential of a gate of the fourth transistor; an on state or an off state of the sixth transistor is controlled according to a potential of a gate of the sixth transistor; when the fourth wiring is electrically connected to the gate of the first transistor through at least a channel region of the fourth transistor, a potential of the fourth wiring is applied to the gate of the first transistor; the first wiring has a function as a first gate signal line, the fifth wiring has a function as a second gate signal line, the third transistor has a smaller ratio of channel width to channel length than the fourth transistor; the seventh transistor has a smaller ratio of channel width to channel length than the first transistor; the eighth transistor has a smaller ratio of channel width to channel length than the second transistor; Semiconductor device.

4. a first transistor to an eighth transistor and a first wiring to a sixth wiring; one of a source and a drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of a source and a drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the third wiring; one of a source and a drain of the third transistor is always electrically connected to the first wiring; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fifth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the fifth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; the gate of the fourth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; one of a source and a drain of the sixth transistor is always electrically connected to the first wiring; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the sixth wiring; the other of the source and the drain of the seventh transistor is always electrically connected to the second wiring; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the sixth wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the third wiring; a gate of the eighth transistor is always electrically connected to a gate of the second transistor; an on state or an off state of the third transistor is controlled according to a potential of a gate of the third transistor; an on state or an off state of the fourth transistor is controlled according to a potential of a gate of the fourth transistor; an on state or an off state of the sixth transistor is controlled according to a potential of a gate of the sixth transistor; when the fourth wiring is electrically connected to the gate of the first transistor through at least a channel region of the fourth transistor, a potential of the fourth wiring is applied to the gate of the first transistor; the first wiring has a function as a first gate signal line, A clock signal is input to the second wiring, A power supply voltage is input to the third wiring, the fifth wiring has a function as a second gate signal line, the sixth wiring has a function of outputting a first signal; the third transistor has a smaller ratio of channel width to channel length than the fourth transistor; the seventh transistor has a smaller ratio of channel width to channel length than the first transistor; the eighth transistor has a smaller ratio of channel width to channel length than the second transistor; Semiconductor device.

5. In any one of claims 1 to 4, the first transistor to the eighth transistor have the same channel type; Semiconductor device.

Images