Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing an increase in contact resistance between semiconductor chips to be stuck or an open failure.SOLUTION: A semiconductor device according to an embodiment comprises a first insulation layer. A first pad is exposed on a surface of the first insulation layer. A second insulation layer is joined to the first insulation layer. A second pad is exposed on a surface of the second insulation layer and joined to the first pad. In a first plan view from a direction approximately vertical to the surface of the first insulation layer, a first conductive material and a first insulating material having a lower etching rate than the first conductive material are provided inside the first pad. The first insulating material is provided inside the first conductive material in an island shape.SELECTED DRAWING: Figure 3A

Description

Technical Field

[0001] This embodiment relates to a semiconductor device.

Background Art

[0002] In recent years, a technique has been developed for bonding a plurality of semiconductor chips to electrically connect pads. On the other hand, in polishing methods such as the CMP (Chemical Mechanical Polishing) method, dishing (depressions) may occur depending on the material to be polished. When the pads on the bonding surface are recessed due to dishing, when a plurality of semiconductor chips are bonded together, the contact resistance between the pads may increase or an open defect between the pads may occur.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device capable of suppressing an increase in contact resistance between bonded semiconductor chips or suppressing an open defect.

Means for Solving the Problems

[0005] The semiconductor device according to this embodiment includes a first insulating layer. The first pad is exposed on the surface of the first insulating layer. The second insulating layer is bonded to the first insulating layer. The second pad is exposed on the surface of the second insulating layer and is bonded to the first pad. In a first plan view from a direction substantially perpendicular to the surface of the first insulating layer, inside the first pad, there are a first conductive material and a first insulating material having an etching rate lower than that of the first conductive material. The first insulating material is provided in an island shape inside the first conductive material.

Brief Description of the Drawings

[0006]

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Best Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. In the following embodiments, the vertical direction of the semiconductor chip may be different from the vertical direction according to the gravitational acceleration. The drawings are schematic or conceptual, and the ratios of the respective parts are not necessarily the same as those in reality. In the specification and the drawings, the same reference numerals are given to the same elements as those described above with respect to the already presented drawings, and detailed descriptions are appropriately omitted.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor package 1 according to the first embodiment. The semiconductor package 1 of this embodiment is an example of a package of a semiconductor memory. However, this embodiment can also be applied to other semiconductor devices.

[0009] The semiconductor package 1 includes a wiring substrate 10, metal bumps 20, solder balls 70, a controller chip 30, a memory chip stack 40 including a plurality of stacked memory chips, electrodes 50 provided so as to penetrate each memory chip, and a sealing resin 60.

[0010] The wiring board 10 includes an insulator 11, a wiring layer 12, and a solder resist layer 13. For the insulator 11, an insulating material such as a glass epoxy resin is used, for example. The wiring layer 12 is a conductor provided on the front and back surfaces of the insulator 11. For the wiring layer 12, a low-resistance metal material such as copper is used, for example. The solder resist layer 13 is provided on the wiring layer 12.

[0011] The metal bump 20 is provided on the front side of the wiring board 10 and is electrically connected to a part of the wiring layer 12. The solder ball 70 is provided on the back side of the wiring board 10 and is electrically connected to a part of the wiring layer 12.

[0012] The controller chip 30 is provided above the front surface of the wiring board 10. The controller chip 30 is provided to control a plurality of memory chips.

[0013] The memory chip stack 40 is stacked on the controller chip 30. The plurality of memory chips are semiconductor chips mounting, for example, NAND type memory cells. Each memory chip and the controller chip 30 are electrically connected via the electrode 50. The electrode 50 transmits power supply power, ground voltage, control signals, data, or the like. For the electrode 50, a conductive material such as tungsten, nickel, copper, gold, aluminum, polysilicon, or the like is used.

[0014] The encapsulating resin 60 is provided on the front surface of the wiring board 10 and encapsulates the controller chip 30 and the memory chip stack 40.

[0015] FIG. 2 is a cross-sectional view showing a configuration example of a part of the semiconductor package 1 according to the first embodiment. In FIG. 2, cross-sections of two stacked memory chips 40_1 and 40_2 are shown. The memory chip 40_1 and the memory chip 40_2 are joined at the joining surface B_chip.

[0016] Memory chip 40_1 includes an array chip CH_A1 containing a memory cell array MCA1 and a circuit chip CH_C1 containing a CMOS (Complementary Metal Oxide Semiconductor) circuit CMOS1. Memory chip 40_2 includes an array chip CH_A2 containing a memory cell array MCA2 and a circuit chip CH_C2 containing a CMOS circuit CMOS2.

[0017] (Memory chip 40_1) Array chip CH_A1 includes a memory cell array MCA1 covered with an interlayer insulating film ILD1_1. Memory cell array MCA1 has a plurality of word lines WL1 stacked in the Z direction and insulated from each other, and a plurality of columnar bodies CL1 extending so as to penetrate the stacked plurality of word lines WL1 in the stacking direction (Z direction). Memory cells MC1 are provided corresponding to the intersections of word lines WL1 and columnar bodies CL1. One ends of the plurality of columnar bodies CL1 are commonly connected to a source line SL1. The other ends of the plurality of columnar bodies CL1 are connected to any one of bit lines BL1 extending in the Y direction.

[0018] Memory cell array MCA1 is provided in an array region R_Arr. Word lines WL1 extend in the X direction up to a terrace region R_Trr, and in the terrace region R_Trr, they are formed in a stepped shape. Contact plugs CC1 are connected to the step surfaces of each of the word lines WL1 formed in a stepped shape. Contact plugs CC1 are electrically connected to pads P1_1a provided in the array region R_Arr and word lines WL1 via a wiring layer W1_1. Pad P1_1a is an electrode pad exposed from the surface of the interlayer insulating film ILD1_1 and provided on the bonding surface B_mc1 of the array chip CH_A1. Wiring layer W1_1 electrically connects between memory cell array MCA1 and pad P1_1a via contact plugs CC1.

[0019] A peripheral region R_Pri is provided around the array region R_Arr and the terrace region R_Trr. The peripheral region R_Pri may be provided at various positions, including not only the peripheral part of the memory chip but also the central part of the memory chip. In the peripheral region R_Pri, a contact plug Cpri1 is provided so as to penetrate the interlayer insulating film ILD1_1 of the array chip CH_A1 in the Z direction. One end of the contact plug Cpri1 is electrically connected via a wiring layer W1_1 to a pad P1_1a provided on the bonding surface B_mc1 of the peripheral region R_Pri. The other end of the contact plug Cpri1 is electrically connected to a pad P1_1b provided on the surface opposite to the bonding surface B_mc1 of the array chip CH_A1.

[0020] The circuit chip CH_C1 is provided below (-Z direction) the array chip CH_A1 and includes a CMOS circuit CMOS1 covered with an interlayer insulating film ILD1_2. The CMOS circuit CMOS1 is provided on a semiconductor layer SUB1 and is a circuit including a P-type MOSFET (MOS Field Effect Transistor) and an N-type MOSFET. The CMOS circuit CMOS1 may include other semiconductor elements (for example, a resistance element, a capacitance element). The CMOS circuit CMOS1 is covered with the interlayer insulating film ILD1_2. An interlayer wiring layer W1_2 is provided in the interlayer insulating film ILD1_2. The multilayer wiring layer W1 electrically connects between the CMOS circuit CMOS1 and the pad P1_2a. The pad P1_2a is an electrode pad exposed from the surface of the interlayer insulating film ILD1_2 and provided on the bonding surface B_mc1 of the circuit chip CH_C1. The pad P1_2a may be provided in any of the array region R_Arr, the terrace region R_Trr, and the peripheral region R_Pri.

[0021] A through electrode TSV1 is provided in the peripheral region R_Pri of the circuit chip CH_C1. The through electrode TSV1 is a part of the electrode 50. The through electrode TSV1 penetrates the semiconductor layer SUB1 in the Z direction and is electrically connected between the pad P1_2a and the pad P1_2b. The pad P1_2b is an electrode pad provided at the end of the through electrode TSV1 on the side opposite to the bonding surface B_mc1.

[0022] The array chip CH_A1 and the circuit chip CH_C1 are bonded together at the bonding surface B_mc1. At the bonding surface B_mc1, the interlayer insulating films ILD1_1 and ILD1_2 are bonded, and the pads P1_1a and P1_2a are bonded. As a result, the CMOS circuit CMOS1 of the circuit chip CH_C1 is electrically connected to the memory cell array MCA1 via the multilayer wiring layer W1_2, the pads P1_2a, P1_1a, and the contact plug CC1. Consequently, the CMOS circuit CMOS1 can control the memory cell array MCA1. Also, the through electrode TSV1 is electrically connected to the contact plug Cpri1 via the pads P1_2a, P1_1a, and the wiring layer W1_1. The through electrode TSV1 is provided, for example, to enable the common transmission of power supply power or ground potential between chips.

[0023] (Memory chip 40_2) The array chip CH_A2 includes a memory cell array MCA2 covered with an interlayer insulating film ILD2_1. The memory cell array MCA2 has a plurality of word lines WL2 stacked in the Z direction and insulated from each other, and a plurality of columnar bodies CL2 extending so as to penetrate the stacked plurality of word lines WL2 in the stacking direction (Z direction). Memory cells MC2 are provided corresponding to the intersections of the word lines WL2 and the columnar bodies CL2. One ends of the plurality of columnar bodies CL2 are commonly connected to the source line SL2. The other ends of the plurality of columnar bodies CL2 are connected to any one of the bit lines BL2 extending in the Y direction.

[0024] The memory cell array MCA2 is provided in the array region R_Arr. The word line WL2 extends in the X direction up to the terrace region R_Trr, and in the terrace region R_Trr, it is formed in a stepped shape. Contact plugs CC2 are connected to the step surfaces of each of the word lines WL2 formed in a stepped shape. The contact plugs CC2 are electrically connected to the pads P2_1a provided in the array region R_Arr and the word lines WL2 via a wiring layer W2_1, respectively. The pads P2_1a are exposed on the surface of the interlayer insulating film ILD2_1 and are electrode pads provided on the bonding surface B_mc2 of the array chip CH_A2. The wiring layer W2_1 electrically connects between the memory cell array MCA2 and the pads P2_1a via the contact plugs CC2.

[0025] A peripheral region R_Pri is provided around the array region R_Arr and the terrace region R_Trr. In the peripheral region R_Pri, contact plugs Cpri2 are provided so as to penetrate the interlayer insulating film ILD2_1 of the array chip CH_A2 in the Z direction. One end of the contact plug Cpri2 is electrically connected to the pad P2_1a provided on the bonding surface B_mc2 of the peripheral region R_Pri via a wiring layer W2_1. The other end of the contact plug Cpri2 is electrically connected to a pad P2_1b provided on the surface of the array chip CH_A2 opposite to the bonding surface B_mc2.

[0026] The circuit chip CH_C2 is provided below (-Z direction) the array chip CH_A2 and includes a CMOS circuit CMOS2 covered with an interlayer insulating film ILD2_2. The CMOS circuit CMOS2 is provided on a semiconductor layer SUB2 and is a circuit including a P-type MOSFET and an N-type MOSFET. The CMOS circuit CMOS2 may include other semiconductor elements (e.g., a resistor element, a capacitor element). The CMOS circuit CMOS2 is covered with the interlayer insulating film ILD2_2. A multilayer wiring layer W2_2 is provided in the interlayer insulating film ILD2_2. The multilayer wiring layer W2_2 electrically connects between the CMOS circuit CMOS2 and the pad P2_2a. The pad P2_2a is exposed on the surface of the interlayer insulating film ILD2_2 and is an electrode pad provided on the bonding surface B_mc2 of the circuit chip CH_C2. The pad P2_2a may be provided in any of the array region R_Arr, the terrace region R_Trr, and the peripheral region R_Pri.

[0027] Through electrodes TSV2 are provided in the peripheral region R_Pri of the circuit chip CH_C2. The through electrodes TSV2 penetrate the semiconductor layer SUB2 in the Z direction and are electrically connected between the pad P2_2a and the pad P2_2b. The pad P2_2b is an electrode pad provided at the end of the through electrode TSV2 on the side opposite to the bonding surface B_mc2.

[0028] The array chip CH_A2 and the circuit chip CH_C2 are bonded at the bonding surface B_mc2. At the bonding surface B_mc2, the interlayer insulating films ILD2_1 and ILD2_2 are bonded, and the pads P2_1a and P2_2a are bonded. As a result, the CMOS circuit CMOS2 of the circuit chip CH_C2 is electrically connected to the memory cell array MCA2 via the multilayer wiring layer W2_2, the pads P2_2a, P2_1a, and the contact plug CC2. As a result, the CMOS circuit CMOS2 can control the memory cell array MCA2. Also, the through electrode TSV2 is electrically connected to the contact plug Cpri2 via the pads P2_2a, P2_1a, and the wiring layer W2_1. The through electrode TSV2 is also provided, for example, to enable the common transmission of power supply power or ground potential between chips.

[0029] (Bonding between memory chips 40_1 and 40_2) The memory chip 40_1 and the memory chip 40_2 are bonded at the bonding surface B_chip. At the bonding surface B_chip, the pad P1_1b and the pad P2_1b are bonded. The memory chips 40_1 and 40_2 are electrically connected via the pads P1_1b and P2_1b bonded to each other. As a result, the through electrodes TSV1, TSV2 and the contact plugs Cpri1, Cpri2 are electrically connected, and for example, power supply power or ground potential can be commonly transmitted between the plurality of stacked memory chips 40_1 and 40_2.

[0030] (Configuration of pad P1_1a, etc.) FIG. 3A is a plan view showing a configuration example of the pad P1_1a. In FIG. 3A, in a first plan view (plan view seen from the Z direction) from a direction substantially perpendicular to the surface of the interlayer insulating film ILD1_1 (bonding surface B_mc1) of the array chip CH_A1, the pad P1_1a is exposed from the surface of the interlayer insulating film ILD1_1. In the above plan view, the pad P1_1a is surrounded by the interlayer insulating film ILD1_1 around it, and has, for example, a substantially octagonal shape. The planar shape of the pad P1_1a may be a polygon other than an octagon, a substantially circular shape, or a substantially elliptical shape.

[0031] Inside the pad P1_1a, a barrier metal film 101_1a, a conductive material 102_1a, and an insulating material 103_1a are provided.

[0032] The barrier metal film 101_1a is provided at the outer edge of the pad P1_1a and is provided between the interlayer insulating film ILD1_1 or the insulating material 103_1a and the conductive material 102_1a. For the barrier metal film 101_1a, a conductive material such as a laminated film of a titanium film and a titanium nitride film is used, for example.

[0033] The conductive material 102_1a is provided inside the pad P1_1a surrounded by the barrier metal film 101_1a. For the conductive material 102_1a, a conductive material such as copper or tungsten is used, for example. The insulating material 103_1a is provided in an island shape inside the conductive material 102_1a, and its periphery is surrounded by the conductive material 102_1a.

[0034] In the above plan view, the plurality of insulating materials 103_1a each extend in the Y direction on the surface of the conductive material 102_1a and have an elongated shape. Also, in the above plan view, the plurality of insulating materials 103_1a are arranged in a stripe shape or a line and space shape in the X direction orthogonal to the Y direction on the surface of the conductive material 102_1a. In other words, the plurality of insulating materials 103_1a are provided in a slit shape or a strip shape extending substantially in parallel. The plurality of insulating materials 103_1a are provided inside the pad P1_1a in the above plan view and do not reach the barrier metal film 101_1a and the interlayer insulating film ILD1_1. Incidentally, the insulating material 103_1a may be connected to the interlayer insulating film ILD1_1 below the pad P1_1a. The same material as the interlayer insulating film ILD1_1 (for example, a silicon oxide film) can be used for the insulating material 103_1a.

[0035] Also, in the above plan view, the area of the insulating material 103_1a of the pad P1_1a is smaller than the area of the conductive material 102_1a. By making the area of the conductive material 102_1a relatively large, the contact area between the conductive material 102_2a of the pad P1_2a of the circuit chip CH_C1 becomes large, and the contact resistance between the pad P1_1a and the pad P1_2a can be kept low.

[0036] Here, the insulating material 103_1a is a material (for example, a material such as an oxide film such as a silicon oxide film, a nitride film such as a silicon nitride film, a carbide film such as a silicon carbide film, or a composite material thereof) having a lower etching rate in the CMP process than the material of the conductive material 102_1a (for example, a metal material such as copper or tungsten). For example, the insulating material 103_1a may be formed of a physically hard material that is more difficult to polish than the material of the conductive material 102_1a. Alternatively, the insulating material 103_1a may be formed of a material that is more difficult to be chemically etched by an abrasive (slurry) than the material of the conductive material 102_1a. Therefore, in the CMP process, the insulating material 103_1a serves as a support inside the conductive material 102_1a, and it is possible to mitigate the thinning of the film thickness at the central portion of the conductive material 102_1a and the formation of a depression (dishing).

[0037] The width Wp1_1a of the pad P1_1a in the X direction or the Y direction is, for example, about 1 μm. The width W103_1a of the insulating material 103_1a is, for example, about several 10 nm.

[0038] The wiring layer W1_1 shown by the dashed line is provided under the pad P1_1a. The wiring layer W1_1 is electrically connected to the pad P1_1a via the via contact V1_1. In this embodiment, nine via contacts V1_1 are provided between the pad P1_1a and the wiring layer W1_1. However, the number of via contacts V1_1 is not limited to nine and may be arbitrary. Also, FIG. 3C is a plan view showing an example of the configuration of the wiring layer W1_1. The wiring layer W1_1 is formed in a cross shape within a substantially square frame below the pad P1_1a in the above plan view. Nine via contacts V1_1 are provided on the wiring layer W1_1. Also, the wiring layer W1_1 may not be in a cross shape but may be in a solid shape.

[0039] FIG. 3B is a cross-sectional view showing a configuration example of the pad P1_1a. FIG. 3B shows a cross section along the line B-B of FIG. 3A. The pad P1_1a is embedded in the interlayer insulating film ILD1_1 and is exposed on the surface of the interlayer insulating film ILD1_1. The conductive material 102_1a is electrically connected to the wiring layer W1_1 provided thereunder via the via contact V1_1. The insulating material 103_1a may be a part of the interlayer insulating film ILD1_1 and may be the same material. Incidentally, the height of the conductive material 102_1a is, for example, about 1 μm.

[0040] Thus, according to this embodiment, the pad P1_1a includes the insulating material 103_1a provided in an island shape inside the conductive material 102_1a in a plan view from a direction substantially perpendicular to the bonding surface B_mc1. The insulating material 103_1a is formed of a material having a lower etching rate than the conductive material 102_1a. Therefore, in the CMP process of polishing the interlayer insulating film ILD1_1 and the conductive material 102_1a, the insulating material 103_1a serves as a support within the conductive material 102_1a, and the dishing of the conductive material 102_1a can be alleviated.

[0041] When the insulating material 103_1a is not provided, the conductive material 102_1a is polished over a relatively large area. In this case, inside the conductive material 102_1a, significant dishing occurs and it becomes concave.

[0042] In contrast, according to the present embodiment, the insulating material 103_1a divides the conductive material 102_1a into a relatively small area and serves as a support inside the conductive material 102_1a. As a result, dishing is suppressed inside the conductive material 102_1a.

[0043] The insulating material 103_1a is preferably arranged substantially evenly inside the conductive material 102_1a. Thereby, it is possible to suppress the occurrence of significant local dishing in the conductive material 102_1a.

[0044] Although FIGS. 3A and 3B illustrate the pad P1_1a, the pads P1_2a, P2_1a, P2_2a, P1_2b, and P2_1b may be configured in the same manner. As a result, dishing is also suppressed in the CMP process for the pads P1_2a, P2_1a, P2_2a, P1_2b, and P2_1b other than the pad P1_1a. Note that the configuration of the pads P1_2a, P2_1a, P2_2a, P1_2b, and P2_1b can be easily understood by referring to FIGS. 3A and 3B, and thus a detailed description thereof is omitted.

[0045] FIG. 4 is a cross-sectional view showing a configuration example of a portion of the bonding surface B_mc1. The pad P1_1a on the array chip CH_A1 side and the pad P1_2a on the circuit chip CH_C1 side are bonded at the bonding surface B_mc1.

[0046] Both the pad P1_1a and the pad P1_2a have the configuration shown in FIGS. 3A and 3B. Therefore, similar to the pad P1_1a shown in FIG. 3A, inside the pad P1_2a, a barrier metal film 101_2a, a conductive material 102_2a, and an insulating material 103_2a are provided in a plan view from a direction substantially perpendicular to the surface of the interlayer insulating film ILD1_2.

[0047] Further, in the following description of the pad P1_2a, the pad P1_1a, the interlayer insulating film ILD1_1, the barrier metal film 101_1a, the conductive material 102_1a, and the insulating material 103_1a in FIGS. 3A and 3B shall be read as the pad P1_2a, the interlayer insulating film ILD1_2, the barrier metal film 101_2a, the conductive material 102_2a, and the insulating material 103_2a, respectively.

[0048] The barrier metal film 101_2a is provided at the outer edge of the pad P1_2a and is provided between the interlayer insulating film ILD1_2 or the insulating material 103_2a and the conductive material 102_2a. For the barrier metal film 101_2a, a conductive material such as a laminated film of a titanium film and a titanium nitride film is used, for example.

[0049] The conductive material 102_2a is provided inside the pad P1_2a surrounded by the barrier metal film 101_2a. For the conductive material 102_2a, a conductive material such as copper or tungsten is used, for example. The insulating material 103_2a is provided in an island shape inside the conductive material 102_2a, and its periphery is surrounded by the conductive material 102_2a.

[0050] In the above plan view, the plurality of insulating materials 103_2a each extend in the Y direction on the surface of the conductive material 102_2a and have an elongated shape. Also, in the above plan view, the plurality of insulating materials 103_2a are arranged in a stripe shape or a line-and-space shape in the X direction orthogonal to the Y direction on the surface of the conductive material 102_2a. In other words, the plurality of insulating materials 103_2a are provided in a slit shape or a strip shape extending substantially in parallel. The plurality of insulating materials 103_2a are provided inside the pad P1_2a in the above plan view and do not reach the barrier metal film 101_2a and the interlayer insulating film ILD1_2. Note that the same material as the interlayer insulating film ILD1_2 (for example, a silicon oxide film) can be used for the insulating material 103_2a.

[0051] Here, the insulating material 103_2a is formed of a material with an etching rate lower than that of the conductive material 102_2a (for example, a metal material such as copper or tungsten) (for example, a silicon oxide film). For example, the insulating material 103_2a may be formed of a physically hard material that is more difficult to polish than the material of the conductive material 102_2a. Alternatively, the insulating material 103_2a may be formed of a material that is more difficult to chemically etch by an abrasive (slurry) than the material of the conductive material 102_2a. Therefore, in the CMP process, the insulating material 103_2a serves as a support inside the conductive material 102_2a, and the dishing of the conductive material 102_2a can be alleviated.

[0052] The width Wp1_2a of the pad P1_2a in the X direction or the Y direction is, for example, about 1 μm. The width W103_2a of the insulating material 103_2a is, for example, about several 10 nm.

[0053] The pad P1_2a is embedded in the interlayer insulating film ILD1_2 and is exposed on the surface of the interlayer insulating film ILD1_2. The conductive material 102_2a is electrically connected to the wiring layer W1_2 provided thereunder. The insulating material 103_2a may be a part of the interlayer insulating film ILD1_2 and may be the same material. Incidentally, the height of the conductive material 102_2a is, for example, about 1 μm.

[0054] Thus, pads P1_1a and P1_2a have substantially the same configuration. The pads P1_1a and P1_2a are joined at the joint surface B_mc1 between the pad P1_1a and the pad P1_2a such that the extending direction of the insulating material 103_1a and the extending direction of the insulating material 103_2a are substantially in the same direction (e.g., the Y direction). Thereby, when the array chip CH_A1 and the circuit chip CH_C1 are bonded together, as shown in FIG. 4, the conductive materials 102_1a and 102_2a are joined so as to be substantially opposed and coincide with each other at the joint surface B_mc1. At this time, the pads P1_1a and P1_2a are hardly dished, and the conductive materials 102_1a and 102_2a are hardly recessed at the joint surface B_mc1. That is, the conductive materials 102_1a and 102_2a are provided substantially flush with each other at the joint surface B_mc1. Therefore, although the insulating materials 103_1a and 103_2a are provided inside the respective conductive materials 102_1a and 102_2a, the conductive materials 102_1a and 102_2a can be joined with sufficiently low resistance at the joint surface B_mc1.

[0055] If the insulating materials 103_1a and 103_2a are not provided, although the areas of the conductive materials 102_1a and 102_2a at the joint surface B_mc1 become wider accordingly, the conductive materials 102_1a and 102_2a are likely to have poor bonding due to dishing in the CMP process. Therefore, there is a possibility that the contact resistance between the conductive material 102_1a and the conductive material 102_2a becomes high.

[0056] On the other hand, according to the present embodiment, since the insulating materials 103_1a and 103_2a are provided, the areas of the conductive materials 102_1a and 102_2a at the joint surface B_mc1 become smaller accordingly. However, the dishing of the conductive materials 102_1a and 102_2a is suppressed, and the conductive materials 102_1a and 102_2a are hardly recessed at the joint surface B_mc1. Therefore, the contact resistance between the conductive material 102_1a and the conductive material 102_2a can be made low and stable.

[0057] Next, a method for manufacturing the pads P1_1a and P1_2a according to the first embodiment will be described.

[0058] Figs. 5 to 11 are cross-sectional views showing an example of a method for manufacturing the pad P1_1a according to the first embodiment. Note that since the method for manufacturing the pad P1_2a is the same as that for manufacturing the pad P1_1a, a detailed description thereof will be omitted.

[0059] First, a memory cell array MCA1, an interlayer insulating film ILD1_1, etc. are formed on a substrate (for example, a silicon substrate) of the array chip CH_A1. Next, a wiring layer W1_1 is formed on the interlayer insulating film ILD1_1 of the array chip CH_A1. Next, an insulating film is further deposited on the wiring layer W1_1 and the interlayer insulating film ILD1_1. The insulating film may be made of the same material as the interlayer insulating film ILD1_1 (for example, a silicon oxide film). Therefore, the insulating film on the wiring layer W1_1 is also referred to as the interlayer insulating film ILD1_1. Thereby, the structure shown in Fig. 5 is obtained.

[0060] Next, the interlayer insulating film ILD1_1 on the wiring layer W1_1 is processed using lithography technology and etching technology. Thereby, as shown in Fig. 6, the interlayer insulating film ILD1_1 on the wiring layer W1_1 is processed into a pattern of via contact V1_1.

[0061] Next, as shown in Fig. 7, a barrier metal film 201_1a and a conductive material 202_1a are deposited on the interlayer insulating film ILD1_1 and the wiring layer W1_1. For the barrier metal film 201_1a, for example, a laminated film of a titanium film and a titanium nitride film is used. For the conductive material 202_1a, for example, a conductive material such as copper or tungsten is used.

[0062] Next, using the CMP method, the barrier metal film 201_1a and the conductive material 202_1a are polished until the interlayer insulating film ILD1_1 is exposed. Thereby, as shown in Fig. 8, a via contact V1_1 composed of the barrier metal film 201_1a and the conductive material 202_1a is formed.

[0063] Next, an insulating film is further deposited on the via contact V1_1. The insulating film may be made of the same material as the interlayer insulating film ILD1_1 (for example, a silicon oxide film). Therefore, the insulating film on the via contact V1_1 is also referred to as the interlayer insulating film ILD1_1. Next, using lithography technology and etching technology, as shown in FIG. 9, the interlayer insulating film ILD1_1 on the via contact V1_1 is processed into the pattern of the pad P1_1a.

[0064] Next, as shown in FIG. 10, a barrier metal film 101_1a and a conductive material 102_1a are deposited on the interlayer insulating film ILD1_1 and the via contact V1_1. For the barrier metal film 101_1a, for example, a laminated film of a titanium film and a titanium nitride film is used. For the conductive material 102_1a, for example, a conductive material such as copper or tungsten is used.

[0065] Next, using the CMP method, the barrier metal film 101_1a and the conductive material 102_1a are polished until the interlayer insulating film ILD1_1 is exposed. Thereby, as shown in FIG. 11, a pad P1_1a including the barrier metal film 101_1a and the conductive material 102_1a is formed. Note that the interlayer insulating film ILD1_1 exposed in the CMP process becomes the insulating material 103_1a.

[0066] Here, as shown in FIG. 3A, the insulating material 103_1a is provided in an island shape (for example, a stripe shape or a line and space shape) inside the conductive material 102_1a. In the CMP process of the barrier metal film 101_1a and the conductive material 102_1a, the insulating material 103_1a functions as a support inside the conductive material 102_1a. Thereby, dishing (depression) of the conductive material 102_1a in the pad P1_1a is suppressed.

[0067] The manufacturing method of the pad P1_1a of the array chip CH_A1 has been described above. Although the pad P1_2a of the circuit chip CH_C1 is connected to the CMOS circuit CMOS1, it is formed in the same manner as the pad P1_1a. Therefore, dishing (depression) of the conductive material 102_2a is also suppressed in the pad P1_2a.

[0068] Dishing of the pad P1_1a of the array chip CH_A1 and the pad P1_2a of the circuit chip CH_C1 is suppressed. Therefore, when the array chip CH_A1 and the circuit chip CH_C1 are bonded together, as shown in FIG. 4, the pads P1_1a and P1_2a are sufficiently bonded with almost no gap. As a result, an increase in the contact resistance between the pads between the array chip CH_A1 and the circuit chip CH_C1 can be suppressed, and an open defect can be suppressed.

[0069] The bonding between the array chip CH_A1 and the circuit chip CH_C1 has been described above, but this embodiment can also be applied to the bonding between the memory chips 40_1 and 40_2.

[0070] (Bonding between the memory chips 40_1 and 40_2) As shown in FIG. 2, the memory chip 40_1 and the memory chip 40_2 are bonded at the bonding surface B_chip. The memory chips 40_1 and 40_2 have the same configuration as each other.

[0071] At the bonding surface B_chip, the pad P1_2b of the memory chip 40_1 and the pad P2_1b of the memory chip 40_2 are electrically connected. The pad P1_2b is electrically connected to the through electrode TSV1 provided in the circuit chip CH_C1 of the memory chip 40_1 via a redistribution layer (not shown). The pad P2_1b is electrically connected to the contact plug Cpri2 of the array chip CH_A2 of the memory chip 40_2.

[0072] Here, the pads P1_2b and P2_1b may each have the same configuration as the pad P1_1a shown in FIGS. 3A and 3B. Thereby, the pad P1_2b and the pad P1_1a are joined in the same manner as the pad P1_1a and the pad P1_2a shown in FIG. 4. Therefore, even in the joining between the memory chips 40_1 and 40_2, the effects of the present embodiment can be obtained.

[0073] FIGS. 12 to 17 are cross-sectional views showing an example of the formation process of the region of the through electrode TSV1 of the circuit chip CH_C1.

[0074] First, using a semiconductor manufacturing process, a CMOS circuit CMOS1 is formed on a substrate (for example, a silicon substrate) SUB1. As shown in FIG. 12, the CMOS circuit CMOS1 is electrically connected to the through electrode TSV1 via the pad P1_2b and the wiring W1_2 (or the receiving electrode of the through electrode). Note that in FIGS. 13 and later, the illustration of the CMOS circuit CMOS1, the pad P1_2b, and the wiring W1_2 is omitted.

[0075] Next, using lithography technology and etching technology, a hole is formed in the formation region of the through electrode TSV1. A spacer insulating film SP1 is formed on the inner wall of this hole. Next, using a plating method or the like, a material (for example, copper, tungsten) of the through electrode TSV1 is embedded inside the spacer insulating film (for example, a silicon oxide film) SP1. Next, an interlayer insulating film ILD1_2 is deposited on the substrate SUB1. Thereby, the structure shown in FIG. 12 is obtained.

[0076] In this way, the through electrode TSV1 is formed after the formation of the CMOS circuit. Therefore, since the through electrode TSV1 is formed after the high-temperature heat treatment of the CMOS circuit, a material (for example, copper, tungsten) of the through electrode TSV1 can be formed using a plating method. The end portion of the through electrode TSV1 on the CMOS circuit side may be electrically connected to the CMOS circuit or may be electrically connected to an external electrode.

[0077] Next, the circuit chip CH_C1 is bonded to the array chip CH_A1. At this time, the pad P1_1a and the pad P1_2a are joined (see FIG. 2).

[0078] Next, as shown in FIG. 13, the substrate SUB1 is inverted up and down. Next, as shown in FIG. 14, the back side of the substrate SUB1 is etched to expose the ends of the through electrode TSV1 and the spacer insulating film SP1.

[0079] Next, as shown in FIG. 15, the insulating films 91 and 92 are deposited on the substrate SUB1 and the through electrode TSV1. The insulating film 91 is, for example, a silicon nitride film, and the insulating film 92 is, for example, a silicon oxide film.

[0080] Next, as shown in FIG. 16, using the CMP method, the insulating films 91 and 92 are polished until the through electrode TSV1 is exposed. Thereby, the through electrode TSV1 is formed in the substrate SUB1. The through electrode TSV1 penetrates the substrate SUB1 while being electrically insulated from the substrate SUB1 by the spacer insulating film SP1.

[0081] Next, as shown in FIG. 17, the rewiring layer RW1 is formed. Next, the pad P1_2b is formed on the rewiring layer RW1. The configuration and formation method of the pad P1_2b are as described with reference to FIGS. 3A to 11.

[0082] Thereafter, the memory chips 40_1 and 40_2 are bonded together. Thereby, as shown in FIG. 2, the pad P1_2b and the pad P2_1b are bonded together.

[0083] In addition, when the through electrode is provided on the array chip CH_A1, the through electrode of the array chip CH_A1 can also be formed in the same manner as the method shown in FIGS. 12 to 17.

[0084] (Modification 1) Figs. 18A to 18D are cross-sectional views showing another example of the manufacturing method of the pad P1_1a. Note that since the manufacturing method of the pad P1_2a is the same as that of the pad P1_1a, a detailed description thereof will be omitted.

[0085] After forming the structure shown in Fig. 5, the interlayer insulating film ILD1_1 on the wiring layer W1_1 is processed using lithography technology and etching technology. As a result, as shown in Fig. 18A, the interlayer insulating film ILD1_1 on the wiring layer W1_1 is processed into the pattern of the via contact V1_1.

[0086] Next, again using lithography technology and etching technology, the interlayer insulating film ILD1_1 is processed, and as shown in Fig. 18B, the upper part of the interlayer insulating film ILD1_1 is processed into the pattern of the pad P1_1a. As a result, the pattern of the pad P1_1a is formed on the upper part of the interlayer insulating film ILD1_1, and the pattern of the via contact V1_1 is formed so as to follow under the pattern of the pad P1_1a.

[0087] Next, as shown in Fig. 18C, a barrier metal film 101_1a and a conductive material 102_1a are deposited on the interlayer insulating film ILD1_1 and the wiring layer W1_1.

[0088] Next, using the CMP method, the barrier metal film 101_1a and the conductive material 102_1a are polished until the interlayer insulating film ILD1_1 is exposed. As a result, as shown in Fig. 18D, the via contact V1_1 and the pad P1_1a composed of the barrier metal film 101_1a and the conductive material 102_1a are simultaneously formed. In this CMP process, the insulating material 103_1a serves as a support inside the conductive material 102_1a, and the dishing of the conductive material 102_1a can be alleviated.

[0089] In Modification 1, the via contact V1_1 and the pad P1_1a are formed simultaneously. Therefore, Modification 1 can form the pad P1_1a with fewer processes than the first embodiment. Other manufacturing processes of Modification 1 may be the same as those of the first embodiment. Thus, this Modification 1 can obtain the same effects as the first embodiment.

[0090] (Modification 2) Figs. 19A to 19G are cross-sectional views showing still another example of the method for manufacturing the pad P1_1a. Since the method for manufacturing the pad P1_2a is the same as the method for manufacturing the pad P1_1a, detailed description thereof will be omitted.

[0091] After forming the structure shown in Fig. 5, using lithography technology and etching technology, among the interlayer insulating film ILD1_1 on the wiring layer W1_1, the entire interlayer insulating film ILD1_1 in the formation region of the pad P1_1a is removed. Thereby, the structure shown in Fig. 19A is obtained.

[0092] Next, as shown in Fig. 19B, a barrier metal film 101_1a and a conductive material 102_1a are deposited on the interlayer insulating film ILD1_1 and the wiring layer W1_1.

[0093] Next, using the CMP method, the barrier metal film 101_1a and the conductive material 102_1a are polished until the interlayer insulating film ILD1_1 is exposed. Thereby, as shown in Fig. 19C, the barrier metal film 101_1a and the conductive material 102_1a are formed over the entire formation region of the pad P1_1a.

[0094] Next, using lithography technology and etching technology, the upper part of the conductive material 102_1a is processed to remove the conductive material 102_1a in the formation region of the insulating material 103_1a. Thereby, the structure shown in Fig. 19D is obtained.

[0095] Next, as shown in Fig. 19E, a barrier metal film 101_3 is deposited on the interlayer insulating film ILD1_1 and the conductive material 102_1a.

[0096] Next, as shown in FIG. 19F, an insulating material 103_1a is deposited on the barrier metal film 101_3.

[0097] Next, using the CMP method, the insulating material 103_1a is polished until the interlayer insulating film ILD1_1 is exposed. As a result, as shown in FIG. 19G, a pad P1_1a is formed. In this CMP process, even if the conductive material 102_1a is exposed, the insulating material 103_1a serves as a support inside the conductive material 102_1a, and the dishing of the conductive material 102_1a can be alleviated.

[0098] In Modification 2, the via contact V1_1 is provided over the entire formation region of the pad P1_1a. In this case, the pad P1_1a is connected to the wiring layer W1_1 via the via contact V1_1.

[0099] In Modification 2 as well, the via contact V1_1 and the pad P1_1a are formed simultaneously. Therefore, Modification 2 can form the pad P1_1a in fewer steps than the first embodiment. Other formation steps of Modification 2 may be the same as those of the first embodiment. Thus, this Modification 2 can obtain the same effects as the first embodiment. Note that an embodiment using the pad P1_1a formed by Modification 2 will be described later with reference to FIG. 25.

[0100] (Modification 3) FIGS. 20A to 20F are cross-sectional views showing another example of the formation process of the region of the through electrode TSV1 of the circuit chip CH_C1. In this modification, after forming a CMOS circuit and inverting the substrate SUB1, the through electrode TSV1 is formed.

[0101] First, a CMOS circuit (not shown) is formed on the substrate SUB1, and an interlayer insulating film ILD1_2 is deposited thereon. As a result, the structure shown in FIG. 20A is obtained.

[0102] Next, as shown in FIG. 20B, a hole is formed in the formation region of the through electrode TSV1 using lithography technology and etching technology.

[0103] Next, as shown in FIG. 20C, a spacer insulating film SP1 is formed on the inner wall of this hole, and by etch-back, the spacer insulating film SP1 at the bottom of the hole is removed.

[0104] Next, as shown in FIG. 20D, using a plating method or the like, the material of the through electrode TSV1 is embedded inside the spacer insulating film SP1.

[0105] In this way, the through electrode TSV1 is formed after the formation of the CMOS circuit. Therefore, since the through electrode TSV1 is formed after the high-temperature heat treatment of the CMOS circuit, the material of the through electrode TSV1 (for example, copper, tungsten) can be formed by using a plating method.

[0106] Next, using the CMP method, the material of the through electrode TSV1 is polished until the surface of the spacer insulating film SP1 is exposed. As a result, as shown in FIG. 20E, the through electrode TSV1 is formed in the substrate SUB1. The through electrode TSV1 penetrates the substrate SUB1 while being electrically insulated from the substrate SUB1 by the spacer insulating film SP1.

[0107] Next, as shown in FIG. 20F, a rewiring layer RW1 is formed. Next, a pad P1_2b is formed on the rewiring layer RW1. The configuration and formation method of the pad P1_2b are as described with reference to FIGS. 3A to 11.

[0108] Thereafter, the memory chips 40_1 and 40_2 are bonded together. As a result, as shown in FIG. 2, the pad P1_2b and the pad P2_1b are bonded together.

[0109] In addition, when a through electrode is provided in the array chip CH_A1, the through electrode of the array chip CH_A1 can also be formed in the same manner as in this modified example.

[0110] (Second Embodiment) FIG. 21 is a plan view showing a configuration example of the pad P1_2a according to the second embodiment. When the pads P1_1a and P1_2a have the same configuration as in the first embodiment, if the pads P1_1a and P1_2a are relatively displaced in the X direction in FIG. 4, there is a possibility that the conductive material 102_1a faces the insulating material 103_2a and the conductive material 102_2a faces the insulating material 103_1a. In this case, the contact area between the conductive material 102_1a and the conductive material 102_12a becomes extremely small, the contact resistance between the pads P1_1a and P1_2a becomes high, and there is a possibility that it becomes unstable.

[0111] On the other hand, in the second embodiment, in a plan view seen from the Z direction, the insulating material 103_2a of the pad P1_2a extends in a direction inclined with respect to the X and Y directions. The configuration of the pad P1_1a may be the same as that of the first embodiment.

[0112] FIG. 22 is a cross-sectional view showing a configuration example of the region of the bonding surface B_mc1 according to the second embodiment. In the second embodiment, when the array chip CH_A1 and the circuit chip CH_C1 are bonded together, the pads P1_1a and P1_2a are bonded at the bonding surface B_mc1 such that the extending direction of the insulating material 103_1a (for example, the Y direction) and the extending direction of the insulating material 103_2a (the direction inclined with respect to the X and Y directions) intersect. Note that the cross section along the line B-B in FIG. 21 is shown as the pad P1_2a in FIG. 22.

[0113] Since the extending direction of the insulating material 103_1a and the extending direction of the insulating material 103_2a intersect, even if the pads P1_1a and P1_2a are displaced to some extent in the X or Y direction, the contact area between the conductive material 102_1a and the conductive material 102_2a does not decrease so much. Therefore, the second embodiment can keep the contact resistance low and stable against the displacement between the pads P1_1a and P1_2a at the bonding surface B_mc1.

[0114] (Third Embodiment) FIG. 23 is a plan view showing a configuration example of the pad P1_1a according to the third embodiment. In the second embodiment, in a plan view seen from the Z direction, the conductive material 102_1a of the pad P1_1a has a mesh structure formed by an elongated shape extending in the X direction and an elongated shape extending in the Y direction on the surface of the interlayer insulating film ILD1_1. Therefore, in a plan view seen from the Z direction, the insulating material 103_1a is formed in an island shape (dot shape) on the surface of the interlayer insulating film ILD1_1 and is two-dimensionally arranged in a matrix in the X and Y directions.

[0115] The insulating material 103_1a is formed of a material (e.g., a silicon oxide film) having an etching rate lower than that of the material of the conductive material 102_1a (e.g., a metal material such as copper or tungsten). For example, the insulating material 103_1a may be formed of a physically hard material that is more difficult to polish than the material of the conductive material 102_1a. Alternatively, the insulating material 103_1a may be formed of a material that is more difficult to be chemically etched by an abrasive (slurry) than the material of the conductive material 102_1a. Therefore, in the CMP process, the insulating material 103_1a serves as a support inside the conductive material 102_1a, and the dishing of the conductive material 102_1a can be alleviated.

[0116] Also, the pad P1_2a has the same configuration as the pad P1_1a in FIG. 23. Therefore, although not shown, in a plan view seen from the Z direction, the conductive material 102_2a of the pad P1_2a also has a mesh structure formed by an elongated shape extending in the X direction and an elongated shape extending in the Y direction on the surface of the interlayer insulating film ILD1_2. That is, in a plan view seen from the Z direction, the insulating material 103_2a is formed in an island shape (dot shape) on the surface of the interlayer insulating film ILD1_2 and is two-dimensionally arranged in a matrix in the X and Y directions. Therefore, in the CMP process, the insulating material 103_2a serves as a support inside the conductive material 102_2a, and the dishing of the conductive material 102_2a can be alleviated.

[0117] As a result, the contact resistance between the conductive material 102_1a and the conductive material 102_2a can be made low and stable.

[0118] In addition, the third embodiment may be combined with any one of the first embodiment, the second embodiment, modification example 1, and modification example 2. That is, the pad P1_1a according to the third embodiment and the pad P1_2a according to any one of the first embodiment, the second embodiment, modification example 1, and modification example 2 may be joined.

[0119] Further, the third embodiment may be used for joining between the memory chips 40_1 and 40_2. That is, the third embodiment may be applied to the pad P1_2b of the memory chip 40_1 and the pad P2_1b of the memory chip 40_2. As a result, dishing of the pad P1_2b and the pad P2_1b is suppressed, and the joining between the memory chips 40_1 and 40_2 can also be stabilized with low resistance.

[0120] (Fourth Embodiment) FIG. 24 is a plan view showing a configuration example of the pad P1_2a according to the fourth embodiment. In the fourth embodiment, in a plan view seen from the Z direction, the conductive material 102_2a of the pad P1_2a extends in a direction inclined with respect to the X and Y directions. The configuration of the pad P1_1a may be the same as any one of the first to third embodiments, modification example 1, and modification example 2.

[0121] In the fourth embodiment, when the array chip CH_A1 and the circuit chip CH_C1 are bonded together, the pad P1_1a and the pad P1_2a are bonded on the bonding surface B_mc1 such that the extending direction of the conductive material 102_1a and the extending direction of the conductive material 102_2a intersect. Since the extending direction of the insulating material 103_1a and the extending direction of the insulating material 103_2a intersect, even if the pad P1_1a and the pad P1_2a are displaced to some extent in the X or Y direction, the contact area between the conductive material 102_1a and the conductive material 102_2a does not change much. Therefore, the fourth embodiment can stabilize the contact resistance with respect to the displacement between the pad P1_1a and the pad P1_2a on the bonding surface B_mc1.

[0122] Other configurations of the fourth embodiment may be the same as the corresponding configurations of the first to third embodiments. Therefore, the fourth embodiment can also obtain any of the effects of the first to third embodiments.

[0123] (Fifth Embodiment) FIG. 25 is a cross-sectional view showing a configuration example of the region of the bonding surface B_mc1 according to the fifth embodiment. In the fifth embodiment, the pads P1_1a and P1_2a formed by the above-described modification 2 are used.

[0124] In the fifth embodiment, the via contact V1_1 is provided below the pad P1_1a and is electrically commonly connected to the conductive material 102_1a. The via contact V1_1 electrically connects the conductive material 102_1a to the wiring layer W1_1. In this way, the via contact V1_1 is provided integrally with the conductive material 102_1a over the entire formation region of the pad P1_1a. As a result, due to the volume expansion (thermal expansion) of the via contact V1_1 and the conductive material 102_1a, the conductive material 102_1a of the pad P1_1a bulges somewhat from the bonding surface B_mc1.

[0125] Similarly, for the pad P1_2a, the via contact V1_2 is provided below the pad P1_2a and is electrically commonly connected to the conductive material 102_2a. The via contact V1_2 electrically connects the conductive material 102_2a to the wiring layer W1_2. In this way, the via contact V1_2 is also provided integrally with the conductive material 102_2a over the entire formation region of the pad P1_2a. As a result, due to the volume expansion (thermal expansion) of the via contact V1_2 and the conductive material 102_2a, the conductive material 102_2a of the pad P1_2a bulges somewhat from the bonding surface B_mc1.

[0126] Since the pads P1_1a and P1_2a rise from the bonding surface B_mc1 with respect to each other, the pads P1_1a and P1_2a on the bonding surface B_mc1 are surely bonded to each other. Thereby, the pads P1_1a and P1_2a can be stably connected to each other with low resistance.

[0127] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0128] 1 semiconductor package, 40_1, 40_2 memory chips, CH_A1, CH_A2 array chips, CH_C1, CH_C2 circuit chips, MCA1, MCA2 memory cell arrays, CMOS1, CMOS2 CMOS circuits, P1_1a to P2_2b pads, 101_1a, 101_2a barrier metal films, 102_1a, 102_2a conductive materials, 103_1a, 103_2a insulating materials, ILD1_1, ILD1_2 interlayer insulating films

Claims

1. a first insulating layer; a first pad exposed on the surface of the first insulating layer; a second insulating layer bonded to the first insulating layer; a second pad exposed on the surface of the second insulating layer and bonded to the first pad; a first wiring layer provided on the back side opposite to the surface of the first insulating layer; and a first via contact electrically connecting the first wiring layer and the first pad, in a first plan view from a direction substantially perpendicular to the surface of the first insulating layer, inside the first pad, there are a first conductive material and a first insulating material having an etching rate lower than that of the first conductive material, and the first insulating material is provided in an island shape inside the first conductive material; in the first plan view, the first via contact is provided over the entire formation region of the first pad; in the first plan view, the area of the first via contact is larger than the area of the first conductive material, a semiconductor device.

2. In the first plan view, the first insulating material has an elongated shape extending in a first direction on the surface of the first insulating layer, the semiconductor device according to claim 1.

3. In the first plan view, the area of the first insulating material of the first pad is smaller than the area of the first conductive material, the semiconductor device according to claim 1 or claim 2.

4. In a second plan view from a direction substantially perpendicular to the surface of the second insulating layer, inside the second pad, there are a second conductive material and a second insulating material having an etching rate lower than that of the second conductive material, and the second insulating material is provided in an island shape inside the second conductive material, the semiconductor device according to any one of claims 1 to 3.

5. The semiconductor device according to claim 4, wherein in the second plan view, the second insulating material has an elongated shape extending in a third direction on the surface of the second insulating layer.

6. The semiconductor device according to claim 1, wherein in the first plan view, the first conductive material has a mesh structure including a first elongated shape extending in a first direction and a second elongated shape extending in a second direction intersecting the first direction on the surface of the first insulating layer.

7. The semiconductor device according to claim 4 or 5, wherein in the second plan view, the second conductive material has a mesh structure including a third elongated shape extending in a third direction and a fourth elongated shape extending in a fourth direction intersecting the third direction on the surface of the second insulating layer.

8. A memory cell array covered with the first insulating layer, A CMOS circuit covered with the second insulating layer, And a second wiring layer electrically connected between the CMOS circuit and the second pad, The semiconductor device according to any one of claims 1 to 7, wherein the first wiring layer is electrically connected between the memory cell array and the first pad.

9. A first chip including a first memory cell array covered with the first insulating layer and a first CMOS circuit provided below the first memory cell array, and A second chip including a second memory cell array and a second CMOS circuit provided below the second memory cell array and covered with the second insulating layer, The semiconductor device according to any one of claims 1 to 7, wherein the first and second chips are electrically connected by the first and second pads.

10. Metal is used for the first conductive material, The semiconductor device according to claim 1, wherein a nitride film or a carbide film is used for the first insulating material.

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