Selective Gate Structure and Manufacturing Method for 3D Memory

Abstract

A semiconductor memory device and method for manufacturing the same are described. The semiconductor memory device comprises a memory array including at least one drain side select gate (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting the drain side select gate (SGD) transistor to a strapping line.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices, as well as methods and apparatuses for manufacturing electronic devices. More specifically, embodiments of the present disclosure present a select-gate-for-drain (SGD) transistor and a forming method thereof.

Background Art

[0002]

[0002] Semiconductor technology has been advancing at a rapid pace. With the progress of technology, the dimensions of devices have been reduced, and the processing speed and memory speed per unit area have been improved. In NAND devices, in order to obtain a current sufficient to distinguish between ON cells and OFF cells, it is necessary to make the string current large enough. The string current depends on the carrier mobility improved by increasing the grain size of the silicon channel.

[0003]

[0003] Current 3D-NAND devices have a memory stack including alternating layers of oxide and nitride materials, and have multiple memory holes between two slits. To access each cell with word lines and bit lines, it is necessary to divide the memory holes between the slits with a drain-side select gate (SGD) cut. For example, Toshiba's 96L stacked 3D NAND has 8 memory holes and 1 dummy hole, and 1 SGD cut separates the holes into two groups. To reduce the array size of 3D-NAND, it is necessary to increase the number of holes (nHole) between the slits. When nHole exceeds 8 and increases, multiple SGD cuts are required with the same technology. Holes at the same bit line level should be separately accessible by a combination of bit line (BL) and word line (WL). That is, holes in the same bit line are independently selected by the drain-side select gate (select gate for drain: SGD) and the bit line. For this purpose, the SGD between the slits should be separated by SGD cuts. When the number of holes (nHole) between the slits is small (e.g., ≤ 8), 1 SGD cut separates the drain-side select gate (SGD). However, when the number of holes (nHole) between the slits is large (e.g., ≥ 12), SGD cuts need to be added for every 4 holes.

[0004]

[0004] Therefore, there is a need in the art for a 3D-NAND device having a drain-side select gate (SGD) cut and a method of manufacturing a 3D-NAND device.

Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to semiconductor memory devices. In one or more embodiments, a semiconductor memory device is a memory array including at least one drain-side select gate (SGD) transistor and at least one memory transistor, the memory array having at least one stripping region and at least one stripping contact, and at least one stripping contact connecting the drain-side select gate (SGD) transistor to a stripping line.

[0006]

[0006] Other embodiments of the present disclosure are directed to semiconductor memory devices. In one or more embodiments, a semiconductor memory device is a memory stack on a substrate, the memory stack including alternating layers of word lines and dielectric material, a plurality of memory transistors extending through the memory stack, a fill slit extending through the memory stack and adjacent to the plurality of memory transistors, and a plurality of drain-side select gate (SGD) transistors at an upper portion of the memory stack, at least one of the plurality of drain-side select gate (SGD) transistors being electrically connected to a stripping line.

[0007]

[0007] Additional embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, a method of forming a semiconductor device includes forming a plurality of memory holes extending through a memory stack, the memory stack including alternating layers of a first layer and a second layer on a substrate; depositing a transistor layer within the plurality of memory holes to form a plurality of memory strings; forming bit line pads on top of each of the plurality of memory strings; forming a drain side select gate (SGD) transistor on top of the memory stack; forming a slit extending through the memory stack to the substrate; removing the first layer to form an opening within the memory stack; depositing a dielectric material within the opening; recessing the second layer to form a recessed region; depositing a low resistance material within the recessed region; filling the slit to form a filled slit; forming a drain side select gate contact; and forming a strapping line on top of the memory stack in contact with the drain side select gate contact.

[0008]

[0008] To better understand the features of the present disclosure described above, a more detailed description of the present disclosure, briefly summarized above, is obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that since the present disclosure may admit to other equally effective embodiments, the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure. The embodiments described herein are illustrated in the accompanying drawings by way of example and not limitation, and like reference numerals in the drawings indicate like elements.

Brief Description of the Drawings

[0009]

Figure 1

[0009] A process flow diagram of a method of forming a memory device according to an embodiment described herein is shown.

Figure 2

[0010] A cross-sectional view of an electronic device including a memory stack according to one or more embodiments is shown.

Figure 3

[0011] A cross-sectional view of an electronic device after forming a stepped pattern of a memory stack according to one or more embodiments is shown.

Figure 4

[0012] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 5A

[0013] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 5B

[0014] An enlarged view of region 132 according to one or more embodiments is shown.

Figure 6A

[0015] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 6B

[0016] An enlarged view of region 132 according to one or more embodiments is shown.

Figure 7A

[0017] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 7B

[0018] An enlarged view of region 132 according to one or more embodiments is shown.

Figure 8

[0019] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 9

[0020] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 10

[0021] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 11

[0022] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 12A

[0023] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 12B

[0024] An enlarged view of region 132 according to one or more embodiments is shown.

Figure 13A

[0025] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 13B

[0026] Shows an enlarged view of region 132 according to one or more embodiments.

Figure 14A

[0027] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 14B

[0028] Shows an enlarged view of region 132 according to one or more embodiments.

Figure 15A

[0029] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 15B

[0030] Shows an enlarged view of region 132 according to one or more embodiments.

Figure 16

[0031] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 17

[0032] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 18A

[0033] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 18B

[0034] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 19A

[0035] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 19B

[0036] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 20A

[0037] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 20B

[0038] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 21A

[0039] Shows a cross-sectional view of an electronic device according to one or more embodiments.

Figure 21B

[0040] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 21C

[0041] A cross-sectional view of an electronic device according to one or more embodiments is shown.

Figure 22

[0042] A cluster tool according to one or more embodiments is shown.

DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0043] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure can have other embodiments and can be implemented or executed in various ways.

[0011]

[0044] In the following description, numerous specific details (such as specific materials of elements, chemical properties, dimensions, etc.) are presented to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to those skilled in the art that one or more embodiments of the present disclosure can be practiced without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, etc. are not described in detail so as not to unnecessarily obscure this description. Those skilled in the art will be able to implement appropriate functionality without performing more experiments than necessary using the description contained herein.

[0012]

[0045] Although specific exemplary embodiments of the present disclosure are described and shown in the accompanying drawings, such embodiments are merely illustrative and do not limit the present disclosure. Since those skilled in the art can conceive of variations, it should be understood that the present disclosure is not limited to the specific structures and arrangements shown and described.

[0013]

[0046] Terms such as "precursor", "reactant", "reactive gas", etc. used in this specification and the appended claims are used interchangeably and refer to any gas species that can react with the substrate surface.

[0014]

[0047] According to one or more embodiments, with respect to a film or layer of a film, the term "on" includes the film or layer being directly present on a surface (e.g., a substrate surface), as well as one or more underlying layers being present between the film or layer and the surface (e.g., the substrate surface). Thus, in one or more embodiments, the expression "on the substrate surface" is intended to include one or more underlying layers. In other embodiments, the term "directly" refers to a layer or film in contact with a surface (e.g., a substrate surface) and there is no intervening layer. Thus, a "layer directly on the substrate surface" refers to a layer that is in direct contact with the substrate surface and there is no layer therebetween.

[0015]

[0048] In existing 3D NAND devices based on a memory stack of alternating layers of oxide and nitride materials, a non-replacement word line process that uses a silicon (Si)-based material as a word line is an alternative method to avoid the process difficulties of the word line replacement process. However, one of the drawbacks of polysilicon-based word lines is that the word line resistance is higher compared to tungsten (W) in an oxide / nitride (ON) mold. To reduce the word line resistance of polysilicon, word line edge silicidation has been used. However, a drain side select gate (SGD) not exposed to a slit cannot use a word line capped with a low resistance material. The performance of the entire cell is affected by the resistance (R) of the SGD gate, the capacitance (C) connected to the SGD gate, and the delay time (RC delay) of the SGD. Thus, reduction of the RC delay of the SGD is an important issue in the Si-based word line scheme. Accordingly, one or more embodiments advantageously provide a structure and an integration method for improving the RC delay of the SGD by employing a strapping line. In one or more embodiments, at least one SGD is fixed using a low resistance metal line at two or more positions.

[0016]

[0049] One or more embodiments provide a structure and method for manufacturing a memory array that includes at least one drain-side select gate (SGD) transistor and at least one memory transistor. The memory array has at least one stripping region and at least one stripping contact. The stripping contact connects the drain-side select gate (SGD) transistor to a stripping line. The devices and manufacturing methods of one or more embodiments advantageously have an SGD with reduced RC delay. In one or more embodiments, at least one stripping region includes a first plurality of memory holes that are less dense than a second plurality of memory holes in a non-stripping region.

[0017]

[0050] In one or more embodiments, metal deposition and other processes can be performed in a separate environment (e.g., a cluster process tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system with associated process modules for performing the method.

[0018]

[0051] FIG. 1 shows a flowchart of an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that method 10 can include any or all of the illustrated processes. Further, the order of the individual processes can be partially changed. Method 10 can start from any of the recited processes without departing from the present disclosure.

[0019]

[0052] Referring to FIG. 1, in step 15, a memory stack is formed. In step 20, a word line staircase is formed within the memory stack. In step 25, memory holes penetrating the memory stack are patterned. In step 30, a transistor layer is deposited in the memory holes. In step 35, bit line pads are formed. In step 40, a drain side select gate (SGD) cut is patterned. In step 45, a dielectric is deposited in the opening formed by the drain side select gate cut. In step 50, the device is slit patterned. In step 55, the sacrificial layer of the common source line is removed and replaced. In step 60, the common source line is etched to form a common source line contact region. In step 65, word lines are formed. In step 70, a low resistance material is formed on the word lines. In step 75, the slit is filled with a dielectric material. In step 80, drain side select gate contacts are formed. In step 85, strapping lines are formed. In step 90, bit line pad studs are formed. In step 95, word line contacts are formed.

[0020]

[0053] FIGS. 2 to 21C show a part of the memory device 100 according to the process flow illustrated for the method 10 of FIG. 1.

[0021]

[0054] FIG. 2 shows an initial or starting memory stack of the electronic device 100 according to one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 shown in FIG. 2 is formed in layers on a bare substrate 102 as shown. The electronic device of FIG. 2 is composed of a substrate 102, a common source line 103, and a memory stack 130.

[0022]

[0055] The substrate 102 can be made of any suitable material known to those skilled in the art. As used in this specification and the appended claims, the term "substrate" refers to the surface or a portion of the surface on which the process acts. It will also be understood by those skilled in the art that references to the substrate can, unless otherwise explicitly stated in the context, refer only to a portion of the substrate. Further, references to deposition on the substrate can mean both the bare substrate and the substrate on which one or more films or features have been deposited or formed on the surface.

[0023]

[0056] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, the substrate surface on which processing can be performed can include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. The substrate includes, but is not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In the present disclosure, in addition to performing film processing directly on the surface of the substrate itself, any of the disclosed film processing steps may be performed on a lower layer formed on the substrate, as will be described in more detail later. The term "substrate surface" is intended to include such a lower layer, as will be understood from the context. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0024]

[0057] In one or more embodiments, a common source line 103 is on the substrate 102. The common source line 103 may also be referred to as a semiconductor layer. The common source line 103 can be formed by any suitable technique known to those skilled in the art and can be made from any suitable material including, but not limited to, polysilicon (poly-Si). In some embodiments, the common source line 103 includes a plurality of different conductive or semiconductor materials. For example, in one or more embodiments, as shown in FIG. 2, the common source line 103 includes a polysilicon layer 104 on the substrate 102, a sacrificial layer 106 on the polysilicon layer, and a second polysilicon layer 104 on the sacrificial layer 106.

[0025]

[0058] In one or more embodiments, the sacrificial layer 106 is formed on the polysilicon layer 104 and can be made from any suitable material. In some embodiments, the sacrificial layer 106 is removed and replaced in a subsequent process. In some embodiments, the sacrificial layer 106 is not removed and remains within the memory device 100. In this case, the term "sacrificial" has an extended meaning that includes a permanent layer and may be referred to as a conductive layer. In the illustrated embodiment, as further described below, the sacrificial layer 106 is removed in step 70. In one or more embodiments, the sacrificial layer 106 includes a material that can be selectively removed with respect to the adjacent polysilicon layer 104. In one or more embodiments, the sacrificial layer includes a nitride material, such as silicon nitride (SiN), or an oxide material, such as silicon oxide (SiOx).

[0026]

[0059] In one or more embodiments, an oxide layer 108 is formed on the upper surface of the common source line 103. The oxide layer 108 can include any suitable material known to those skilled in the art. In one or more embodiments, the oxide layer 108 includes silicon oxide (SiOx).

[0027]

[0060] In one or more embodiments, a memory stack 130 is formed on an oxide layer 108 on a common source line 103. The memory stack 130 in the illustrated embodiment includes a plurality of first layers 110 and second layers 112 that are alternately arranged. The memory stack 130 shown in FIG. 2 has three pairs of alternately arranged first layers 110 and second layers 112, but those skilled in the art will recognize that this is merely for illustrative purposes. The memory stack 130 can have any number of alternately arranged first layers 110 and second layers 112. For example, in some embodiments, the memory stack 130 includes 192 pairs of alternately arranged first layers 110 and second layers 112. In other embodiments, the memory stack 130 includes more than 50 pairs of alternately arranged first layers 110 and second layers 112, or more than 100 pairs of alternately arranged first layers 110 and second layers 112, or more than 300 pairs of alternately arranged first layers 110 and second layers 112.

[0028]

[0061] In one or more embodiments, the second layer 112 is a replacement layer. In one or more embodiments, the first layer 110 and the second layer 112 independently include a dielectric material. In one or more embodiments, the dielectric material includes any suitable dielectric material known to those skilled in the art. As used herein, the term "dielectric material" refers to an electrical insulator that is polarizable in an electric field. In some embodiments, the dielectric material includes one or more of an oxide, a carbon-doped oxide, porous silicon dioxide (SiO2), silicon monoxide (SiO), silicon nitride (SiN), silicon dioxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate (SiOCH) glass.

[0029]

[0062] In one or more embodiments, the second layer 112 comprises a material having an etching selectivity with respect to the first layer 110 such that the second layer 112 can be removed without substantially affecting the first layer 110. In one or more embodiments, the first layer 110 comprises a silicon (Si) layer and the second layer 112 comprises a silicon germanium (SiGe) layer.

[0030]

[0063] The individual alternating layers can be formed to any suitable thickness. In some embodiments, the thickness of each second layer 112 is substantially equal. In one or more embodiments, each second layer 112 has a thickness of the second layer. In some embodiments, the thickness of each first layer 110 is substantially equal. As used in this context, substantially equal thickness means within ±5% of each other. In some embodiments, a silicon layer (not shown) is formed between the second layer 112 and the first layer 110. The thickness of the silicon layer may be relatively thin compared to the thickness of the second layer 112 or the first layer 110. In one or more embodiments, the first layer 110 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the first layer 110 has a thickness in the range of about 0.5 to about 40 nm. In one or more embodiments, the second layer 112 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second layer 112 has a thickness in the range of about 0.5 to about 40 nm.

[0031]

[0064] In one or more embodiments, the first layer 110 and the second layer 112 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, the first layer 110 and the second layer 112 are deposited by plasma enhanced chemical vapor deposition (PE-CVD). The individual alternating layers can be formed to any suitable thickness. In some embodiments, the thicknesses of each of the second layers 112 are substantially equal. In one or more embodiments, each of the second layers 112 has a first second layer thickness. In some embodiments, the thicknesses of each of the first layers 110 are substantially equal. As used in this context, substantially equal thickness means within ±5% of each other. In one or more embodiments, the first layer 110 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second layer 112 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.

[0032]

[0065] In one or more embodiments, the drain side select gate material 116 is formed on the upper surface of the memory stack 130. In one or more embodiments, the drain side select gate material 116 is formed on the upper surface of the oxide layer 114. In one or more embodiments, the gate material 116 of the drain side select gate includes one or more of polysilicon or metal. The metal can include any suitable metal known to those skilled in the art. In some embodiments, the metal is a high melting point metal. In one or more embodiments, the metal can be selected from one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), and osmium (Os).

[0033]

[0066] In one or more embodiments, an oxide material 118 is formed on the upper surface of the drain-side select gate material 116. The oxide material 118 may include any suitable material known to those skilled in the art. In some embodiments, the oxide material includes silicon oxide (SiOx).

[0034]

[0067] Referring to FIG. 3, in step 20 of method 10, a staircase formation is created. In one or more embodiments, the staircase formation exposes the upper surface 134 of the second layer 112. The upper surface 134 can be used to provide a space for forming word line contacts, as will be described later. A suitable filler 135 can be deposited to occupy the space outside the staircase formation. As will be understood by those skilled in the art, the suitable filler 135 can be any material that prevents electrical short circuits between adjacent word lines. The staircase formation has each word line having a smaller width (from left to right in the figure) than the lower word line. When using relative terms such as "above" and "below", the scope of the present disclosure should not be construed as being limited to the physical orientation in space.

[0035]

[0068] For ease of illustration, FIGS. 4-21 do not show the staircase formation, but it should be noted that the staircase formation exists as will be recognized by those skilled in the art.

[0036]

[0069] FIGS. 4-5B show the formation of a memory string through the memory stack 130. Referring to FIG. 4, in step 25, a memory hole channel 120 is opened / patterned through the memory stack 130. In some embodiments, opening the memory hole channel 120 includes etching through the oxide layer 118, the drain-side select gate material 116, the oxide layer 114, the memory stack 130, the common source line 103, and into the substrate 102. The memory hole channel 120 has sidewalls that extend through the memory stack 130 and expose the surface 126 of the second layer 112 and the surface 124 of the first layer 110.

[0037]

[0070] The gate material 116 of the drain-side select gate has a surface 136 that is exposed as a sidewall of the memory hole channel 120. The memory hole channel 120 extends a distance within the substrate 102 such that the sidewall surfaces 136, 124, 126 and the bottom 115 of the memory hole channel 120 are formed within the substrate 102. The bottom 115 of the memory hole channel 120 can be formed at any point within the thickness of the substrate 102. In some embodiments, the memory hole channel 120 extends within the substrate 102 at a thickness within the range of about 10% to about 90% of the thickness of the substrate 102, or within the range of about 20% to about 80% of the thickness of the substrate 102, or within the range of about 30% to about 70% of the thickness of the substrate 102, or within the range of about 40% to about 60% of the thickness of the substrate 102. In some embodiments, the memory hole channel 120 extends a distance of 10 nm or more into the interior of the substrate 102. In some embodiments, the memory hole channel 120 extends from the upper surface of the drain-side select gate (SGD) gate 116 and the oxide layer 118 through the memory stack to the bottom surface of the substrate.

[0038]

[0071] Figure 5A shows step 30 in which the transistor layer 128 is formed within the memory hole channel 120. The transistor layer 128 can be formed by any suitable technique known to those skilled in the art. In some embodiments, the transistor layer is formed by a conformal deposition process. In some embodiments, the transistor layer is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0039]

[0072] In one or more embodiments, the deposition of the transistor layer 128 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer that has substantially the same thickness throughout (e.g., the upper, central, bottom, and bottom of the sidewalls of the memory hole channel 120). The thickness of a substantially conformal layer varies by about 5% or less, 2% or less, 1% or less, 0.5% or less. The transistor layer 128 within the memory hole includes one or more of an aluminum oxide (AlO) layer, a blocking oxide layer, a trap layer, a tunnel oxide layer, and a channel layer.

[0040]

[0073] Referring to FIG. 5B, which is an enlarged view of region 132 in FIG. 5A, in one or more embodiments, the transistor layer 128 includes an aluminum oxide layer 128a, a blocking oxide layer 128b, a nitride trap layer 128c, a tunnel oxide layer 128d, and a channel material 128e within the memory hole channel 120. In one or more embodiments, the channel material 128e includes polysilicon. In one or more embodiments, the aluminum oxide layer 128a is deposited within the memory hole channel 120 on the sidewalls of the memory hole channel 120.

[0041]

[0074] The transistor layer 128 can have any suitable thickness, for example, depending on the dimensions of the memory hole channel 120. In some embodiments, the transistor layer 128 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm.

[0042]

[0075] In one or more embodiments, the transistor layer 128 includes a memory transistor, and the transistor layer 128 independently includes one or more transistor layers selected from aluminum oxide (AlO), a blocking oxide, a trap material, a tunnel oxide, and a channel layer / channel material.

[0043]

[0076] FIGS. 6A - 7B illustrate step 35 of method 10 in which the bit - line pad 136 is formed within the upper surface of the transistor layer 128 and the oxide layer 118. In one or more embodiments, the bit - line pad 136 is formed on the drain side of a drain - side select - gate (SGD) transistor. The bit - line pad 136 can be any suitable material known to those skilled in the art, including but not limited to polysilicon. Referring to FIGS. 6A and 6B, the transistor layer 128 is etched back to form a recess 131. As shown in FIGS. 7A and 7B, the recess 131 is then filled with the bit - line pad 136.

[0044]

[0077] Referring to FIG. 8, in step 40, a select gate is etched / cut within the memory stack, forming an opening 138. In some embodiments, this may be referred to as patterning a drain side select gate cut (SGD). The opening 138 extends from the upper surface of the oxide layer 118 to the upper surface of the oxide layer 114. The etching / patterning can be performed by any suitable means known to those skilled in the art. In one or more embodiments, forming the opening 138 includes drain side select gate (SGD) isolation etching.

[0045]

[0078] Referring to FIG. 9, in step 45, drain side select gate (SGD) insulation is formed in the opening 138. In one or more embodiments, forming the drain side select gate (SGD) insulation includes depositing a dielectric material 140 within the opening 138. The dielectric material 140 can be deposited by any suitable method known to those skilled in the art. In one or more embodiments, the dielectric material 140 is deposited by atomic layer deposition (ALD). The dielectric material 140 can include any suitable dielectric material known to those skilled in the art. In one or more embodiments, the dielectric material 140 includes one or more of silicon oxide (SiOx) or silicon oxynitride (SiON).

[0046]

[0079] In some non - illustrated embodiments, the dielectric material 140 can be deposited within the opening 138 to form an overburden on the upper surface of the oxide layer 118. Thereafter, the overburden can be removed by any suitable technique known to those skilled in the art. For example, in one or more embodiments, the overburden can be removed by chemical mechanical planarization (CMP).

[0047]

[0080] Referring to FIG. 10, in step 50 of method 10, the memory stack 130 is slit - patterned to form a slit pattern opening 142 that extends from the upper surface of the oxide layer 118 to the sacrificial layer 106 of the common source line 103.

[0048]

[0081] FIG. 11 shows step 55 of method 10 in which the sacrificial layer 106 in the common source line 103 is removed to form the opening 144. The sacrificial layer 106 can be removed by any suitable technique known to those skilled in the art, including but not limited to selective etching, hot phosphoric acid, etc.

[0049]

[0082] FIG. 12A and FIG. 12B, which is an enlarged view of region 132 of FIG. 12A, show step 60 of method 10 in which the channel material 128e is exposed to form the common source line contact region 145. The channel material 128e is exposed by removing the aluminum oxide (AlO) layer 128a, the blocking oxide layer 128b, the trap layer 128c, and the tunnel oxide layer 128d within the common source line contact region 145.

[0050]

[0083] FIGS. 13A and 13B show step 55 of method 10 in which the polysilicon layer 146 is deposited within the opening 144 to replace the common source line sacrificial layer 106. The polysilicon layer 146 may or may not be doped.

[0051]

[0084] Step 65 with word line

[0085] FIGS. 14A through 15B show step 65 in which the word line is formed. Referring to FIGS. 14A and 14B, the second layer 112 is removed to form the opening 148. The second layer 112 can be removed by any suitable means known to those skilled in the art. In one or more embodiments, the second layer 112 is removed by selective etching, such as selective wet etching or selective dry etching. When the second layer 112 is removed, the opening 148 is formed.

[0052]

[0086] Figures 15A and 15B show the deposition of conformal dielectric layer 150 at the opening 148. Figure 15B is an enlarged view of region 132 of Figure 15A. The dielectric layer 150 can include any suitable dielectric material known to those skilled in the art. In one or more embodiments, the dielectric layer 150 is, for example, a low-k dielectric including, but not limited to, silicon dioxide, silicon oxide, carbon-doped oxide ("CDO"), for example, carbon-doped silicon dioxide, porous silicon dioxide (SiO2), silicon nitride (SiN), or any combination thereof. The term "silicon oxide" can be used to describe the dielectric layer 136, but those skilled in the art will recognize that the present disclosure is not limited to a specific stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" can be used to describe materials having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same applies to other materials listed in the present disclosure, such as silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, etc. In a specific embodiment, the dielectric layer 150 includes silicon oxide.

[0053]

[0087] In step 70, advantageously, a low-resistance word line is formed. In one or more embodiments, it may be advantageous for the word line to include a low-resistance material. In some embodiments, the low-resistance material has a resistance in the range of 5 μΩcm to 100 μΩcm. In some embodiments, as shown in Figures 16 and 17, the low-resistance material can be formed by indenting the word line and selectively growing the low-resistance material in the indented portion of the word line. In other embodiments, the low-resistance material can be formed by depositing a metal layer and siliciding the metal in the word line region and the common source line region.

[0054]

[0088] Referring to FIG. 16, the first material layer 110 of the word line forms a recessed and indented region 147. Referring to FIG. 17, the low-resistance material 152 is conformally deposited within the slit 142 in the recessed region 147. The low-resistance material 152 can include any suitable material known to those skilled in the art. In one or more embodiments, the low-resistance material 152 includes tungsten (W), ruthenium (Ru), aluminum (Al), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), nickel (Ni), or one or more of their silicon compounds. Thus, in one or more embodiments, the low-resistance material 152 includes one or more of tungsten (W), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), nickel (Ni), tungsten silicon compound (WSi), ruthenium silicon compound (RuSi), aluminum silicon compound (AlSi), iridium silicon compound (IrSi), tantalum silicon compound (TaSi), titanium silicon compound (TiSi), platinum silicon compound (PtSi), molybdenum silicon compound (MoSi), nickel silicon compound (NiSi). Thus, in one or more embodiments, the memory transistor includes the first material 110 and the second material 152, and the first material 110 has a higher resistance than the second material 152. Thus, the polysilicon word line includes the first material and the second material. The first material 110 has a higher resistance than the second material 152, and the second material 152 is adjacent to the slit region (i.e., the filled slit 142).

[0055]

[0089] In one or more embodiments, the slit 142 is filled with an insulator material. The insulator material can be any suitable material known to those skilled in the art. In one or more embodiments, the insulator material is selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0056]

[0090] Figures 18A through 21C show cross-sectional views 103, 100, 105, and 107 for both the normal array region and the SGD stripping region to clearly show the SGD stripping lines.

[0057]

[0091] Referring to FIGS. 18A and 18B, a contact connecting the SGD and the stripping line is formed. The SGD contact hole 158 is patterned and formed in a region lacking a memory hole. A stripping contact line can be formed together with other contacts in the non-array region.

[0058]

[0092] Referring to FIGS. 19A and 19B, a stripping line region 160 is formed. The stripping line region 160 can be formed together with other metallizations in the non-array region.

[0059]

[0093] Referring to FIGS. 20A and 20B, the stripping line region 160 is filled with one or more of a barrier metal and a metal to form a stripping line 162. The barrier metal can include any suitable material known to those skilled in the art. In one or more embodiments, the barrier metal includes one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The metal can include any suitable metal known to those skilled in the art. In one or more embodiments, the metal includes one or more of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), and molybdenum (Mo). In a specific embodiment, the stripping line 162 includes tungsten (W).

[0060]

[0094] Referring to FIGS. 21A through 21C, a stripping contact including a bit line 168, a bit line contact 166, and a bit line stud 164 is formed.

[0061]

[0095] In other embodiments, a method of forming a semiconductor device is provided. The semiconductor device can have a three-dimensional vertical memory string including a drain-side select gate (SGD) transistor. In one or more embodiments, the method of forming a semiconductor device includes forming a plurality of memory holes extending through a memory stack. The memory stack includes alternating layers of a first layer and a second layer on a substrate. The transistor layer is deposited within the plurality of memory holes to form a plurality of memory strings. A bit line pad is formed on top of each of the plurality of memory strings. Thereafter, a drain-side select gate (SGD) transistor is formed on top of the memory stack. The memory stack is patterned to form a slit extending through the memory stack to the substrate. To form an opening in the memory stack, the first layer is removed and a dielectric material is deposited within the opening. The second layer is recessed to form a recessed region, and a low-resistance material is deposited in the recessed region. The slit is filled to form a filled slit. Thereafter, a drain-side select gate contact is formed, and a strap line is formed on top of the memory stack. The strap line contacts the drain-side select gate contact.

[0062]

[0096] Additional embodiments of the present disclosure are directed to a processing tool 900 for forming a memory device and the method described, as shown in FIG. 22.

[0063]

[0097] The cluster tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Robots 925, 935 are disposed within the central transfer stations 921, 931 and are configured to move a robot blade and a wafer to each of the plurality of sides.

[0064]

[0098] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. The various processing chambers provide separate processing areas separated from adjacent processing stations. The processing chambers can be any suitable chambers including, but not limited to, a pre-cleaning chamber, a buffer chamber, one or more transfer spaces, a wafer orientation / gassing chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a word line deposition chamber. The specific arrangement of the processing chambers and components can be changed according to the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0065]

[0099] In some embodiments, the cluster tool 900 includes a drain side select gate (SGD) patterning chamber. The drain side select gate (SGD) patterning chamber of some embodiments includes one or more selective etching chambers.

[0066]

[0100] In the embodiment shown in FIG. 22, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front surface 951 of the factory interface 950. The loading chamber 954 is shown on the left side and the unloading chamber 956 is shown on the right side, but those skilled in the art will understand that this represents only one possible configuration.

[0067]

[0101] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary, for example, according to the substrate processed within the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette in which a plurality of wafers are disposed within the cassette.

[0068]

[0102] Robot 952 is within factory interface 950 and can move between loading chamber 954 and unloading chamber 956. Robot 952 can transfer wafers from a cassette in loading chamber 954 through factory interface 950 to load lock chamber 960. Also, robot 952 can transfer wafers from load lock chamber 962 through factory interface 950 to a cassette in unloading chamber 956. As will be understood by those skilled in the art, factory interface 950 can have a plurality of robots 952. For example, factory interface 950 can have a first robot that transfers wafers between loading chamber 954 and load lock chamber 960 and a second robot that transfers wafers between load lock chamber 962 and unloading chamber 956.

[0069]

[0103] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is disposed. Robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located with respect to load lock chambers 960, 962, processing chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, robot 925 is a multi-arm robot that can independently move a plurality of wafers at a time. In some embodiments, the first transfer chamber 921 includes a plurality of robotic wafer transfer mechanisms. The robot 925 within the first transfer chamber 921 is configured to move wafers between the chambers around the first transfer chamber 921. Individual wafers are carried on a wafer transfer blade located at the distal end of the first robotic mechanism.

[0070]

[0104] After processing the wafer within the first section 920, the wafer can pass through the pass-through chamber to the second section 930. For example, chambers 922, 924 can be unidirectional or bidirectional pass-through chambers. Pass-through chambers 922, 924 can be used, for example, to cryogenically cool the wafer prior to processing in the second section 930, or to allow wafer cooling or post-processing before returning to the first section 920.

[0071]

[0105] System controller 990 communicates with a first robot 925, a second robot 935, a first plurality of processing chambers 902, 904, 916, 918, and a second plurality of processing chambers 906, 908, 910, 912, 914. System controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, system controller 990 can be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0072]

[0106] When generally executed by a processor, the process can be stored in the memory of system controller 990 as software routines that cause the processing chambers to execute the processes of the present disclosure. The software routines can be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be executed in hardware. Thus, the present process can be implemented in software, using a computer system, in hardware, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routines convert a general-purpose computer into a special-purpose computer (controller) that controls chamber operation such that the process is executed.

[0073]

[0107] In one or more embodiments, the processing tool comprises a central transfer station having a robot configured to move a wafer, a plurality of process stations, each process station being connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations including a drain side select gate (SGD) patterning chamber, and a controller connected to the central transfer station and the plurality of process stations, the controller being configured to activate the robot to move the wafer between the process stations and to control the processes performed at each of the process stations.

[0074]

[0108] One or more embodiments provide a non-transitory computer-readable medium that, when executed by a controller of a processing chamber, causes the processing chamber to perform the following operations: forming a plurality of memory holes extending through a memory stack, the memory stack including alternating layers of a first layer and a second layer on a substrate; depositing a transistor layer in the plurality of memory holes to form a plurality of memory strings; forming bit line pads on top of each of the plurality of memory strings; forming a drain side select gate (SGD) transistor on top of the memory stack; forming a slit extending through the memory stack to the substrate; removing the first layer to form an opening in the memory stack; depositing a dielectric material in the opening; recessing the second layer to form a recessed region; depositing a low resistance material in the recessed region; filling the slit to form a fill slit; forming a drain side select gate contact; and forming a strapping line on top of the memory stack that contacts the drain side select gate contact.

[0075]

[0109] In the context of describing the materials and methods discussed in this specification, particularly in the context of the following claims, the use of "a", "an", "the", and similar referents should be construed to include both the singular and the plural, unless otherwise indicated in this specification or clearly contradicted by the context. The recitation of numerical ranges in this specification is merely intended to serve as a shorthand for referring individually to each distinct value falling within that range, and each distinct value is incorporated into the specification as if it were individually recited herein. All methods described in this specification may be performed in any suitable order, unless otherwise indicated in this specification or clearly inconsistent with the context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the materials and methods and is not limiting of the scope, unless otherwise claimed. No language in this specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0076]

[0110] Throughout this specification, references to "one embodiment", "a particular embodiment", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in a particular embodiment", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0077]

[0111] Although the disclosure of this specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and changes within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor memory device, comprising a memory array including at least one drain-side select gate (SGD) transistor and at least one memory transistor, the memory array having at least one stripping region and at least one stripping contact, the at least one stripping contact connecting the drain-side select gate (SGD) transistor to a stripping line, and the at least one stripping region comprises a first plurality of memory holes having a lower density than a second plurality of memory holes in a non-stripping region. A semiconductor memory device.

2. The semiconductor memory device according to claim 1, wherein the drain-side select gate (SGD) transistor includes a polysilicon word line.

3. The semiconductor memory device according to claim 1, wherein the memory transistor includes a first material and a second material, and the first material has a higher resistance than the second material.

4. The semiconductor memory device according to claim 3, wherein the second material is adjacent to a slit region of the memory array.

5. The semiconductor memory device according to claim 1, wherein the stripping line includes one or more of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru).

6. A semiconductor memory device, a memory stack on a substrate, the memory stack including an alternating layer of word lines and a dielectric material, a plurality of memory transistors extending through the memory stack, a filling slit extending through the memory stack and adjacent to the plurality of memory transistors, A plurality of drain side select gate (SGD) transistors at the upper part of the memory stack, wherein at least one of the plurality of drain side select gate (SGD) transistors is electrically connected to a stripping line, and the plurality of drain side select gate (SGD) transistors comprising The word line includes a first material and a second material, the first material has a higher resistance than the second material, and the second material is adjacent to the filling slit The second material includes one or more of molybdenum (Mo), titanium (Ti), ruthenium (Ru), tantalum (Ta), or silicon compounds thereof, and the semiconductor memory device. Claim 7 The semiconductor memory device according to claim 6, wherein each of the plurality of drain side select gate (SGD) transistors includes a polysilicon word line. Claim 8 The semiconductor memory device according to claim 6, wherein each of the plurality of memory transistors includes one or more transistor layers selected from aluminum oxide (AlO), blocking oxide, trap material, tunnel oxide, and channel material. Claim 9 The semiconductor memory device according to claim 6, wherein the filling slit includes an insulator material selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride. Claim 10 The semiconductor memory device according to claim 6, wherein the substrate is a common source line, and the common source line includes a sacrificial layer and a polysilicon layer. Claim 11 The semiconductor memory device according to claim 6, wherein the stripping line includes one or more of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru). Claim 12 A method of forming a semiconductor device, comprising Forming a plurality of memory holes extending through a memory stack, wherein the memory stack includes alternating layers of a first layer and a second layer on a substrate, forming the plurality of memory holes; Depositing a transistor layer in the plurality of memory holes to form a plurality of memory strings; Forming bit line pads on top of each of the plurality of memory strings; Forming a drain side select gate (SGD) transistor on top of the memory stack; Forming a slit extending through the memory stack to the substrate; Removing the first layer to form an opening in the memory stack; Depositing a dielectric material in the opening; Indent the second layer to form an indented region; Depositing a low resistance material in the indented region; Filling the slit to form a filled slit; Forming a drain side select gate contact; Forming a strapping line on top of the memory stack that contacts the drain side select gate contact comprising, wherein the strapping line comprises one or more of tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), and ruthenium (Ru); A method.

13. The method according to claim 12, wherein the transistor layer comprises one or more of an aluminum oxide (AlO) layer, a blocking oxide layer, a trap layer, a tunnel oxide layer, and a channel layer.

14. The method according to claim 12, wherein the low-resistance material includes one or more of tungsten (W), ruthenium (Ru), aluminum (Al), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), nickel (Ni), or silicon compounds thereof.

15. The method according to claim 12, wherein the filling slit includes an insulator material selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride.

16. The method according to claim 12, wherein the substrate is a common source line, and the common source line includes a sacrificial layer and a polysilicon layer.

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