Layout design support apparatus, layout design support method, layout design support apparatus, and method of manufacturing a semiconductor device

Abstract

To provide a layout design support device capable of easily specifying a region having the same potential even when circuit elements having different breakdown voltages are mixed in one chip.SOLUTION: Whether or not to short-circuit one terminal connected to the first external terminal P1 and the other terminal in the circuit element connected to the first external terminal P1 to which the first potential identification label is attached is determined according to the determination criteria according to the element type information and the withstand voltage information. If it is determined that there is no short circuit, the first potential identification label is applied to the circuit element in the path from the first external terminal P1 to one terminal of the circuit element to identify the first equipotential region, and if it is determined that there is a short circuit, the determination is repeated for circuit elements connected to other terminals to identify the first equipotential region. The layout design support device 100 identifies a second equipotential region when receiving a second potential identification label to be added to a second external terminal P2.SELECTED DRAWING: Figure 5E

Description

Technical Field

[0001] The present invention relates to a layout design support device, a layout design support method, and a manufacturing method of a layout design support device and a semiconductor device.

Background Art

[0002] In a semiconductor integrated circuit, circuit elements having different operating voltages may be mixed on one chip. In such a case, for example, when a circuit element H operating at a high voltage V H and a circuit element L operating at a voltage V H lower than V are mixed on one chip, the circuit element H needs to have a breakdown voltage corresponding to the voltage V L , and the circuit element L needs to have a breakdown voltage corresponding to the voltage V H . L If each circuit element is not designed with a breakdown voltage corresponding to its operating voltage, the layout area of the entire chip will increase or the breakdown voltage of the circuit element will become insufficient. That is, if the entire chip is designed with a breakdown voltage corresponding to a high voltage V

[0003] H , it is necessary to increase the dimensions of each component in the circuit element and widen the distance between the components, so that the layout area of the circuit element L becomes larger than necessary. Furthermore, since it is necessary to increase the distance between the circuit elements, the layout area of the entire chip becomes larger. Conversely, if the entire chip is designed with a breakdown voltage corresponding to a low voltage V L L , the circuit element H cannot obtain a sufficient breakdown voltage. Therefore, when circuit elements operated by power supplies having different voltage values are mixed on one chip, each circuit element is designed to have a breakdown voltage corresponding to its operating voltage.

[0004] When designing a semiconductor integrated circuit, it is often the case that verification is performed using a layout design support device as to whether the layout of circuit elements and wiring is appropriate. When a user constructs a "netlist", which is data on connection information for each terminal of each circuit element, a layout design support device first executes DRC (Design Rule Check) to verify whether the layout created from the netlist satisfies the design rules according to the breakdown voltage. Then, the layout design support device adds the DRC error information as a verification result to the netlist and supports the layout design by displaying a layout diagram in which the netlist and the error information are combined.

[0005] In such a layout design support device, for example, for the purpose of efficiently performing layout verification of an integrated circuit including elements with different breakdown voltages in a short time, a dummy layer generated according to the breakdown voltage of each element is proposed to be displayed overlaid on the layout diagram together with the error information (see Patent Document 1). In addition, for example, in a semiconductor device in which two transistors with different breakdown voltages are mounted, a layout design support device is proposed that prevents the occurrence of a short circuit between wirings via dummy wirings so that the electrically isolated dummy wirings are not arranged adjacent to the wirings with a high breakdown voltage (see Patent Document 2).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] In one aspect of the present invention, even when circuit elements with different breakdown voltages are mixed on one chip, it is possible to easily identify regions of the same potential. Therefore, it becomes possible to layout the wiring space at the minimum size according to the breakdown voltage, and an object is to provide a layout design support device capable of designing a semiconductor device with a small chip size and low cost.

Means for Solving the Problems

[0008] A layout design support device according to an embodiment of the present invention is a layout design support device for an integrated circuit in which a plurality of circuit elements with different breakdown voltages are mixed, and a storage device that stores circuit connection data of the integrated circuit combining a first external terminal, a second external terminal, and circuit elements including the circuit elements to which element type information and breakdown voltage information are added; an input device that receives first potential information to be added to the first external terminal; In the circuit element connected to the first external terminal to which the first potential information is added, it is determined whether or not to short-circuit one terminal connected to the first external terminal and the other terminal according to a determination criterion according to the element type information and the breakdown voltage information, When it is determined that the one terminal and the other terminal of the circuit element are not short-circuited, the first potential information is added to the circuit elements on the path from the first external terminal to the one terminal of the circuit element to identify a first region of the same potential, When it is determined that the one terminal and the other terminal of the circuit element are short-circuited, the determination is repeatedly performed for the circuit element connected to the other terminal to identify the first region of the same potential; a control device; and When the input device receives second potential information to be added to the second external terminal, the control device identifies a second region of the same potential.

Advantages of the Invention

[0009] According to one aspect of the present invention, even when circuit elements with different breakdown voltages are mixed on one chip, it is possible to easily identify regions of the same potential. Therefore, it becomes possible to layout the wiring space at the minimum size according to the breakdown voltage, and it is possible to provide a layout design support device that can design a semiconductor device with a small chip size and low cost.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 6A

Figure 6B

Figure 7

[0011] In order for a layout design support apparatus as described in Patent Documents 1 and 2 to perform appropriate processing, it is necessary for a user to add a potential identification label as potential information to each circuit element of a terminal, an external terminal, and a wiring of a circuit element without omission and without mistake.

[0012] However, when there are a large number of wiring layers and the number of circuit elements and wirings in a netlist is enormous, there is a possibility that a user cannot add potential identification labels without omission and without mistake, and there are times when appropriate verification results cannot be obtained. Further, even if a user adds potential identification labels without omission and without mistake, when a high withstand voltage potential identification label is added to one terminal of a low withstand voltage circuit element and a low withstand voltage potential identification label is added to the other terminal of the circuit element, the layout design support apparatus may process it as if a high withstand voltage is applied between the terminals of the circuit element, and there are times when appropriate verification results cannot be obtained.

[0013] Therefore, when a potential identification label, which is a value of an operating voltage to be applied, is added by a user to one external terminal, the layout design support apparatus according to an embodiment of the present invention determines whether to short-circuit between terminals in a circuit element based on the withstand voltage information of the circuit element at the end of the wiring traced from the external terminal to which the potential information has been input. When this layout design support apparatus determines to short-circuit, it repeatedly determines the next circuit element connected to the terminal at the end of the short-circuit to extract circuit elements having the same potential, and adds the potential information input to the external terminal to each of the extracted circuit elements. As a result, even when circuit elements with different withstand voltages are mixed on one chip, the layout design support device according to an embodiment of the present invention can easily identify regions with the same potential.

[0014] Hereinafter, embodiments of the layout design support device according to the present invention will be described in detail with reference to the drawings, taking circuit connection data as a netlist and potential information as a potential identification label. In the drawings, the same reference numerals are assigned to the same components, and redundant descriptions may be omitted.

[0015] The layout design support device according to an embodiment of the present invention is a device that implements the layout design support method according to an embodiment of the present invention by executing the layout design support program according to an embodiment of the present invention. Therefore, the description of the layout design support program and the layout design support method according to an embodiment of the present invention is replaced with the description of the operation of the layout design support device according to an embodiment of the present invention. Also, the method for manufacturing a semiconductor device according to an embodiment of the present invention is a method for manufacturing a semiconductor device including a step of designing an integrated circuit of the semiconductor device using the layout design support device according to an embodiment of the present invention. Therefore, in the method for manufacturing a semiconductor device according to an embodiment of the present invention, steps such as manufacturing a semiconductor device from a semiconductor wafer are general steps, and thus the description thereof is omitted.

[0016] FIG. 1 is a block diagram showing the hardware configuration of the layout design support device according to the first embodiment. The layout design support device 100 according to the first embodiment has a function of executing a layout design support program and also has a function of executing various processes related to the design support of the layout of circuit elements arranged in the integrated circuit of the semiconductor device. As shown in FIG. 1, the layout design support device 100 includes a control device 110, an input device 120, a display device 130, a communication device 140, and a storage device 150.

[0017] The control device 110 is used to control the operation of the entire layout design support device 100. In addition to the function of executing the layout design support program, this control device 110 has functions for executing various processes.

[0018] Specifically, the control device 110 causes the user to input from the input device 120 a code indicating a circuit element including various circuit elements, external terminals, and wiring, and can construct a netlist 150a in which the terminals of the circuit elements and the external terminals are connected. Further, the control device 110 can create layout data 150b indicating a pattern of the physical shape of the integrated circuit from the netlist 150a. Furthermore, the control device 110 can display a layout diagram based on the layout data 150b for the user by the display device 130. Also, the control device 110 can create circuit diagram data 150c by applying circuit diagram symbols to the code based on the netlist 150a. The control device 110 can display a circuit diagram based on the circuit diagram data 150c for the user by the display device 130. This control device 110 stores the netlist 150a, the layout data 150b, and the circuit diagram data 150c in the storage device 150.

[0019] Examples of the circuit elements include various circuit elements, external terminals, wiring, and the like.

[0020] The circuit element has element type information and breakdown voltage information. The element type information is information indicating the type of the circuit element, and includes information indicating the number of terminals according to the type and the functions of the respective terminals. The type of the circuit element is not particularly limited and can be appropriately selected according to the purpose. Examples include MOS (Metal-Oxide-Semiconductor) transistors, bipolar transistors, diodes, capacitors, and the like. A potential identification label is added to each terminal of the circuit element. The breakdown voltage information may be selected by the user according to the operating voltage of the circuit element. Also, the breakdown voltage information may be classified as low breakdown voltage or high breakdown voltage according to the degree of the miniaturization process. For example, in an integrated circuit formed by a certain process, an element that requires an operating voltage of +100V may be regarded as a high breakdown voltage element, and an element that requires an operating voltage of +1.8V or +5.0V may be classified as a low breakdown voltage element. Further, in an integrated circuit formed by a finer process, an element that requires an operating voltage of +1.2V may be regarded as a high breakdown voltage element, and an element that requires an operating voltage of +0.8V may be distinguished as a low breakdown voltage element.

[0021] The external terminal is a part called a bonding pad in an IC (Integrated Circuit) chip and has breakdown voltage information. Also, a potential identification label is added to the external terminal by the user.

[0022] The wiring is the wiring on the IC chip and has breakdown voltage information. Note that a potential identification label is added to the wiring.

[0023] There is no particular limitation on the potential indicated by the potential identification label, and it can be appropriately selected according to the purpose. For example, it may be a high potential of +100V, a low potential of 0V, etc.

[0024] The control device 110 includes a processor 111, a RAM (Random Access Memory) 112, and a ROM (Read Only Memory) 113.

[0025] The processor 111 is a CPU (Central Processing Unit) or the like, and realizes various functions by executing the OS (Operating System) and various programs stored in the ROM 113 or the storage device 150.

[0026] The RAM 112 functions as a work area or the like where various programs such as the layout design support program 113a are expanded when executed by the processor 111.

[0027] The ROM 113 stores various programs such as the BIOS (Basic Input / Output System) including the layout design support program 113a. In this embodiment, although the layout design support program 113a is stored in the ROM 113, it is not limited to this. Instead of the ROM 113, for example, a solid state drive, magnetic tape, portable storage device, storage device on a network, etc. may be used. Examples of the portable storage device include a CD (Compact Disc) drive, a USB (Universal Serial Bus) memory, etc.

[0028] The input device 120 is, for example, a keyboard, a mouse, etc. This input device 120 receives various instructions and input of various information from the user.

[0029] The display device 130 is, for example, a display such as an LCD (Liquid Crystal Display). This display device 130 displays various data such as codes, netlists, circuit diagrams, layout diagrams, etc.

[0030] The communication device 140 is, for example, a wireless LAN (Local Area Network) module, a wired LAN module, etc. This communication device 140 communicably connects the layout design support device 100 to other personal computers, etc. through an Internet line, an Ethernet line, etc.

[0031] The storage device 150 is, for example, an HDD (Hard Disk Drive) that stores programs, data, etc. This storage device 150 stores, in addition to the netlist 150a, the layout data 150b, and the circuit diagram data 150c, a high withstand voltage design rule 150d and a low withstand voltage design rule 150e. The high breakdown voltage design rule 150d and the low breakdown voltage design rule 150e are design rules defined for each breakdown voltage regarding the layout. For example, the dimensions of circuit elements, the distances between circuit elements, the wiring widths, the wiring lengths, the wiring intervals, etc. are defined.

[0032] Figure 2 is a block diagram showing the functional configuration of the control device of the layout design support device in the first embodiment. As shown in Figure 2, as functions of the processor 111, a determination unit 111a, an equipotential region identification unit 111b, an update unit 111c, and a verification unit 111d are provided.

[0033] The determination unit 111a determines whether or not to short-circuit one terminal connected to the external terminal and the other terminal in the circuit element connected to the first external terminal to which the potential identification label is added, according to the determination criteria corresponding to the element type information and the breakdown voltage information. Specifically, when a potential identification label is added to one external terminal among a plurality of external terminals by the input device 120, the determination unit 111a determines whether or not to short-circuit between each terminal in the circuit element according to the determination criteria corresponding to the element type information and the breakdown voltage information of the circuit element at the end of the wiring traced starting from the external terminal to which the potential identification label is added.

[0034] Here, the "determination criteria" for the circuit element with high breakdown voltage information will be described. In addition, in the circuit element with low breakdown voltage information, it is determined that all terminals are short-circuited regardless of the element type information.

[0035] In this embodiment, if the element type information in the circuit element is an NMOS transistor and the breakdown voltage information is high breakdown voltage, the determination unit 111a determines not to short-circuit between the gate and drain and between the drain and source, and to short-circuit between the gate and source. In addition, depending on the type of high breakdown voltage NMOS transistor, there may be those that determine not to short-circuit all terminals. However, as described above, if the breakdown voltage information is low breakdown voltage, it is determined that all terminals are short-circuited.

[0036] Also, when the NMOS transistor is diode-connected, even if it has a high breakdown voltage, it is determined that a short circuit occurs between each terminal when shorted. Note that diode connection means connecting the gate and drain of the NMOS transistor, and is used when making the NMOS transistor operate like a diode.

[0037] If the element type information in the circuit element is a diode and the breakdown voltage information is high breakdown voltage, it is determined that a short circuit occurs when a DC voltage is applied in the forward direction, and it is determined that no short circuit occurs when a DC voltage is applied in the reverse direction. Note that if the breakdown voltage information is low breakdown voltage as described above, it is determined that both ends are short-circuited regardless of the direction of voltage application.

[0038] If the element type information in the circuit element is a capacitor and the breakdown voltage information is high breakdown voltage, it is determined that no short circuit occurs. Note that if the breakdown voltage information is low breakdown voltage as described above, it is determined that both ends are short-circuited.

[0039] Based on the above determination criteria, the determination unit 111a determines whether to short-circuit one terminal and the other terminal of the circuit element.

[0040] When the same potential region specifying unit 111b determines that the determination unit 111a does not short-circuit one terminal and the other terminal of the circuit element, it adds potential information to the circuit elements on the path from the external terminal to one terminal of the circuit element to specify the same potential region. Also, when the determination unit 111a determines that one terminal and the other terminal of the circuit element are short-circuited, the same potential region specifying unit 111b repeatedly makes determinations for the circuit elements connected to the other terminal to specify the same potential region.

[0041] In this way, starting from the first external terminal to which the first potential identification label is added by the user, the determination unit 111a determines whether to short-circuit between the terminals in the circuit element based on the element type information and withstand voltage information of the circuit element at the end of the traced wiring. When the determination unit 111a determines to short-circuit, it repeatedly determines the next circuit element connected to the terminal at the end of the short circuit to extract the circuit elements having the same potential. The same potential region specifying unit 111b can specify the first same potential region by adding the first potential identification label added to the first external terminal to each of the extracted circuit elements.

[0042] When specifying the second same potential region having a potential different from that of the first same potential region, the determination unit 111a and the same potential region specifying unit 111b specify the second same potential region starting from the second external terminal to which the second potential identification label is added by the user, in the same manner as when specifying the first same potential region.

[0043] Next, the operation of specifying the range of the same potential region performed by the layout design support apparatus 100 will be described with reference to FIGS. 1 and 2 according to the flowchart shown in FIG. 3.

[0044] FIG. 3 is a flowchart showing the flow of the process of specifying the range of the same potential region in the first embodiment. As shown in FIG. 3, first, the input device 120 receives the codes of the respective circuit elements, and the storage device 150 stores the received codes as a netlist (step S01). At this time, for the next step S02, the control device 110 extracts the external terminals from among the respective circuit elements and stores them in the netlist.

[0045] Next, when the input device 120 receives from the user the information on the potential identification label to be added to the external terminal (step S02), the determination unit 111a of the control device 110 determines whether to short-circuit between one terminal and the other terminal of the circuit element connected to the external terminal to which the potential identification label is added, based on a determination criterion (step S03). Note that the other terminal may be singular or plural.

[0046] When the determination unit 111a determines that a short circuit has occurred between one terminal and the other terminal of a circuit element connected to the external terminal, the same potential region specifying unit 111b adds the potential identification label to the circuit elements in the path up to one terminal of the next circuit element connected to the short-circuited other terminal (step S04). Subsequently, the determination unit 111a determines whether or not to short-circuit one terminal and the other terminal of the next circuit element (step S05). If it is determined that a short circuit is to be performed, the process returns to step S04, and the process of adding the potential identification label to the circuit elements in the path up to one terminal of the next circuit element is repeated until it is determined in step S05 that no short circuit is to be performed.

[0047] Also, in step S05, if the determination unit 111a determines that no short circuit is to be performed, it is determined whether or not there is an external terminal to which the potential identification label has not been added (step S06). If it is determined that there is an external terminal to which the potential identification label has not been added, the process returns to step S02, and the process of receiving information on the potential identification label from the user for the external terminal to which the potential identification label has not been added is performed. Note that the potential identification label added here may be a potential identification label having a potential different from the potential of the original potential identification label, or may be a potential identification label having the same potential. Then, in step S06, if it is determined that there is no external terminal to which the potential identification label has not been added, this operation is terminated.

[0048] Also, in step S03, when the determination unit 111a determines that a short circuit between one terminal and the other terminal of the circuit element connected to the external terminal is not performed, the same potential region specifying unit 111b adds a potential identification label to the circuit element between the external terminal with the potential identification label added and the circuit element connected to the external terminal (step S07). Subsequently, the process proceeds to step S06. When the determination unit 111a determines that there is an external terminal to which a potential identification label has not been added, the process returns to step S02, and the potential identification label is received from the user for the external terminal to which the potential identification label has not been added. Also, when the determination unit 111a determines that there is no external terminal to which a potential identification label has not been added, this operation ends.

[0049] In this way, even when circuit elements with different withstand voltages are mixed on one chip, the layout design support device 100 can easily specify the range of the same potential region.

[0050] Next, the operation of the layout design support device 100 will be described with reference to FIGS. 5A to 5E taking the circuit shown in FIG. 4 as an example.

[0051] FIG. 4 is a circuit diagram based on an example of circuit diagram data created from a netlist constructed by the user. As shown in FIG. 4, in the circuit 10, a DC power supply 11 is connected between an external terminal P1 and an external terminal P2. Also, the external terminal P2 and the negative electrode side of the DC power supply 11 are connected to a 0V potential. To the power supply voltage line 12 connected to the positive electrode side of the DC power supply 11, the power supply terminal of the amplifier 13 and the drain terminal of the NMOS transistor 14 are connected. The amplifier 13 has an output terminal connected to the gate terminal of the NMOS transistor 14. The NMOS transistor 14 has a source terminal connected to the external terminal P3 and the source terminal of the PMOS transistor 15. To the GND line 16 connected to the negative electrode side of the DC power supply 11, the GND terminal of the amplifier 17 and the drain terminal of the PMOS transistor 15 are connected. The amplifier 17 has an output terminal connected to the gate terminal of the PMOS transistor 15.

[0052] In this circuit 10, as shown in FIG. 5A, assuming that a potential identification label of "+100V" is added to the external terminal P1 by the user, a potential identification label of "+100V" (represented by hatching in the figure) is added to the power supply voltage line 12, which is the wiring connected to the external terminal P1.

[0053] Next, as shown in FIG. 5B, assuming that a potential identification label of "0V" is added to the external terminal P2 by the user, a potential identification label of "0V" is added to the GND line 16, which is the wiring connected to the external terminal P2.

[0054] Next, consider the NMOS transistor 14 and the PMOS transistor 15.

[0055] For the NMOS transistor 14, a potential identification label of "+100V" is added to the drain terminal. According to the determination criterion of this embodiment, it is assumed that the gate-source voltage is low and the transistor is short-circuited. Therefore, as shown in FIG. 5C, when the NMOS transistor 14 is in the ON state, the drain-source voltage is conductive, and a potential identification label of "+100V" is added to the source terminal, the gate terminal of the NMOS transistor 14, and the external terminal P3.

[0056] For the PMOS transistor 15, a potential identification label of "0V" is added to the drain terminal. According to the determination criterion of this embodiment, it is assumed that the gate-source voltage is low and the transistor is short-circuited. Therefore, as shown in FIG. 5D, when the PMOS transistor 15 is in the ON state, the drain-source voltage is conductive, and a potential identification label of "0V" is added not only to the source terminal, the gate terminal of the PMOS transistor 15, and the external terminal P3, but also to the source terminal and the gate terminal of the NMOS transistor 14.

[0057] Therefore, it can be understood that circuit elements to which potential identification labels of "+100V" and "0V" are redundantly added depending on the switching states of NMOS transistor 14 and PMOS transistor 15 require high voltage resistance. Therefore, circuit elements existing in region A surrounded by the dotted line in FIG. 5E, that is, the source terminal and gate terminal of NMOS transistor 14, the source terminal and gate terminal of PMOS transistor 15, and external terminal P3 can be classified as high voltage resistance region A, and the other regions can be classified as low voltage resistance regions.

[0058] In this way, for example, if there is a circuit element with low voltage resistance in the classified high voltage resistance region, the layout design support device 100 can guide the user to make corrections by adding error information to the circuit element and displaying it. Note that the layout design support device 100 identifies the range of regions with the same potential by adding potential identification labels to external terminals, but may also identify locations that become floating or GND potential depending on the circuit form as high voltage resistance regions. Also, for locations that cannot be identified only by adding potential identification labels to external terminals, the user may be allowed to identify them individually.

[0059] Here, returning to FIG. 2, the update unit 111c and the verification unit 111d will be described.

[0060] The update unit 111c updates the netlist 150a based on the potential identification labels added to each circuit element by the same potential region identification unit 111b.

[0061] The verification unit 111d verifies whether the layout data 150b created based on the netlist 150a updated by the update unit 111c satisfies the high voltage resistance design rule 150d and the low voltage resistance design rule 150e according to the voltage resistance information added to the circuit elements. Taking the explanatory diagram shown in FIG. 5E as an example, the verification unit 111d checks the NMOS transistor 14, PMOS transistor 15, external terminal P3, and the wiring connecting these, which are circuit elements within and in contact with region A of the high breakdown voltage region, using the high breakdown voltage design rule 150d, and checks the other circuit elements using the low breakdown voltage design rule 150e.

[0062] If there is an error, the verification unit 111d adds DRC error information to the layout data 150b, and causes the display device 130 to display a layout diagram formed by synthesizing the layout data 150b and the error information, thereby assisting the user in layout design by indicating the location of the error.

[0063] (Modification of the First Embodiment) In the above, as shown in FIGS. 5A to 5E, an example of the process of roughly specifying the range of the same potential region for the entire circuit was described. Next, with reference to FIGS. 6A and 6B, an example of the process of specifying the range of the same potential region for a part of a circuit with more circuit elements will be described.

[0064] FIGS. 6A and 6B are explanatory diagrams showing another example of the process of specifying the range of the same potential region in the first embodiment, and are obtained by further adding circuit elements to a part of the circuit diagram shown in FIG. 4. As shown in FIG. 6A, the power supply voltage line 21 of the circuit 20 is connected to the power supply terminal of the amplifier 22, the source terminals of the PMOS transistors 23 and 25 forming the current mirror circuit, and the drain terminal of the NMOS transistor 26. Also, the NMOS transistor 26 and the PMOS transistor 29 form a source follower push-pull circuit.

[0065] The PMOS transistor 23 is diode-connected, the drain terminal is connected to the drain terminal of the NMOS transistor 24, and the gate terminal is connected to its own drain terminal and the gate terminal of the PMOS transistor 25. The NMOS transistor 24 operates as a current source, with its gate terminal connected to the output terminal of the amplifier 22 and its source terminal connected to the GND potential. For the PMOS transistor 25, its drain terminal is connected to the gate terminal of the NMOS transistor 26, as well as the gate terminal and drain terminal of the NMOS transistor 27.

[0066] For the NMOS transistor 26, its source terminal is connected to the external terminal P4 and the source terminal of the PMOS transistor 29. The NMOS transistor 27 is diode-connected, and its source terminal is connected to the gate terminal and drain terminal of the NMOS transistor 28. The NMOS transistor 28 is diode-connected, and its source terminal is connected to the gate terminal of the NMOS transistor 29 and the GND potential. For the PMOS transistor 29, its drain terminal is connected to the GND potential.

[0067] When the layout design support device 100 performs a process of specifying the range of the same potential region for the circuit shown in FIG. 6A, it becomes as shown in FIG. 6B. As shown in FIG. 6B, the layout design support device 100 classifies the power supply voltage line 21 of the circuit 20 and the wiring connected to this power supply voltage line 21 into the low withstand voltage region B. Also, the layout design support device 100 processes all the terminals of the diode-connected PMOS transistor 23 as being short-circuited. The NMOS transistor 24, PMOS transistor 25, and NMOS transistor 26 are classified into the low withstand voltage region B with the drain terminal as the boundary. The amplifier 22, as well as the gate terminal and source terminal of the NMOS transistor 24, are classified into the low withstand voltage region C. In addition, the NMOS transistor 26 and PMOS transistor 29 that form the source follower push-pull circuit, as well as the diode-connected NMOS transistors 27 and 28, are classified into the high withstand voltage region D.

[0068] (Second Embodiment) FIG. 7 is a block diagram showing a control device of the layout design support apparatus according to the second embodiment. As shown in FIG. 7, the layout design support apparatus 200 according to the second embodiment is the same as that of the first embodiment, except that the control device 110 of the layout design support apparatus 100 in the first embodiment is replaced with a control device 210 provided with a dummy layer generation unit 211e. Therefore, the dummy layer generation unit 211e will be described here. Note that the determination unit 211a, the same potential region specifying unit 211b, the update unit 211c, and the verification unit 211d are the same as the determination unit 111a, the same potential region specifying unit 111b, the update unit 111c, and the verification unit 111d, respectively, and thus the description thereof will be omitted.

[0069] When creating layout data from a netlist, the dummy layer generation unit 211e generates a dummy layer according to the withstand voltage information added to circuit elements and arranges it on the layout. Specifically, the dummy layer generation unit 211e generates and arranges a dummy layer at the minimum pitch of each design rule so as not to connect to other wiring layers on the element isolation same potential region of the peripheral circuit section. By arranging this dummy layer, the loading effect is less likely to occur, so that variations in wiring width and cross-sectional shape can be reduced, and the electrical characteristics of circuit elements can be prevented from changing depending on the location.

[0070] Further, the verification unit 211d verifies whether or not the layout including the dummy layer generated and arranged by the dummy layer generation unit 211e satisfies the design rules according to the withstand voltage information. If there is an error, the layout design support apparatus 100 adds DRC error information to the layout data including the dummy layer, and displays a layout diagram formed by synthesizing the layout data and the error information on the display device 130 to assist the user in layout design by indicating the location where there is an error.

[0071] As described above, in the layout design support device according to an embodiment of the present invention, in a circuit element connected to a first external terminal to which a first potential identification label is added, it is determined whether or not to short-circuit one terminal connected to the first external terminal and another terminal, based on a determination criterion according to element type information and withstand voltage information. When this layout design support device determines that a short circuit does not occur, it adds a first potential identification label to the circuit elements on the path from the first external terminal to one terminal of the circuit element to identify the first equipotential region. When it determines that a short circuit occurs, it repeatedly makes a determination for the circuit elements connected to the other terminal to identify the first equipotential region. After identifying the first equipotential region, when this layout design support device receives a second potential identification label to be added to the second external terminal, it identifies the second equipotential region. Thereby, even when circuit elements with different withstand voltages are mixed in one chip, this layout design support device can easily identify the equipotential regions. For this reason, the layout design support device can layout the space between wirings to the minimum size according to the withstand voltage, and can design a semiconductor device with a small chip size and low cost.

[0072] In each of the above embodiments, the case of classifying into either a low withstand voltage region or a high withstand voltage region has been described, but it is not limited to the classification of two types of withstand voltage regions, and it may be classified into three or more types of withstand voltage regions. As three or more types of withstand voltage regions, for example, it may be classified as a region less than +10V, a region of +10V or more and less than +60V, a region of +60V or more and less than +100V, a region of +100V or more, and the like.

Explanation of Reference Numerals

[0073] 100, 200 Layout design support device 110, 210 Control device 111 Processor 111a, 211a Determination unit 111b, 211b Equipotential region identification unit 111c, 211c Update unit 111d, 211d Verification unit 211e Dummy layer generation unit 112 RAM 113 ROM 113a Layout design support program 120 Input device 130 Display device 140 Communication device 150 Storage device 150a Netlist 150b Layout data 150c Circuit diagram data P1, P2 External terminals

Claims

1. A layout design support device for an integrated circuit in which a plurality of circuit elements having different withstand voltages are mixed, a storage device that stores circuit connection data of the integrated circuit combined with a first external terminal, a second external terminal, and circuit elements including the circuit elements to which element type information and withstand voltage information are added; an input device that receives first potential information to be added to the first external terminal; in the circuit element connected to the first external terminal to which the first potential information is added, it is determined whether or not to short-circuit one terminal and the other terminal connected to the first external terminal according to a determination criterion according to the element type information and the withstand voltage information; when it is determined that the one terminal and the other terminal of the circuit element are not short-circuited, the first potential information is added to the circuit element on the path from the first external terminal to the one terminal of the circuit element to identify a first equipotential region; when it is determined that the one terminal and the other terminal of the circuit element are short-circuited, the determination is repeatedly performed for the circuit element connected to the other terminal to identify the first equipotential region, and a control device; having When the input device receives second potential information to be added to the second external terminal, the control device identifies a second equipotential region. A layout design support device characterized by this.

2. The first equipotential region and the second equipotential region are specified as low withstand voltage regions, The layout design support device according to claim 1, wherein a region specified in neither the first equipotential region nor the second equipotential region is specified as a high withstand voltage region.

3. When the circuit element having high withstand voltage exists in the low withstand voltage region or the circuit element having low withstand voltage exists in the high withstand voltage region, the control device adds error information to the target circuit element. The layout design support device according to claim 2.

4. The determination criteria are as follows: When the circuit element included in the high breakdown voltage region or the circuit element located at a position in contact with the high breakdown voltage region is an NMOS transistor, it is determined that the gate-drain and drain-source are not short-circuited, and the gate-source is short-circuited. The layout design support apparatus according to claim 2 or 3, including this.

5. When creating layout data from the circuit connection data, the control device creates the layout data including a dummy layer generated according to the breakdown voltage information added to the circuit element. The layout design support apparatus according to any one of claims 1 to 4.

6. A layout design support method for an integrated circuit in which a plurality of circuit elements having different breakdown voltages are mixed, including: Storing circuit connection data of the integrated circuit combined with a first external terminal, a second external terminal, and a circuit element including the circuit element to which element type information and breakdown voltage information are added; Receiving first potential information to be added to the first external terminal; In the circuit element connected to the first external terminal to which the first potential information is added, it is determined whether or not one terminal connected to the first external terminal and another terminal are short-circuited according to a determination criterion according to the element type information and the breakdown voltage information; When it is determined that the one terminal and the other terminal of the circuit element are not short-circuited, the first potential information is added to the circuit element on the path from the first external terminal to the one terminal of the circuit element to identify a first equipotential region; When it is determined that the one terminal and the other terminal of the circuit element are short-circuited, the determination is repeatedly performed for the circuit element connected to the other terminal to identify the first equipotential region; Including: When receiving second potential information to be added to the second external terminal, identifying a second equipotential region; A layout design support method characterized by including this.

7. A layout design support program for an integrated circuit in which a plurality of circuit elements with different withstand voltages are mixed, causing a computer to store circuit connection data of the integrated circuit obtained by combining a first external terminal, a second external terminal, and circuit elements including the circuit elements to which element type information and withstand voltage information are added, receive first potential information to be added to the first external terminal, in the circuit element connected to the first external terminal to which the first potential information is added, determining whether to short-circuit one terminal connected to the first external terminal and the other terminal according to a determination criterion according to the element type information and the withstand voltage information, when it is determined that the one terminal and the other terminal of the circuit element are not short-circuited, adding the first potential information to the circuit elements on the path from the first external terminal to the one terminal of the circuit element to identify a first equipotential region, when it is determined that the one terminal and the other terminal of the circuit element are short-circuited, repeating the determination for the circuit element connected to the other terminal to identify the first equipotential region, including when receiving second potential information to be added to the second external terminal, identifying a second equipotential region, A layout design support program, characterized by including the above.

8. A method for manufacturing a semiconductor device, characterized by including a step of designing using the layout design support device according to any one of Claims 1 to 5.

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