Semiconductor device

Abstract

To impart excellent electric characteristics to a semiconductor device.SOLUTION: A semiconductor device comprises a first insulation layer, a second insulation layer, an oxide semiconductor layer, and first to third conductive layers. The oxide semiconductor layer includes a region in contact with the first insulation layer. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulation layer includes a region in contact with the oxide semiconductor layer. The third conductive layer includes a region in contact with the second insulation layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are provided separated from each other. The third region is provided between the first region and the second region. The third region and the third conductive layer include an overlapping region via the second insulation layer. The first region and the second region include a portion having a higher carbon concentration than the third region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes, as an example, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a storage device, a display device, and an electronic device may include a semiconductor device.

[0003] Note that in this specification and the like, the semiconductor device generally refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a storage device, a display device, and an electronic device may include a semiconductor device. a display device, and an electronic device may include a semiconductor device.

Background Art

[0004] Techniques for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface have drawn attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). As a semiconductor thin film applicable to transistors, silicon-based semiconductor materials are widely known, but oxide semiconductors are attracting attention as other materials. Note that in this specification, the display device also simply refers to an image display device. As a semiconductor thin film applicable to transistors, silicon-based semiconductor materials are widely known, but oxide semiconductors are attracting attention as other materials. Note that in this specification, the display device also simply refers to an image display device.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to impart good electrical characteristics to a semiconductor device. Another object is to provide a semiconductor device having a high on-state current. Another object of the present invention is to provide a semiconductor device suitable for a highly integrated semiconductor device. Another object of the present invention is to provide a semiconductor device with low power consumption. Another object is to provide a highly reliable semiconductor device. Alternatively, the present invention aims to provide a semiconductor device that retains data even when the power supply is cut off. Another object of the present invention is to provide a novel semiconductor device. It is another object of the present invention to provide a method for manufacturing the semiconductor device.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other problems from descriptions such as the surface and claims.

Means for Solving the Problems

[0009] One aspect of the present invention relates to a transistor having an oxide semiconductor layer in a channel formation region.

[0010] One aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The oxide semiconductor layer has a region in contact with the first insulating layer. The first conductive layer is electrically connected to the oxide semiconductor layer. The second conductive layer is electrically connected to the oxide semiconductor layer. The second insulating layer has a region in contact with the oxide semiconductor layer. The third conductive layer has a region in contact with the second insulating layer. The second insulating layer has a region that can function as a gate insulating film. The first conductive layer has a region that can function as one of a source electrode or a drain electrode. The second conductive layer has a region that can function as the other of the source electrode or the drain electrode. The third conductive layer has a region that can function as a gate electrode. The oxide semiconductor layer has first to third regions. The first region and the second region are provided separately. The third region is provided between the first region and the second region. The third region and the third conductive layer have a region overlapping via the second insulating layer. The first region and the second region have portions where the carbon concentration is higher than that in the third region. The semiconductor device is characterized in that. Note that ordinal numbers such as "first" and "second" in this specification and the like are attached to avoid confusion of components and are not numerically limiting.

[0011]

[0012] ​​​​​​​​ In the first region and the second region, the concentration of one or more elements selected from phosphorus, arsenic, antimony, boron, aluminum , silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and hydrogen may be higher than that in the third region.

[0013] Also, the first region and the second region may be configured to have a region in contact with a hydrogen-containing insulating nitride film.

[0014] Another aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The oxide semiconductor layer has a region in contact with the first insulating layer, the first conductive layer is electrically connected to the oxide semiconductor layer, the second conductive layer is electrically connected to the oxide semiconductor layer, the second insulating layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the second insulating layer, the second insulating layer has a region that can function as a gate insulating film, the first conductive layer has a region that can function as one of a source electrode or a drain electrode, the second conductive layer has a region that can function as the other of the source electrode or the drain electrode, the third conductive layer has a region that can function as a gate electrode, the oxide semiconductor layer has first to fifth regions, the first region and the second region are provided separately, the first region has a region overlapping with the first conductive layer, the second region has a region overlapping with the second conductive layer, the third region and the third conductive layer have a region overlapping via the second insulating layer, and the third region is between the first region and the second region. electrode, the oxide semiconductor layer has first to fifth regions, the first region and the second region are provided separately, the first region has a region overlapping with the first conductive layer, the second region has a region overlapping with the second conductive layer, the third region and the third conductive layer have a region overlapping via the second insulating layer, and the third region is between the first region and the second region. layer have a region overlapping via the second insulating layer, and the third region is between the first region and the second is provided between regions, the fourth region is provided between the first region and the third region, and the fifth region is provided between the second region and the third region, and the fourth region and the fifth region have portions with a carbon concentration higher than those of the first region, the second region, and the third region, characterizing the semiconductor device.

[0015] In the fourth region and the fifth region, the concentration of one or more elements selected from phosphorus, arsenic, antimony, boron, aluminum , silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and hydrogen may be configured to have a portion higher than those of the first region, the second region, and the third region.

[0016] Further, the fourth region and the fifth region may be configured to have a region in contact with a hydrogen-containing nitride insulating film.

[0017] The semiconductor device may be configured such that a fourth conductive layer overlapping the oxide semiconductor layer is formed via a first insulating layer.

[0018] The oxide semiconductor layer may have a first and a second oxide semiconductor layer, and may be configured to be provided in the order of the second oxide semiconductor layer, the first oxide semiconductor layer from the side of the first insulating layer. Also , the first oxide semiconductor layer may be provided so as to cover the second oxide semiconductor layer.

[0019] In the configuration of the oxide semiconductor layer, the first and second oxide semiconductor layers have In, Zn, , and M (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), and the first oxide semiconductor layer preferably has a larger atomic ratio of M to In than the second oxide semiconductor layer. ​​​​​

[0020] Further, the oxide semiconductor layer has first to third oxide semiconductor layers, and from the side of the first insulating layer, the third oxide semiconductor layer, the second oxide semiconductor layer, and the first oxide semiconductor layer are provided in this order. It may have such a configuration. Further, the first oxide semiconductor layer may be provided so as to cover the second oxide semiconductor layer and the third oxide semiconductor layer.

[0021] In the configuration of the oxide semiconductor layer, the first to third oxide semiconductor layers contain In, Zn, and M (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), and the atomic ratio of M to In in the first and third oxide semiconductor layers is preferably larger than that in the second oxide semiconductor layer.

[0022] Further, a non-single crystal can be used for the oxide semiconductor layer, and it preferably has a crystal oriented along the c-axis.

[0023] Another aspect of the present invention is to form an oxide semiconductor film on an insulating surface, form a first resist mask on the oxide semiconductor film, selectively etch the oxide semiconductor film using the first resist mask to form an oxide semiconductor layer, peel off the first resist mask, form a first insulating film on the oxide semiconductor layer, form a conductive film on the first insulating film, form a second resist mask on the conductive film, and selectively etch the conductive film and the first insulating film using the second resist mask to form a laminate composed of a first insulating layer and a conductive layer, expose a first region and a second region of the oxide semiconductor layer, add impurities to the first region and the second region by plasma treatment to form oxygen vacancies, and form a laminate composed of a first insulating layer and a conductive layer while exposing a first region and a second region of the oxide semiconductor layer, and form oxygen vacancies by adding impurities to the first region and the second region by plasma treatment. Peel off the resist mask, and form a second insulating film containing hydrogen on the first region and the second region of the oxide semiconductor layer, the first insulating layer, and the conductive layer, and diffuse hydrogen from the second insulating film into the first region and the second region to reduce the resistance of the first region and the second region. This is a method for manufacturing a semiconductor device.

Advantages of the Invention

[0024] By using one aspect of the present invention, good electrical characteristics can be imparted to a semiconductor device. Or, a semiconductor device with a high on-current can be provided. Or, a semiconductor device suitable for high-speed operation can be provided. A semiconductor device with a high integration degree can be provided. Or, a semiconductor device with low power consumption can be provided. Or, a highly reliable semiconductor device can be provided. Or, a semiconductor device that can retain data even when the power supply is cut off can be provided. Or, a novel semiconductor device can be provided. Also, a method for manufacturing the above semiconductor device can be provided.

[0025] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be obvious from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0026]

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Mode for Carrying Out the Invention

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description content of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description may be omitted. In addition, the matching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings. Furthermore, in the present specification and the like, when it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, but also includes those other than the connection relationship shown in the figure or the text.

[0028] In addition, in the present specification and the like, when it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, but also includes those other than the connection relationship shown in the figure or the text.

[0029] As an example of the case where X and Y are electrically connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode One or more of an audio, a display element, a light-emitting element, a load, etc. can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch enters a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching a path through which current flows.

[0030] As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power source circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase a signal amplitude or a current amount, an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) can be connected between X and Y by one or more. Note that, as an example, even if another circuit is sandwiched between X and Y, when the signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0031] When it is explicitly described that X and Y are connected, it includes the case where X and Y are electrically connected (that is, the case where they are connected with another element or another circuit sandwiched between X and Y), the case where X and Y are functionally connected (that is, the case where they are functionally connected with another circuit sandwiched between X and Y), and the case where X and Y are directly connected (that is, including the case where they are connected without another element or another circuit being sandwiched between X and Y) That is, when it is explicitly described that they are electrically connected, it is considered the same as the case where it is only explicitly described that they are connected.

[0032] Note that even when components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of multiple components combined. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the component of the wiring function and the component of the electrode function combined. Therefore, the electrically connected in this specification also includes such a case where one conductive film has the functions of multiple components combined within its scope.

[0033] Note that, for example, when the source (or the first terminal, etc.) of the transistor is electrically connected to X via (or without passing through) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without passing through) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows.

[0034] For example, "X, Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and X, the source (or the first ​​​​​​​​​The drain of the transistor (or the second terminal, etc.) is electrically connected in the order of the terminal of 1, etc., and Y.」 It can be expressed as. Or, 「The source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.」 It can be expressed as. Or, 「X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.」 It can be expressed as. By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). It can be expressed as 「... are electrically connected in the order of the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y.」 Or, 「The source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.」 Or, 「X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.」 By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). The source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.」 It can be expressed as. Or, 「X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.」 By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). The source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.」 It can be expressed as. Or, 「X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.」 By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.」 It can be expressed as. Or, 「X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.」 By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). It can be expressed as 「... are electrically connected in the order of the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y.」 Or, 「The source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.」 Or, 「X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.」 By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). It can be expressed as 「... are electrically connected in the order of the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y.」 Or, 「The source of the transistor (or the first terminal, etc.) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.」 Or, 「X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.」 By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.」 By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). By using the same expression method as these examples to define the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0035] In addition, in this specification, etc., transistors can be formed using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil, etc. can be used. In addition, in this specification, etc., transistors can be formed using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil, etc. can be used. In addition, in this specification, etc., transistors can be formed using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil, etc. can be used. In addition, in this specification, etc., transistors can be formed using various substrates. The type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a stainless steel foil, etc. can be used. Substrate, tungsten substrate, substrate with tungsten foil, flexible substrate, bonding film, paper containing fibrous material, or base film, etc. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass, etc. Examples of flexible substrates include plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or flexible synthetic resins such as acrylic. Examples of bonding films include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride, etc. Examples of base films include polyester, polyamide, polyimide, inorganic vapor deposition film, or papers, etc. In particular, by manufacturing transistors using semiconductor substrates, single crystal substrates, or SOI substrates, etc., transistors with less variation in characteristics, size, or shape, etc., high current capacity, and small size can be manufactured. When a circuit is configured with such

[0036] transistors, power consumption reduction of the circuit or high integration of the circuit can be achieved. Also, as the substrate, a flexible substrate can be used, and transistors can be formed directly on the flexible substrate. Or a release layer can be provided between the substrate and the transistors. The release layer Configurations of the stacked structure, configurations in which an organic resin film such as polyimide is formed on a substrate, etc. can be used. This is possible.

[0037] That is, a transistor can be formed using a certain substrate, and then the transistor can be transferred to another substrate and arranged on the other substrate. As an example of the substrate to which the transistor is transferred, in addition to the substrate on which the above-described transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, recycled polyester), etc.), a leather substrate, or a rubber substrate, etc. By using these substrates, it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a device that is difficult to break, impart heat resistance, reduce weight, or make it thinner.

[0038] (Embodiment 1) In this embodiment, a transistor according to one aspect of the present invention will be described with reference to the drawings.

[0039] A transistor according to one aspect of the present invention can use silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or an oxide semiconductor, etc. in the channel formation region. In particular, it is preferable to form the channel formation region including an oxide semiconductor having a larger bandgap than silicon.

[0040] For example, as the above oxide semiconductor, at least indium (In) or zinc (Zn)​​​​​​​​​​​​ Preferably, it contains. More preferably, it is composed of an In-M-Zn-based oxide (M is a metal such as Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce, or Hf).

[0041] Hereinafter, unless otherwise specified, as an example, a transistor including an oxide semiconductor in a channel formation region will be described.

[0042] FIGS. 1(A) and (B) are a top view and a cross-sectional view of a transistor 101 according to one embodiment of the present invention. FIG. 1(A) is a top view, and a cross-section in the direction of the dashed line A1-A2 shown in FIG. 1(A) corresponds to FIG. 1 (B). Also, a cross-section in the direction of the dashed line A3-A4 shown in FIG. 1(A) corresponds to FIG. 2(A) or FIG. 2(B). In the above drawings, some elements are enlarged, reduced, or omitted for clarity. Also, the direction of the dashed line A1-A2 may be referred to as the channel length direction, and the direction of the dashed line A3-A4 may be referred to as the channel width direction.

[0043] Note that the channel length is, for example, in the top view of the transistor, the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed. ​​​​

[0044] Also, the channel width refers to, for example, the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) overlaps with the gate electrode, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. Note that depending on the structure of the transistor, there may be a difference between the actual channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. In the case of a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, it is difficult to estimate the effective channel width from the design value. That is, in one transistor, the channel width may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. That is, in one transistor, the channel width may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. In this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed. In this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0045] Note that depending on the structure of the transistor, there may be a difference between the actual channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view.

[0046] In the case of a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, it is difficult to estimate the effective channel width from the design value. In order to measure it, an assumption that the shape of the semiconductor is known is necessary. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0047] Therefore, in this specification, in the top view of the transistor, the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap is defined as the apparent channel width, which is sometimes referred to as the "surrounded channel width (SCW: Surrounded Channel W idth)". Also, in this specification, when simply described as the channel width , it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. In addition, the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image, etc. and analyzing the image. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. In addition, the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image, etc. and analyzing the image. In addition, the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image, etc. and analyzing the image. In addition, the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image, etc. and analyzing the image. For example, the values can be determined by obtaining a cross-sectional TEM image and analyzing the image. The values can be determined.

[0048] In addition, when calculating the field-effect mobility of the transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case of calculating using the effective channel width. In that case, the value may be different from the case of calculating using the effective channel width. The transistor 101 includes an insulating layer 120 in contact with the substrate 110, an oxide semiconductor layer 130 in contact with the insulating layer 120, a gate insulating film 160 in contact with the oxide semiconductor layer 130, a gate electrode layer 170 in contact with the gate insulating film 160, an insulating layer 175 covering the oxide semiconductor layer 130, the gate insulating film 160, and the gate electrode layer 170, and an insulating layer 180 in contact with the insulating layer 175.

[0049] The transistor 101 includes an insulating layer 120 in contact with the substrate 110, an oxide semiconductor layer 130 in contact with the insulating layer 120, a gate insulating film 160 in contact with the oxide semiconductor layer 130, a gate electrode layer 170 in contact with the gate insulating film 160, an insulating layer 175 covering the oxide semiconductor layer 130, the gate insulating film 160, and the gate electrode layer 170, and an insulating layer 180 in contact with the insulating layer 175. The transistor 101 includes an insulating layer 120 in contact with the substrate 110, an oxide semiconductor layer 130 in contact with the insulating layer 120, a gate insulating film 160 in contact with the oxide semiconductor layer 130, a gate electrode layer 170 in contact with the gate insulating film 160, an insulating layer 175 covering the oxide semiconductor layer 130, the gate insulating film 160, and the gate electrode layer 170, and an insulating layer 180 in contact with the insulating layer 175. The transistor 101 includes an insulating layer 120 in contact with the substrate 110, an oxide semiconductor layer 130 in contact with the insulating layer 120, a gate insulating film 160 in contact with the oxide semiconductor layer 130, a gate electrode layer 170 in contact with the gate insulating film 160, an insulating layer 175 covering the oxide semiconductor layer 130, the gate insulating film 160, and the gate electrode layer 170, and an insulating layer 180 in contact with the insulating layer 175. The transistor 101 includes an insulating layer 120 in contact with the substrate 110, an oxide semiconductor layer 130 in contact with the insulating layer 120, a gate insulating film 160 in contact with the oxide semiconductor layer 130, a gate electrode layer 170 in contact with the gate insulating film 160, an insulating layer 175 covering the oxide semiconductor layer 130, the gate insulating film 160, and the gate electrode layer 170, and an insulating layer 180 in contact with the insulating layer 175. Through the openings provided in the insulating layer 175 and the insulating layer 180, the oxide semiconductor layer 130 is electrically connected to the source electrode layer 140 and the drain electrode layer 150, and an insulating layer 185 formed on the above configuration is provided. Further, an insulating layer 190 (planarization film) or the like may be provided in contact with the insulating layer 185 as necessary.

[0050] Note that the functions of "source" and "drain" of a transistor may be interchanged when transistors with different polarities are employed or when the direction of current changes in a circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable. Also, "electrode layer" can be rephrased as "wiring".

[0051] In addition, although an example in which the gate electrode layer 170 is formed of two layers, the conductive layer 171 and the conductive layer 172, is illustrated, it may be a single layer or a laminate of three or more layers.

[0052] In addition, although an example in which the source electrode layer 140 is formed of two layers, the conductive layer 141 and the conductive layer 142, is illustrated, it may be a single layer or a laminate of three or more layers. The same applies to the drain electrode layer 150 formed of the conductive layer 151 and the conductive layer 152.

[0053] When the channel width is shortened, as shown in FIG. 2(A), it is preferable to form the upper surface of the oxide semiconductor layer 130 so as to have a curvature. By having the upper surface with a curvature, the covering property of the film formed on the upper part can be improved. However, when the channel width is relatively long , as shown in FIG. 2(B), there may be a flat region on the upper part of the oxide semiconductor layer 130. ​​​​​Oh, the description regarding the channel width is also applicable to other transistors disclosed in this specification. .

[0054] The transistor according to one aspect of the present invention has a self-aligned structure in which there is no overlapping region between the gate electrode layer 170, the source electrode layer 140, and the drain electrode layer 150. The transistor with a self-aligned structure has extremely small parasitic capacitance between the gate electrode layer, the source electrode layer, and the electrode layers, so it is suitable for high-speed operation applications.

[0055] The oxide semiconductor layer 130 in the transistor 101 has regions 231 (source region) and 232 (drain region) provided separately, and a region 233 (channel region) provided between the regions 231 and 232 and overlapping with the gate electrode layer 170 via the gate insulating film 160.

[0056] Here, the regions 231 and 232 have regions in contact with the insulating layer 175 as shown in FIG. 1(B). By using an insulating material containing hydrogen for the insulating layer 175, the regions 231 and 232 can be made to have low resistance.

[0057] Specifically, due to the interaction between the oxygen vacancies generated in the regions 231 and 232 by the process until the formation of the insulating layer 175 and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232, the regions 231 and 232 become low-resistance n-type. Note that, as the insulating material containing hydrogen, for example, a silicon nitride film or an aluminum nitride film can be used.

[0058] Also, impurities for forming oxygen vacancies and increasing the conductivity are introduced into the regions 231 and 232. It may be added. As an impurity for forming oxygen vacancies in the oxide semiconductor layer, for example, phosphorus , arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon , krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon One or more selected from any of them can be used. As a method for adding the impurity , a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used.

[0059] When the above elements are added as impurity elements to the oxide semiconductor layer, the bonds between metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen vacancies are formed. Due to the interaction between the oxygen vacancies contained in the oxide semiconductor layer and hydrogen remaining or added later in the oxide semiconductor layer, the conductivity of the oxide semiconductor layer can be increased.

[0060] In addition, as a method for adding the above impurity, it is preferable to use a plasma treatment method that is easy to handle large areas. For example, a substrate on which a transistor is formed is placed on one (cathode side) of a pair of electrodes so as to be biased, and high-frequency power (such as 13.56 MHz) is applied between the pair of electrodes in an argon atmosphere under reduced pressure to generate argon plasma for treatment. At this time, a part of the gate electrode layer 170 may be sputtered and deposited on the end portion of the gate insulating film 160, resulting in a short-circuit state between the regions 231 and 232 and the gate electrode layer 170.

[0061] Therefore, when performing the plasma treatment method, a resist mask for forming the patterns of the gate electrode layer 170 and the gate insulating film 16 0 is left on the gate electrode layer 170 and the plasma treatment is performed. It is preferable to perform a plasma treatment.

[0062] By performing a plasma treatment with the resist mask left on the gate electrode layer 170, sputtering of the gate electrode layer 170 is suppressed, so that short - circuit prevention between the regions 231 and 232 and the gate electrode layer 170 and reduction of gate leakage current can be achieved. Also, since a part of the resist mask is sputtered, for example, when treated with an argon plasma, argon and carbon can be added to the regions 231 and 232. As described above, when carbon is added to the oxide semiconductor layer, oxygen deficiency is formed, so that the conductivity of the oxide semiconductor layer can be further increased.

[0063] That is, the regions 231 and 232 in the transistor 101 have portions where the concentration of impurities that form the above - described oxygen deficiency is higher than that in the region 233. Also, since hydrogen enters the oxygen deficiency, the regions 231 and 232 have portions where the hydrogen concentration is higher than that in the region 233. By forming a transistor with such a configuration, the source region and the drain in region can be made to have lower resistance, and the on - current of the transistor can be increased. .

[0064] Note that an element that forms an oxygen deficiency in the oxide semiconductor layer is described as an impurity (impurity element). Representative examples of impurity elements include boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, noble gas elements, etc. Representative examples of noble gas elements include helium, neon, argon, krypton, and xenon.

[0065] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of an impurity element, the oxygen vacancies Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide semiconductor The conductivity of the oxide semiconductor increases and it becomes a conductor. An oxide semiconductor that has become a conductor is called an oxide conductor. In general, oxide semiconductors have a large energy gap and are therefore highly resistant to visible light. On the other hand, an oxide conductor is an oxide semiconductor having a donor level near the conduction band. Therefore, the effect of absorption due to the donor level is small, and it is oxidized by visible light. It has the same level of transparency as a semiconductor.

[0066] Here, the resistance of a film formed of an oxide conductor (hereinafter referred to as an oxide conductor layer) The temperature dependency of the rate will be explained with reference to FIG.

[0067] Here, a sample having an oxide conductor layer was prepared. The oxide conductor layer (OC_SiN x ), In a doping apparatus, argon is added to the oxide semiconductor layer and the oxide semiconductor layer is in contact with the silicon nitride film. The oxide conductor layer (OC_Ar doped + SiN x ), or Pla In the plasma processing apparatus, the oxide semiconductor layer is exposed to argon plasma, and the silicon nitride film is The oxide conductor layer formed by contacting with the plasma (OC_Ar+SiN x ) The silicon nitride film contains hydrogen.

[0068] Oxide conductor layer (OC_SiN x The method for preparing a sample containing the ZnO film is as follows. , after forming a silicon oxynitride film with a thickness of 400 nm by plasma CVD method, it was exposed to oxygen plasma, and oxygen ions were added to the silicon oxynitride film to form a silicon oxynitride film that releases oxygen by heating. Next, a silicon oxynitride film that releases oxygen by heating was formed. Then, an In-Ga-Zn oxide film with a thickness of 100 nm was formed on the silicon oxynitride film that releases oxygen by heating using a sputtering target with an atomic ratio of In:Ga:Zn = 5:5:6 by sputtering method, and heat-treated in a nitrogen atmosphere at 450 °C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450 °C. Next, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD method. Then, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 35 0 °C. A method for producing a sample containing an oxide conductor layer (OC_Ar dope + SiN ) is shown below. On a glass substrate, a silicon oxynitride film with a thickness of 400 nm was formed by plasma CVD method, and then exposed to oxygen plasma, and oxygen ions were added to the silicon oxynitride film to form a silicon oxynitride film that releases oxygen by heating. Next, an In-Ga-Zn oxide film with a thickness of 100 nm was formed on the silicon oxynitride film that releases oxygen by heating using a sputtering target with an atomic ratio of In:Ga:Zn = 5:5:6 by sputtering method, and heat-treated in a nitrogen atmosphere at 450 °C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450 °C.

[0069] Next, using a doping device, argon with an acceleration voltage of 10 kV and a dose amount of 5×10 x / cm was added to the In-Ga-Zn oxide film to form oxygen vacancies in the In-Ga-Zn oxide film. Then, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD method. Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 35 0 °C. A method for producing a sample containing an oxide conductor layer (OC_Ar dope + SiN ) is shown below. On a glass substrate, a silicon oxynitride film with a thickness of 400 nm was formed by plasma CVD method, and then exposed to oxygen plasma, and oxygen ions were added to the silicon oxynitride film to form a silicon oxynitride film that releases oxygen by heating. Next, an In-Ga-Zn oxide film with a thickness of 100 nm was formed on the silicon oxynitride film that releases oxygen by heating using a sputtering target with an atomic ratio of In:Ga:Zn = 5:5:6 by sputtering method, and heat-treated in a nitrogen atmosphere at 450 °C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450 °C. Next, using a doping device, argon with an acceleration voltage of 10 kV and a dose amount of 5×10 / cm 14 was added to the In-Ga-Zn oxide film to form oxygen vacancies in the In-Ga-Zn oxide film. Then, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD method. 2 Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 35 0 °C. A silicon nitride film was formed. Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 350 °C. treated.

[0070] A method for preparing a sample containing an oxide conductor layer (OC_Ar plasma + SiN x ) is shown below. On a glass substrate, a silicon oxynitride film with a thickness of 400 nm was formed by plasma CVD method. After that, by exposing it to oxygen plasma, a silicon oxynitride film that releases oxygen by heating was formed. Next, on the silicon oxynitride film that releases oxygen by heating, by sputtering method using a sputtering target with an atomic ratio of In :Ga:Zn = 5:5:6, an In-Ga-Zn oxide film with a thickness of 100 nm was formed and heat-treated in a nitrogen atmosphere at 450 °C. After that, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450 °C. Next, in a plasma processing device argon plasma was generated, and oxygen deficiency was formed by colliding accelerated argon ions with the In-Ga-Z n oxide film. Next, a 1 00 nm silicon nitride film was formed by plasma CVD method. Next, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 350 °C. treated.

[0071] Next, the results of measuring the resistivity of each sample are shown in Fig. 57. Here, the resistivity was measured by the four-terminal van-der-Pauw method. In Fig. 57, the horizontal axis represents the measurement temperature, and the vertical axis represents the resistivity. Also, the measurement results of the oxide conductor layer (OC_SiN x ) are shown by square marks, and the measurement results of the oxide conductor layer (OC_Ar plasma + SiN x ) are shown by triangular marks, and the measurement results of the oxide conductor layer (OC_Ar dope + SiN x ) are shown by round marks.

[0072] Note that, although not shown, the oxide semiconductor layer not in contact with the silicon nitride film has a high resistivity and it was difficult to measure the resistance rate. Therefore, it can be seen that the resistivity of the oxide conductor layer is lower than that of the oxide semiconductor layer.

[0073] As can be seen from FIG. 57, the oxide conductor layer (OC_Ar dope+SiN x ) and the oxide conductor layer (OC_Ar plasma+SiN x ) have small resistivity fluctuations in an environment containing oxygen deficiency and hydrogen. Typically, at 80K or higher and 290K or lower, the resistivity fluctuation rate is less than ±20%. Or, at 150K or higher and 250K or lower, the resistivity fluctuation rate is less than ±10%. That is, the oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide or are substantially coincident. Therefore, by using the oxide conductor layer as the source region and the drain region of the transistor, the contact between the oxide conductor layer and the conductive film functioning as the source electrode and the drain electrode becomes an ohmic contact, and the contact resistance between the oxide conductor layer and the conductive film functioning as the source electrode and the drain electrode can be reduced. Further, since the resistivity of the oxide conductor has low temperature dependence, the amount of variation in the contact resistance between the oxide conductor layer and the conductive film functioning as the source electrode and the drain electrode is small, and it is possible to fabricate a highly reliable transistor.

[0074] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 3(A) and (B). FIG. 3(A) is a top view of the transistor 102, and the cross section in the direction of the dashed-dotted line B1-B 2 shown in FIG. 3(A) corresponds to FIG. 3(B). Also, in the direction of the dashed-dotted line B3-B4 shown in FIG. 3(A) The cross-section is the cross-section in the channel width direction of the transistor 101 shown in FIGS. 2(A) and (B). It is the same as that. In the above drawings, some elements are enlarged, reduced, or omitted for clarity and shown. Also, the direction of the dashed line B1 - B2 may be referred to as the channel length direction, and the direction of the dashed line B3 - B4 may be referred to as the channel width direction.

[0075] The transistor 102 includes an insulating layer 120 in contact with the substrate 110, an oxide semiconductor layer 130 in contact with the insulating layer 120, a source electrode layer 140 and a drain electrode layer 150 electrically connected to the oxide semiconductor layer 130, a gate insulating film 160 in contact with the oxide semiconductor layer 130, a gate electrode layer 170 in contact with the gate insulating film 160, and an insulating layer 175 covering the oxide semiconductor layer 130, the gate insulating film 160, the source electrode layer 140, the drain electrode layer 150, and the gate electrode layer 170, an insulating layer 180 in contact with the insulating layer 175, and an insulating layer 1 85 formed on the above configuration. Also, an insulating layer 190 (planarization film) etc. may be provided in contact with the insulating layer 185 as necessary

[0076] Note that the transistor 102 has the same configuration as the transistor 101 except that the source electrode layer 140 and the drain electrode layer 150 are directly formed on the oxide semiconductor layer 130 and the configuration of the source region and the drain region

[0077] Also, the oxide semiconductor layer 130 in the transistor 102 is provided between the separated regions 33 1 and region 332, and between region 331 and region 332, and has a region 333 that overlaps with the gate electrode layer 170 via the gate insulating film 160, and between region 331 and region 333 ​​​The region 334 provided between them, and the region 335 provided between the region 332 and the region 333 and have.

[0078] In the transistor 102, the region 331 has a region in contact with the source electrode layer 140, and the region 332 has a region in contact with the drain electrode layer 150. Therefore, the region 331 and the region 332 are used as the source electrode layer 140 and the drain electrode layer 150, and oxygen is absorbed by the metal material, resulting in oxygen deficiency, n-type conversion, and low resistance.

[0079] In addition, the regions 334 and 335 do not contact the source electrode layer 140 and the drain electrode layer 150, but have a region in contact with the insulating layer 175 containing hydrogen. Due to the interaction between the oxygen deficiency generated in the regions 334 and 335 during the process up to the formation of the insulating layer 175 and the hydrogen diffusing from the insulating layer 175 into the regions 334 and 335, the regions 334 and 335 become low-resistance n-type. Therefore, the regions 331 and 334 can act as source regions, and the regions 332 and 335 can act as drain regions. Note that impurities for increasing oxygen deficiency may be added to the regions 334 and 335 in the same manner as the regions 231 and 232 of the transistor 101.

[0080] At this time, when adding impurities by plasma treatment, since a part of the gate electrode layer 170 may be sputtered and deposited on the end of the gate insulating film 160, it is preferable to perform plasma treatment in the state where a resist mask remains on the gate electrode layer 170, similar to the transistor 101.

[0081] For the regions 334 and 335, impurities for increasing oxygen deficiency may be added in the same manner as the regions 231 and 232 of the transistor 101.

[0082] At this time, when adding impurities by plasma treatment, since a part of the gate electrode layer 170 may be sputtered and deposited on the end of the gate insulating film 160, it is preferable to perform plasma treatment in the state where a resist mask remains on the gate electrode layer 170, similar to the transistor 101. Part of the gate electrode layer 170 may be sputtered and deposited on the end of the gate insulating film 160, so, similar to the transistor 101, it is preferable to perform plasma treatment with a resist mask remaining on the gate electrode layer 170. ​

[0083] By performing plasma processing in this state, sputtering of the gate electrode layer 170 is suppressed, The prevention of short circuits between the regions 334 and 335 and the gate electrode layer 170 and the gate leakage current In addition, since a part of the resist mask is sputtered, e.g. When the treatment was performed with argon plasma, argon and As described above, when carbon is added to the oxide semiconductor layer, Since oxygen vacancies are formed, the electrical conductivity of the oxide semiconductor layer can be further increased.

[0084] That is, regions 334 and 335 in transistor 102 form oxygen vacancies. The region 331, the region 332, and the region 333 have a higher impurity concentration for the purpose of In addition, since hydrogen enters the oxygen vacancies, the regions 334 and 335 have a hydrogen concentration has a portion higher than the region 333. A transistor is formed by such a structure. This allows the source and drain regions to have lower resistance, The on-current can be increased.

[0085] The width of the region 334 and the region 335 in the channel length direction is preferably 100 nm or less. In the case of a thickness of 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Therefore, it is possible to adopt a configuration in which the above-mentioned resistance reduction is not performed.

[0086] As shown in FIGS. 4A and 4B, the transistor of one embodiment of the present invention is an oxide semiconductor. A conductive layer 172 may be provided between the dielectric layer 130 and the substrate 110. The conductive layer may be a second By using it as a gate electrode layer (back gate), further increase in on-current and control of the threshold voltage can be achieved. In the cross-section in the channel length direction shown in Fig. 4(A), the width of the conductive layer 172 may be shortened so as not to overlap with the source electrode layer 140, the drain electrode layer 150, etc. Further, the width of the conductive layer 172 may be made shorter than the width of the gate electrode layer 170.

[0087] To increase the on-current, for example, the gate electrode layer 170 and the conductive layer 172 may be set to the same potential and driven as a double-gate transistor. Also, to control the threshold voltage, a fixed potential different from that of the gate electrode layer 170 may be supplied to the conductive layer 172. To set the gate electrode layer 170 and the conductive layer 172 to the same potential, for example, as shown in Fig. 4(C), the gate electrode layer 170 and the conductive layer 172 may be electrically connected via a contact hole. Note that, although Figs. 4(A), (B), and (C) are exemplified as modified examples of the transistor 101, the said form can also be applied to the transistor 102 shown in Fig. 3.

[0088] Also, the transistor according to one aspect of the present invention may have the configuration shown in Figs. 5(A) and (B). Fig. 5(A) is a top view of the transistor 103, and the cross-section in the two-point chain line C1-C 2 direction shown in Fig. 5(A) corresponds to Fig. 5(B). Also, the cross-section in the two-point chain line C3-C4 direction shown in Fig. 5(A) corresponds to Fig. 6(A) or Fig. 6(B). In the above drawings, for clarity, some elements are shown enlarged, reduced, or omitted. Also, the two-point chain line C1-C2 direction may be referred to as the channel length direction, and the two-point chain line C3-C4 direction may be referred to as the channel width direction.

[0089] The transistor 103 shown in FIGS. 5(A) and 5(B) is the same as the transistor 101 in configuration, except that the oxide semiconductor layer 130 is formed in the order of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c from the side of the insulating layer 120. For example, different oxide semiconductor layers or the like can be used for the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, respectively. The configuration of the other parts is the same as that of the transistor 101.

[0090] For example, different oxide semiconductor layers or the like can be used for the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, respectively. For example, different oxide semiconductor layers or the like can be used for the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, respectively.

[0091] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 7(A) and 7(B). FIG. 7(A) is a top view of the transistor 104, and the cross section in the direction of the dashed-dotted line D1-D2 shown in FIG. 7(A) corresponds to FIG. 7(B). In addition, the cross section in the direction of the dashed-dotted line D3-D4 shown in FIG. 7(A) corresponds to FIG. 8(A) or FIG. 8(B). In the above drawings, some elements are enlarged, reduced, or omitted for clarity. In addition, the direction of the dashed-dotted line D1-D2 may be referred to as the channel length direction, and the direction of the dashed-dotted line D3-D4 may be referred to as the channel width direction. In addition, the direction of the dashed-dotted line D1-D2 may be referred to as the channel length direction, and the direction of the dashed-dotted line D3-D4 may be referred to as the channel width direction.

[0092] The transistor 104 shown in FIGS. 7(A) and 7(B) is the same as the transistor 103 in configuration, except that the oxide semiconductor layer 130b is covered with the oxide semiconductor layer 130c. The configuration of the other parts is the same as that of the transistor 103. The configuration of the other parts is the same as that of the transistor 103.

[0093] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 9(A) and 9(B). FIG. 9(A) is a top view of the transistor 105, and the cross section in the direction of the dashed-dotted line E1-E2 shown in FIG. 9(A) corresponds to FIG. 9(B). In addition, the cross section in the direction of the dashed-dotted line E3-E4 shown in FIG. 9(A) is the same as the cross section in the channel width direction of the transistor 103 shown in FIG. 6. In addition, the cross section in the direction of the dashed-dotted line E3-E4 shown in FIG. 9(A) is the same as the cross section in the channel width direction of the transistor 103 shown in FIG. 6. In the above drawings, some elements are enlarged, reduced, or omitted for clarity. Also, the direction of the dashed-dotted line E1 - E2 may be referred to as the channel length direction, and the direction of the dashed-dotted line E3 - E4 may be referred to as the channel width direction.

[0094] The transistor 105 shown in FIGS. 9(A) and (B) is the same as the transistor 102 except that the oxide semiconductor layer 130 is formed in the order of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c from the insulating layer 120 side. The oxide semiconductor layer 130 of the transistor 105 may be configured such that the oxide semiconductor layer 130b is covered with the oxide semiconductor layer 130c as in the transistor 104.

[0095] Also, a transistor according to an aspect of the present invention may include a conductive layer 172 between the oxide semiconductor layer 130 and the substrate 110 as shown in FIGS. 10(A), (B), and (C). By using the conductive layer as a second gate electrode layer (back gate), further increase in on-current and control of the threshold voltage can be achieved. In the cross-section in the channel length direction shown in FIG. 10(A), the width of the conductive layer 172 may be shortened so as not to overlap with the source electrode layer 140, the drain electrode layer 150, etc. Further, the width of the conductive layer 172 may be shorter than the width of the gate electrode layer 170. Also, FIGS. 10(A), (B), and (C) are illustrated as a modification of the transistor 104, but this form can also be applied to the transistor 103 and the transistor 105.

[0096] Also, a transistor according to an aspect of the present invention may have the configuration shown in FIGS. 11(A) and (B). FIG. 11(A) is a top view of the transistor 106, and the dashed-dotted line F shown in FIG. 11(A) ​​​​​​​​​​​​​​ The cross-section in the F2 direction of 1 corresponds to FIG. 11(B). Also, the dashed-dotted line F3 shown in FIG. 11(A) - The cross-section in the F4 direction corresponds to FIG. 12(A) or FIG. 12(B). In the above drawings, For clarity, some elements are shown enlarged, reduced, or omitted. Also, the dashed-dotted line The F1-F2 direction is sometimes referred to as the channel length direction, and the dashed-dotted line F3-F4 direction is sometimes referred to as the channel width direction. There are cases.

[0097] The transistor 106 shown in FIGS. 11(A) and (B) has an oxide semiconductor layer 130, and the insulating layer 12 From the 0 side, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c Except for the points formed in this order, other configurations are the same as those of the transistor 101.

[0098] For example, for the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 13 0c, oxide semiconductor layers with different compositions can be used respectively.

[0099] Also, the transistor of one aspect of the present invention may have the configuration shown in FIGS. 13(A) and (B). FIG. 13(A) is a top view of the transistor 107, and the dashed-dotted line G shown in FIG. 13(A) The cross-section in the G2 direction of 1 corresponds to FIG. 13(B). Also, the dashed-dotted line G3 shown in FIG. 13(A) - The cross-section in the G4 direction corresponds to FIG. 14(A) or FIG. 14(B). In the above drawings, For clarity, some elements are shown enlarged, reduced, or omitted. Also, the dashed-dotted line The G1-G2 direction is sometimes referred to as the channel length direction, and the dashed-dotted line G3-G4 direction is sometimes referred to as the channel width direction. There are cases.

[0100] The transistor 107 shown in FIGS. 13(A) and (B) has an oxide semiconductor layer 130a and an oxide The other configuration is the same as that of the transistor 106, except that the semiconductor layer 130b is covered with the oxide semiconductor layer 130c. is the same as the transistor 106.

[0101] Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 15(A) and (B). FIG. 15(A) is a top view of the transistor 108, and the cross section taken along the dash-dotted line H1-H2 shown in FIG. 15(A) corresponds to FIG. 15(B). Also, the cross section taken along the dash-dotted line H3-H4 shown in FIG. 15(A) corresponds to FIG. 16(A) or FIG. 16(B). Note that in the above drawings, for clarity, some elements are shown enlarged, reduced, or omitted. Also, the direction of the dash-dotted line H1-H2 is sometimes referred to as the channel length direction, and the direction of the dash-dotted line H3-H4 is sometimes referred to as the channel width direction.

[0102] The transistor 108 shown in FIGS. 15(A) and (B) has the same configuration as the transistor 106, except that a part of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b is covered with the oxide semiconductor layer 130c.

[0103] Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 17(A) and (B). FIG. 17(A) is a top view of the transistor 109, and the cross section taken along the dash-dotted line I1-I2 shown in FIG. 17(A) corresponds to FIG. 17(B). Also, the cross section taken along the dash-dotted line I3-I 4 in FIG. 17(A) is the same as the cross section in the channel width direction of the transistor 108 shown in FIG. 16. Note that in the above drawings, for clarity, some elements are enlarged, reduced, or omitted. Also, the direction of the dash-dotted line I1-I2 is sometimes referred to as the channel length direction, and the direction of the dash-dotted line I3-I 4 is sometimes referred to as the channel width direction. ​​

[0104] In the transistor 109 shown in FIGS. 17A and 17B, the oxide semiconductor layer 130 is disposed between the insulating layer 12 and the From the 0 side, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c The other configurations are the same as the transistor 102, except that the transistors are formed in the same order. The oxide semiconductor layer 130 of the transistor 109 is As shown in FIG. 1, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b or a part of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are oxide semiconductors. It may be configured to be covered with a conductor layer 130c.

[0105] In addition, the transistor of one embodiment of the present invention can be configured as follows: A conductive layer 172 may be provided between the oxide semiconductor layer 130 and the substrate 110. By using the layer as a second gate electrode layer (back gate), it is possible to further increase the on-current and In addition, the threshold voltage can be controlled by the channel length direction shown in FIG. In the cross section, the width of the conductive layer 172 is shortened to reduce the width of the source electrode layer 140 and the drain electrode layer 15 0. Furthermore, the width of the conductive layer 172 may be set so as not to overlap with the gate electrode layer 170. 18(A), (B), and (C) show the width of the transistor 10. 7, this embodiment is similar to the transistors 106, 108, and The same can also be applied to the transistor 109.

[0106] In the transistors of one embodiment of the present invention (transistors 101 to 109), In either configuration, the gate electrode layer 170 is formed of an oxide semiconductor via the gate insulating film 160. The transistor 130 is electrically surrounded in the channel width direction, and the on-current is increased. The structure of the transistor is called a surrounded channel (s-channel) structure. It is called a structure.

[0107] Also, in a transistor having an oxide semiconductor layer 130b and an oxide semiconductor layer 130c, as well as in a transistor having an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c, by appropriately selecting the two or three materials constituting the oxide semiconductor layer 130, current can be made to flow through the oxide semiconductor layer 130b. By current flowing through the oxide semiconductor layer 130b, it is less susceptible to the influence of interface scattering and a high on-current can be obtained. Note that increasing the thickness of the oxide semiconductor layer 130b can improve the on-current. For example, the film thickness of the oxide semiconductor layer 130b may be set to 100 nm to 200 nm. By making current flow through the oxide semiconductor layer 130b, it is less susceptible to the influence of interface scattering and a high on-current can be obtained. By making current flow through the oxide semiconductor layer 130b, it is less susceptible to the influence of interface scattering and a high on-current can be obtained. Note that increasing the thickness of the oxide semiconductor layer 130b can improve the on-current. For example, the film thickness of the oxide semiconductor layer 130b may be set to 100 nm to 200 nm. By making current flow through the oxide semiconductor layer 130b, it is less susceptible to the influence of interface scattering and a high on-current can be obtained. Note that increasing the thickness of the oxide semiconductor layer 130b can improve the on-current. For example, the film thickness of the oxide semiconductor layer 130b may be set to 100 nm to 200 nm. By making current flow through the oxide semiconductor layer 130b, it is less susceptible to the influence of interface scattering and a high on-current can be obtained. Note that increasing the thickness of the oxide semiconductor layer 130b can improve the on-current. For example, the film thickness of the oxide semiconductor layer 130b may be set to 100 nm to 200 nm. It may be.

[0108] By using a transistor having the above configuration, good electrical characteristics can be imparted to the semiconductor device. It can be.

[0109] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. It is.

[0110] (Embodiment 2) In this embodiment, details of the components of the transistor shown in Embodiment 1 will be described. It will be described.

[0111] The substrate 110 is not limited to a mere support material and may be a substrate on which other devices such as other transistors are formed. In this case, one or more of the gate electrode layer 170, source electrode layer 140, and drain electrode layer 150 of the transistor may be electrically connected to the above-described other devices. It may be a substrate. In this case, one or more of the gate electrode layer 170, source electrode layer 140, and drain electrode layer 150 of the transistor may be electrically connected to the above-described other devices. It may be.

[0112] For example, the substrate 110 can be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. A single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI (Silicon On Insulator) substrate, etc. can also be used.

[0113] The insulating layer 120 not only has the role of preventing the diffusion of impurities from the substrate 110, but can also play the role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, in the TDS method performed by heat treatment at a film surface temperature of 100 °C or higher and 700 °C or lower, preferably 100 °C or higher and 500 °C or lower, the insulating layer 120 is a film with an oxygen release amount of 1.0×10 19 atoms / cm 3 or more. Further, when the substrate 110 is a substrate on which other devices are formed as described above, the insulating layer 120 also has the function of an interlayer insulating film. In that case, it is preferable to perform a planarization treatment by a method such as CMP (Chemical Mechanical Polishing) so that the surface becomes flat.

[0114] For example, the insulating layer 120 includes oxide insulating films such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride. ​​​​​​​​​​​​​​A chemical compound insulating film or a mixed material thereof can be used. Also, a laminate of the above materials may be used. It may be.

[0115] In this embodiment, the oxide semiconductor layer 130 included in the transistors 106, 107, 10 8 and 109 has a three-layer structure in which the oxide semiconductor layers 13 0a, 130b, and 130c are stacked in this order from the side of the insulating layer 120. The details will be mainly described for this case.

[0116] In the case where the oxide semiconductor layer 130 is a single layer as in the transistors 101 and 102, a layer corresponding to the oxide semiconductor layer 130b may be used. In the case where the oxide semiconductor layer 130 is a single layer as in the transistors 101 and 102, a layer corresponding to the oxide semiconductor layer 130b may be used.

[0117] Also, in the case where the oxide semiconductor layer 130 is a two-layer structure as in the transistors 103, 104, and 105, a laminate in which a layer corresponding to the oxide semiconductor layer 130b and a layer corresponding to the oxide semiconductor layer 130c are stacked in this order from the side of the insulating layer 120 may be used. In this configuration, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c may be interchanged. configuration, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c may be interchanged. configuration, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c may be interchanged. It is possible.

[0118] Also, when the oxide semiconductor layer 130 has four or more layers, for example, a structure in which another oxide semiconductor layer is stacked on the three-layer oxide semiconductor layer 130 described in this embodiment or a structure in which another oxide semiconductor layer is inserted at any interface in the three-layer structure can be adopted. can be adopted.

[0119] As an example, the oxide semiconductor layer 130b has a larger electron affinity (energy from the vacuum level to the lower end of the conduction band) than the oxide semiconductor layers 130a and 130c. As an example, the oxide semiconductor layer 130b has a larger electron affinity (energy from the vacuum level to the lower end of the conduction band) than the oxide semiconductor layers 130a and 130c. A compound semiconductor is used. The electron affinity can be obtained as a value obtained by subtracting the energy difference (energy gap) between the lower end of the conduction band and the upper end of the valence band from the energy difference (ionization potential) between the vacuum level and the upper end of the valence band. The energy difference between the lower end of the conduction band and the upper end of the valence band (energy gap) can be subtracted from the energy difference (ionization potential) between the vacuum level and the upper end of the valence band. The value can be obtained by subtracting the energy difference (energy gap) between the lower end of the conduction band and the upper end of the valence band from the energy difference (ionization potential) between the vacuum level and the upper end of the valence band.

[0120] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c contain one or more metal elements constituting the oxide semiconductor layer 130b. For example, the energy of the lower end of the conduction band is any one of 0.05 eV, 0.07 eV, 0.1 eV, and 0.15 eV or more than that of the oxide semiconductor layer 130b, and it is preferably formed of an oxide semiconductor close to the vacuum level in the range of any one of 2 eV, 1 eV, 0.5 eV, and 0.4 eV or less. than that of the oxide semiconductor layer 130b, and it is preferably formed of an oxide semiconductor close to the vacuum level in the range of any one of 2 eV, 1 eV, 0.5 eV, and 0.4 eV or less. than that of the oxide semiconductor layer 130b, and it is preferably formed of an oxide semiconductor close to the vacuum level in the range of any one of 2 eV, 1 eV, 0.5 eV, and 0.4 eV or less. than that of the oxide semiconductor layer 130b, and it is preferably formed of an oxide semiconductor close to the vacuum level in the range of any one of 2 eV, 1 eV, 0.5 eV, and 0.4 eV or less.

[0121] In such a structure, when an electric field is applied to the gate electrode layer 170, a channel is formed in the oxide semiconductor layer 130b having the smallest energy at the lower end of the conduction band among the oxide semiconductor layers 130. In such a structure, when an electric field is applied to the gate electrode layer 170, a channel is formed in the oxide semiconductor layer 130b having the smallest energy at the lower end of the conduction band among the oxide semiconductor layers 130. In such a structure, when an electric field is applied to the gate electrode layer 170, a channel is formed in the oxide semiconductor layer 130b having the smallest energy at the lower end of the conduction band among the oxide semiconductor layers 130.

[0122] Further, since the oxide semiconductor layer 130a is formed by containing one or more metal elements constituting the oxide semiconductor layer 130b, compared with the interface when the oxide semiconductor layer 130b is in contact with the insulating layer 120, compared with the interface when the oxide semiconductor layer 130b is in contact with the insulating layer 120, compared with the interface when the oxide semiconductor layer 130b is in contact with the insulating layer 120, it is less likely to form interface levels at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. Since the interface levels may form a channel, the threshold voltage of the transistor may fluctuate. Therefore, by providing the oxide semiconductor layer 130a, the variation in electrical characteristics such as the threshold voltage of the transistor can be reduced. Further, the reliability of the transistor can be improved.

[0123] The oxide semiconductor layer 130c contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film 160 are in contact with each other, Compared to the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, the interface Therefore, by providing the oxide semiconductor layer 130c, the scattering of the ions is suppressed. This can increase the field effect mobility of the transistor.

[0124] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf is a material having a higher atomic number than the oxide semiconductor layer 130b. Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably at least two times, and more preferably at least three times. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0125] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c is at least indium (In) or It is preferable that the alloy contains lead (Zn). Alternatively, it is preferable that the alloy contains both In and Zn. In addition, in order to reduce variation in electrical characteristics of transistors using the oxide semiconductor, Both preferably include a stabilizer.

[0126] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. There are aluminum (Al), zirconium (Zr), etc. Also, as other stabilizers there are lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium ( Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. .

[0127] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn oxide , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn acid oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn acid oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxidation oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide can be used. .

[0128] Here, for example, the In-Ga-Zn oxide means that In, Ga, and Zn are the main components It means an oxide having [a certain property]. Also, it is acceptable even if there are metal elements other than In, Ga, and Zn. In this specification, a film composed of an In-Ga-Zn oxide is also called an IGZO film.

[0129] Also, a material represented by InMO3(ZnO) m (where m > 0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Y, Zr, La, Ce, or Nd. Also, a material represented by In2SnO5(ZnO) (where n > 0 and n is an integer) may be used. n

[0130] Note that when the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are In-M-Zn oxides containing at least indium, zinc, and M (a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La Ce, or Hf), if the oxide semiconductor layer 130a is In:M:Zn = x1:y1:z1 [atomic ratio], the oxide semiconductor layer 130b is In:M:Zn = x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Zn = x3:y3:z3 [atomic ratio], it is preferable that y1 / x1 and y3 / x3 are larger than y2 / x2. y1 / x1 and y3 / x3 are preferably 1.5 times or more, more preferably 2 times or more, and even more preferably 3 times or more than y2 / x2. At this time, in the oxide semiconductor layer 130b, when y2 is equal to or more than x2, the electrical characteristics of the transistor can be stabilized. However, when y2 becomes 3 times or more of x2, the field-effect mobility of the transistor decreases. Therefore, it is preferable that y2 is less than 3 times of x2.

[0131] In the case of excluding Zn and O from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, the atomic ratio of In and M is preferably less than 50 atomic% for In and 50 atomic% or more for M, more preferably less than 25 atomic% for In and 7 5 atomic% or more for M. Further, excluding Zn and O from the oxide semiconductor layer 130b, the atomic ratio of In and M is preferably 25 atomic% or more for In and 75 at omic% or less for M, more preferably 34 atomic% or more for In and 66 atomi c% or less.

[0132] In addition, the oxide semiconductor layer 130b preferably has a higher indium content than the oxide semiconductor layer 130a and the oxide semiconductor layer 130 c. In an oxide semiconductor, mainly the s-orbitals of heavy metals contribute to carrier conduction. By increasing the In content, more s-orbitals overlap. Therefore, an oxide with a composition where In is more than M has a higher mobility than an oxide with a composition where In is equal to or less than M. Therefore, by using an oxide with a high indium content for the oxide semiconductor layer 130b, a transistor with high field-effect mobility can be realized.

[0133] The thickness of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. Further, the thickness of the oxide semiconductor layer 130b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less, more preferably 10 nm or more and 100 nm or less. Also, the oxide semiconductor layer 130b is preferably thicker than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c.

[0134] In order to impart stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel it is effective to reduce the impurity concentration in the oxide semiconductor layer and make the oxide semiconductor layer intrinsic or substantially intrinsic (i-type). Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is less than 1×10 19 / cm 3 preferably less than 1×10 15 / cm 3 less more preferably less than 1×10 13 / cm 3 and most preferably less than 1×10 1×10 8 / cm 3 less than 1×10 -9 / cm 3 or more.

[0135] In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Also, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and may deteriorate the electrical characteristics of the transistor . Therefore, it is preferable to reduce the impurity concentration in the layers of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c and at their respective interfaces.

[0136] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, in SIMS (Secondary Ion Mass Spectrometry) analysis, for example, at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer, the silicon concentration is 1×10 1×10 19 atoms / cm 3less than, preferably 5×10 18 atoms / cm 3 less than , more preferably 1×10 18 atoms / cm 3 less than. Also, the hydrogen concentration is, for example at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer , 2×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less , more preferably 1×10 19 atoms / cm 3 or less, still more preferably 5×10 1 8 atoms / cm 3 or less. Also, the nitrogen concentration is, for example, at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer, 5×10 atoms / c 19 m m 3 less than, preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 1 8 atoms / cm 3 or less, still more preferably 5×10 17 atoms / cm 3 or less .

[0137] Also, when the oxide semiconductor layer contains crystals, if silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced. To prevent the crystallinity of the oxide semiconductor layer from being reduced , for example, at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer , the silicon concentration is 1×10 19 atoms / cm 3 less than, preferably 5×10 1 8 atoms / cm 3 less than, more preferably 1×10 18 atoms / cm 3 is sufficient if it has a portion that is less than it suffices if it has a portion that is less than. Also, for example, at a certain depth of the oxide semiconductor layer, or in a certain region of the oxide semiconductor layer, the carbon concentration is 1×10 19 atoms / cm 3 less than preferably 5×10 18 atoms / cm 3 less than, more preferably 1×10 18 at oms / cm 3 is sufficient if it has a portion that is less than.

[0138] Also, the off-current of a transistor using the oxide semiconductor film purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm. When the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm.

[0139] Note that as the gate insulating film of the transistor, an insulating film containing silicon is often used. Therefore, for the above reasons, the region that becomes the channel of the oxide semiconductor layer can be preferably structured not to be in contact with the gate insulating film like a transistor of one aspect of the present invention. Also, when a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, carrier scattering may occur at the interface, and the field-effect mobility of the transistor may decrease. From this point of view as well it can be said that the region that becomes the channel of the oxide semiconductor layer is preferably separated from the gate insulating film. it can be said that the region that becomes the channel of the oxide semiconductor layer is preferably separated from the gate insulating film. When a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface, and the field-effect mobility of the transistor may decrease. From this point of view as well it can be said that the region that becomes the channel of the oxide semiconductor layer is preferably separated from the gate insulating film. .

[0140] Therefore, by forming the oxide semiconductor layer 130 into a stacked structure of an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b, and a transistor having high field-effect mobility and stable electrical characteristics can be formed.

[0141] In the band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, the energy at the lower end of the conduction band changes continuously. This can also be understood from the fact that the compositions of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are similar, and oxygen diffuses easily among them. Therefore, although the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are a laminate of layers with different compositions, it can be said that they are physically continuous. In the drawings of this specification, the respective interfaces of the laminate are represented by dotted lines. the oxide semiconductor layer 130 is formed by stacking layers having a common main component, not simply by stacking the layers, but by forming a continuous junction (here, a U-shaped well structure (U Shape Well) in which the energy at the lower end of the conduction band changes continuously between the layers). That is, the stacking structure is formed so that there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of the respective layers.

[0142] If impurities are mixed between the stacked oxide semiconductor layers, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface and disappear.

[0143] For example, in the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In:Ga:Zn =​​​​​​​​​​ 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: 9:6 (atomic ratio). In the oxide semiconductor layer 130b, In:Ga:Zn = 1:1:1, 2: 1:3, 5:5:6, or 3:1:2 (atomic ratio) of In-Ga-Zn oxide, etc. can be used. Note that the atomic ratios of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and also the oxide semiconductor layer 130c each include a fluctuation of plus or minus 20% of the above atomic ratio as an error.

[0144] In the oxide semiconductor layer 130, the oxide semiconductor layer 130b serves as a well, and in a transistor using the oxide semiconductor layer 130, the channel is formed in the oxide semiconductor layer 130b. Note that since the energy at the lower end of the conduction band of the oxide semiconductor layer 130 changes continuously, it can also be called a U-shaped well. Also, the channel formed in such a configuration can be called a buried channel.

[0145] In addition, near the interfaces between the oxide semiconductor layers 130a and 130c and an insulating film such as a silicon oxide film, trap levels may be formed due to impurities and defects. Due to the presence of the oxide semiconductor layers 130a and 130c, the oxide semiconductor layer 13 0b can be separated from the trap levels.

[0146] However, when the difference between the energy at the lower end of the conduction band of the oxide semiconductor layers 130a and 130c and the energy at the lower end of the conduction band of the oxide semiconductor layer 130b is small, electrons in the oxide semiconductor layer 130b may reach the trap levels across the energy difference. When electrons that become the charge of the eggplant are trapped in the trap level, the threshold voltage of the transistor shifts in the positive direction.

[0147] Therefore, in order to reduce the variation in the threshold voltage of the transistor, the lower energy of the conduction band of the oxide semiconductor layer 130 a and the oxide semiconductor layer 130c, and the oxide semiconductor layer 130b It is necessary to provide a difference of a certain level or more from the energy of the lower end of the conduction band. Each The energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0148] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c preferably contain a crystal part. In particular, by using a crystal oriented along the c-axis, the transistor can be given stable electrical characteristics. In addition, the crystal oriented along the c-axis is resistant to distortion, and the reliability of the semiconductor device using the flexible substrate can be improved.

[0149] The gate insulating film 160 can use an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Further, the gate insulating film 160 may be a laminate of the above materials. Note that the gate insulating film 160 may contain lanthanum (La), nitrogen zirconium (Zr), etc. as impurities.

[0150] In addition, an example of the laminated structure of the gate insulating film 160 will be described. The gate insulating film 160 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0151] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. The dielectric constant is high. Therefore, the physical thickness can be made larger than the equivalent oxide thickness. Even if the thickness of the valence oxide film is set to 10 nm or less or 5 nm or less, the leakage current due to the tunnel current is In other words, a transistor with a small off-state current can be realized. Furthermore, hafnium oxide having a crystalline structure can be used in combination with hafnium oxide having an amorphous structure. Therefore, in order to make a transistor with a small off-current, For this purpose, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal system include monoclinic and cubic crystal systems. However, one embodiment of the present invention is not limited to these. I can't.

[0152] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface states may function as trap centers. When hafnium oxide is placed adjacent to the channel region of a transistor, the interface states This may cause degradation of the electrical characteristics of the transistor. To achieve this, another film is placed between the channel region of the transistor and the hafnium oxide. It may be preferable to separate the membranes from each other by using a The film having the buffer function may be a film included in the gate insulating film 160, or may be an oxide semiconductor. The film may be a film included in the conductor film. That is, the film having a buffer function may be silicon oxide. , silicon oxynitride, an oxide semiconductor, etc. can be used. Note that for the film having a buffer function , for example, a semiconductor or insulator having a larger energy gap than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffer function, for example, a semiconductor or insulator having a smaller electron affinity than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffer function, for example, a semiconductor or insulator having a larger ionization energy than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffer function, for example, a semiconductor or insulator having a larger ionization energy than the semiconductor that becomes the channel region is used. Alternatively, for the film having a buffer function, for example, a semiconductor or insulator having a larger ionization energy than the semiconductor that becomes the channel region is used.

[0153] On the other hand, there is a case where the threshold voltage of the transistor can be controlled by trapping charges at the interface levels (trap centers) on the formed surface of hafnium oxide having the above-described crystal structure. In order to stably exist the charges, for example, an insulator having a larger energy gap than hafnium oxide may be disposed between the channel region and hafnium oxide. Alternatively, a semiconductor or insulator having a smaller electron affinity than hafnium oxide may be disposed. Alternatively, for the film having a buffer function, a semiconductor or insulator having a larger ionization energy than hafnium oxide may be disposed. By using such an insulator, the release of the charges trapped at the interface levels is less likely to occur, and the charges can be retained for a long period of time. Examples of such an insulator include silicon oxide and silicon oxynitride. In order to capture charges at the interface levels in the gate insulating film 160, electrons may be moved from the oxide semiconductor layer 130 toward the gate electrode layer 170. As a specific example, at a high temperature ( for example, 125 ° C or higher and 450 ° C or lower, typically 150 ° C or higher and 300 ° C or lower),

[0154] Examples of such an insulator include silicon oxide and silicon oxynitride. To capture charges at the interface levels in the gate insulating film 160, electrons may be moved from the oxide semiconductor layer 130 toward the gate electrode layer 170. Specifically, at a high temperature ( for example, 125 ° C or higher and 450 ° C or lower, typically 150 ° C or higher and 300 ° C or lower), for example, 125 ° C or higher and 450 ° C or lower, typically 150 ° C or higher and 300 ° C or lower), The potential of the gate electrode layer 170 may be maintained at a level higher than the potential of the source electrode or the drain electrode for 1 second or more, typically for 1 minute or more.

[0155] In this way, in the transistor in which a desired amount of electrons are trapped in the interface levels such as the gate insulating film 160, the threshold voltage shifts to the positive side. By adjusting the voltage of the gate electrode layer 170 and the time for applying the voltage, the amount of electrons trapped (the amount of variation in the threshold voltage) can be controlled. Note that as long as charges can be trapped, it does not have to be within the gate insulating film 160. A laminated film having a similar structure may be used for other insulating layers. For the gate electrode layer 170, for example, conductive films such as Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo,

[0156] Ru, Ag, Mn, Nd, Sc, Ta, and W can be used. Also, alloys of the above materials or conductive nitrides of the above materials may be used. Further, a laminate of a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials may be used. Typically, tungsten, a laminate of tungsten and titanium nitride, a laminate of tungsten and tantalum nitride, etc. can be used. Also, a low-resistance Cu or Cu-Mn alloy or a laminate of the above materials and a Cu or Cu-Mn alloy may be used. In the present embodiment, tantalum nitride is used for the conductive layer 171 and tungsten is used for the conductive layer 172 to form the gate electrode layer 170.

[0157]

[0157] For the insulating layer 175, it is preferable to use a silicon nitride film containing hydrogen or an aluminum nitride film. As described above, by using an insulating film containing hydrogen as the insulating layer 175, oxidation A part of the semiconductor layer can be made n-type. Also, the nitride insulating film also functions as a moisture-blocking film and can improve the reliability of the transistor. It also has the function as a blocking film for moisture and the like, and can improve the reliability of the transistor.

[0158] Also, it is preferable that an insulating layer 180 is formed on the insulating layer 175. The insulating layer may be an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Also, the oxide insulating layer may be a laminate of the above materials. Here, it is preferable that the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. Since the oxygen released from the insulating layer 180 can diffuse through the gate insulating film 160 into the channel formation region of the oxide semiconductor layer 130, oxygen can fill the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. For the source electrode layer 140 and the drain electrode layer 150, for example, a single layer or a laminate of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of the metal materials can be used. Typically, W with a high melting point is preferably used because Ti, which easily binds to oxygen, and the subsequent process temperature can be relatively high. Also, a laminate of a low-resistance material such as Cu or Cu-Mn and the above materials can be used. In this embodiment, W is used for the conductive layer 141 and the conductive layer 151, and the conductive layer 142 and the conductive For the source electrode layer 140 and the drain electrode layer 150, for example, a single layer or a laminate of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of the metal materials can be used. Typically, W with a high melting point is preferably used because Ti, which easily binds to oxygen, and the subsequent process temperature can be relatively high. Also, a laminate of a low-resistance material such as Cu or Cu-Mn and the above materials can be used. In this embodiment, W is used for the conductive layer 141 and the conductive layer 151, and the conductive layer 142 and the conductive

[0159] Here, it is preferable that the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. Since the oxygen released from the insulating layer 180 can diffuse through the gate insulating film 160 into the channel formation region of the oxide semiconductor layer 130, oxygen can fill the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. For the source electrode layer 140 and the drain electrode layer 150, for example, a single layer or a laminate of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of the metal materials can be used. Typically, W with a high melting point is preferably used because Ti, which easily binds to oxygen, and the subsequent process temperature can be relatively high. Also, a laminate of a low-resistance material such as Cu or Cu-Mn and the above materials can be used. In this embodiment, W is used for the conductive layer 141 and the conductive layer 151, and the conductive layer 142 and the conductive Here, it is preferable that the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. Since the oxygen released from the insulating layer 180 can diffuse through the gate insulating film 160 into the channel formation region of the oxide semiconductor layer 130, oxygen can fill the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. Here, it is preferable that the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. Since the oxygen released from the insulating layer 180 can diffuse through the gate insulating film 160 into the channel formation region of the oxide semiconductor layer 130, oxygen can fill the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. Here, it is preferable that the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. Since the oxygen released from the insulating layer 180 can diffuse through the gate insulating film 160 into the channel formation region of the oxide semiconductor layer 130, oxygen can fill the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained.

[0160] For the source electrode layer 140 and the drain electrode layer 150, for example, a single layer or a laminate of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of the metal materials can be used. For the source electrode layer 140 and the drain electrode layer 150, for example, a single layer or a laminate of materials selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of the metal materials can be used. Typically, W with a high melting point is preferably used because Ti, which easily binds to oxygen, and the subsequent process temperature can be relatively high. Also, a laminate of a low-resistance material such as Cu or Cu-Mn and the above materials can be used. In this embodiment, W is used for the conductive layer 141 and the conductive layer 151, and the conductive layer 142 and the conductive Typically, W with a high melting point is preferably used because Ti, which easily binds to oxygen, and the subsequent process temperature can be relatively high. Also, a laminate of a low-resistance material such as Cu or Cu-Mn and the above materials can be used. In this embodiment, W is used for the conductive layer 141 and the conductive layer 151, and the conductive layer 142 and the conductive Typically, W with a high melting point is preferably used because Ti, which easily binds to oxygen, and the subsequent process temperature can be relatively high. Also, a laminate of a low-resistance material such as Cu or Cu-Mn and the above materials can be used. In this embodiment, W is used for the conductive layer 141 and the conductive layer 151, and the conductive layer 142 and the conductive Typically, W with a high melting point is preferably used because Ti, which easily binds to oxygen, and the subsequent process temperature can be relatively high. Also, a laminate of a low-resistance material such as Cu or Cu-Mn and the above materials can be used. In this embodiment, W is used for the conductive layer 141 and the conductive layer 151, and the conductive layer 142 and the conductive The source electrode layer 140 and the drain electrode layer 150 are formed on the electroconductive layer 152 using Cu.

[0161] The above material has the property of extracting oxygen from the oxide semiconductor film. Therefore, in a part of the region of the oxide semiconductor layer in contact with the above material, oxygen in the oxide semiconductor film desorbs, forming oxygen vacancies. Hydrogen slightly contained in the film enters the oxygen vacancies, causing the region to be significantly n-type doped. Therefore, the n-type doped region can function as the source or drain of the transistor.

[0162] It is preferable to form an insulating layer 185 as a protective film on the source electrode layer 140, the drain electrode layer 150, and the insulating layer 180. As the insulating layer 185, an insulating film similar to the insulating layer 175 can be used. Also, an aluminum oxide film can be used as the insulating layer 185. The aluminum oxide film has a high blocking effect that does not allow impurities such as hydrogen and moisture, and oxygen to permeate through the film. Therefore, the aluminum oxide film is suitable for use as a protective film that prevents the mixing of impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of the transistor, into the oxide semiconductor layer 130 during and after the manufacturing process of the transistor, prevents the release of oxygen, which is the main component material constituting the oxide semiconductor layer 130, from the oxide semiconductor layer, and prevents the unnecessary release of oxygen from the insulating layer 120. Also, the oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer.

[0163] To highly integrate the semiconductor device, miniaturization of the transistor is essential. On the other hand, it is known that the electrical characteristics of the transistor deteriorate due to the miniaturization of the transistor, and the channel width is reduced. ​​​​​​​​​​​​When it becomes small, the on-current decreases.

[0164] In the transistors 103 to 109 of one aspect of the present invention, an oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b in which a channel is formed. The channel formation layer and the gate insulating film are not in contact with each other. Therefore, scattering of carriers generated at the interface between the channel formation layer and the gate insulating film can be suppressed, and the on-current of the transistor can be increased. Moreover, in the transistor of one aspect of the present invention, as described above, since the gate electrode layer 170 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 130, in addition to the gate electric field from the vertical direction to the oxide semiconductor layer 130, a gate electric field from the side direction is applied. That is, a gate electric field is applied to the entire channel formation layer, and the effective channel width is expanded, so that the on-current can be further increased.

[0165] Also, in the transistors 106 to 109 of one aspect of the present invention, by forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a, it is difficult to form interface levels, and by positioning the oxide semiconductor layer 130b as a layer in the middle of the three-layer structure, the effect of eliminating the influence of impurity mixing from above and below can be achieved. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized, and the S value (sub-threshold value) can be reduced. Therefore, Icut (current when the gate voltage VG is 0V) can be lowered, and the power consumption can be reduced. Also, the transistor

[0166] Also, in the transistors 106 to 109 of one aspect of the present invention, by forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a, it is difficult to form interface levels, and by positioning the oxide semiconductor layer 130b as a layer in the middle of the three-layer structure, the effect of eliminating the influence of impurity mixing from above and below can be achieved. Therefore, in addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized, and the S value (sub-threshold value) can be reduced. Therefore, Icut (current when the gate voltage VG is 0V) can be lowered, and the power consumption can be reduced. Also, the transistor In addition to the improvement of the on-current of the transistor described above, the threshold voltage can be stabilized, and the S value (sub-threshold value) can be reduced. Therefore, Icut (current when the gate voltage VG is 0V) can be lowered, and the power consumption can be reduced. Also, the transistor ​​​​​​​​​​​Since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved. In addition, since the deterioration of the electrical characteristics due to miniaturization of the transistor according to one aspect of the present invention can be suppressed, it can be said that it is suitable for forming a highly integrated semiconductor device.

[0167] Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0168] (Embodiment 3) In this embodiment, an oxide semiconductor film that can be used for a transistor according to one aspect of the present invention will be described.

[0169] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0170] In this specification, when a crystal is trigonal or rhombohedral, it is expressed as a hexagonal system.

[0171] <Structure of Oxide Semiconductor> Hereinafter, the structure of the oxide semiconductor will be described.

[0172] The oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. As the non-single crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor Conductors, nc-OS (nanocrystalline Oxide Semicon ctor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous li ke Oxide Semiconductor), amorphous oxide semiconductors, and the like exist.

[0173] From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide sem ductors. Examples of crystalline oxide semiconductors include single-crystalline oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, nc-OS, and the like.

[0174] Generally, the definition of an amorphous structure is known to include not being fixed in a metastable state, being isotropic, and not having a heterogeneous structure. Also, it can be rephrased as a structure with flexible bond angles, having short-range order but not having long-range order. Looking at it from the opposite perspective, in the case of an essentially stable oxide semiconductor, it cannot be called a completely amorphous (complet

[0175] ely amorphous) oxide semiconductor. Also, an anisotropic (for example, having a periodic structure in a microscopic region) oxide semiconductor cannot be called a completely amorphous oxide semiconductor. However, although a-like OS has a periodic structure in a microscopic region, it has looseness and an unstable structure. Therefore, it can be said that its physical properties are close to those of an amorphous oxide semiconductor.

[0176] <caac-os> First, CAAC-OS will be described.

[0177] CAAC-OS is one of the oxide semiconductors having a plurality of c-axis oriented crystal parts (also referred to as pellets). conductors.

[0178] By a transmission electron microscope (TEM: Transmission Electron Micro scope), when observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of CAAC-OS, a plurality of pellets can be confirmed. On the other hand In a high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries. That is, the grain boundaries (also called grain boundaries).) cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries. That is, the grain boundaries (also called grain boundaries).) cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries.

[0179] Hereinafter, CAAC-OS observed by TEM will be described. FIG. 19(A) shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction substantially parallel to the sample surface. High For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function was used. The high-resolution TEM image using the spherical aberration correction function is Specifically called a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image is, for example, by Specifically called a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image is, for example, by A JEOL JEM-ARM200F atomic-resolution analytical electron microscope manufactured by JEOL Ltd. can be used. It can be done.

[0180] An enlarged Cs-corrected high-resolution TEM image of the region (1) in FIG. 19(A) is shown in FIG. 19(B). From FIG. 19(B), it can be confirmed that in the pellet, the metal atoms are arranged in layers. . The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface on which the CAAC-OS film is formed, and is parallel to the surface to be formed or the upper surface of the CAAC-OS. Moreover, it is parallel to the surface to be formed or the upper surface of the CAAC-OS, reflecting the unevenness of the surface to be formed or the upper surface.

[0181] As shown in FIG. 19(B), CAAC-OS has a characteristic atomic arrangement. FIG. 19(C) shows the characteristic atomic arrangement indicated by auxiliary lines. From FIGS. 19(B) and 19(C) , it can be seen that the size of one pellet is about 1 nm or more and 3 nm or less, and the size of the gap formed by the inclination between pellets is about 0.8 nm. Therefore, the pellet can also be called a nanocrystal (nc). In addition, CA AC-OS can also be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals) .

[0182] Here, when schematically showing the arrangement of the pellets 5100 of CAAC-OS on the substrate 5120 based on the Cs-corrected high-resolution TEM image, it has a structure like bricks or blocks stacked (see FIG. 19(D)). The location where the inclination occurs between the pellets observed in FIG. 19(C) corresponds to the region 5161 shown in FIG. 19(D).

[0183] In addition, FIG. 20(A) shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The regions (1), (2), and (3) in FIG. 20(A) are enlarged Cs-corrected high-resolution TEM images shown in FIGS. 20(B), 20(C), and FIG. 20(D), respectively. From FIGS. 20(B), 20(C), and 20(D), it can be confirmed that the metal atoms in the pellet are arranged in a triangular, square, or hexagonal shape. However However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0184] Next, the CA analyzed by X-ray diffraction (XRD) will be described for AC-OS. For example, for CAAC-OS having a crystal of InGaZnO4 when a structural analysis is performed by the out-of-plane method, as shown in Fig. 21(A) a peak may appear near a diffraction angle (2θ) of about 31°. Since this peak is attributed to the (009) plane of the crystal of InGaZ nO4, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0185] In the structural analysis of CAAC-OS by the out-of-plane method, in addition to the peak near 2θ of 31° a peak may also appear near 2θ of 36°. The peak near 2θ of 36° indicates that a part of CAAC-OS contains crystals without c-axis orientation. More preferable CAAC-OS shows a peak near 2θ of 31° and does not show a peak near 2θ of 36° in the structural analysis by the out-of-plane method.

[0186] On the other hand, when a structural analysis is performed on CAAC-OS by the in-plane e method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears near 2θ of 56°. This peak is attributed to the (110) plane of the crystal of In GaZnO4. In the case of CAAC-OS, even when the analysis ( φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56° as shown in Fig. 21(B), no distinct peak appears. In contrast When the single-crystalline oxide semiconductor is InGaZnO4 and 2θ is fixed near 56°, if φ scanning is performed, six peaks attributed to crystal planes equivalent to the (110) plane are observed as shown in Fig. 21(C). Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular orientations of the a-axis and b-axis. Next, CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface on CAAC-OS having a crystal of InGaZnO4, a diffraction pattern (also referred to as a limited-field transmission electron diffraction pattern) as shown in Fig. 68(A) may appear. This diffraction pattern contains spots due to the (009) plane of the InGaZnO4 crystal. Therefore, it can also be seen by electron diffraction that the pellets included in the CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, Fig. 68(B) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface on the same sample. From Fig. 68(B), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen by electron diffraction that the a-axis and b-axis of the pellets included in the CAAC-OS do not have orientation. Note that the first ring in Fig. 68(B) is considered to be due to the (010) plane and the (100) plane, etc. of the InGaZnO4 crystal. Also, the second ring in Fig. 68(B) is considered to be due to the (110) plane, etc. As described above, CAAC-OS is a highly crystalline oxide semiconductor.

[0187]

[0188] ​​​​​​​​​​​​​​Crystallinity may decrease due to contamination by impurities or generation of defects, so the opposite view can be taken. CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0189] Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. Elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor, can deprive the oxide semiconductor of oxygen, disrupting the atomic arrangement of the oxide semiconductor and becoming a factor in reducing crystallinity. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a large atomic radius (or molecular radius), so they disrupt the atomic arrangement of the oxide semiconductor and become a factor in reducing crystallinity.

[0190] When the oxide semiconductor has impurities or defects, its characteristics may vary depending on light, heat, etc. For example, impurities contained in the oxide semiconductor may become carrier traps or carrier generation sources. Also, oxygen vacancies in the oxide semiconductor may become carrier traps or carrier generation sources by capturing hydrogen.

[0191] CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with a low carrier density. Specifically, the carrier density is less than 8×10 / cm 11 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and can be 1×10 -9 / cm 3 or more. Such an oxide semiconductor is called highly pure intrinsic or substantially highly pure. It is called a true oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

[0192] <nc-os> Next, nc-OS will be described.

[0193] In a high-resolution TEM image, nc-OS has a region where crystalline parts can be confirmed and a region where distinct crystalline parts cannot be confirmed. The crystalline parts contained in nc-OS are often sized 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. Incidentally, an oxide semiconductor with crystalline parts sized greater than 10 nm and 100 nm or less may be referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image, for example, nc-OS may not clearly show grain boundaries. Incidentally, the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, hereinafter, the crystalline parts of nc-OS may be referred to as pellets.

[0194] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS does not show regularity in the crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when using an X-ray with a diameter larger than that of the pellet for nc-OS, in the analysis by the out-of-plane method, peaks indicating crystal planes are not detected. Also, when performing electron diffraction using an electron beam with a probe diameter larger than that of the pellet (for example, 50 nm or more) for nc-OS, a diffraction pattern such as a halo pattern is observed. On the other hand, for nc-OS, when using a probe size close to or smaller than that of the pellet When performing nanobeam electron diffraction using an electron beam with a diameter of ーブ, spots are observed. Also, n When performing nanobeam electron diffraction on c-OS, a region with high luminance may be observed in a circular (ring-shaped) pattern. Furthermore, multiple spots may be observed within the ring-shaped region. There are cases.

[0195] Thus, since the crystal orientations among the pellets (nanocrystals) do not have regularity, nc- OS can also be called an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide semiconductor having NANC (Non-Aligned nanocrystals ).

[0196] nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. Therefore, nc-OS has a lower density of defect levels than a-like OS and an amorphous oxide semiconductor. . However, nc-OS does not show regularity in crystal orientation among different pellets. Therefore , nc-OS has a higher density of defect levels than CAAC-OS.

[0197] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. conductor.

[0198] In a high-resolution TEM image, voids (also called voids) may be observed in a-like OS. Also, in a high-resolution TEM image, there are regions where the crystal part can be clearly confirmed and regions where the crystal part cannot be confirmed.

[0199] Due to having voids, a-like OS has an unstable structure. Below, a-like To show that the OS has an unstable structure compared to CAAC-OS and nc-OS , the change in structure due to electron irradiation is shown.

[0200] As samples for electron irradiation, a-like OS (denoted as sample A), nc-OS( denoted as sample B), and CAAC-OS (denoted as sample C) are prepared. Any of the samples is In-Ga-Zn oxide.

[0201] First, high-resolution cross-sectional TEM images of each sample are obtained. From the high-resolution cross-sectional TEM images, it can be seen that each sample has a crystalline part.

[0202] Note that the determination of which part is regarded as one crystalline part can be performed as follows. For example, the unit cell of the InGaZnO4 crystal has three In-O layers and six Ga-Zn-O layers, and it is known to have a structure in which a total of nine layers are stacked in the c-axis direction. The distance between these adjacent layers is about the same as the lattice plane spacing of the (009) plane (also referred to as the d value), and its value is determined to be 0.29 nm from crystal structure analysis. Therefore, a portion where the lattice fringe spacing is between 0.28 nm and 0.30 nm can be regarded as the crystalline part of InGaZnO4. Note that the lattice fringes correspond to the a-b plane of the InGaZnO4 crystal.

[0203] Fig. 69 shows an example of investigating the average size of the crystalline parts (from 22 to 45 locations) of each sample . However, the length of the lattice fringes described above is used as the size of the crystalline part. From Fig. 69, it can be seen that the a-like OS shows that the crystalline part becomes larger as the cumulative electron irradiation dose increases. Specifically , as shown by (1) in Fig. 69, at the initial stage of observation by TEM, it is about 1.2 nm The crystal part (also referred to as the initial nucleus) of the size of... has grown to about 2.6 nm when the cumulative irradiation dose is 4.2×10 8 e - / nm 2 It can be seen that it has grown in. On the other hand, nc-OS and CAAC-OS show no change in the size of the crystal part from the start of electron irradiation until the cumulative irradiation dose of electrons reaches 4.2×10 8 e - / nm 2 Specifically, as shown in (2) and (3) of Fig. 69, regardless of the cumulative irradiation dose of electrons, the sizes of the crystal parts of nc-OS and CAAC-OS are about 1.4 nm and about 2.1 nm respectively, as can be seen. as can be seen. It can be seen.

[0204] Thus, a-like OS may show growth of the crystal part by electron irradiation. On the other hand, it can be seen that nc-OS and CAAC-OS hardly show growth of the crystal part by electron irradiation. That is, it can be seen that a-like OS has a less stable structure than nc-OS and CAAC-OS. On the other hand, it can be seen that nc-OS and CAAC-OS hardly show growth of the crystal part by electron irradiation. That is, it can be seen that a-like OS has a less stable structure than nc-OS and CAAC-OS. OS.

[0205] Also, because it has looseness, a-like OS has a lower density structure than nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition. Also, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor with a density less than 78% of that of a single crystal is difficult to form a film itself. For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], rhombic -OS are 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor with a density less than 78% of that of a single crystal is difficult to form a film itself. For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], rhombic

[0206] For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], rhombic The density of single-crystalline InGaZnO4 having a hexahedral crystal structure is 6.357 g / cm 3 Thus, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the a-like OS is 5.0 g / cm or more and less than 5.9 g / cm 3 Moreover, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], 3 the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm or more and less than 6.3 g / cm 3 3

[0207] Note that there may be cases where single crystals of the same composition do not exist. In such cases, by combining single crystals with different compositions in any ratio, the density corresponding to the single crystal in the desired composition can be estimated. The density corresponding to the single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

[0208]

[0209] As described above, the oxide semiconductor has various structures, each having various characteristics. In addition, the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0209] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0210] (Embodiment 4) In this embodiment, a display device according to an aspect of the present invention will be described with reference to the drawings.

[0211] ​ In addition, the display device in this specification refers to an image display device or a light source (including lighting devices). Also, a module to which a connector, for example, an FPC or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the end of the TCP, or a module in which a driving circuit is directly mounted on a display element by the COG method are all included in the display device. Figure 22 is a top view of a display device 500 according to an aspect of the present invention. Note that in Figure 22, some elements are enlarged, reduced, made transparent, or omitted for clarity of the drawing. The display device 500 has a pixel portion 502 provided on a substrate 501, circuit portions 504 and 505 for driving the pixel portion, a sealing material 512 disposed so as to surround the pixel portion 502, the circuit portions 504, and the circuit portions 505, and a substrate 507 provided so as to face the substrate 501. As the circuit portion 504, for example, a signal line driving circuit (source driver) can be provided, and as the circuit portion 505, for example, a scanning line driving circuit (gate driver) can be provided.

[0212] The substrate 501 and the substrate 507 are adhered by the sealing material 512. Although not shown in Figure 22, a display element is provided between the substrate 501 and the substrate 507. That is, the pixel portion 502, the circuit portions 504 and 505, and the display element are sealed by the substrate 501, the sealing material 512, and the substrate 507. In addition, the display device 500 is an area surrounded by the sealing material 512 on the substrate 501.

[0213] The display device 500 includes a pixel portion 502 provided on a substrate 501, circuit portions 504 and 505 for driving the pixel portion, and a sealing material 512 arranged to surround the pixel portion 502, the circuit portions 504, and the circuit portions 505, and a substrate 507 provided to face the substrate 501. Note that as the circuit portion 504, for example, a signal line driving circuit (source driver) can be included, and as the circuit portion 505, for example, a scanning line driving circuit (gate driver) can be included. The substrate 501 and the substrate 507 are adhered by the sealing material 512. Also, although not shown in Figure 22, a display element is provided between the substrate 501 and the substrate 507. That is, the pixel portion 502, the circuit portions 504, the circuit portions 505, and the display element are sealed by the substrate 501, the sealing material 512, and the substrate 507. Moreover, the display device 500 is an area surrounded by the sealing material 512 on the substrate 501. The substrate 501 and the substrate 507 are adhered by the sealing material 512. Also, although not shown in Figure 22, a display element is provided between the substrate 501 and the substrate 507. That is, the pixel portion 502, the circuit portions 504, the circuit portions 505, and the display element are sealed by the substrate 501, the sealing material 512, and the substrate 507. Furthermore, the display device 500 is an area surrounded by the sealing material 512 on the substrate 501. The substrate 501 and the substrate 507 are adhered by the sealing material 512. Also, although not shown in Figure 22, a display element is provided between the substrate 501 and the substrate 507. That is, the pixel portion 502, the circuit portions 504, the circuit portions 505, and the display element are sealed by the substrate 501, the sealing material 512, and the substrate 507.

[0214] The substrate 501 and the substrate 507 are adhered by the sealing material 512. Also, although not shown in Figure 22, a display element is provided between the substrate 501 and the substrate 507. That is, the pixel portion 502, the circuit portions 504, the circuit portions 505, and the display element are sealed by the substrate 501, the sealing material 512, and the substrate 507. In addition, the display device 500 is an area surrounded by the sealing material 512 on the substrate 501. The substrate 501 and the substrate 507 are adhered by the sealing material 512. Also, although not shown in Figure 22, a display element is provided between the substrate 501 and the substrate 507. That is, the pixel portion 502, the circuit portions 504, the circuit portions 505, and the display element are sealed by the substrate 501, the sealing material 512, and the substrate 507. Moreover, the display device 500 is an area surrounded by the sealing material 512 on the substrate 501.

[0215] In addition, the display device 500 is an area surrounded by the sealing material 512 on the substrate 501. In different regions, an F that is electrically connected to the pixel portion 502, the circuit portion 504, and the circuit portion 505 is provided with a PC terminal portion 508 (FPC: Flexible printed circuit).

[0216] Also, an FPC 516 is connected to the FPC terminal portion 508, and various signals and the like are supplied to the pixel portion 502, the circuit portion 504, and the circuit portion 505 by the FPC 516. Also, signal lines 510 are respectively connected to the pixel portion 502, the circuit portion 504, the circuit portion 505, and the FPC terminal portion 508. Various signals and the like supplied by the FPC 516 are given to the pixel portion 502, the circuit portion 504, and the circuit portion 505 via the signal lines 510.

[0217] Note that in FIG. 22, a configuration in which circuits for driving the pixel portion 502 are arranged in two regions is shown as an example, but the configuration of the circuit is not limited to this. For example, the circuit may be arranged together in one region. Also, the circuit may be divided into three or more parts and arranged. Also, only one of the circuit portion 504 and the circuit portion 505 may be formed on the substrate 501, and the other circuit may be external attached.

[0218] Also, the circuit for driving the pixel portion 502 may be configured to be formed on the substrate 501 in the same way as the transistors included in the pixel portion 502, or may be configured to mount an IC chip by COG (Chip On Glas s) or the like. Also, it may be configured to connect a TCP or the like.

[0219] Note that the pixel portion 502, the circuit portion 504, and the circuit portion 505 included in the display device 500 have a plurality of transistors in which the channel formation region is formed of an oxide semiconductor layer. ​​​​

[0220] Since the transistor using an oxide semiconductor layer has a high mobility, the occupied area of the transistor can be reduced, and the aperture ratio can be improved. Also, the circuit unit 504 and the circuit unit 505 can be formed on the same substrate as the pixel unit 502 using the transistor. Since the transistor has an extremely small off-current and can increase the holding time of an image signal or the like, the frame frequency can be lowered, and the power consumption of the display device can be reduced. Also, as the oxide semiconductor layer, it preferably has a crystal oriented in the c-axis direction. When an oxide semiconductor layer having such a crystal is used for the channel formation region of the transistor, for example, when the display device 500 is bent, cracks or the like are less likely to occur in the oxide semiconductor layer, so that the reliability can be improved. Therefore, by using a transistor using an oxide semiconductor layer, a display device superior to that using, for example, an amorphous silicon layer or a polycrystalline silicon layer can be formed. As the display element included in the display device 500, typically, a liquid crystal element or a light-emitting element can be used. Next, the liquid crystal display device 500a will be described. FIG. 23 is a cross-sectional view taken along the one-dot chain line J1-J2 shown in FIG. 22 when a liquid crystal element is used in the display device 500.

[0221] The liquid crystal display device 500a has a substrate 501, a first element layer, a second element layer, and a substrate 507 laminated in the above order.

[0222]

[0223]

[0224]

[0225]

[0226] ​​​​​​​​​​​ In FIG. 23, the first element layer includes transistors 550 and 552, a planarized insulating film 570, a connection electrode 560, a conductive film 572, and the like. The second element layer includes a conductive film 574, an insulating film 534, a coloring layer 536 (color filter), a light-shielding layer 538 (black matrix), and the like. Note that in the first and second element layers, some of the above elements may not be included, and other elements may be included.

[0227] Here, the first element layer and the second element layer are sealed by a liquid crystal layer 576 and a sealing material 512 to form a liquid crystal element 575.

[0228] The liquid crystal display device 500a includes a routing wiring portion 511, a pixel portion 502, a first circuit portion 50 4, and an FPC terminal portion 508. The routing wiring portion 511 has signal lines 510.

[0229] In the liquid crystal display device 500a, an example of a configuration in which transistors 550 are provided in the pixel portion 502 and transistors 552 are provided in the circuit portion 3 04 is illustrated.

[0230] In FIG. 23, the configurations of the transistors 550 and 552 are merely examples and are not limited thereto. The transistors 550 and 552 can have appropriate sizes (such as channel length and channel width) or numbers changed as appropriate. Also, in FIG. 23, although the circuit portion 505 is not shown, it can have the same configuration as the circuit portion 504.

[0231] The signal lines 510 included in the routing wiring portion 511 can be formed in the process of forming the source electrode layer and the drain electrode layer of the transistor 550. ​​​

[0232] The FPC terminal portion 508 includes a connection electrode 560, an anisotropic conductive film 580, and an FPC 516. The connection electrode 560 is connected to the source electrode layer and the drain electrode layer of the transistor 550. The connection electrode 560 can be formed in the process of forming the layer. The terminal is electrically connected to the anisotropic conductive film 580 .

[0233] In addition, a signal connected to a transistor in a pixel portion and a transistor used in a driver circuit portion It is preferable to use wiring containing copper as the wire. By using wiring containing copper, This makes it possible to reduce signal delays and the like caused by wiring resistance.

[0234] In addition, in FIG. 23, a planarizing insulating film is formed on the transistor 550 and the transistor 552. 570 is provided.

[0235] The planarization insulating film 570 may be made of a polyimide resin, an acrylic resin, a polyimide amide resin, or Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin In addition, by stacking a plurality of insulating films made of these materials, A planarization insulating film 570 may be formed. Alternatively, a structure in which the planarization insulating film 570 is not provided may be used. Good too.

[0236] In addition, one of the source electrode layer and the drain electrode layer of the transistor 550 has a conductive The conductive film 572 is formed on the planarization insulating film 570. The conductive film 572 functions as an electrode, that is, one of the electrodes of the liquid crystal element. In the above, it is preferable to use a light-transmitting conductive film. It is advisable to use a material containing one selected from indium (In), zinc (Zn), and tin (Sn).

[0237] The liquid crystal element 575 has a conductive film 572, a conductive film 574, and a liquid crystal layer 576. The conductive film 574 is provided on the substrate 507 side and functions as a counter electrode. The liquid crystal shown in FIG. 23 display device 500a controls the transmission and non - transmission of light by changing the alignment state of the liquid crystal layer 5 76, thereby enabling image display. It can be done.

[0238] Although not shown in FIG. 23, alignment films may be provided on the sides of the conductive films 572 and 574 that are in contact with the liquid crystal layer 576. In addition, optical members (optical substrates) such as polarizing members, retardation members, and antireflection members may be provided as appropriate. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source.

[0239] Also, a spacer 578 is provided between the substrate 501 and the substrate 507. The spacer 578 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the film thickness (cell gap) of the liquid crystal layer 57 6. Note that a spherical spacer may be used as the spacer 578.

[0240] As the liquid crystal material constituting the liquid crystal layer 576, thermotropic liquid crystal, low - molecular liquid crystal, polymer liquid crystal, polymer - dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials may exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions. ​​​​​

[0241] In addition, when adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used. . The blue phase is one of the liquid crystal phases. When the cholesteric liquid crystal is heated up, it is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. The blue phase appears only within a narrow temperature range. Therefore, in order to improve the temperature range, a liquid crystal composition mixed with a chiral agent of several weight % or more is used for the liquid crystal layer. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependency. Since it does not need an alignment film, rubbing treatment is also unnecessary. Therefore, electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. When using a liquid crystal element as the display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. In addition, for a normally black type liquid crystal display device, for example, a transmissive type adopting the vertical alignment (VA) mode

[0242]

[0243] ​​​​​​​​​​​​It may also be a transflective liquid crystal display device. Examples of the vertical alignment mode include, but are not limited to, for example, the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, the ASV mode, etc.

[0244] In addition, the display method in the pixel portion 502 can use a progressive method, an interlace method, or the like. When performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (where R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, like a pentile arrangement, one color element is composed of two of the RGB colors, and different two colors are selected and configured by the color elements. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB . Note that the size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device and can also be applied to a monochrome display device.

[0245] Next, the EL display device 500b using a light-emitting element will be described. FIG. 24 is a cross-sectional view taken along the dashed-dotted line J1-J2 shown in FIG. 22 when a light-emitting element is used in the display device 5 00. Note that descriptions overlapping with those of the above-described liquid crystal display device 500a are omitted.

[0246] The EL display device 500b includes a substrate 501, a first element layer 610, a second element layer 611, and a substrate 507, which are laminated in the above order.

[0247] In FIG. 24, the first element layer 610 includes transistors 550 and 552, a planarized insulating film 5 70, connection electrodes 560, a light-emitting element 680, an insulating film 530, signal lines 510, and connection electrodes 560. The second element layer 611 includes an insulating film 534, a coloring layer 536, and a light-shielding layer 538. The first element layer 610 and the second element layer 611 are sealed by a sealing layer 632 and a sealing material 512. Note that in the first element layer 610 and the second element layer 611, some of the above elements may not be included. Also, elements other than the above may be included.

[0248] The light-emitting element 680 includes a conductive film 644, an EL layer 646, and a conductive film 648. The EL display device 500b can display an image by the EL layer 646 included in the light-emitting element 680 emitting light. An insulating film 530 is provided on the conductive film 644 on the planarized insulating film 570. The insulating film 530

[0249] covers a part of the conductive film 644. By using a conductive film with a high reflectance for the light emitted by the EL layer for the conductive film 644 and a conductive film with high light transmittance for the light emitted by the EL layer for the conductive film 648, the light-emitting element 680 can be formed in a top emission structure. Also, by using a conductive film with high light transmittance for the light for the conductive film 64 4 and a conductive film with a high reflectance for the light for the conductive film 648, the light-emitting element 680 can be formed in a bottom emission structure. Also, by using a conductive film with high light transmittance for the light for both the conductive film 644 and the conductive film 648, a dual emission structure can be formed.

[0250] Also, a colored layer 536 is provided at a position overlapping the light-emitting element 680, and overlaps with the insulating film 530. A light-shielding layer 538 is provided at a position, the routing wiring portion 511, and the circuit portion 504 that overlap with the insulating film 530. The colored layer 536 and the light-shielding layer 538 are covered with the insulating film 534. The space between the light-emitting element 680 and the insulating film 534 is filled with a sealing layer 632. In the EL display device 500b, although the configuration of providing the colored layer 536 has been exemplified, it is not limited to this. For example, when the EL layer 646 is formed by painting separately, the colored layer 536 may not be provided.

[0251] Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0252] (Embodiment 5) In this embodiment, a transistor included in a display device which is one aspect of the present invention will be described.

[0253] The transistors included in the display device of one aspect of the present invention do not have to have a uniform structure. For example, by making the transistors included in the pixel portion of the display device and the transistors used in the drive circuit portion for driving the pixel portion have different configurations, electrical characteristics suitable for each can be given, and the reliability of the display device can be improved.

[0254] Also, the transistors included in the drive circuit portion can be made into transistors with high electric field effect mobility by adopting a double gate structure.

[0255] Also, the channel lengths of the transistors included in the drive circuit portion and the pixel portion may be different. Representative Specifically, the channel length of the transistor included in the drive circuit section can be less than 2.5 μm, or 1. 45 μm or more and 2.2 μm or less. On the other hand, the channel length of the transistor included in the pixel section can be 2.5 μm or more, or 2.5 μm or more and 20 μm or less. .

[0256] By setting the channel length of the transistor included in the drive circuit section to less than 2.5 μm, preferably 1.4 5 μm or more and 2.2 μm or less, the field-effect mobility can be increased compared to the transistor included in the pixel section, and the on-current can be increased. As a result, a drive circuit section capable of high-speed operation can be fabricated.

[0257] In addition, since the field-effect mobility of the transistor included in the drive circuit section is high, the number of input terminals can be reduced.

[0258] The liquid crystal display device 500a shown in FIG. 23 and the EL display device 500b shown in FIG. 24 are examples in which the transistor 101 shown in FIG. 1 is applied as the transistor included in the pixel section, and the transistor 104 shown in FIG. 7 is applied as the transistor included in the drive circuit section.

[0259] For the transistor included in the pixel section, a highly reliable transistor against light irradiation from a backlight or an EL element is desired. For example, by using, as a target, a material having an atomic ratio of In:Ga:Zn = 1:1:1 or In:Ga:Zn = 5:5:6 and forming a film by a sputtering method, a highly reliable transistor against light irradiation can be formed using an oxide semiconductor layer formed in the channel formation region.

[0260] ​​​On the other hand, a transistor included in the drive circuit section is preferably a transistor having a high field-effect mobility. For example, by using a material having an atomic ratio of In:Ga:Zn = 3:1:2 as a target and forming an oxide semiconductor layer by sputtering method in the channel formation region, a transistor having a high field-effect mobility can be formed.

[0261] In the present embodiment, by forming the oxide semiconductor layer of one transistor into a stacked structure, a method for easily fabricating the above two types of transistors on the same substrate will be described with reference to FIGS. 25 and 26. Note that, on the left side of the drawing, a cross-section in the channel length direction of a transistor A having the same configuration as the transistor 101 shown in FIG. 1 as a transistor used for the pixel portion is illustrated. Also, on the right side of the drawing, a cross-section in the channel length direction of a transistor B having the same configuration as the transistor 104 shown in FIG. 7 as a transistor used for the drive circuit section is illustrated. Note that the reference numerals of the elements common to the transistor A and the transistor B are attached to only one of them.

[0262] First, an insulating layer 120 is formed on a substrate 110. The type of the substrate 110 and the material of the insulating layer 120 can be referred to the description of Embodiment 2. Note that the insulating layer 120 can be formed by using a sputtering method, a CVD method, an MBE method, or the like.

[0263] Also, oxygen may be added to the insulating layer 120 by using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. By adding oxygen, the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130 can be further facilitated.

[0264] Note that when the surface of the substrate 110 is an insulator and there is no influence of impurity diffusion into the oxide semiconductor layer 130 to be provided later, the insulating layer 120 may not be provided.

[0265] Next, an oxide semiconductor film 130B that becomes the oxide semiconductor layer 130b in the transistor for the drive circuit is formed on the insulating layer 120 using a sputtering method, a CVD method, an MBE method, or the like.

[0266] Next, a resist mask 821 is formed in the drive circuit region using a lithography method (see Fig. 25(A)). Then, the oxide semiconductor film 130B is selectively etched using the resist mask to form the oxide semiconductor layer 130b (see Fig. 25(B)).

[0267] Next, an oxide semiconductor film 130C is formed so as to cover the oxide semiconductor layer 130b.

[0268] The oxide semiconductor film is preferably formed using a multi-chamber type film forming apparatus (for example, a sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus is evacuated to a high vacuum (up to about 5×10 -7 -4 Pa to 1×10 Pa) using an adsorption type vacuum exhaust pump such as a cryopump so as to remove water and the like that become impurities for the oxide semiconductor as much as possible, and it is preferable that the substrate to be formed can be heated to 100°C or higher, preferably 500°C or higher. Alternatively, it is preferable to prevent a gas containing a carbon component, moisture, etc. from flowing back into the chamber from the exhaust system by combining a turbo molecular pump and a cold trap. Also, an exhaust system combining a turbo molecular pump and a cryopump may be used.

[0269] ​​​​​​​​​​​​​ In order to obtain a high-purity true oxide semiconductor, not only the inside of the chamber needs to be evacuated to a high vacuum, but also the high-purity of the sputtering gas is necessary. The oxygen gas and argon gas used as the sputtering gas should have a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor film as much as possible.

[0270] For the oxide semiconductor film 130B and the oxide semiconductor film 130C, the materials of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c described in Embodiment 2 can be used. In this embodiment, for example, an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 3:1:2 is used for the oxide semiconductor film 130B, and an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:1 or In:Ga:Zn = 5:5:6 is used for the oxide semiconductor film 130C. Note that the atomic ratios of the oxide semiconductor film 130B and the oxide semiconductor film 130C each include a variation of plus or minus 20% of the above atomic ratio as an error. Also, when the sputtering method is used for the film formation method, the above materials can be used as targets for film formation.

[0271] Note that it is preferable to use the sputtering method for forming the oxide semiconductor film. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, etc. can be used.

[0272] After the formation of the oxide semiconductor film 130C, a first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under a reduced pressure state. Also ​ The atmosphere of the first heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere. By the first heat treatment, the crystallinity of the oxide semiconductor film 130B and the oxide semiconductor film 130C is enhanced, and furthermore, impurities such as hydrogen and water can be removed from the insulating layer 120, the oxide semiconductor film 130B, and the oxide semiconductor film 130C. Note that the first heat treatment may be performed after the etching for forming the stack of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, which will be described later.

[0273] Next, a resist mask 822 is formed in the pixel region using a lithography method. Also, a resist mask 823 is formed on the stack of the oxide semiconductor layer 130b and the oxide semiconductor film 130C in the drive circuit region (see FIG. 25(C)).

[0274] Next, using the resist mask, the oxide semiconductor film 130C is selectively etched to form an oxide semiconductor layer 130c in the pixel region. Also, a stack of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is formed in the drive circuit region (see FIG. 25(D)). At this time, the oxide semiconductor layer 130c in the drive circuit region is formed so as to cover the oxide semiconductor layer 130b.

[0275] Next, an insulating film 160a serving as a gate insulating film is formed on the oxide semiconductor layer in the pixel region and on the stack of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c in the drive circuit region. The insulating film 160a may be formed of a material that can be used for the gate insulating film 160 described in Embodiment 3. For the formation of the insulating film 160a, a sputtering method, a CVD method, an MBE method, etc. may be used. ​​​​​​​​​​​​​​etc. can be used.

[0276] Next, a conductive film 171a and a conductive film 172 that will become the gate electrode layer 170 are formed on the insulating film 160a. a. The conductive film 171a and the conductive film 172a may be formed of a material that can be used for the gate electrode layer 170 described in Embodiment 2. The conductive film 171a and the conductive film 172a can be formed using a sputtering method, a CVD method, an MBE method, etc. (see Fig. 2 6(A)).

[0277] Next, a resist mask 824 is formed on the conductive film 172a, and using this resist mask, the conductive film 172a, the conductive film 171a, and the insulating film 160a are selectively etched to form the gate electrode layer 170 and the gate insulating film 160.

[0278] Next, with the resist mask 824 formed in the above process remaining, impurities 830 that form oxygen deficiencies are added to regions 231 and regions 232 to reduce the resistance and form the source region and the drain region (see Fig. 26(B)). As the impurities 830, for example, argon is added by a plasma treatment method.

[0279] Since the above resist mask is altered by argon plasma, it is preferable to perform oxygen ashing to remove it.

[0280] Next, an insulating layer 175 is formed on the above configuration. The material of the insulating layer 175 can be referred to in the description of Embodiment 2. Also, the insulating layer 175 can be formed by a sputtering method, a CVD method, an MBE method, etc.

[0281] Next, an insulating layer 180 is formed on the insulating layer 175 (see Fig. 26(C)). The The material can be referred to the description of Embodiment 2. Further, the insulating layer 180 can be formed by sputtering method, CVD method, MBE method, etc.

[0282] Next, a resist mask is formed on the insulating layer 180, and using the resist mask, the insulating layer 1 80 and the insulating layer 175 are selectively etched to form contact holes leading to the regions 231 and 232.

[0283] Next, a conductive film is formed to cover the contact holes, and by selectively etching the conductive film, the source electrode layer 140 and the drain electrode layer 150 are formed. The material of the conductive film can be referred to the description of Embodiment 2. Further, the conductive film can be formed by sputtering method, CVD method, MBE method, etc.

[0284] Next, an insulating layer 185 is formed on the above configuration (see FIG. 26(D)). The material of the insulating layer 185 can be referred to the description of Embodiment 3. Further, the insulating layer 185 can be formed by sputtering method, CVD method, MBE method, etc.

[0285] Also, oxygen can be added to the insulating layer 180 and / or the insulating layer 185 by using a plasma treatment method, ion implantation method, ion doping method, plasma immersion ion implantation method, etc. By adding oxygen, the supply of oxygen from the insulating layer 180 and / or the insulating layer 1 85 to the oxide semiconductor layer can be made easier.

[0286] Next, a second heat treatment may be performed. The second heat treatment is under the same conditions as the first heat treatment It can be carried out by the second heat treatment. By the second heat treatment, it becomes easier for excess oxygen to be released from the insulating layer 120, the insulating layer 180, and the insulating layer 18 5, and the oxygen deficiency in the oxide semiconductor layer can be reduced .

[0287] In the above steps, a transistor having an oxide semiconductor layer with a stacked structure and a transistor having an oxide semiconductor layer with a single-layer structure can be easily formed on the same substrate. Also , it is possible to fabricate a display device having a pixel portion that can operate at high speed, has little degradation due to light irradiation, and has excellent display quality .

[0288] Note that various films such as the metal film, semiconductor film, and inorganic insulating film described in this embodiment can typically be formed by a sputtering method or a plasma CVD method, but other methods, for example, thermal CVD (Chemical Vapor Deposition) method may also be used to form them . Examples of the thermal CVD method include MOCVD (Metal Organic Chemic al Vapor Deposition) method and ALD (Atomic Layer D eposition) method and the like

[0289] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage .

[0290] Also, in the thermal CVD method, a source gas and an oxidizing agent are simultaneously fed into the chamber, and the inside of the chamber is set to atmospheric pressure or reduced pressure, and the reaction is carried out near or on the substrate to deposit on the substrate, thereby forming a film

[0291] In the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially fed into the ch ​It may be possible to form a film by introducing it into the chamber and repeating the order of gas introduction. For example , by switching each switching valve (also called a high-speed valve), two or more types of raw material gases are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced simultaneously or thereafter with the first raw material gas so that the plurality of types of raw material gases do not mix , and then the second raw material gas is introduced. When introducing an inert gas simultaneously, the inert gas serves as a carrier gas, and an inert gas may also be introduced simultaneously when introducing the second raw material gas. Also , instead of introducing an inert gas, after discharging the first raw material gas by vacuum exhaust, the second raw material gas may be introduced. The first raw material gas adsorbs on the surface of the substrate to form the first layer , and reacts with the second raw material gas introduced later, so that the second layer is laminated on the first layer to form a thin film . By repeating this gas introduction order multiple times until the desired thickness is reached while controlling the gas introduction order , a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times of repeating the gas introduction order , precise film thickness adjustment is possible, which is suitable for producing a fine FET . . Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films described in the embodiments disclosed so far . For example, when forming an In-Ga

[0292] -ZnO (X>0) film, trimethylindium, trimethylgallium , and dimethylzinc can be used. The chemical formula of trimethylindium is X , In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3 . . Also ​​​​​​​​​​​The chemical formula for dimethylzinc is Zn(CH3)2. The combination is not limited to the above, and triethylgallium (chemical formula Ga(C2 H5)3) can be used instead of dimethyl zinc, and diethyl zinc (chemical formula Zn(C2 H5)2) can also be used.

[0293] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrakis The raw material gas was vaporized with trimethylsilyl dimethylamide hafnium (TDMAH) as an oxidizing agent. Two types of gases are used: tetrakisdimethylamidohafnium (O3) and tetrakisdimethylamidohafnium (TDMHA). The chemical formula is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethy) (dimethylamido) hafnium.

[0294] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent A liquid containing an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is vaporized. Two types of gases are used: the source gas and H2O as an oxidizing agent. The chemical formula for nium is Al(CH3)3. Other materials include tris(dimethylamino) Aluminum tris(2,2,3-triisobutylaluminum), aluminum tris(2,2,3-triisobutylaluminum), 6,6-tetramethyl-3,5-heptanedionate).

[0295] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , a radical of dinitrogen monoxide is supplied to react with the adsorbate.

[0296] For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then, WF6 gas and H2 gas are simultaneously introduced to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0297] For example, when forming an oxide semiconductor film, such as an In-Ga-ZnO X (X>0) film using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, and then, Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a G aO layer. Further, thereafter, Zn(CH3)2 and O3 gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, these gases may be mixed to form a mixed compound layer such as an In -Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3) 3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas , Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used .

[0298] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. .

[0299] (Embodiment 6) ​​In this embodiment, a configuration example of a display device using a transistor according to an aspect of the present invention will be described. It will be described.

[0300] [Configuration Example] FIG. 27(A) is a top view of a display device according to an aspect of the present invention, and FIG. 27(B) is a circuit diagram for explaining a pixel circuit that can be used when a liquid crystal element is applied to a pixel of the display device according to an aspect of the present invention. Further, FIG. 27(C) is a circuit diagram for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel of the display device according to an aspect of the present invention. It is a circuit diagram for explaining. Also, FIG. 27(C) is a circuit diagram for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel of the display device according to an aspect of the present invention. It is a circuit diagram for explaining. .

[0301] The transistors arranged in the pixel portion can be formed according to the above embodiment. Also, since it is easy to make the transistor an n-channel type, a part of the drive circuit that can be composed of n-channel type transistors in the drive circuit is formed on the same substrate as the transistors in the pixel portion. In this way, by using the transistors shown in the above embodiment in the pixel portion and the drive circuit, a highly reliable display device can be provided. , since it is easy to make the transistor an n-channel type, a part of the drive circuit that can be composed of n-channel type transistors in the drive circuit is formed on the same substrate as the transistors in the pixel portion. The transistors arranged in the pixel portion can be formed according to the above embodiment. Also, since it is easy to make the transistor an n-channel type, a part of the drive circuit that can be composed of n-channel type transistors in the drive circuit is formed on the same substrate as the transistors in the pixel portion. The transistors arranged in the pixel portion can be formed according to the above embodiment. Also, since it is easy to make the transistor an n-channel type, a part of the drive circuit that can be composed of n-channel type transistors in the drive circuit is formed on the same substrate as the transistors in the pixel portion. By using the transistors shown in the above embodiment in the pixel portion and the drive circuit, a highly reliable display device can be provided.

[0302] An example of the top view of an active matrix type display device is shown in FIG. 27(A). On the substrate 700 of the display device, there are a pixel portion 701, a scanning line drive circuit 702, a scanning line drive circuit 703, and a signal line drive circuit 704. A plurality of signal lines extend from the signal line drive circuit 704 and are arranged in the pixel portion 701, and a plurality of scanning lines extend from the scanning line drive circuit 702 and the scanning line drive circuit 703 and are arranged. In the intersection region of the scanning line and the signal line, pixels each having a display element are provided in a matrix. Also, the substrate 700 of the display device is an FPC (Fl On the substrate 700 of the display device, there are a pixel portion 701, a scanning line drive circuit 702, a scanning line drive circuit 703, and a signal line drive circuit 704. A plurality of signal lines extend from the signal line drive circuit 704 and are arranged in the pixel portion 701, and a plurality of scanning lines extend from the scanning line drive circuit 702 and the scanning line drive circuit 703 and are arranged. A plurality of signal lines extend from the signal line drive circuit 704 and are arranged in the pixel portion 701, and a plurality of scanning lines extend from the scanning line drive circuit 702 and the scanning line drive circuit 703 and are arranged. In the intersection region of the scanning line and the signal line, pixels each having a display element are provided in a matrix. Also, the substrate 700 of the display device is an FPC (Fl In the intersection region of the scanning line and the signal line, pixels each having a display element are provided in a matrix. Also, the substrate 700 of the display device is an FPC (Fl Through connection parts such as Flexible Printed Circuit, it is connected to a timing control circuit (also referred to as a controller or control IC).

[0303] In FIG. 27(A), the scanning line driving circuit 702, the scanning line driving circuit 703, and the signal line driving circuit 70 4 are formed on the same substrate 700 as the pixel portion 701. Therefore, the number of components such as external driving circuits is reduced, so cost reduction can be achieved. Also, when a driving circuit is provided outside the substrate 700, it is necessary to extend the wiring, increasing the number of connections between the wirings. When the driving circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced, improving reliability or yield.

[0304] 〔Liquid Crystal Display Device〕 Also, an example of the circuit configuration of a pixel is shown in FIG. 27(B). Here, as an example, a pixel circuit applicable to the pixels of a VA-type liquid crystal display device is shown.

[0305] This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal so that the signals applied to the individual pixel electrode layers of the multi-domain designed pixels can be independently controlled. The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are

[0306] separated so that different gate signals can be applied. On the other hand, the data line 714 is commonly used by the transistor 716 and the transistor 717. Transistor 7 ​The transistor 716 and the transistor 717 can appropriately use the transistors described in the above embodiments. Thereby, a highly reliable liquid crystal display device can be provided.

[0307] The shape of the first pixel electrode layer electrically connected to the transistor 716 and the shape of the second pixel electrode layer electrically connected to the transistor 717 will be described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V-shaped spreading shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer. The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 713. Different gate signals are applied to the gate wiring 712 and the gate wiring 713 to make the operation timings of the transistor 716 and the transistor 717 different, and the liquid crystal alignment can be controlled. Also, a holding capacitor may be formed by the capacitance wiring 710, a gate insulating film functioning as a dielectric, and a capacitance electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer. The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween, and the second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween.

[0308] Note that the pixel circuit shown in FIG. 27(B) is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, sensor, or logic circuit is added to the pixel shown in FIG. 27(B). The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 713. By applying different gate signals to the gate wiring 712 and the gate wiring 713, the operation timings of the transistor 716 and the transistor 717 can be made different, and the liquid crystal alignment can be controlled.

[0309] Also, a holding capacitor may be formed by the capacitance wiring 710, a gate insulating film functioning as a dielectric, and a capacitance electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

[0310] The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween.

[0311] Note that the pixel circuit shown in FIG. 27(B) is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, sensor, or logic circuit is added to the pixel shown in FIG. 27(B). to the pixel shown, or a combination thereof may be added.​​​ You may also add etc.

[0312] 〔Organic EL Display Device〕 Another example of the circuit configuration of a pixel is shown in Fig. 27(C). Here, a display using an organic EL element shows the pixel structure of the device.

[0313] When a voltage is applied to the light-emitting element of the organic EL element, electrons are emitted from one of the pair of electrodes, and holes are injected from the other into the layer containing the light-emitting organic compound, and a current flows. And when the electrons and holes recombine, the light-emitting organic compound forms an excited state, and light is emitted when this excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

[0314] Fig. 27(C) is a diagram showing an example of an applicable pixel circuit. Here, an example of using two n-channel type transistors in one pixel is shown. Note that the metal oxide film of one aspect of the present invention can be used in the channel formation region of an n-channel type transistor. Also, the pixel circuit can apply digital time-division driving.

[0315] The configuration of the applicable pixel circuit and the operation of the pixel when digital time-division driving is applied will be described.

[0316] Pixel 720 has a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitive element 723. The switching transistor 721 has a gate electrode layer connected to the scanning line 726, a first electrode (one of the source electrode layer and the drain electrode layer) connected to the signal line 725, and a second electrode (the other of the source electrode layer and the drain electrode layer) ) is connected to the gate electrode layer of the driving transistor 722. The driving transistor 7 22 has its gate electrode layer connected to the power supply line 727 via the capacitor element 723, its first electrode connected to the power supply line 727, and its second electrode connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light-emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed on the same substrate.

[0317] For the switching transistor 721 and the driving transistor 722, transistors described in other embodiments can be appropriately used. Thereby, a highly reliable organic EL display device can be provided.

[0318] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. Note that the low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, and for example, GND , 0 V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the forward threshold voltage of the light-emitting element 724 or higher, and the potential difference is applied to the light-emitting element 724 to cause a current to flow through the light-emitting element 724 and emit light. Note that the forward voltage of the light-emitting element 72 4 refers to the voltage in the case of a desired luminance, and includes at least the forward threshold value voltage.

[0319] Note that the capacitor element 723 can be omitted by substituting the gate capacitance of the driving transistor 722. Regarding the gate capacitance of the driving transistor 722, a capacitance may be formed between the channel formation region and the gate electrode layer.

[0320] ​​Next, the signal input to the driving transistor 722 will be described. In the case of voltage input voltage driving method In the case of the formula, a video signal that causes the driving transistor 722 to be in one of two states, fully on or off, is input to the driving transistor 722. Note that in order to operate the driving transistor 722 in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722. Also, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the power supply line voltage is applied to the signal line 725.

[0321] When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the forward voltage of the light emitting element 724 is applied to the gate electrode layer of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in the saturation region, and a current flows through the light emitting element 724. Also, in order to operate the driving transistor 722 in the saturation region, the potential of the power supply line 727 is made higher than the gate potential of the driving transistor 722. By using an analog video signal, a current corresponding to the video signal can flow through the light emitting element 724, and analog gradation driving can be performed.

[0322] Note that the configuration of the pixel circuit is not limited to the pixel configuration shown in Fig. 27(C). For example, a switch, a resistance element, a capacitance element, a sensor, a transistor, or a logic circuit may be added to the pixel circuit shown in Fig. 27(C). (C)

[0323] When the transistors exemplified in the above embodiments are applied to the circuits exemplified in Fig. 27, the source electrode (first electrode) is on the low potential side and the drain electrode (second electrode) is on the high potential side, respectively. ​​​​​​​​​​​​configured to be connected thereto. Further, the potential of the first gate electrode is controlled by a control circuit or the like and the second gate electrode has a potential lower than the potential applied to the source electrode by a wiring (not shown), and may be configured to be able to input the potentials exemplified above.

[0324] For example, in this specification and the like, a display element, a display device which is a device having the display element, a light-emitting element, and a light-emitting device which is a device having the light-emitting element can use various forms or can have various elements. The display element, the display device, the light-emitting element, or the light-emitting device can be, for example, an EL (electroluminescence) element (an EL element including an organic and an inorganic substance, an organic EL element, an inorganic EL element), an LED (a white LED, a red LED, a green LED, a blue LED, etc.), a transistor (a transistor that emits light according to an electric current), an electron-emitting element, a liquid crystal element, an electro-ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using MEMS (micro electro mechanical system), a digital micromirror device (DMD), a DMS (digital micro shutter), a MIRASOL (registered trademark), an IMOD (interference modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electro-wetting element, a piezoelectric ceramic display, a display element using a carbon nanotube, etc., and has at least one of them. In addition to these, it may have a display medium in which contrast, luminance, reflectance, transmittance, etc. change due to an electrical or magnetic action. As an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron-emitting element, there are a field emission display ( FED) or a SED method flat panel display (SED: Surface-conduc tion Electron-emitter Display), etc. As an example of a display device using a liquid crystal element there are a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, a projection-type liquid crystal display), etc. As an example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoresis element there is electronic paper, etc. In addition, when realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes should have the function as a reflective electrode. For example, part or all of the pixel electrodes should have aluminum, silver, etc. Further, in that case, it is also possible to provide a memory circuit such as SRAM under the reflective electrode. Thereby, further power consumption can be reduced. Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0325]

[0326] (Embodiment 7) In this embodiment, a display module to which a semiconductor device according to one aspect of the present invention is applied will be described with reference to FIG. 28.

[0327] The display module 8000 shown in FIG. 28 has a touch panel 8004 connected to an FPC 8003 and an FPC 8005 connected to between an upper cover 8001 and a lower cover 8002. ​​It includes a display panel 8006, a backlight unit 8007, a frame 8009, a printed circuit board 8010, and a battery 8011. Note that the backlight unit 8007, the battery 8011, the touch panel 8004, etc. may not be provided in some cases.

[0328] The semiconductor device according to one aspect of the present invention can be used, for example, for the display panel 8006.

[0329] The upper cover 8001 and the lower cover 8002 can be appropriately changed in shape and dimensions according to the sizes of the touch panel 8004 and the display panel 8006.

[0330] The touch panel 8004 can be used by superimposing a touch panel of a resistive film type or a capacitive type on the display panel 8 006. Also, it is possible to provide a touch panel function on the counter substrate (sealing substrate ) of the display panel 8006. Or, it is also possible to provide an optical sensor in each pixel of the display panel 8 006 to form an optical touch panel. Or, it is also possible to provide a touch sensor electrode in each pixel of the display panel 8 006 to form a capacitive type touch panel.

[0331] The backlight unit 8007 has a light source 8008. The light source 8008 may be provided at the end of the backlight unit 8007, and a light diffusion plate may be used.

[0332] The frame 8009 has, in addition to the protection function of the display panel 8006, a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. Also, the frame 8009 may have a function as a heat dissipation plate.

[0333] The printed circuit board 8010 has a power circuit and a signal processing circuit for outputting video signals and clock signals. As the power source for supplying power to the power circuit, an external commercial power source may be used, or a separately provided battery 8011 may be used. When using a commercial power source, the battery 8011 can be omitted. In addition, members such as a polarizing plate, a retardation plate, and a prism sheet may be additionally provided in the display module 8000. It should be noted that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0334]

[0335]

[0336] (Embodiment 8) In this embodiment, an example of a circuit using a transistor according to one aspect of the present invention will be described with reference to the drawings.

[0337] [Cross-sectional structure] FIG. 29(A) shows a cross-sectional view of a semiconductor device according to one aspect of the present invention. The semiconductor device shown in FIG. 29(A) has a transistor 2200 using a first semiconductor material at the lower part and a transistor 2100 using a second semiconductor material at the upper part. In FIG. 29(A), as the transistor 2100 using the second semiconductor material, an example in which the transistor exemplified in the previous embodiment is applied is shown. Note that the left side of the dashed-dotted line is the cross-section in the channel length direction of the transistor, and the right side is the cross-section in the channel width direction. It is preferable that the first semiconductor material and the second semiconductor material have different bandgaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (including silicon (strained silicon)).

[0338] (mu), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.), and the second semiconductor The material can be an oxide semiconductor. Transistors using materials other than oxide semiconductors, such as single-crystal silicon etc., are easy to operate at high speed. On the other hand, transistors using oxide semiconductors have a low off-current.

[0339] The transistor 2200 can be either an n-channel type transistor or a p-channel type transistor , and an appropriate transistor can be used according to the circuit. In addition, except for using the transistor of one aspect of the present invention using an oxide semiconductor, there is no need to limit the specific configuration of the semiconductor device to what is shown here in terms of the materials and structures used .

[0340] In the configuration shown in FIG. 29(A), a transistor 2100 is provided above the transistor 2200 via an insulating film 2201 and an insulating film 2207. In addition, a plurality of wirings 2202 are provided between the transistor 2200 and the transistor 2100. Also, a plurality of plugs 2203 embedded in various insulating films electrically connect the wirings and electrodes provided in the upper layer and the lower layer, respectively. Further, an insulating film 2204 covering the transistor 2100 , a wiring 2205 on the insulating film 2204, and a wiring 2206 obtained by processing the same conductive film as a pair of electrodes of the transistor 2100 are provided .

[0341] In this way, by stacking two types of transistors, the occupied area of the circuit is reduced, and a plurality of circuits can be arranged with higher density.

[0342] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, hydrogen in the insulating film provided near the semiconductor film of the transistor 2200 terminates the dangling bonds of silicon, and has the effect of improving the reliability of the transistor 2200. On the other hand, when an oxide semiconductor is used for the transistor 2100 provided in the upper layer, hydrogen in the insulating film provided near the semiconductor film of the transistor 21 00 becomes one of the factors for generating carriers in the oxide semiconductor, and thus may be a factor for reducing the reliability of the transistor 2100. Therefore, when the transistor 2100 using an oxide semiconductor is laminated and provided on the upper layer of the transistor 2200 using a silicon-based semiconductor material, it is particularly effective to provide the insulating film 2207 having a function of preventing the diffusion of hydrogen between them. By the insulating film 220 7, by confining hydrogen in the lower layer, the reliability of the transistor 2200 is improved In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the reliability of the transistor 2100 can also be improved at the same time. As the insulating film 2207, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0343]

[0344] Also, so as to cover the transistor 2100 including the oxide semiconductor film, it is preferable to form a block film 2208 (corresponding to the insulating layer 180 in transistors 101 to 103) having a function of preventing the diffusion of hydrogen on the transistor 2100. 101 to the transistor As the blocking film 2208, the same material as the insulating film 2207 can be used, and in particular, applying aluminum oxide is preferable. The aluminum oxide film has a high blocking effect of not allowing the film to permeate both impurities such as hydrogen and moisture and oxygen. Therefore, by using an aluminum oxide film as the blocking film 2208 covering the transistor 2100, it is possible to prevent the desorption of oxygen from the oxide semiconductor film included in the transistor 2100 and prevent the entry of water and hydrogen into the oxide semiconductor film.

[0345] Note that the transistor 2200 can be not only a planar transistor but also various types of transistors. For example, it can be a FIN (fin) type, TRI-GATE (tri-gate) type, or other types of transistors. An example of a cross-sectional view in that case is shown in FIG. 29(D). An insulating film 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at the tip. Note that an insulating film may be provided on the convex portion. The insulating film functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the convex portion does not have to have a thin tip, and for example, it may be a substantially rectangular parallelepiped convex portion or a convex portion with a thick tip. A gate insulating film 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. It is not determined. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion. It doesn't matter.

[0346] [Circuit configuration example] In the above configuration, various circuits can be configured by varying the connection configurations of the electrodes of the transistors 2100 and 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described. By making them different, various circuits can be configured. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described. By using the semiconductor device, an example of a circuit configuration will be described.

[0347] [CMOS circuit] The circuit diagram shown in FIG. 29(B) shows a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. It shows the configuration of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. It shows the configuration of a so-called CMOS circuit.

[0348] [Analog switch] Also, the circuit diagram shown in FIG. 29(C) shows a configuration in which the sources and drains of the transistors 2100 and 2200 are connected. By adopting such a configuration, it can function as a so-called analog switch. It shows a configuration in which the sources and drains of the transistors 2100 and 2200 are connected. By adopting such a configuration, it can function as a so-called analog switch. It can function as a so-called analog switch.

[0349] [Example of memory device] An example of a semiconductor device (memory device) that can maintain stored content even when power is not supplied and has no limitation on the number of write operations by using the transistor according to one aspect of the present invention is shown in FIG. 30. An example of a semiconductor device (memory device) that can maintain stored content even when power is not supplied and has no limitation on the number of write operations by using the transistor according to one aspect of the present invention is shown in FIG. 30. It is shown in FIG. 30.

[0350] The semiconductor device shown in FIG. 30(A) includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that as the transistor 3300, the transistor described in the above embodiment can be used. Note that as the transistor 3300, the transistor described in the above embodiment can be used. It can be used.

[0351] FIG. 30(B) shows a cross-sectional view of the semiconductor device shown in FIG. 30(A). The semiconductor device in this cross-sectional view shows a configuration in which a back gate is provided for transistor 3300, but a configuration without a back gate may also be used.

[0352] Transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since transistor 3300 has a small off-current, it is possible to retain the stored content for a long time by using this transistor. That is, it is possible to configure a semiconductor memory device that does not require a refresh operation or requires only an extremely infrequent refresh operation, thereby significantly reducing power consumption.

[0353] In FIG. 30(A), wiring 3001 is electrically connected to the source electrode of transistor 3200, and wiring 3002 is electrically connected to the drain electrode of transistor 3200. Also, wiring 3003 is electrically connected to either the source electrode or the drain electrode of transistor 3300, and wiring 3004 is electrically connected to the gate electrode of transistor 3300. The gate electrode of transistor 3200 is electrically connected to the other of the source electrode or the drain electrode of transistor 3300 and to one of the electrodes of capacitor element 3400, and wiring 3005 is electrically connected to the other electrode of capacitor element 3400.

[0354] In the semiconductor device shown in FIG. 30(A), by taking advantage of the feature that the potential of the gate electrode of transistor 3200 can be retained, information can be written, retained, and read as follows.

[0355] The writing and holding of information will be described. First, the potential of wiring 3004 is set to the potential at which transistor 3300 is turned on, and transistor 3300 is turned on. As a result, the potential of wiring 3003 is applied to the gate electrode of transistor 3200 and capacitor element 3400. That is, a predetermined charge is applied to the gate of transistor 3200 (writing). Here, it is assumed that either one of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. Thereafter, the potential of wiring 3004 is set to the potential at which transistor 3300 is turned off, and transistor 3300 is turned off, so that the charge applied to the gate of transistor 3200 is held (holding). Since the off-current of transistor 3300 is extremely small, the charge on the gate of transistor 3200 is held for a long time. Next, the reading of information will be described. When an appropriate potential (reading potential) is applied to wiring 3005 in a state where a predetermined potential (constant potential) is applied to wiring 3001, wiring 3002 takes on different potentials according to the amount of charge held on the gate of transistor 3200. Generally, when transistor 3200 is an n-channel type, the apparent threshold value V when a High level charge is applied to the gate electrode of transistor 3200 is lower than the apparent threshold value V when a Low level charge is applied to the gate electrode of transistor 3200. Here, the apparent threshold voltage refers to the voltage at which transistor 3200 is

[0356]

[0357] th_H th_L ​​​​​​​​​​​​​​​​Refers to the potential of the wiring 3005 required to set it to the "on state". Therefore, the potential of the wir ing 3005 is set to the potential V0 between V th_H and V th_L so that the charge applied to the gate of the transistor 3200 can be determined. For example, in writing, when a Hi gh-level charge is applied, if the potential of the wiring 3005 becomes V0 (> V ) th_H ) , the transistor 3200 will be in the "on state". When a Low-level charge is applied , even if the potential of the wiring 3005 becomes V0 (< V th_L ), the transistor 3 200 will remain in the "off state". Therefore, by determining the potential of the wiring 3002, the stored information can be read out.

[0358] Note that when the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. If the information is not read in this way, a potential such that the transistor 3200 is in the "off state" regardless of the state of the gate, that is, a potential lower than V , may be applied to the wiring 3005. Or, a potential such that the transistor 3200 is in the "on state" regardless of the state of the gate, that is, a potential higher than V , may be applied to the wiring 3005. th_H than , may be applied to the wiring 3005. Or, a potential such that the transistor 3200 is in the "on state" regardless of the state of the gate, that is, a potential higher than V , may be applied to the wiring 3005. th_L than , may be applied to the wiring 3005.

[0359] The semiconductor device shown in FIG. 30(C) is different from FIG. 30(A ) in that it does not have the transistor 3200. In this case as well, the writing and holding operations of information are possible by the same operation as described above.

[0360] Next, the reading of information will be described. When the transistor 3300 is turned on, the floating​ In the floating state, the wiring 3003 and the capacitive element 3400 are electrically connected, and charges are redistributed between the wiring 3003 and the capacitive element 34 00. As a result, the potential of the wiring 3003 changes. The amount of change in the potential of the wiring 300 3 depends on the potential of the first terminal of the capacitive element 3400 (or the charge stored in the capacitive element 3400 ), and takes different values.

[0361] For example, let the potential of the first terminal of the capacitive element 3400 be V, the capacitance of the capacitive element 3400 be C, the capacitance component of the wiring 3003 be CB, and the potential of the wiring 3003 before charge redistribution be VB0 . Then, the potential of the wiring 3003 after charge redistribution is (CB×VB0 + C×V) / (CB + C). Therefore, assuming that the first terminal of the capacitive element 3400 takes two states of potential V1 and V0 (V1 > V0) as the state of the memory cell, the potential of the wiring 3003 when holding the potential V1 (=(CB×VB0 + C×V1) / (CB + C)) is higher than the potential of the wiring 3003 when holding the potential V0 (=(CB×VB0 + C×V0) / (CB + C)). It can be seen that + C)).

[0362] Then, information can be read by comparing the potential of the wiring 3003 with a predetermined potential.

[0363] In this case, a transistor in which the first semiconductor material is applied to a drive circuit for driving the memory cell, and a transistor in which the second semiconductor material is applied as the transistor 3300 are stacked and provided on the drive circuit.

[0364] In the semiconductor device shown in this embodiment, an off-current using an oxide semiconductor in the channel formation region By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0365] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, Problems such as deterioration of the gate insulating film are unlikely to occur. In this device, there is no limit to the number of times that can be rewritten, which is an issue with conventional non-volatile memory, and it is reliable. Furthermore, the on and off states of transistors allow the writing and reading of information to be performed Since the data is written into the memory, high speed operation can be easily achieved.

[0366] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0367] (Embodiment 9) In this embodiment, an RF device including a transistor or a memory device described in the previous embodiment is The tag will be described with reference to FIG.

[0368] The RF tag in this embodiment has a memory circuit therein and stores necessary information in the memory circuit. In addition, information is exchanged with the outside world using non-contact means, such as wireless communication. From these characteristics, the RF tag can be used for individual authentication systems such as identifying articles by reading individual information such as articles. It can be used for individual authentication systems and the like. In addition, extremely high reliability is required for use in these applications.

[0369] The configuration of the RF tag will be described with reference to FIG. 31. FIG. 31 is a block diagram showing a configuration example of the RF tag.

[0370] As shown in FIG. 31, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, a material capable of sufficiently suppressing the reverse current, for example, an oxide semiconductor, may be used for the transistor showing the rectifying action included in the demodulation circuit 807. Thus, it is possible to suppress a decrease in the rectifying action caused by the reverse current and prevent the output of the demodulation circuit from saturating. That is, it is possible to make the output of the demodulation circuit closer to linearity with respect to the input of the demodulation circuit. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in the present embodiment can be used in any of these methods.

[0371] Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. Also, the rectifier circuit 8 ​​​​​​​​​​​​​05 rectifies the input AC signal generated by receiving a wireless signal with the antenna 804 , for example, performs half-wave voltage doubler rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit that controls so that when the amplitude of the input AC signal is large and the internally generated voltage is large, power exceeding a certain level is not input to the subsequent circuit .

[0372] The constant voltage circuit 806 is a circuit that generates a stable power supply voltage from the input potential and supplies it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside . The reset signal generation circuit is a circuit that generates a reset signal for the logic circuit 80 9 by utilizing the rise of the stable power supply voltage.

[0373] The demodulation circuit 807 is a circuit that demodulates by envelope detection of the input AC signal and generates a demodulated signal. Also, the modulation circuit 808 is a circuit that performs modulation according to the data output from the antenna 804 .

[0374] The logic circuit 809 is a circuit that analyzes and processes the demodulated signal. The memory circuit 810 is a circuit that holds the input information and has a row decoder, a column decoder, a memory area, etc. . Also, the ROM 811 is a circuit that stores a unique number (ID), etc., and outputs according to the processing .

[0375] Note that each of the above circuits can be appropriately selected or discarded as needed.

[0376] Here, the storage device described in the previous embodiment can be used for the storage circuit 810. Since the storage circuit according to one aspect of the present invention can hold information even when the power supply is cut off, it can be suitably used for an RF tag. Furthermore, since the power (voltage) required for writing data in the storage circuit according to one aspect of the present invention is significantly smaller than that of a conventional nonvolatile memory, it is also possible not to cause a difference in the maximum communication distance between the time of reading data and the time of writing data. Furthermore, it is possible to suppress malfunction or incorrect writing due to insufficient power during data writing.

[0377] In addition, since the storage circuit according to one aspect of the present invention can be used as a nonvolatile memory, it can also be applied to the ROM 811. In that case, it is preferable to separately prepare a command for the producer to write data into the ROM 811 and prevent the user from freely rewriting it. By the producer writing a unique number before shipping and then shipping the product, it becomes possible to assign a unique number not to all the manufactured RF tags but only to the non-defective products to be shipped, and customer management corresponding to the products after shipping becomes easy because the unique numbers of the products after shipping do not become discontinuous.

[0378] Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0379] (Embodiment 10) In this embodiment, a CPU including the storage device described in the previous embodiment will be described.

[0380] FIG. 32 shows an example of a CPU that uses at least a part of the transistors described in the previous embodiment. It is a block diagram showing the configuration of an example.

[0381] The CPU shown in FIG. 32 has, on the substrate 1190, an ALU 1191 (ALU: Arithmet ic logic unit, arithmetic circuit), an ALU controller 1192, an instruct ion decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1 198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI sub strate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 32 is only an example shown with its configuration simplified, and an actual CPU has a wide variety of configurations depending on its application. For exam ple, a configuration including the CPU or the arithmetic circuit shown in FIG. 32 can be regarded as one core, and a configuration in which a plurality of such cores are included and each core operates in parallel may be used.

[0382] The instruction input to the CPU via the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0383] The ALU controller 1192, the interrupt controller 1194, the register control Based on the decoded instructions, the timing controller 1195 and the like perform various controls. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU program according to their priorities and mask states. The register controller 1197 generates addresses for the registers 1196 and reads from and writes to the registers 1196 according to the state of the CPU. Moreover, the timing controller 1195 generates signals for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1 and supplies the internal clock signal CLK2 to the various circuits described above. In the CPU shown in FIG. 32, memory cells are provided in the register 1196. As the memory cells of the register 1196, the transistors shown in the previous embodiment can be used. In the CPU shown in FIG. 32, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the memory cells of the register 1196, whether to hold data by a flip-flop or the capacitance is selected.

[0384]

[0385]

[0386] ​​​​​​​​​​​​​​Select whether to hold data by an element. When data holding by a flip-flop is selected, the power supply voltage is supplied to the memory cells in the register 1196 . When data holding in the capacitive element is selected, data rewriting to the capacitive element is performed, and the supply of the power supply voltage to the memory cells in the register 1196 can be stopped.

[0387] FIG. 33 is an example of a circuit diagram of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatile when the power supply is cut off, a circuit 1202 in which stored data is non-volatile when the power supply is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitive element 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistive element, and an inductor as necessary.

[0388] Here, the storage device described in the previous embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the gate of the transistor 120 9 in the circuit 1202 is configured to continuously receive a ground potential (0 V) or a potential at which the transistor 1209 is turned off. For example, the first gate of the transistor 1209 is grounded via a load such as a resistor .

[0389] The switch 1203 is configured by using a transistor 1213 of one conductivity type (for example, an n-channel type), and the switch 1204 is of a conductivity type opposite to that of the one conductivity type (for example, a p-channel type) . ​An example configured using the transistor 1214 is shown. Here, the first end of the switch 1203 corresponds to one of the source and drain of the transistor 1213, and the second terminal of the switch 1203 corresponds to the other of the source and drain of the transistor 1213. The switch 1203 is made conductive or non-conductive between the first terminal and the second terminal (that is, the on state or off state of the transistor 1213) by the control signal RD input to the gate of the transistor 1213. The first terminal of the switch 1204 corresponds to one of the source and drain of the transistor 1214, and the second terminal of the switch 1204 corresponds to the other of the source and drain of the transistor 1214. The switch 1204 is made conductive or non-conductive between the first terminal and the second terminal (that is, the on state or off state of the transistor 1214) by the control signal RD input to the gate of the transistor 1214. One of the source and drain of the transistor 1209 is electrically connected to one of the pair of electrodes of the capacitive element 1208 and to the gate of the transistor 1210. Here, this connection

[0390] portion is designated as node M2. One of the source and drain of the transistor 1210 is electrically connected to a wiring (for example, a GND line) that can supply a low power supply potential , and the other is electrically connected to the first terminal of the switch 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (one of the source and drain of the transistor 1214). The second terminal of the switch 1204 (the source and drain of the transistor 1214) is electrically connected to the first terminal of the switch 1203 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (one of the source and drain of the transistor 1214). The second terminal of the switch 1204 (one of the source and drain of the transistor 1214) is electrically connected to the first terminal of the switch 1204 (one of the source and drain of the transistor 1214). One of the source and drain of the transistor 1210 is electrically connected to a wiring (for example, a GND line) that can supply a low power supply potential, and the other is electrically connected to the first terminal of the switch 1203 (one of the source and drain of the transistor 1213). ​The other of the source and the drain) is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) and the first terminal of the switch 1204 (one of the source and the drain of the transistor 1214) and the input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor element 1207 are electrically connected. Here, the connection part is defined as the node M1. The other of the pair of electrodes of the capacitor element 1207 can be configured to receive a constant potential. For example, it can be configured to receive a low power supply potential (such as GND) or a high power supply potential (such as VDD). The other of the pair of electrodes of the capacitor element 1207 is electrically connected to a wiring (for example, a GND line) capable of supplying a low power supply potential. The other of the pair of electrodes of the capacitor element 1208 can be configured to receive a constant potential. For example, it can be configured to receive a low power supply potential (such as GND) or a high power supply potential (such as VDD). The other of the pair of electrodes of the capacitor element 1208 is electrically connected to a wiring (for example, a GND line) capable of supplying a low power supply potential. Note that the capacitor elements 1207 and 1208 can also be omitted by actively using the parasitic capacitances of transistors and wirings, etc. The control signal WE is input to the first gate (the first gate electrode) of the transistor 1209. The switches 1203 and 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. One of the switches

[0391]

[0392] ​​​​​​When the first terminal and the second terminal of the switch are in a conducting state, the first terminal and the second terminal of the other switch are in a non-conducting state. When the first terminal and the second terminal of the switch are in a conducting state, the first terminal and the second terminal of the other switch are in a non-conducting state.

[0393] Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used. Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used. Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used. Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used. Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used. Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used. Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used. Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used. Note that in the transistor 1209 in FIG. 33, a configuration having a second gate (second gate electrode: back gate) is illustrated. A control signal WE is input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 1209 is selected. At this time, the control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 1209, and the Ic ut of the transistor 1209 can be further reduced. Further, the control signal WE2 may be the same potential signal as the control signal WE. Note that as the transistor 1209, a transistor having no second gate can also be used.

[0394] To the other of the source and drain of the transistor 1209, a signal corresponding to the data held in the circuit 1201 is input. In FIG. 33, an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209 is shown. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. To the other of the source and drain of the transistor 1209, a signal corresponding to the data held in the circuit 1201 is input. In FIG. 33, an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209 is shown. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. To the other of the source and drain of the transistor 1209, a signal corresponding to the data held in the circuit 1201 is input. In FIG. 33, an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209 is shown. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. To the other of the source and drain of the transistor 1209, a signal corresponding to the data held in the circuit 1201 is input. In FIG. 33, an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209 is shown. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. To the other of the source and drain of the transistor 1209, a signal corresponding to the data held in the circuit 1201 is input. In FIG. 33, an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209 is shown. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220. To the other of the source and drain of the transistor 1209, a signal corresponding to the data held in the circuit 1201 is input. In FIG. 33, an example in which the signal output from the circuit 1201 is input to the other of the source and drain of the transistor 1209 is shown. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) becomes an inverted signal whose logical value is inverted by the logic element 1206 and is input to the circuit 1201 via the circuit 1220.

[0395] Note that in FIG. 33, the signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) passes through the logic element 1206 and the circuit 1220 and then returns Note that in FIG. 33, the signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) passes through the logic element 1206 and the circuit 1220 and then returns Although an example of input to path 1201 has been shown, it is not limited thereto. The second terminal of switch 1203 (the other of the source and drain of transistor 1213), the output signal may be input to circuit 1201 without inverting the logic value. For example, if there is a node in circuit 1201 that holds a signal whose logic value is the inversion of the signal input from the input terminal , the signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) can be input to the node. In FIG. 33, among the transistors used in memory element 1200, transistors other than transistor 1209 can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, they can be transistors in which a channel is formed in a silicon layer or

[0396] a silicon substrate. Also, all the transistors used in memory element 1200 can be transistors in which a channel is formed in an oxide semiconductor layer. Or, memory element 1200 may also include transistors in which a channel is formed in an oxide semiconductor layer other than transistor 1209, and the remaining transistors can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. In FIG. 33, for circuit 1201, for example, a flip-flop circuit can be used. Also, as logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

[0397]

[0398] ​​​​​​​In the semiconductor device according to one aspect of the present invention, while the power supply voltage is not supplied to the memory element 1200, the data stored in the circuit 1201 can be held by the capacitor element 1208 provided in the circuit 1202.

[0399] Also, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer is significantly lower than the off-current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor element 1208 can be maintained for a long time even while the power supply voltage is not supplied to the memory element 1200. Thus, the memory element 1200 can hold the stored content (data) even while the supply of the power supply voltage is stopped.

[0400] Also, since the memory element is characterized by performing a precharge operation by providing the switch 1203 and the switch 1204, the time until the circuit 1201 restores the original data after the resumption of the power supply voltage can be shortened.

[0401] Also, in the circuit 1202, the signal held by the capacitor element 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is resumed, the signal held by the capacitor element 1208 can be converted into the state (on state or off state) of the transistor 1210 and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal can be accurately read out. ​​​​​​​​​

[0402] By using such a memory element 1200 in a memory device such as a register or a cache memory that the processor has, it is possible to prevent the loss of data in the memory device due to the supply stop of the power supply voltage. Also, after the supply of the power supply voltage is resumed, it is possible to return to the state before the power supply stop in a short time. Therefore, in the entire processor or one or a plurality of logic circuits constituting the processor, power supply stop can be performed even for a short time, so that power consumption can be suppressed. In the present embodiment, an example in which the memory element 1200 is used for the CPU has been described. However, the memory element 1 200 can also be applied to LSIs such as DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device), and RFID (Radio Frequency Identification).

[0403] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0404]

[0405] (Embodiment 11) In the present embodiment, a modified example of a transistor according to one aspect of the present invention will be described with reference to FIGS. 34 to 38.

[0406] The transistor shown in FIG. 34 includes an oxide semiconductor layer 755 formed on an insulating layer 753 on a substrate 751, an insulating layer 757 in contact with the oxide semiconductor layer 755, and a conductive layer 759 in contact with the insulating layer 757 and overlapping the oxide semiconductor layer 755. Note that the insulating layer 757 is a gate It has a function as a gate insulating layer. Further, the conductive layer 759 has a function as a gate electrode layer. It does.

[0407] Further, a nitride insulating layer 765 in contact with the oxide semiconductor layer 755 and an insulating layer 767 in contact with the nitride insulating layer 765 are provided in the transistor. Also, at the openings of the nitride insulating layer 765 and the insulating layer 767, conductive layers 768 and 769 in contact with the oxide semiconductor layer 755 are provided in the transistor. Note that the conductive layers 768 and 769 have functions as a source electrode layer and a drain electrode layer. It does. At the openings of the nitride insulating layer 765 and the insulating layer 767, conductive layers 768 and 769 in contact with the oxide semiconductor layer 755 are provided in the transistor. Note that the conductive layers 768 and 769 have functions as a source electrode layer and a drain electrode layer. It does.

[0408] In the transistor shown in FIG. 34(A), the oxide semiconductor layer 755 has a channel region 755a formed in a region overlapping with the conductive layer 759, and low-resistance regions 755b and 755c that sandwich the channel region 755a and contain impurity elements. Also, the conductive layers 768 and 769 are in contact with the low-resistance regions 755b and 755c. Note that the conductive layers 768 and 769 function as wiring. It does. It does. Note that the conductive layers 768 and 769 are in contact with the low-resistance regions 755b and 755c. Note that the conductive layers 768 and 769 function as wiring.

[0409] Alternatively, as in the transistor shown in FIG. 34(B), impurity elements may not be added to regions 755d and 755e in contact with the conductive layers 768 and 769 in the oxide semiconductor layer 755. In this case, regions having impurity elements, that is, low-resistance regions 755b and 755c, are provided between regions 755d and 755e in contact with the conductive layers 768 and 769 and the channel region 755a. Note that since regions 755d and 755e have conductivity when a voltage is applied to the conductive layers 768 and 769, they function as a source region and a drain region. It does. It does. It does. It does. It does.

[0410] Note that the transistor shown in FIG. 34(B) can be formed by adding impurity elements to the oxide semiconductor layer using the conductive layers 759 and 768, 769 as masks after forming the conductive layers 759 and the conductive layers 768, 769.

[0411] In the conductive layer 759, the end portion of the conductive layer 759 may have a tapered shape. That is, the angle θ1 formed by the surface where the insulating layer 757 and the conductive layer 759 are in contact and the side surface of the conductive layer 759 is less than 90°, or 30° or more and 85° or less, or 45° or more and 85° or less, or 60° or more and 85 ° or less. By setting the angle θ1 to less than 90°, or 30° or more and 85° or less, or 45° or more and 85° or less, or 60° or more and 85° or less, it is possible to improve the coverage of the nitride insulating layer 765 on the side surfaces of the insulating layer 757 and the conductive layer 759.

[0412] Next, a modified example of the low resistance regions 755b and 755c will be described. FIGS. 34(C) to 34(F) are enlarged views of the vicinity of the oxide semiconductor layer 755 shown in FIG. 34(A). Here, the channel length L is the interval between a pair of low resistance regions.

[0413] As shown in FIG. 34(C), in the cross-sectional shape in the channel length direction, the boundaries of the channel region 755a and the low resistance regions 755b and 755c coincide or substantially coincide with the end portions of the conductive layer 759 via the insulating layer 757. That is, in the top surface shape, the boundaries of the channel region 755a and the low resistance regions 755b and 755c coincide or substantially coincide with the end portions of the conductive layer 759.

[0414] Alternatively, as shown in FIG. 34(D), in the cross-sectional shape in the channel length direction, the channel region ​​​​​​​755a has a region that does not overlap with the conductive layer 759. This region functions as an offset region. The length of the offset region in the channel length direction is denoted as Loff. When there are multiple offset regions, the length of one offset region is referred to as Loff. Loff is included in the channel length L. Also, Loff is less than 20% of the channel length L, or less than 10%, or less than 5%, or less than 2%. Or, as shown in FIG. 34(E), in the cross-sectional shape in the channel length direction, the low-resistance regions 7 55b and 755c have a region that overlaps with the conductive layer 759 via the insulating layer 757. This region functions as an overlap region. The length of the overlap region in the channel length direction is denoted as Lov. Lov is less than 20% of the channel length L, or less than 10%, or less than 5%, or less than 2%.

[0415] Or, as shown in FIG. 34(F), in the cross-sectional shape in the channel length direction, there is a low-resistance region 755f between the channel region 755a and the low-resistance region 755b, and a low-resistance region 755g between the channel region 755a and the low-resistance region 755c. The low-resistance regions 755f and 755 g have a lower impurity element concentration and a higher resistivity than the low-resistance regions 755b and 755c. Here, the low-resistance regions 755f and 755g overlap with the insulating layer 757, but may also overlap with the insulating layer 757 and the conductive layer 759.

[0416] Note that in FIGS. 34(C) to 34(F), the transistor shown in FIG. 34(A) has been described. However, in the transistor shown in FIG. 34(B) as well, the structures of FIGS. 34(C) to 34(F ) can be appropriately applied as needed.

[0417] ​​​​​​​​​​​

[0418] In the transistor shown in FIG. 35(A), the end of the insulating layer 757 is located outside the end of the conductive layer 759. That is, the insulating layer 757 has a shape protruding from the conductive layer 759. Since it is possible to keep the nitride insulating layer 765 away from the channel region 755a, it is possible to suppress nitrogen, hydrogen, etc. contained in the nitride insulating layer 765 from entering the channel region 755a. In the transistor shown in FIG. 35(B), the insulating layer 757 and the conductive layer 759 are in a tapered shape, and the angles of the respective tapered portions are different. That is, the angle θ1 formed by the surface where the insulating layer 757 and the conductive layer 759 are in contact and the side surface of the conductive layer 759, and the angle θ2 formed by the surface where the oxide semiconductor layer 755 and the insulating layer 757 are in contact and the side surface of the insulating layer 757 are different. The angle θ2 may be less than 90°, or 30° or more and 85° or less, or 45° or more and 70° or less. For example, when the angle θ2 is smaller than the angle θ1, the coverage of the nitride insulating layer 765 is increased. Also, when the angle θ2 is larger than the angle θ1, since it is possible to keep the nitride insulating layer 765 away from the channel region 755a, it is possible to suppress nitrogen, hydrogen, etc. contained in the nitride insulating layer 765 from entering the channel region 755a. Next, a modified example of the low-resistance regions 755b and 755c will be described with reference to FIGS. 35(C) to 35(F). FIGS. 35(C) to 35(F) are enlarged views of the vicinity of the oxide semiconductor layer 755 shown in FIG. 35(A). As shown in FIG. 35(C), in the cross-sectional shape in the channel length direction, the channel region 755a

[0419]

[0420]

[0421] and the boundaries of the low-resistance regions 755b and 755c coincide or approximately coincide with the end of the conductive layer 759 via the insulating layer 757. That is, in the top surface shape, the boundary between the channel region 755a and the low-resistance regions 755b and 755c coincides or approximately coincides with the end of the conductive layer 759. That is, in the top surface shape, the boundary between the channel region 755a and the low-resistance regions 755b and 755c coincides or approximately coincides with the end of the conductive layer 759. That is.

[0422] Alternatively, as shown in FIG. 35(D), in the cross-sectional shape in the channel length direction, the channel region 755a has a region that does not overlap with the conductive layer 759. This region functions as an offset region. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c coincide or approximately coincide with the end of the insulating layer 757 and do not overlap with the end of the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c coincide or approximately coincide with the end of the insulating layer 757 and do not overlap with the end of the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c coincide or approximately coincide with the end of the insulating layer 757 and do not overlap with the end of the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c coincide or approximately coincide with the end of the insulating layer 757 and do not overlap with the end of the conductive layer 759.

[0423] Alternatively, as shown in FIG. 35(E), in the cross-sectional shape in the channel length direction, the low-resistance regions 755b and 755c have a region that overlaps with the conductive layer 759 via the insulating layer 757. This region is called an overlap region. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759.

[0424] Alternatively, as shown in FIG. 35(F), in the cross-sectional shape in the channel length direction, there is a low-resistance region 755f between the channel region 755a and the low-resistance region 755b, and a low-resistance region 755g between the channel region 755a and the low-resistance region 755c. The low-resistance regions 755f and 755g have a lower concentration of impurity elements and a higher resistivity than the low-resistance regions 755b and 755c. Here, the low-resistance regions 755f and 755g overlap with the insulating layer 757, but may also overlap with the insulating layer 757 and the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759. That is, in the top surface shape, the ends of the low-resistance regions 755b and 755c overlap with the conductive layer 759.

[0425] In FIGS. 35(C) to 35(F), the transistor shown in FIG. 35(A) has been described. However, in the transistor shown in FIG. 35(B) as well, the structure of FIGS. 35(C) to 35(F) can be appropriately applied. In FIGS. 35(C) to 35(F), the transistor shown in FIG. 35(A) has been described. However, in the transistor shown in FIG. 35(B) as well, the structure of FIGS. 35(C) to 35(F) can be appropriately applied. In FIGS. 35(C) to 35(F), the transistor shown in FIG. 35(A) has been described. However, in the transistor shown in FIG. 35(B) as well, the structure of FIGS. 35(C) to 35(F) can be appropriately applied.

[0426] The transistor shown in FIG. 36(A) has a laminated structure of a conductive layer 759, and includes a conductive layer 759a in contact with an insulating layer 757 and a conductive layer 759b in contact with the conductive layer 759a. Further, an end portion of the conductive layer 759a is located outside an end portion of the conductive layer 759b. That is, the conductive layer 759a has a shape protruding from the conductive layer 759b. The transistor shown in FIG. 36(A) has a laminated structure of a conductive layer 759, and includes a conductive layer 759a in contact with an insulating layer 757 and a conductive layer 759b in contact with the conductive layer 759a. Further, an end portion of the conductive layer 759a is located outside an end portion of the conductive layer 759b. That is, the conductive layer 759a has a shape protruding from the conductive layer 759b. The transistor shown in FIG. 36(A) has a laminated structure of a conductive layer 759, and includes a conductive layer 759a in contact with an insulating layer 757 and a conductive layer 759b in contact with the conductive layer 759a. Further, an end portion of the conductive layer 759a is located outside an end portion of the conductive layer 759b. That is, the conductive layer 759a has a shape protruding from the conductive layer 759b. The transistor shown in FIG. 36(A) has a laminated structure of a conductive layer 759, and includes a conductive layer 759a in contact with an insulating layer 757 and a conductive layer 759b in contact with the conductive layer 759a. Further, an end portion of the conductive layer 759a is located outside an end portion of the conductive layer 759b. That is, the conductive layer 759a has a shape protruding from the conductive layer 759b.

[0427] Next, modified examples of the low resistance regions 755b and 755c will be described. FIGS. 36(B) to 36(E) and FIGS. 37(A) and (B) are enlarged views of the vicinity of the oxide semiconductor layer 755 shown in FIG. 36(A). Next, modified examples of the low resistance regions 755b and 755c will be described. FIGS. 36(B) to 36(E) and FIGS. 37(A) and (B) are enlarged views of the vicinity of the oxide semiconductor layer 755 shown in FIG. 36(A). Next, modified examples of the low resistance regions 755b and 755c will be described. FIGS. 36(B) to 36(E) and FIGS. 37(A) and (B) are enlarged views of the vicinity of the oxide semiconductor layer 755 shown in FIG. 36(A).

[0428] As shown in FIG. 36(B), in a cross-sectional shape in the channel length direction, a boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759a included in the conductive layer 759 via the insulating layer 757. That is, in a top surface shape, the boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759. As shown in FIG. 36(B), in a cross-sectional shape in the channel length direction, a boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759a included in the conductive layer 759 via the insulating layer 757. That is, in a top surface shape, the boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759. As shown in FIG. 36(B), in a cross-sectional shape in the channel length direction, a boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759a included in the conductive layer 759 via the insulating layer 757. That is, in a top surface shape, the boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759. As shown in FIG. 36(B), in a cross-sectional shape in the channel length direction, a boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759a included in the conductive layer 759 via the insulating layer 757. That is, in a top surface shape, the boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759. As shown in FIG. 36(B), in a cross-sectional shape in the channel length direction, a boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759a included in the conductive layer 759 via the insulating layer 757. That is, in a top surface shape, the boundary between the channel region 755a and the low resistance regions 755b and 755c coincides or substantially coincides with an end portion of the conductive layer 759.

[0429] Alternatively, as shown in FIG. 36(C), in a cross-sectional shape in the channel length direction, the channel region 755a has a region that does not overlap with the conductive layer 759. This region functions as an offset region. That is, in a top surface shape, ends of the low resistance regions 755b and 755c do not overlap with an end portion of the conductive layer 759. Alternatively, as shown in FIG. 36(C), in a cross-sectional shape in the channel length direction, the channel region 755a has a region that does not overlap with the conductive layer 759. This region functions as an offset region. That is, in a top surface shape, ends of the low resistance regions 755b and 755c do not overlap with an end portion of the conductive layer 759. Alternatively, as shown in FIG. 36(C), in a cross-sectional shape in the channel length direction, the channel region 755a has a region that does not overlap with the conductive layer 759. This region functions as an offset region. That is, in a top surface shape, ends of the low resistance regions 755b and 755c do not overlap with an end portion of the conductive layer 759. Alternatively, as shown in FIG. 36(C), in a cross-sectional shape in the channel length direction, the channel region 755a has a region that does not overlap with the conductive layer 759. This region functions as an offset region. That is, in a top surface shape, ends of the low resistance regions 755b and 755c do not overlap with an end portion of the conductive layer 759.

[0430] Or, as shown in FIG. 36(D), in the cross-sectional shape in the channel length direction, the low-resistance regions 7 55b and 755c have regions overlapping with the conductive layer 759, here the conductive layer 759a. The region is called an overlap region. That is, in the top surface shape, the ends of the low-resistance regions 755b and 75 5c overlap with the conductive layer 759a.

[0431] Or, as shown in FIG. 36(E), in the cross-sectional shape in the channel length direction, there is a low-resistance region 755f between the channel region 755a and the low-resistance region 755b, and there is a low-resistance region 755g between the channel region 755a and the low-resistance region 755c. The impurity element passes through the conductive layer 759 a and is added to the low-resistance regions 755f and 755g. Therefore, the low-resistance regions 755f and 7 55g have a lower concentration of impurity elements and a higher resistivity than the low-resistance regions 755b and 755c. Here, the low-resistance regions 755f and 755g overlap with the conductive layer 759a, but may also overlap with the conductive layer 759a and the conductive layer 759b.

[0432] Or, as shown in FIG. 37(A), in the cross-sectional shape in the channel length direction, the end of the conductive layer 759 a is located outside the end of the conductive layer 759b, and the conductive layer 759a may be in a tapered shape That is, the angle formed by the surface where the insulating layer 757 and the conductive layer 759a are in contact and the side surface of the conductive layer 759a is less than 90°, or 5° or more and 45° or less, or 5° or more and 30° or less may also be acceptable.

[0433] Furthermore, the end of the insulating layer 757 may be located outside the end of the conductive layer 759a.

[0434] Furthermore, the side surface of the insulating layer 757 may be curved.

[0435] Furthermore, the insulating layer 757 may be in a tapered shape. That is, the angle formed between the surface where the oxide semiconductor layer 755 and the insulating layer 757 are in contact and the side surface of the insulating layer 757 may be less than 90°, preferably 3 0° or more and less than 90°.

[0436] The oxide semiconductor layer 755 shown in FIG. 37(A) includes a channel region 755a, low-resistance regions 755f and 755g sandwiching the channel region 7 55a, low-resistance regions 755h and 755i sandwiching the low-resistance regions 755f and 755g, and low-resistance regions 755 b and 755c sandwiching the low-resistance regions 755h and 755i. Since impurity elements pass through the insulating layer 757 and the conductive layer 759a and are added to the low -resistance regions 755f, 755g, 755h, and 755i, the low-resistance regions 755 f, 755g, 755h, and 755i have a lower impurity element concentration and a higher resistivity than the low-resistance regions 755b and 755c.

[0437] The oxide semiconductor layer 755 shown in FIG. 37(B) includes a channel region 755a, low-resistance regions 755h and 755i sandwiching the channel region 7 55a, and low-resistance regions 755b and 755c sandwiching the low-resistance regions 755h and 755i. Since impurity elements pass through the insulating layer 757 and are added to the low-resistance regions 755h and 755i, the low-resistance regions 755h and 755i have a lower impurity element concentration and a higher resistivity than the low-resistance regions 755b and 755c.

[0438] Note that in the channel length direction, the channel region 755a overlaps with the conductive layer 759b, and the low-resistance regions 755f and 755g overlap with the conductive layer 759a protruding outside the conductive layer 759b, and the low-resistance regions 755h and 755i overlap with the insulating layer 7 protruding outside the conductive layer 759a It overlaps with 57, and the low-resistance regions 755b and 755c are provided outside the insulating layer 757.

[0439] As shown in FIGS. 36(E) and 37(A) and (B), the oxide semiconductor layer 755 has low-resistance regions 755f, 755g, 755h, and 755i where the concentration of impurity elements is lower and the resistivity is higher than in the low-resistance regions 755b and 755c, by which the electric field relaxation in the drain region can be achieved, and the variation in the threshold voltage of the transistor can be reduced.

[0440] Note that FIG. 37(C) is an enlarged view of the vicinity of the end of the conductive layer 759 in the channel width direction of the transistor shown in FIGS. 37(A) and (B).

[0441] The transistor shown in FIG. 38(A) has an oxide semiconductor layer 755 including a channel region 755a and low-resistance regions 755b and 755c, and the low-resistance regions 755b and 755c have regions with a smaller film thickness than the channel region 755a. Typically, the low-resistance regions 755b and 755c have regions with a thickness smaller by 0.1 nm or more and 5 nm or less than the channel region 755a.

[0442] In the transistor shown in FIG. 38(B), at least one of the insulating layers 753 and 757 in contact with the oxide semiconductor layer 755 has a multilayer structure. For example, the insulating layer 753 has an insulating layer 753a and an insulating layer 753b in contact with the insulating layer 753a and the oxide semiconductor layer 755. Also, the insulating layer 757 has an insulating layer 757a in contact with the oxide semiconductor layer 755 and an insulating layer 757b in contact with the insulating layer 757a.

[0443] The insulating layers 753b and 757a have the energy (E at the upper end of the valence band of the oxide semiconductor film v_o s ​​​​) and the energy (E at the lower end of the conduction band c_os ) can be formed using an oxide insulating film with a low density of nitrogen oxide levels between them. E v_os and E c_os between them, as an oxide insulating film with a low density of nitrogen oxide levels, a silicon oxynitride film with a low nitrogen oxide emission amount, or an aluminum oxynitride film with a low nitrogen oxide emission amount, etc. can be used. Note that the insulating layers 753b and 757a have an average film thickness of 0.1 nm or more and 50 nm or less, or 0.5 nm or more and 10 nm or less.

[0444] Note that a silicon oxynitride film with a low nitrogen oxide emission amount is a film in which the ammonia emission amount is larger than the nitrogen oxide emission amount in temperature-programmed desorption gas analysis (TDS (Thermal Desorption Spectroscopy)), and typically, the ammonia emission amount is 1×10 or more and 5×10 18 atoms / cm 3 or less. Note that the ammonia 19 emission amount is the emission amount by heat treatment at a film surface temperature of 50°C or more and 650°C or less, preferably 50°C or more and 550°C or less. 3

[0445] The insulating layers 753a and 757b can be formed using an oxide insulating film that releases oxygen upon heating. Note that the insulating layers 753a and 757b have an average film thickness of 5 nm or more and 1000 nm or less, or 10 nm or more and 500 nm or less.

[0446] Representative examples of the oxide insulating film that releases oxygen upon heating include a silicon oxynitride film, an aluminum oxynitride film, etc.

[0447] Nitrogen oxide (NO x 、x is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO2 Or NO forms levels in the insulating layers 753 and 757 and the like. The said levels are located within the energy gap of the oxide semiconductor layer 755. Therefore, when nitrogen oxide diffuses to the interface of the insulating layers 753, 757 and the oxide semiconductor layer 755, the said levels may trap electrons on the insulating layer 75 3, 757 side. As a result, the trapped electrons stay near the interface of the insulating layers 753, 757 and the oxide semiconductor layer 755, thus shifting the threshold voltage of the transistor in the positive direction. layer 753, 757 and the oxide semiconductor layer 755 interface near, so that the threshold voltage of the transistor is shifted in the positive direction. 3, 757 side, there is a case where electrons are trapped. As a result, the trapped electrons stay near the interface of the insulating layers 753, 757 and the oxide semiconductor layer 755, so that the threshold voltage of the transistor is shifted in the positive direction.

[0448] Also, nitrogen oxide reacts with ammonia and oxygen in the heat treatment. The nitrogen oxide contained in the insulating layers 753a and 757b reacts with the ammonia contained in the insulating layers 753b and 757a in the heat treatment, so that the nitrogen oxide contained in the insulating layers 753a and 757b is low ereduced. Therefore, at the interface of the insulating layers 753, 757 and the oxide semiconductor layer 755, electrons are less likely to be trapped. Electrons are less likely to be trapped.

[0449] As the insulating layers 753b and 757a, E v_os ...

Claims

1. A semiconductor device including a transistor including an oxide semiconductor layer, A conductive layer; a first insulating layer having a region overlying the conductive layer; the oxide semiconductor layer having a region located above the first insulating layer; a source electrode and a drain electrode having a region located above the oxide semiconductor layer; a gate insulating layer having a region located above the oxide semiconductor layer; a gate electrode having a region located above the gate insulating layer; a second insulating layer having a region located above the gate electrode; the second insulating layer has a region in contact with an upper surface of the gate electrode, a region in contact with an upper surface of the source electrode, and a region in contact with an upper surface of the drain electrode; the first insulating layer has a first region in contact with the oxide semiconductor layer and a second region in contact with the second insulating layer; a thickness of the first insulating layer in the first region is greater than a thickness of the first insulating layer in the second region; In a cross-sectional view parallel to a channel length direction of a transistor, the oxide semiconductor layer has a third region in contact with the gate insulating layer, a fourth region in contact with the second insulating layer and adjacent to the third region, and a fifth region in contact with the source electrode or the drain electrode, a thickness of the oxide semiconductor layer in the third region is greater than a thickness of the oxide semiconductor layer in the fourth region; the oxide semiconductor layer has a region overlapping with the conductive layer.

2. A semiconductor device including a transistor including an oxide semiconductor layer, A conductive layer; a first insulating layer having a region overlying the conductive layer; the oxide semiconductor layer having a region located above the first insulating layer; a source electrode and a drain electrode having a region located above the oxide semiconductor layer; a gate insulating layer having a region located above the oxide semiconductor layer; a gate electrode having a region located above the gate insulating layer; a second insulating layer having a region located above the gate electrode; the second insulating layer has a region in contact with an upper surface of the gate electrode, a region in contact with an upper surface of the source electrode, and a region in contact with an upper surface of the drain electrode; the first insulating layer has a first region in contact with the oxide semiconductor layer and a second region in contact with the second insulating layer; a thickness of the first insulating layer in the first region is greater than a thickness of the first insulating layer in the second region; In a cross-sectional view parallel to a channel length direction of a transistor, the oxide semiconductor layer has a third region in contact with the gate insulating layer, a fourth region in contact with the second insulating layer and adjacent to the third region, and a fifth region in contact with the source electrode or the drain electrode, a thickness of the oxide semiconductor layer in the third region is greater than a thickness of the oxide semiconductor layer in the fourth region; in a cross-sectional view parallel to a channel width direction of the transistor, the gate electrode has a region facing a top surface of the oxide semiconductor layer with the gate insulating layer interposed therebetween and a region facing a side surface of the oxide semiconductor layer with the gate insulating layer interposed therebetween; the oxide semiconductor layer has a region overlapping with the conductive layer.

3. A semiconductor device including a transistor including an oxide semiconductor layer, A conductive layer; a first insulating layer having a region overlying the conductive layer; the oxide semiconductor layer having a region located above the first insulating layer; a source electrode and a drain electrode having a region located above the oxide semiconductor layer; a gate insulating layer having a region located above the oxide semiconductor layer; a gate electrode having a region located above the gate insulating layer; a second insulating layer having a region located above the gate electrode; the second insulating layer has a region in contact with an upper surface of the gate electrode, a region in contact with an upper surface of the source electrode, and a region in contact with an upper surface of the drain electrode; the first insulating layer has a first region in contact with the oxide semiconductor layer and a second region in contact with the second insulating layer and adjacent to the first region; a thickness of the first insulating layer in the first region is greater than a thickness of the first insulating layer in the second region; In a cross-sectional view parallel to a channel length direction of the transistor, the oxide semiconductor layer has a third region in contact with the gate insulating layer, a fourth region in contact with the second insulating layer and adjacent to the third region, and a fifth region in contact with the source electrode or the drain electrode, a thickness of the oxide semiconductor layer in the third region is greater than a thickness of the oxide semiconductor layer in the fourth region; the oxide semiconductor layer has a region overlapping with the conductive layer.

4. A semiconductor device including a transistor including an oxide semiconductor layer, A conductive layer; a first insulating layer having a region overlying the conductive layer; the oxide semiconductor layer having a region located above the first insulating layer; a source electrode and a drain electrode having a region located above the oxide semiconductor layer; a gate insulating layer having a region located above the oxide semiconductor layer; a gate electrode having a region located above the gate insulating layer; a second insulating layer having a region located above the gate electrode; the second insulating layer has a region in contact with an upper surface of the gate electrode, a region in contact with an upper surface of the source electrode, and a region in contact with an upper surface of the drain electrode; the first insulating layer has a first region in contact with the oxide semiconductor layer and a second region in contact with the second insulating layer and adjacent to the first region; a thickness of the first insulating layer in the first region is greater than a thickness of the first insulating layer in the second region; In a cross-sectional view parallel to a channel length direction of the transistor, the oxide semiconductor layer has a third region in contact with the gate insulating layer, a fourth region in contact with the second insulating layer and adjacent to the third region, and a fifth region in contact with the source electrode or the drain electrode, a thickness of the oxide semiconductor layer in the third region is greater than a thickness of the oxide semiconductor layer in the fourth region; in a cross-sectional view parallel to a channel width direction of the transistor, the gate electrode has a region facing a top surface of the oxide semiconductor layer with the gate insulating layer interposed therebetween and a region facing a side surface of the oxide semiconductor layer with the gate insulating layer interposed therebetween; the oxide semiconductor layer has a region overlapping with the conductive layer.

5. In any one of claims 1 to 4, A semiconductor device, wherein the gate electrode has a laminated structure with a material selected from Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, W, and alloys of these metal materials.

6. In any one of claims 1 to 5, A semiconductor device, wherein each of the source electrode and the drain electrode has a laminated structure with a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of these metal materials.

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