Low Dropout Regulator

Abstract

To provide a low dropout regulator.SOLUTION: The low dropout regulator includes a first gain stage, a second gain stage, an output setting stage, and a Miller circuit. The first gain stage is used to generate a signal at a first gain stage terminal on the basis of a signal at a second gain stage terminal. The second gain stage receives the signal generated at the first gain stage terminal and generates a signal at a detection terminal. The output setting stage is used to output a load current to an output terminal. The signal at the detection terminal is changed with the load current. The Miller circuit is electrically connected to the first gain stage, the second gain stage, and the output setting stage. The Miller circuit is used to provide a capacitance related to the main pole of the low dropout regulator. The capacitance is changed with the signal at the detection terminal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a low dropout regulator, and more particularly to a capacitorless low dropout regulator having a better power supply voltage rejection ratio.

Background Art

[0002] In an electronic device, a linear regulator is used to stabilize the power supply voltage Vdd and convert it into a stable output voltage Vout. A low dropout (hereinafter abbreviated as LDO) regulator is a linear regulator having advantages such as low cost, low noise, and high-speed voltage conversion. A large output capacitor is required for a conventional off-chip LDO regulator, but since the occupied area is large, a capacitorless LDO regulator has been developed.

Summary of the Invention

Problems to be Solved by the Invention

[0003] In products / applications powered by a battery, since a switching DC / DC regulator has high power efficiency, it is usually directly connected to the battery for voltage conversion. However, when using a switching DC / DC regulator, the switch is frequently switched, and a ripple occurs in the output voltage. For this reason, an LDO for suppressing the ripple is required at the output terminal of the switching DC / DC regulator.

[0004] The power supply voltage ripple rejection ratio (hereinafter abbreviated as PSRR) is a performance index of the LDO that is the key to measuring the amount of ripple suppression. Therefore, a high PSRR is required to effectively reduce the power supply ripple. Since the capacitorless LDO regulator faces various load conditions that affect the PSRR, it has been necessary to develop a capacitorless LDO regulator having a better PSRR.

[0005] Therefore, the inventor of the present invention considered that the above-mentioned drawbacks could be improved, and as a result of intensive studies, the inventor arrived at the proposal of the present invention that effectively improves the above-mentioned problems through a reasonable design.

[0006] As a result of intensive research, the inventor of the present invention has found that an LDO regulator having a load-dependent mirror circuit can achieve the above object. The load-dependent mirror circuit modifies its capacitance value based on the load condition. The dynamic adjustment of the capacitor means that the dominant pole of the LDO regulator can move even under different load conditions and increases the PSRR of the LDO regulator.

Means for Solving the Problems

[0007] According to an embodiment of the present invention, a low dropout regulator is provided. The low dropout regulator according to the present invention includes a first gain stage, a second gain stage, an output setting, and a mirror circuit. Based on the signal of the second gain stage terminal, the first gain stage generates a signal at the first gain stage terminal. The second gain stage is electrically connected to the first gain stage terminal. The second gain stage receives a signal at the first gain stage terminal and generates a signal at the detection terminal. The output setting stage is electrically connected to the first gain stage terminal and the detection terminal. The output setting stage outputs a load current toward the output terminal. The signal of the detection terminal changes according to the load current. The mirror circuit is electrically connected to the first gain stage, the second gain stage, and the output setting stage. The mirror circuit provides a capacitance value related to the dominant pole of the low dropout regulator. The capacitance value changes according to the signal of the detection terminal.

[0008] In this specification, for ease of understanding, many specific details are provided to promote a thorough understanding of the disclosed embodiments. However, it is clear that one or more embodiments can be implemented even without these specific details. In other embodiments, well-known to the public by schematically showing simplified diagrams of structures and devices.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Modes for Carrying Out the Invention

[0010] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0011] FIG. 1 is a block diagram showing a capacitorless LDO regulator according to an embodiment of the present invention. The LDO regulator 20 includes a first gain-stage 23, a second gain-stage 25, a Miller circuit 27, an output setting stage 28, a reference generator 29, a bias stage 21, and a load capacitor Cld. The load capacitor Cld may be electrically connected to the output terminal Nout and the ground terminal Gnd.

[0012] The functions of the elements of the LDO regulator 20 will be described below. The output setting stage 28 has a method based on a flipped voltage follower (hereinafter abbreviated as FVF). The second gain stage 25 belongs to the total loop gain when the LDO regulator 20 operates under heavy load conditions. The first gain stage 23 is electrically connected to the gain stage terminals Ng1 and Ng2, and the second gain stage 25 is electrically connected to the gain stage terminal Ng1 and the detection terminal Nsen.

[0013] The mirror circuit 27 is electrically connected to the output terminal Nout, the gain stage terminal Ng1, and the detection terminal Nsen. The mirror circuit 27 is used for frequency compensation, and the capacitance value of the mirror circuit 27 can be freely adjusted in response to the signal of the detection terminal Nsen.

[0014] The output setting stage 28 is electrically connected to the output terminal Nout, the gain stage terminals Ng1 and Ng2, and the detection terminal Nsen. The output setting stage 28 continuously outputs a stable output voltage Vout toward the output terminal Nout. The reference generator 29 supplies a control voltage Vctl to the output setting stage 28 and supplies a reference voltage Vref to the first gain stage 23.

[0015] The connection relationship between the bias stage 21 and the reference generator 29 will be described below. The bias stage 21 is electrically connected to the first gain stage 23 and the second gain stage 25 via the bias terminal Nb1, and is also electrically connected to the output setting stage 28 via the output terminal Nout and the bias terminal Nb2. The reference generator 29 is electrically connected to the bias stage 21, the first gain stage 23, and the output setting stage 28. An exemplary internal design of the bias stage 21, the first gain stage 23, the second gain stage 25, the mirror circuit 27, and the reference generator 29 is shown (see FIG. 2).

[0016] The output setting stage 28 includes power transistors Qp1, Qp2, an output setting transistor Qos, and output bias transistors Qob1, Qob2. The power transistors Qp1, Qp2 and the output setting transistor Qos are PMOS transistors, and the output bias transistors Qob1, Qob2 are NMOS transistors.

[0017] The source terminals of the power transistors Qp1, Qp2 are electrically connected to the power supply voltage terminal Vdd, and the source terminals of the output bias transistors Qob1, Qob2 are electrically connected to the ground terminal Gnd. The gate terminal of the power transistor Qp1 is electrically connected to the output terminal of the first gain stage 23 (i.e., the gain stage terminal Ng1), and the gate terminal of the power transistor Qp2 is electrically connected to the output of the second gain stage 25 (i.e., the detection terminal Nsen). By doing so, the power transistor Qp1 is selectively turned on in response to the signal at the gain stage terminal Ng1, and the power transistor Qp2 is selectively turned on in response to the signal at the detection terminal Nsen. The aspect ratio of the power transistor Qp2 is much larger than that of the power transistor Qp1. For example, the aspect ratio of the power transistor Qp2 corresponds to 50 times or 100 times that of the power transistor Qp1.

[0018] The drain terminals of the power transistors Qp1, Qp2 and the source terminal of the output setting transistor Qos are electrically connected to the output terminal Nout. The drain terminal of the output setting transistor Qos and the drain terminal of the output bias transistor Qob1 are electrically connected to the gain stage terminal Ng2. The drain terminal of the output bias transistor Qob2 is electrically connected to the output terminal Nout. The gate terminals of the output bias transistors Qob1, Qob2 are electrically connected to the bias terminal Nb2.

[0019] The aspect ratio of the output bias transistor Qob1 is larger than that of the output bias transistor Qob2. For example, the aspect ratio of the output bias transistor Qob1 corresponds to twice the aspect ratio of the power transistor Qob2. By doing so, the output bias current Iob flowing through the output bias transistor Qob1 corresponds to a multiple of the output setting current Ios2 flowing through the output bias transistor Qob2, which is determined by the aspect ratios of the output bias transistors Qob1 and Qob2.

[0020] FIG. 2 is a schematic diagram showing an exemplary capacitorless LDO regulator according to an embodiment of the present invention. Refer to FIGS. 1 and 2 together. The internal elements of the bias stage 21, the first gain stage 23, the second gain stage 25, the mirror circuit 27, and the reference generator 29 and their interconnections will be described below.

[0021] The bias stage 21 includes bias transistors Qb1, Qb2, Qb3, a current source 211, a resistor R, and a high-pass capacitor Ch. The bias transistor Qb3 is a PMOS transistor, and the bias transistors Qb1 and Qb2 are NMOS transistors.

[0022] Bias transistors Qb1 and Qb2 jointly form a current mirror. Assume that the aspect ratios of bias transistors Qb1 and Qb2 are the same. Current source 211 is electrically connected to power supply voltage terminal Vdd and bias terminal Nb2. The drain terminal and gate terminal of bias transistor Qb1 are electrically connected to bias terminal Nb2. Resistor R is electrically connected to bias terminals Nb2 and Nb3. The drain terminal and gate terminal of bias transistor Qb2 are electrically connected to bias terminal Nb1 and bias terminal Nb3, respectively. High-pass capacitor Ch is electrically connected to output terminal Nout and bias terminal Nb3. The source terminals of bias transistors Qb1 and Qb2 are electrically connected to ground terminal Gnd. The gate terminal and drain terminal of bias transistor Qb3 are electrically connected to bias terminal Nb1, and the source terminal of bias transistor Qb3 is electrically connected to power supply voltage terminal Vdd.

[0023] In bias stage 21, current source 211 continuously supplies sink bias current Ibias. Sink bias current Ibias has a constant voltage current value, and sink bias current Ibias flows through bias transistor Qb1. Based on the current mirror structure, mirror bias current Imb flowing through bias transistors Qb3 and Qb2 is related to sink bias current Ibias.

[0024] High-pass capacitor Ch and resistor R jointly provide a high-pass function. When there is an overshoot in output voltage Vout, the changed high-frequency component of output voltage Vout passes through high-pass capacitor Ch. High-pass capacitor Ch instantaneously injects a high current, and bias terminal Nb3 instantaneously rises. Then, the signal of bias terminal Nb3 gradually recovers to its initial value. Resistor R prevents direct conduction to bias terminal Nb2 even when output voltage Vout suddenly changes, and sink bias current Ibias maintains a constant voltage.

[0025] The first gain stage 23 includes first stage transistors Q1a and Q1b. The first stage transistor Q1a is a PMOS transistor, and the first stage transistor Q1b is an NMOS transistor. The source terminal, gate terminal, and drain terminal of the first stage transistor Q1a are electrically connected to the power supply voltage terminal Vdd, the bias terminal Nb1, and the gain stage terminal Ng1, respectively. Since the bias transistor Qb3 and the first stage transistor Q1a form a current mirror, the first stage current I1 is generated by replicating the mirror bias current Imb. The drain terminal, gate terminal, and source terminal of the first stage transistor Q1b are electrically connected to the gain stage terminal Ng1, the inverting input terminal Nin1, and the gain stage terminal Ng2, respectively.

[0026] In the first gain stage 23, the first stage transistor Q1b is regarded as a common - gate stage that provides the first gain value G1, and the first stage transistor Q1a supplies a bias current to the common - gate stage. When the output voltage Vout changes suddenly, the signal of the gain stage terminal Ng1 is temporarily affected, and the first stage current I1 is temporarily affected.

[0027] The second gain stage 25 includes second stage transistors Q2a, Q2b, Q2c, and Q2d. The second stage transistors Q2a and Q2b are PMOS transistors, and the second stage transistors Q2c and Q2d are NMOS transistors. The source terminal and gate terminal of the second stage transistor Q2a are electrically connected to the power supply voltage terminal Vdd and the gain stage terminal Ng1, respectively. The source terminal and gate terminal of the second stage transistor Q2b are electrically connected to the power supply voltage terminal Vdd and the bias terminal Nb1, respectively.

[0028] Therefore, the second-stage transistor Q2a is controlled by the voltage difference between the power supply voltage Vdd (its source terminal) and the signal at the gain-stage terminal Ng1 (its gate terminal), and the second-stage transistor Q2a is regarded as a voltage-current converter. When the signal at the gain-stage terminal Ng1 increases, the voltage difference between the source terminal and the gate terminal of the second-stage transistor Q2a decreases, and the second-stage current I2a decreases. When the signal at the gain-stage terminal Ng1 decreases, the voltage difference between the source terminal and the gate terminal of the second-stage transistor Q2a increases, and the second-stage current I2a increases.

[0029] The drain terminals of the second-stage transistors Q2a and Q2c and the gate terminal of the second-stage transistor Q2c are electrically connected. The drain terminals of the second-stage transistors Q2b and Q2d are electrically connected. The source terminals of the second-stage transistors Q2c and Q2d are electrically connected to the ground terminal Gnd.

[0030] In the second gain stage 25, the second-stage transistors Q2a and Q2c are regarded as a first second-stage branch, and the second-stage transistors Q2b and Q2d are regarded as a second second-stage branch. For the first second-stage branch, when the second-stage transistor Q2a is turned on, the second-stage current I2a flows through the second-stage transistors Q2a and Q2c. For the second second-stage branch, the second-stage current I2b flows through the second-stage transistors Q2b and Q2d. The combination of the second-stage transistors Q2b and Q2d can be regarded as a common-source amplifier. The second-stage transistor Q2d is an input transistor, and the second-stage transistor Q2b is an active load.

[0031] The second-stage transistors Q2c and Q2d jointly form another current mirror. The bias transistor Q2d replicates the second-stage current I2a from the bias transistor Q2c and generates the second-stage current I2b.

[0032] The signal of the detection terminal Nsen is related to the second-stage current I2b, and the operation of the mirror circuit 27 is related to the signal of the detection terminal Nsen. The mirror circuit 27 includes a mirror capacitor Cm1, Cm2, a comparator CMP, and a switch SW. The capacitance value of the mirror capacitor Cm2 is much larger than that of the mirror capacitor Cm1 (Cm2 > Cm1).

[0033] The capacitor Cm1 is electrically connected to the gain stage terminal Ng1 and the output terminal Nout. The capacitor Cm2 and the switch sw are connected in series. One end of the capacitor Cm2 is electrically connected to one of the gain stage terminal Ng1 and the output terminal Nout, and the other end of the capacitor Cm2 is electrically connected to the switch sw. The switch sw is electrically connected to the output end of the comparator CMP and one of the gain stage terminal Ng1 or the output terminal Nout. The comparator CMP is electrically connected to the detection terminal Nsen and an internal / external voltage source.

[0034] The comparator CMP receives a signal at the detection terminal Nsen and receives a comparison voltage Vcmp. The value of the comparison voltage Vcmp can be freely set based on the conversion point (expressed by the load current Ild) required by the designer. The source of the comparison voltage Vcmp is not restricted. For example, the comparison voltage Vcmp may be from an internal voltage source or an external voltage source.

[0035] The comparator CMP generates an output to the switch SW based on a situation that satisfies a predetermined condition. The predetermined condition is to compare the comparison voltage Vcmp with the signal of the detection terminal Nsen. When the signal of the detection terminal Nsen is equal to or higher than the comparison voltage Vcmp (the predetermined condition is not satisfied), the output of the comparator CMP is set to the logical high level (H). When the signal of the detection terminal Nsen is lower than the comparison voltage Vcmp (the predetermined condition is satisfied), the output of the comparator CMP is set to the logical low level (L).

[0036] Based on the output of the comparator CMP, the switch sw is selectively turned on or off, and the capacitance value of the mirror circuit 27 is dynamically modified. Table 1 summarizes the operation of the mirror circuit 27.

[0037]

Table 1

[0038] The reference generator 29 includes a bandgap circuit 291, reference transistors Qr1, Qr2, Qr3, and an operational amplifier 293. The bandgap circuit 291 outputs a stable reference voltage Vref to the inverting input terminal Nin1 of the operational amplifier 293 and the gate terminal of the first-stage transistor Q1b. By doing so, the first-stage transistor Q1b waits for conduction.

[0039] The source terminal, gate terminal, and drain terminal of the reference transistor Qr1 are electrically connected to the power supply voltage terminal Vdd of the operational amplifier 293, the output terminal of the operational amplifier 293, and the non-inverting input terminal Nin2, respectively. The source terminal of the reference transistor Qr2 is electrically connected to the non-inverting input terminal Nin2 of the operational amplifier 293, and the gate terminal and drain terminal of the reference transistor Q2 are electrically connected to the control terminal Nctl. The drain terminal, gate terminal, and source terminal of the reference transistor Qr3 are electrically connected to the control terminal Nctl, the bias terminal Nb2, and the ground terminal Gnd, respectively.

[0040] It should be noted here that the reference transistor Qr2 and the output setting transistor Qos form a current mirror. By doing so, the output setting current Ios1 flowing through the output setting transistor Qos replicates the reference current Iref flowing through the reference transistor Qr2.

[0041] Also, based on the current mirror structure, the signal at the output terminal Nout is equivalent to the non-inverting input terminal Nin2 of the operational amplifier 293. Combining with the virtual short-circuit characteristic (Nin1 = Nin2) of the operational amplifier 293, it can be seen that the output voltage Vout is equivalent to the reference voltage Vref (Nout = Nin2 = Nin1 = Vref).

[0042] At the gain stage terminal Ng2, the output set current Ios1 and the first stage current I1 are merged to generate the output bias current Iob. Since the output bias transistor Qob1 and the bias transistor Qb1 form a current mirror, and the output bias transistor Qob1 has a large aspect ratio, the output bias current Iob is a constant voltage and is directly proportional to the sink bias current Ibias. By doing so, the changes in the output set current Ios1 and the first stage current I1 have a negative correlation.

[0043] Figure 3 is a state diagram showing the operation of the capacitorless LDO regulator of Figure 2. According to an embodiment of the present invention, the LDO regulator 20 operates in three types of operating states. The details of the internal signals in these operating states of the LDO are shown in Figures 4A, 4B, and 4C respectively.

[0044] Figure 4A is a schematic diagram showing the operation of the capacitorless LDO regulator of Figure 2 in a light load state (ST1). Figure 4B is a schematic diagram showing the operation of the capacitorless LDO regulator of Figure 2 in a transition state (ST2). Figure 4C is a schematic diagram showing the operation of the capacitorless LDO regulator of Figure 2 in a heavy load state (ST3). Also refer to Figures 3, 4A, 4B, and 4C together.

[0045] When the LDO regulator 20 faces light load conditions, the load current Ild suddenly decreases, and the signal at the output terminal Nout suddenly increases (overshoot occurs). At the output terminal Nout, the current flowing through the power transistor Qp1 is divided into two branches, the load current Ild and the output setting current Ios1. By doing so, when the load current Ild decreases, the output setting current Ios1 increases. Also, based on the negative correlation between the output setting current Ios1 and the first-stage current I1, the first-stage current I1 decreases. After some time has passed since the occurrence of the overshoot, it is necessary to decrease / recover the signal at the output terminal Nout. By doing so, the conduction path between the power supply voltage Vdd and the output terminal Nout can suppress the overshoot with a small current.

[0046] When the decreased first-stage current I1 flows through the first-stage transistor Q1a, there is a very small voltage difference between the power supply voltage Vdd and the gain stage terminal Ng1. Therefore, the small voltage difference between the power supply voltage Vdd and the gain stage terminal Ng1 is sufficient to turn on the power transistor Qp1 but insufficient to turn on the second-stage transistor Q2a. When the power transistor Qp1 is turned on, a small current starts to flow from the power supply voltage Vdd toward the output terminal Nout. Also, the cutoff of the second-stage transistor Q2a means that no second-stage currents I2a, I2b are generated and the second-stage transistors Q2c, Q2d are turned off.

[0047] The bias transistor Qb3 and the second-stage transistor Q2b form a current mirror, so that the signals at the drain terminals of the bias transistor Qb3 and the second-stage transistor Q2b are equivalent. Therefore, when the second-stage transistor Q2b is turned on, the bias transistor Qb3 is also turned on. Since there is no second-stage current I2b, the signal at the detection terminal Nsen is not dragged. Thus, since the second-stage transistor Q2b is turned on, the detection terminal Nsen is set to the power supply voltage Vdd (Nsen = Vdd). Once the detection terminal Nsen is set to the power supply voltage Vdd (Nsen = Vdd), the power transistor Qp2 is turned off, and the comparator CMP outputs a logic high level to turn on the switch SW. Briefly speaking, the mirror circuit 27 provides a larger capacitance value in the light load state ST1 (Cm = Cm1 + Cm2) (see Fig. 4A).

[0048] When the LDO regulator 20 faces a heavy load condition, the load current Ild suddenly increases, and the signal at the output terminal Nout suddenly decreases (undershoot occurs). At the same time, the output set current Ios1 decreases, and the first-stage current I1 increases. After a short time after the undershoot occurs, it is necessary to increase / recover the signal at the output terminal Nout. This means that in the conduction path between the power supply voltage Vdd and the output terminal Nout, it is necessary to pull up the output terminal Nout with a large current to eliminate the undershoot.

[0049] When the increased first-stage current I1 flows through the first-stage transistor Q1b, the signal at the gain stage terminal Ng1 is dragged by the first-stage current I1. As a result, there is a larger voltage difference between the power supply voltage Vdd and the gain stage terminal Ng1. Therefore, the voltage difference between the power supply voltage Vdd and the gain stage terminal Ng1 increases, and the gain stage terminal Ng1 becomes high enough to turn on the second-stage transistor Q2a.

[0050] After the second-stage transistor Q2a is turned on, a second-stage current I2a is generated and increases. Since the mirror current of the second-stage current I2a is the second-stage current I2b, as the second-stage current I2b increases, the signal at the detection terminal Nsen gradually decreases from the power supply voltage Vdd, and the power transistor Qp2 is turned on.

[0051] As described above, the aspect ratio of the power transistor Qp2 is much larger than that of the power transistor Qp1. Therefore, when the load current Ild becomes high under heavy load conditions, the power transistor Qp1 cannot support a high current, and the current stops flowing through the power transistor Qp1. Since the current does not flow through the power transistor Qp1, the voltage difference between the gate terminal and the source terminal Vgs of the power transistor Qp1 becomes small. By doing so, the gain stage terminal Ng1 becomes high potential and turns off the power transistor Qp1. Thus, the power transistor Qp1 is turned off, the second-stage transistor Q2a is turned on, and the gain stage terminal Ng1 becomes high potential.

[0052] Based on the output of the comparator CMP, the process of the signal decrease at the detection terminal Nsen can be divided into two parts. In the first part, the signal at the detection terminal Nsen is greater than or equal to the comparison voltage Vcmp (i.e., Vcmp ≦ Nsen < Vdd). In the second part, the signal at the detection terminal Nsen becomes lower than the comparison voltage Vcmp (i.e., Nsen < Vcmp).

[0053] In the process where the comparator CMP outputs a logic high level and the signal at the detection terminal Nsen decreases, when the switch sw is turned on in the first part, the mirror circuit 27 provides a larger capacitance value (Cm = Cm1 + Cm2). Then, the second gain stage 2 5 becomes active, and the mirror circuit 27 provides a larger capacitance value (Cm = Cm1 + Cm2) in the transition state ST2 (see FIG. 4B).

[0054] In the process where the comparator CMP outputs a logic low potential and the signal at the detection terminal Nsen decreases, when the switch sw is turned off in the second part, the mirror circuit 27 provides a small capacitance value (Cm = Cm1). By doing so, the second gain stage 2 5 becomes active, and the mirror circuit 27 provides a small capacitance value in the heavy load state ST3 (Cm = Cm1) (see FIG. 4C).

[0055] The direction of state conversion is related to the change in the signal at the detection terminal Nsen. The dashed arrow indicates how the LDO regulator 20 reflects the change in the detection terminal Nsen in the operating state. For comparison, detailed descriptions regarding state conversion are omitted but summarized in Table 2.

[0056]

Table 2

[0057] For a capacitorless LDO regulator without the mirror circuit 27, if it operates under light load conditions, the load pole at the output terminal Nout is located at a low frequency, and the phase margin is limited. Therefore, a capacitorless LDO regulator without the mirror circuit 27 becomes extremely unstable under light load conditions.

[0058] According to the embodiment of the present invention, when the LDO regulator 20 operates under light load conditions, the mirror circuit 27 provides an even larger capacitance value (Cm = Cm1 + Cm2). By doing so, the load pole moves to an even higher frequency, and the pole at the gain stage terminal Ng1 becomes the main pole of the LDO regulator 20.

[0059] When the LDO regulator 20 operates under heavy load conditions, the load pole at the output terminal Nout is located at a high frequency, and the LDO regulator 20 does not need to have a large capacitance value in the mirror circuit 27. Therefore, the mirror circuit 27 provides a very small capacitance value (Cm = Cm1) to improve the PSRR of the LDO regulator 20.

[0060] According to the embodiments of the present invention, the LDO regulator 20 employs a load-related mirror circuit 27 to adjust the position of the main pole of the LDO regulator 20. By doing so, the stability of the LDO regulator 20 is enhanced, and the LDO regulator 20 has a more favorable PSRR.

[0061] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

Explanation of Reference Numerals

[0062] 20 Low-dropout regulator, 21 Bias stage, 211 Current source, 23 First gain stage, 25 Second gain stage, 27 Mirror circuit, 28 Output setting stage, 29 Reference generator, 291 Bandgap circuit, 293 Operational amplifier, Cld Load capacitor, Cm1 Mirror capacitor, Cm2 Mirror capacitor, CMP Comparator, Ch High-pass capacitor, Gnd Ground terminal, I1 First stage current, I2a Second stage current, I2b Second stage current, Ibias Sink bias current, Ild Load current, Imb Mirror bias current, Iob Output bias current, Ios1 Output setting current, Ios2 Output setting current, Iref Reference current, Nb1 bias terminal, Nb2 bias terminal, Nb3 bias terminal, Nctl control terminal, Ng1 gain stage terminal, Ng2 gain stage terminal, Nin1 inverting input terminal, Nin2 non-inverting input terminal, Nout output terminal, Nsen detection terminal, Q1a first stage transistor, Q1b first stage transistor, Q2a second stage transistor, Q2b second stage transistor, Q2c second stage transistor, Q2d second stage transistor, Qb1 bias transistor, Qb2 bias transistor, Qb3 bias transistor, Qp1 power transistor, Qp2 power transistor, Qob1 output bias transistor, Qob2 output bias transistor, Qos output setting transistor, Qr1 reference transistor, Qr2 reference transistor, Qr3 reference transistor, R resistor, sw switch, ST1 light load state, ST2 transition state, ST3 heavy load state, Vcmp comparison voltage, Vctl control voltage, Vdd power supply voltage terminal (power supply voltage), Vref reference voltage.

Claims

1. A first gain stage for generating a first signal at a first gain stage terminal based on a second signal of a signal terminal of a second gain stage; A second gain stage that is electrically connected to the first gain stage terminal, receives the first signal generated at the first gain stage terminal, and generates a third signal at a detection terminal; An output setting stage that is electrically connected to the first gain stage terminal and the detection terminal and is used to output a load current toward an output terminal, and the third signal of the detection terminal changes according to the load current; A mirror circuit that is electrically connected to the first gain stage, the second gain stage, and the output setting stage, provides a capacitance value related to a main pole of a low dropout regulator, and the capacitance value changes according to the third signal of the detection terminal, comprising: The first gain stage is A first first-stage transistor electrically connected to the first gain stage terminal; A second first-stage transistor electrically connected to the first gain stage terminal and the second gain stage terminal, wherein the first signal of the first gain stage terminal flows through the first first-stage transistor and the second first-stage transistor according to a first gain stage current and is modified, or at least comprising the second first-stage transistor; The output setting stage is A first power transistor electrically connected to the first gain stage terminal and the output terminal and selectively turned on in response to the first signal of the first gain stage terminal; A second power transistor electrically connected to the detection terminal and the output terminal and selectively turned on in response to the third signal of the detection terminal, at least comprising: A fourth signal of the output terminal is modified according to a switching state of the first power transistor and the second power transistor; A low dropout regulator characterized by the above.

2. When the third signal of the detection terminal satisfies a predetermined condition, the capacitance value corresponds to a first capacitance value, and when the third signal of the detection terminal does not satisfy the predetermined condition, the capacitance value corresponds to a second capacitance value. The low dropout regulator according to claim 1, characterized in that.

3. The low dropout regulator according to claim 2, characterized in that the first capacitance value is larger than the second capacitance value.

4. The low dropout regulator according to claim 2, characterized in that when the third signal of the detection terminal is lower than a comparison voltage, the predetermined condition is satisfied.

5. The mirror circuit is A first mirror capacitor electrically connected to the first gain stage terminal and the output terminal; A second mirror capacitor electrically connected to one of the first gain stage terminal and the output terminal, and the capacitance value of the second mirror capacitor is larger than the capacitance value of the first mirror capacitor. The second mirror capacitor; The low dropout regulator according to claim 1, further comprising: a switch that is electrically connected to the second mirror capacitor and the other one of the first gain stage terminal or the output terminal, and is selectively turned on based on the third signal of the detection terminal.

6. The mirror circuit is The low dropout regulator according to claim 5, further comprising: a comparator that is electrically connected to the detection terminal and the switch, receives a comparison voltage, and generates an output based on the comparison voltage and the third signal of the detection terminal.

7. When the third signal of the detection terminal is equal to or higher than the comparison voltage, the output of the comparator is set to a logic high level. When the third signal of the detection terminal is lower than the comparison voltage, the output of the comparator is set to a logic low level. The low dropout regulator according to claim 6, characterized in that.

8. The second gain stage includes A first second-stage transistor electrically connected to the first gain stage terminal and selectively turned on in response to the first signal of the first gain stage terminal; A second second-stage transistor electrically connected to the detection terminal; A third second-stage transistor electrically connected to the first second-stage transistor; At least including a fourth second-stage transistor electrically connected to the second second-stage transistor and the third second-stage transistor; The first second-stage current flowing through the first second-stage transistor and the third second-stage transistor corresponds to the second second-stage current flowing through the second second-stage transistor and the fourth second-stage transistor. The low dropout regulator according to claim 1, characterized in that.

9. The third signal of the detection terminal changes according to the second second-stage current. The low dropout regulator according to claim 8, characterized in that.

10. When the load current suddenly increases, an undershoot occurs at the output terminal. When the load current suddenly decreases, an overshoot occurs at the output terminal. The low dropout regulator according to claim 1, characterized in that.

11. The aspect ratio of the first power transistor is smaller than the aspect ratio of the second power transistor. The low dropout regulator according to claim 1, characterized in that.

12. When the load current is low, the first power transistor is turned on and the second power transistor is turned off. When the load current is high, the low dropout regulator according to claim 1, wherein the first power transistor is turned on.

13. The output setting stage is electrically connected to the output terminal and the second gain stage terminal, and further includes an output setting transistor that sets the fourth signal of the output terminal to be equivalent to a reference voltage based on a control voltage. The low dropout regulator according to claim 1.

14. is electrically connected to the first gain stage and the output setting stage, receives the reference voltage, and is used to supply the control voltage based on the reference voltage. The reference voltage and the control voltage are a reference generator having a constant voltage. The low dropout regulator according to claim 13.

15. The reference generator includes a first input terminal, a second input terminal, and an amplifier output terminal, and an operational amplifier for receiving the reference voltage at the first input terminal, a first reference transistor that is electrically connected to the second input terminal and the amplifier output terminal and is selectively turned on in response to a fifth signal at the amplifier output terminal, a second reference transistor that is electrically connected to the output setting transistor and the second input terminal, and a third reference transistor that is electrically connected to the second reference transistor, wherein the reference current sequentially flows through the first reference transistor, the second reference transistor, and the third reference transistor. The low dropout regulator according to claim 14.

16. The second reference transistor and the output setting transistor form a current mirror and generate an output setting current flowing through the output setting transistor by replicating the reference current, the low dropout regulator according to claim 15, characterized in that.

17. The output setting current varies according to the fourth signal of the output terminal, the low dropout regulator according to claim 16, characterized in that.

18. The first gain stage, the second gain stage, the mirror circuit, the output setting stage, and the reference generator are electrically connected and used to supply a sink bias current, and the reference current is generated based on the sink bias current. The low dropout regulator according to claim 15, further comprising a bias stage.

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