Semiconductor device and memory cell circuit

Abstract

To suppress power consumption in a semiconductor device including a memory cell and a non-volatile storage part.SOLUTION: A semiconductor device includes: a memory cell which holds 1-bit data; a pair of bit lines for writing or reading data into or from the memory cell; a non-volatile storage part which stores the data held by the memory cell; and a writing control part which causes the data currently held by the memory cell to be stored in a first storage part, causes the data currently stored in the non-volatile storage part to be stored in a second storage part, and when the data stored in the first storage part and the data stored in the second storage part differ from each other, causes the data stored in the first storage part to be written into the non-volatile storage part via the pair of bit lines and, when the data stored in the first storage part and the data stored in the second storage part are identical to each other, causes the data stored in the first storage part not to be written into the non-volatile storage part.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a memory cell circuit.

Background Art

[0002] There is known a semiconductor device that becomes a non-volatile memory circuit having high speed and non-volatility by using a non-volatile storage unit in a volatile memory. For example, Non-Patent Documents 1 and 2 describe technologies related to a memory cell circuit of NV-SRAM (Non-Volatile Static Random Access Memory) using an MTJ (Magnetic Tunnel Junction) element which is a magnetoresistive element.

[0003] In the technologies described in Non-Patent Documents 1 and 2, when the semiconductor device is in the sleep state, before power-off is performed by power gating, the data held in the memory cell of the SRAM is stored in the MTJ element, and the data held in the memory cell is memorized. Further, when the supply of power is started after returning from sleep, the data stored in the MTJ element is restored and written to the memory cell. Thereby, in the technologies described in Non-Patent Documents 1 and 2, power consumption can be reduced.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

[0005] However, in the technologies described in Non-Patent Documents 1 and 2 above, when writing the data stored in the memory cell of the SRAM to the MTJ element, unnecessary power may be consumed, and the power consumption may not be sufficiently suppressed.

[0006] The present disclosure has been made to solve the above problems, and an object thereof is to be able to suppress power consumption in a semiconductor device including a memory cell and a non-volatile storage unit. MEANS FOR SOLVING THE PROBLEMS

[0007] A first aspect of the technology of the present disclosure is a semiconductor device, including a memory cell that holds 1-bit data, a pair of bit lines for writing data to or reading data from the memory cell, a non-volatile storage unit that stores the data held by the memory cell, a first storage unit that stores the data currently held by the memory cell, a second storage unit that stores the data currently stored in the non-volatile storage unit, and a writing control unit that, when the data stored in the first storage unit is different from the data stored in the second storage unit, causes the data stored in the first storage unit to be written to the non-volatile storage unit via the pair of bit lines, and when the data stored in the first storage unit is the same as the data stored in the second storage unit, does not cause the data stored in the first storage unit to be written to the non-volatile storage unit.

[0008] Further, in a second aspect of the technology of the present disclosure, in the semiconductor device of the first aspect, the second storage unit detects a potential difference between the pair of bit lines, and based on the potential difference, outputs a determination result of determining a logical value of data read from the memory cell to the first storage unit.

[0009] Further, in a third aspect of the technology of the present disclosure, in the semiconductor device of the first aspect or the second aspect, when the write control unit stores the data held in the memory cell in the nonvolatile storage unit, it is turned on, and when writing the data stored in the nonvolatile storage unit to the memory cell, it is turned off. The nonvolatile storage unit is connected to the second storage unit by a first switch, and when storing the data held in the memory cell in the nonvolatile storage unit, it is turned off, and when writing the data stored in the nonvolatile storage unit to the memory cell, it is turned on. The nonvolatile storage unit is connected to the memory cell by a second switch.

[0010] Further, in a fourth aspect of the technology of the present disclosure, in the semiconductor device of any one of the first to third aspects, the data read from the memory cell is stored in the first storage unit via the second storage unit.

[0011] Further, in a fifth aspect of the technology of the present disclosure, in the semiconductor device of any one of the first to fourth aspects, a store time control unit is further provided that performs control to set either a first time for storing the data held in the memory cell in the nonvolatile storage unit or a second time shorter than the first time.

[0012] Further, in a sixth aspect of the technology of the present disclosure, in the semiconductor device of the fifth aspect, the store time control unit includes a setting unit in which different logical values are set for the first time and the second time, and according to the logical value provided in the setting unit and the logical value of a store time control signal for controlling the first time and the second time, the data held in the memory cell is stored in the nonvolatile storage unit.

[0013] Further, in a seventh aspect of the technology of the present disclosure, in the semiconductor device according to the fifth or sixth aspect, when the data held by the memory cell is a predetermined upper bit among a plurality of bits of data, the store time control unit performs control to set the first time, and when the data is a predetermined lower bit among the plurality of bits of data, the store time control unit performs control to set the second time.

[0014] Further, in an eighth aspect of the technology of the present disclosure, in the semiconductor device according to any one of the first to seventh aspects, the nonvolatile storage unit is a magnetic tunnel junction element.

[0015] Further, a ninth aspect of the technology of the present disclosure is a memory cell circuit, including: a memory cell that holds 1-bit data; a pair of bit lines for writing data to or reading data from the memory cell; a nonvolatile storage unit that stores the data held by the memory cell; a first switch that is turned on when storing the data held by the memory cell in the nonvolatile storage unit and is turned off when writing the data stored in the nonvolatile storage unit to the memory cell, and connects the nonvolatile storage unit and the bit line; and a second switch that is turned off when storing the data held by the memory cell in the nonvolatile storage unit and is turned on when writing the data stored in the nonvolatile storage unit to the memory cell, and connects the nonvolatile storage unit and the memory cell.

Advantages of the Invention

[0016] According to the present disclosure, it is possible to suppress power consumption in a semiconductor device including a memory cell and a nonvolatile storage unit.

Brief Description of the Drawings

[0017]

Figure 1A

Figure 1B

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0018] Hereinafter, examples of embodiments according to the present invention will be described with reference to the drawings. In each drawing, parts having the same function are denoted by the same reference numerals, and overlapping descriptions will be omitted as appropriate.

[0019] [First Embodiment] First, the configuration of the semiconductor integrated circuit of this embodiment will be described. FIG. 1A is a block diagram showing an example of the semiconductor integrated circuit 10 of this embodiment.

[0020] The semiconductor integrated circuit 10 of this embodiment includes a control circuit 12, a power switch 14, a non-volatile memory circuit group 15, and an internal circuit 18.

[0021] As shown in FIG. 1B, as an example, the non-volatile memory circuit group 15 of this embodiment includes m×n memory cell circuits 22 (22 11 ~22 mn ), n peripheral circuits 24 (241~24 n ), and n pairs of bit lines bit, bit_b. For each pair of bit lines bit, bit_b, a non-volatile memory circuit 16 (161~16 n ) is provided. That is, as shown in FIG. 1B, each non-volatile memory circuit 16 includes m memory cell circuits 22 and one peripheral circuit 24. In this embodiment, when collectively referring to the m×n memory cell circuits 22, the symbols “m” and “n” indicating individual ones are not given, and they are simply referred to as “memory cell circuits 22”. Also, in this embodiment, when collectively referring to the n peripheral circuits 24, the symbol “n” indicating individual ones is not given, and they are simply referred to as “peripheral circuits 24”. FIG. 3 shows a circuit diagram representing the circuit configuration of one memory cell circuit 22 among the m memory cell circuits 22 and the peripheral circuit 24 as the non-volatile memory circuit 16. The non-volatile memory circuit 16 of this embodiment shown in FIG. 3 is an example of the semiconductor device of the present disclosure.

[0022] The control circuit 12 has a function of supplying various signals (details will be described later) to the non-volatile memory circuit group 15. Also, the control circuit 12 has an address decoder 20, and the address decoder 20 and the non-volatile memory circuit group 15 are connected by a global word line Glb_WL m . An instruction signal for instructing writing or reading of data to / from the memory cell 21 of the plurality of memory cell circuits 22 included in the non-volatile memory circuit group 15 flows through the global word line Glb_WL m . Also, the control circuit 12 of this embodiment outputs a control signal V PG for controlling the supply of the power supply voltage to the power switch 14.

[0023] As in the example shown in FIG. 2, the power switch 14 of this embodiment uses a PMOS transistor P4. A control signal V output from the control circuit 12 is input to the control terminal of the PMOS transistor P4, and so-called power gating is performed according to the control signal V PG is input, and so-called power gating is performed according to the control signal V PG .

[0024] One terminal of the PMOS transistor P4 is connected to a power supply line that supplies the VDD voltage, which is a normal power supply, and the other terminal is connected to a power supply line that supplies the VVDD voltage, which is a virtual power supply. When the control signal V PG is "0", the PMOS transistor P4 is turned on, and the VVDD voltage obtained by the VDD voltage is output to the non-volatile memory circuit group 15. On the other hand, when the control signal V PG is "1", the PMOS transistor P4 is turned off. As a result, the supply of the VVDD voltage to the non-volatile memory circuit group 15 is cut off. In this way, by cutting off the supply of the VVDD voltage to the non-volatile memory circuit group 15, specifically, the memory cell circuit 22 and the peripheral circuit 24 of the non-volatile memory circuit 16, the power consumption due to the leakage current is reduced. In the following, in each element or the like, being connected to the power supply line that supplies the VVDD voltage may be expressed as "connected to the VVDD voltage".

[0025] The internal circuit 18 has a function of processing data (output Q) held in each non-volatile memory circuit 16 of the non-volatile memory circuit group 15, and is a circuit arranged in the semiconductor integrated circuit 10. The internal circuit 18 is not particularly limited as long as it is a circuit having a function according to the requirements of the user or the like. For example, when the non-volatile memory circuit group 15 holds image data, an image processing circuit can be cited as the internal circuit 18. Note that the internal circuit 18 may include a plurality of functions (circuits).

[0026] The non-volatile memory circuit 16 has a function of holding (latching) the input signal D and outputting an output Q corresponding to the input signal D (having the same logical value (level)). The non-volatile memory circuit 16 of the present embodiment is a SRAM (Static Random Access Memory).

[0027] Referring to FIG. 3, the non-volatile memory circuit 16 of the present embodiment will be described in detail. As described above, FIG. 3 shows a circuit diagram representing the circuit configuration of one memory cell circuit 22 out of the m memory cell circuits 22 included in the non-volatile memory circuit 16 and the peripheral circuit 24. In addition, FIG. 3 also shows a circuit diagram representing an example of a part of the circuits in the control circuit 12 related to the operation of the non-volatile memory circuit 16 together with the non-volatile memory circuit 16 of the present embodiment.

[0028] In front of the memory cell circuit 22 of the non-volatile memory circuit 16, the AND circuits AND1 to AND4, the OR circuits OR1 and OR2, and the NOR circuit NOR1 of the control circuit 12 are connected.

[0029] The non-volatile memory circuit group 15 includes m global word lines Glb_WL for selecting the memory cell circuit 22 corresponding to the non-volatile memory cell 21 for reading and writing data. As shown in FIG. 3, the global word line Glb_WL for word m connected to the address decoder 20 m is connected to the input terminals of the AND circuits AND1, AND4, and the OR circuits OR1, OR2. Also, an RW_EN signal is input to the AND circuit AND1 from the control circuit 12. From the AND circuit AND1, the logical product of the RW_EN signal and the signal flowing through the global word line Glb_WL m is output as an output to the word line Local_WL corresponding to word m m .

[0030] A Restore_All signal for controlling a restore operation, which will be described in detail later, is input to the OR circuit OR1 from the control circuit 12. From the AND circuit AND2, the global word line Glb_WL mThe logical sum of the signal flowing through and the Restore_All signal is input to AND circuit AND2. The GlB_LPG signal is further input to AND circuit AND2 from control circuit 12. From AND circuit AND2, the logical product of the logical sum of OR circuit OR1 and the GlB_LPG signal is output as a signal line Local_LPG.

[0031] Also, the Restore_All signal is input to OR circuit OR2 from control circuit 12. From AND circuit AND3, the global word line Glb_WL m The logical sum of the signal flowing through and the Restore_All signal is input to AND circuit AND3. The GlB_SR1 signal is further input to AND circuit AND3 from control circuit 12. From AND circuit AND3, the logical product of the logical sum of OR circuit OR2 and the GlB_SR1 signal is output as a signal line Local_SR1.

[0032] Also, the Glb_SR2 signal is input to AND circuit AND4 from control circuit 12. From AND circuit AND4, the logical product of the signal flowing through the global word line Glb_WL m and the Glb_SR2 signal is input to NOR circuit NOR1. The Str_Burst signal for controlling the store operation, the details of which will be described later, is further input to NOR circuit NOR1 from control circuit 12. From NOR circuit NOR1, the negative logical sum of the logical product of AND circuit AND4 and the Str_Burst signal is output as a signal line Local_SR2.

[0033] On the one hand, as shown in FIG. 3, among a pair of bit lines bit and bit_b of the non-volatile memory circuit 16, a PMOS transistor P1 is connected to the bit line bit. One terminal of the PMOS transistor P1 is connected to the VVDD voltage, and the other terminal is connected to the bit line bit. Also, among the pair of bit lines bit and bit_b, a PMOS transistor P2 is connected to the bit line bit_b. One terminal of the PMOS transistor P2 is connected to the VVDD voltage, and the other terminal is connected to the bit line bit_b. Control terminals of each of the PMOS transistors P1 and P2 are connected to a signal line to which a PRE signal is supplied by the control circuit 12. Also, a control terminal of a PMOS transistor P3 is connected to the signal line to which the PRE signal is supplied. One terminal of the PMOS transistor P3 is connected to the bit line bit, and the other terminal is connected to the bit line bit_b.

[0034] The memory cell circuit 22 of the non-volatile memory circuit 16 includes inverters INV1 and INV2. The inverters INV1 and INV2 function as a memory cell 21 by an inverter loop that holds 1-bit data.

[0035] The input terminal of the inverter INV1 is connected to the storage node d_b, and the output terminal is connected to the storage node d. Also, the VVDD voltage is supplied as a power source to the inverter INV1 via a PMOS transistor P4. The control terminal of the PMOS transistor P4 is connected to the signal line Local_LPG. On the other hand, the input terminal of the inverter INV2 is connected to the storage node d, and the output terminal is connected to the storage node d_b. Also, the VVDD voltage is supplied as a power source to the inverter INV2 via a PMOS transistor P5. The control terminal of the PMOS transistor P5 is connected to the signal line Local_LPG.

[0036] Further, the memory cell circuit 22 includes transistors TR1 and TR2 that are controlled to read and write data to the memory cell 21. One terminal of the transistor TR1 is connected to the bit line bit, and the other terminal is connected to the storage node d. Also, one terminal of the transistor TR2 is connected to the bit line bit_b, and the other terminal is connected to the storage node d_b. The control terminals of each of the transistors TR1 and TR2 are connected to the word line Local_WL m and are controlled to be turned on and off by a signal flowing through the word line Local_WL m .

[0037] Further, the memory cell circuit 22 includes NMOS transistors RstrTR1 and RstrTR2 that are controlled when performing a restore, which will be described in detail later. The NMOS transistors RstrTR1 and RstrTR2 of the present embodiment are an example of the second switch of the present disclosure. One terminal of the NMOS transistor RstrTR1 is connected to the storage node d, and the other terminal is connected to the MTJ element MTJ1. Also, the control terminal of the NMOS transistor RstrTR1 is connected to the signal line Local_SR1. On the other hand, one terminal of the NMOS transistor RstrTR2 is connected to the storage node d_b, and the other terminal is connected to the MTJ element MTJ2. Also, the control terminal of the NMOS transistor RstrTR2 is connected to the signal line Local_SR1. The NMOS transistors RstrTR1 and RstrTR2 are controlled to be turned on and off by a signal flowing through the signal line Local_SR1. Specifically, the NMOS transistors RstrTR1 and RstrTR2 are turned on when performing a restore and turned off when performing a store.

[0038] Further, the memory cell circuit 22 includes PMOS transistors StrTR1 and StrTR2 that are controlled when performing a store, the details of which will be described later. The PMOS transistors StrTR1 and StrTR2 of the present embodiment are an example of the first switch of the present disclosure. One terminal of the PMOS transistor StrTR1 is connected to the bit line bit, and the other terminal is connected to the other terminal of the NMOS transistor RstrTR1 and the MTJ element MTJ1. Also, the control terminal of the PMOS transistor StrTR1 is connected to the signal line Local_SR2. One terminal of the PMOS transistor StrTR2 is connected to the bit line bit_b, and the other terminal is connected to the other terminal of the NMOS transistor RstrTR2 and the MTJ element MTJ2. Also, the control terminal of the PMOS transistor StrTR2 is connected to the signal line Local_SR2. The PMOS transistors StrTR1 and StrTR2 are controlled to be turned on and off by a signal flowing through the signal line Local_SR2. Specifically, the PMOS transistors StrTR1 and StrTR2 are turned on when performing a store and turned off when performing a restore.

[0039] Furthermore, as shown in FIG. 3, the memory cell circuit 22 of the present embodiment includes MTJ elements MTJ1 and MTJ2. The MTJ elements MTJ1 and MTJ2 of the present embodiment are an example of the non-volatile memory section of the present disclosure. The resistance values of the MTJ elements MTJ1 and MTJ2 change according to the magnitude of the applied voltage. When a current flows in the direction from the free layer f to the pinned layer p, the magnetization direction of the free layer f becomes the same as that of the pinned layer p, and the MTJ element becomes a low resistance, storing data with a logical value of "1". On the other hand, when a current flows in the direction from the pinned layer p to the free layer f, the magnetization direction of the free layer f becomes opposite to that of the pinned layer p, and the MTJ element becomes a high resistance, storing data with a logical value of "0".

[0040] The data stored in the MTJ elements MTJ1 and MTJ2 is retained even after the VVDD voltage supply is stopped. Therefore, when the non-volatile memory circuit 16 of this embodiment performs power gating, before transitioning to the sleep state, the data held by the memory cell 21 is written into and stored in the MTJ elements MTJ1 and MTJ2. Also, when the non-volatile memory circuit 16 resumes from the sleep state, the data written in the MTJ elements MTJ1 and MTJ2 is read out to the memory nodes d and d_b to restore the data in the memory cell 21.

[0041] In this embodiment, the operation of storing the data held by the memory cell 21 (memory nodes d and d_b) in the MTJ elements MTJ1 and MTJ2 is referred to as "store". Also, the operation of reading data from the MTJ elements MTJ1 and MTJ2 and restoring it to the memory nodes d and d_b is referred to as "restore".

[0042] In the MTJ elements MTJ1 and MTJ2 of this embodiment, the p-side of the pin layer is connected to the memory cell 21. The f-side of the free layer of the MTJ elements MTJ1 and MTJ2 is connected to the signal line through which the CTRL signal flows.

[0043] On the other hand, the peripheral circuit 24 includes write registers (Write_reg) 30, tri-state drivers TSDRV1 and TSDRV2, a sense amplifier 32, and a read register (Read_reg) 34.

[0044] Note that the tri-state drivers TSDRV1 and TSDRV2, inverters IV2, AND circuits AND5 and AND6, XOR circuit XOR1, OR circuit OR3, NMOS transistors RstrTR1 and RstrTR2, and PMOS transistors StrTR1 and StrTR2 of this embodiment are examples of the write control unit of the present disclosure. Also, the sense amplifier 32 of this embodiment is an example of the second storage unit of the present disclosure, and the Read_reg 34 of this embodiment is an example of the first storage unit of the present disclosure.

[0045] Write_reg30 temporarily stores the data Q to be written to the memory cell circuit 22. Write_reg30 is connected to the bit line bit via the inverter IV1 and the NMOS transistors N3 and N4.

[0046] The inverter IV1 has Write_reg connected to its input terminal and the control terminal of the NMOS transistor N3 connected to its output terminal. One terminal of the NMOS transistor N3 is connected to the ground, and the other terminal is connected to one terminal of the NMOS transistor N4. The other terminal of the NMOS transistor N4 is connected to the bit line bit. The control terminal of the NMOS transistor N4 is connected to the signal line to which the signal WE is supplied by the control circuit 12.

[0047] Also, Write_reg30 is connected to the bit line bit_b via the NMOS transistors N5 and N6. One terminal of the NMOS transistor N5 is connected to the ground, and the other terminal is connected to one terminal of the NMOS transistor N6. The other terminal of the NMOS transistor N6 is connected to the bit line bit_b. The control terminal of the NMOS transistor N6 is connected to the signal line to which the signal WE is supplied.

[0048] On the other hand, the output terminal of the tri-state driver TSDRV1 and the output terminal of the tri-state driver TSDRV2 are connected via the inverter IV2. Specifically, the input terminal of the inverter IV2 is connected to the input terminal of the tri-state driver TSDRV1, and the output terminal of the inverter IV2 is connected to the input terminal of the tri-state driver TSDRV2. The output of the tri-state driver TSDRV1 is connected to the bit line bit, and the output of the tri-state driver TSDRV2 is connected to the bit line bit_b. The TSEN signal is input to each of the tri-state drivers TSDRV1 and TSDRV2. The tri-state drivers TSDRV1 and TSDRV2 are driven according to the TSEN signal.

[0049] FIG. 4 shows a circuit diagram illustrating an example of the tristate drivers TSDRV1 and TSDRV2 of the present embodiment. As shown in FIG. 4, each of the tristate drivers TSDRV1 and TSDRV2 includes a NAND circuit NAND1, an inverter IV3, a NOR circuit NOR2, a PMOS transistor P5, and an NMOS transistor N7.

[0050] The TSEN signal and the signal A are input to the NAND circuit NAND1. The negative logical product of the NAND circuit NAND1 is input to the control terminal of the PMOS transistor P5. One terminal of the PMOS transistor P5 is connected to the VVDD voltage, and the other terminal is connected to one terminal of the NMOS transistor N7.

[0051] The output of the inverter IV3 and the signal A are input to the NOR circuit NOR2. The negative logical sum of the NOR circuit NOR2 is input to the control terminal of the NMOS transistor N7. The other terminal of the NMOS transistor N7 is connected to the ground. The intermediate node between the PMOS transistor P5 and the NMOS transistor N7 is output as the output Y from the tristate drivers TSDRV1 and TSDRV2.

[0052] Specifically, when the logical value of the TSEN signal is “0”, regardless of the logical value of the signal A, the PMOS transistor P5 and the NMOS transistor N7 are turned off, and the output Y becomes indeterminate. On the other hand, when the logical value of the TSEN signal is “0” and the logical value of the signal A is “1”, the PMOS transistor P5 is turned on and the NMOS transistor N7 is turned off, and the output Y becomes the VVDD voltage (logical value “1”). When the logical value of the signal A is “0”, the PMOS transistor P5 is turned off and the NMOS transistor N7 is turned on, and the output Y becomes the ground potential (logical value “0”).

[0053] On the other hand, when reading the data stored in the memory cell 21, the sense amplifier 32 detects the potentials of the bit lines bit and bit_b, and based on the detected potential difference, determines the logical value of the data read from the memory cell 21, and has a function of storing the read data. Specifically, the sense amplifier 32 outputs, as the sense amplifier output SAO, a determination result of determining whether the logical value of the data read from the memory cell 21 is "0" or "1" based on the potential difference between the bit lines bit and bit_b.

[0054] The bit line bit is connected to the sense amplifier 32 via the NMOS transistor N1, and the bit line bit_b is connected to the sense amplifier 32 via the NMOS transistor N2. Signal lines through which the SA_BD signal output from the control circuit 12 flows are connected to the control terminals of the NMOS transistors N1 and N2, respectively. Further, the GLB_PRE signal and the SA_EN signal output from the control circuit 12 are input to the sense amplifier 32. FIG. 5 shows a circuit diagram illustrating an example of the sense amplifier 32. The sense amplifier 32 shown in FIG. 5 includes PMOS transistors P6 to P14, NMOS transistors N8 to N11, and an IV4 that outputs the sense amplifier output SAO, and is controlled by the GLB_PRE signal, the GBL signal, the GBLB signal, and the signal SA_EN.

[0055] The sense amplifier output SAO, which is the output of the sense amplifier 32, is input to the Read_reg34. Further, the clock signal CLK and the Update_EN1 signal output from the control circuit 12 are input to the Read_reg34.

[0056] On the other hand, the sense amplifier output SAO of the sense amplifier 32 and the Glb_SR2 signal are input to the AND circuit AND5, and the logical product of the sense amplifier output SAO and the GLB_SR2 signal is output. On the other hand, the output Q of the Read_reg34 and the Glb_SR2 signal are input to the AND circuit AND6, and the logical product of the output Q and the GLB_SR2 signal is output.

[0057] The output of the AND circuit AND5 and the output of the AND circuit AND6 are input to the XOR circuit XOR1. The exclusive logical sum of the XOR circuit XOR1 and the SF (Store_Forcibly) signal output from the control circuit 12 are input to the OR circuit OR3. The logical sum of the OR circuit OR3 is output as the TSEN signal.

[0058] Next, the operation of the non-volatile memory circuit 16 of the present embodiment will be described. (Normal operation mode) First, the normal operation in which the memory cell circuit 22 functions as SRAM will be described. The normal operation includes an operation of writing data to the memory cell circuit 22 and an operation of reading data from the memory cell circuit 22.

[0059] When the memory cell circuit 22 performs normal operation, regardless of data reading or writing, the logical values of the GlB_SR2 signal, Str_Burst signal, SF signal, GlB_SR1 signal, and Restore_All signal output from the control circuit 12 are "0".

[0060] Since the logical values of the GlB_SR2 signal and the Str_Burst signal are "0", the logical product of the AND circuit AND4 is "0", and the negative logical sum of the NOR circuit NOR1 becomes "1". Therefore, the PMOS transistors StrTR1 and StrTR2 are in the off state.

[0061] Also, since the logical values of the GlB_SR2 signal and SF are "0", the logical products of the AND circuits AND5 and AND6 are "0", the exclusive logical sum of the XOR circuit XOR1 is "0", and the logical sum of the OR circuit OR3 is "0". Therefore, the potential of the TSEN signal becomes "0", and as described above, in the tri-state drivers TSDRV1 and TSDRV2, the PMOS transistor P5 and the NMOS transistor N7 are in the off state and the output Y becomes indeterminate.

[0062] Also, since the logical values of the GlB_SR1 signal and the Restore_All signal are "0", the logical sum of the OR circuit OR2 is the global word line Glb_WL mbecomes equal to the logical value, and the logical product of the AND circuit AND3 becomes "0". Therefore, the NMOS transistors RstrTR1 and RstrTR2 are in the off state.

[0063] (Normal operation mode: Read operation) First, the operation of reading data from the memory cell circuit 22 (Read operation) will be described. FIG. 6 shows an example of a timing chart in the read operation of the memory cell circuit 22. Note that during the read operation, the logical value of the WE signal is set to "0". Since the logical value of the WE signal is "0", the NMOS transistors N4 and N6 are in the off state.

[0064] Synchronously with the rising timing t11 of the clock signal CLK, the logical value of the RW_EN signal is set to "0". As a result, since the logical product of the AND circuit AND1 becomes "0", the word line Local_WL m becomes "0" in logical value. With the logical value of the word line Local_WL m being "0", by setting the logical value of the PRE signal to "0", the PMOS transistors P1 and P2 are turned on, and the bit lines bit and bit_b are precharged. Also, the logical value of the SA_BD signal is set to "1", and the NMOS transistors N1 and N2 are turned on.

[0065] Furthermore, the decoding operation in the address decoder 20 is also performed during this precharge period. Here, it is assumed that only the global word line Glb_WL m for word m is selected and becomes "1".

[0066] Subsequently, synchronously with the falling timing t12 of the clock signal CLK, the precharge operation is terminated and the logical value of the RW_EN signal is set to "1". As a result, the logical value of the global word line Glb_WL m becomes equal to the logical value of the word line Local_WL m Here, since the logical value of the global word line Glb_WL m is "1", the word line Local_WL mThe logical value of becomes "1", and transistors TR1 and TR2 turn on. As a result, the data of word m, specifically, the data held by memory cell 21, starts to be read.

[0067] When the reading starts, the data of memory node d is read out to bit line bit, and the data of memory node d_b is read out to bit line bit_b and sensed via sense amplifier 32. When the data of memory node d is "1", the logical value of sense amplifier output SAO of sense amplifier 32 becomes "1". On the other hand, when the data of memory node d is "0", the logical value of sense amplifier output SAO of sense amplifier 32 becomes "0". That is, sense amplifier 32 outputs a sense amplifier output SAO whose logical value matches the logical value of the read data as a determination result of determining the logical value of the data read from memory cell 21. The sense amplifier output SAO of memory cell 21 and sense amplifier 32 is stored in Read_reg34 at the rising timing t13 of the next clock signal CLK, (refer to "VALID" in FIG. 6) and the reading ends.

[0068] (Normal operation mode: Write operation) Next, the operation of writing data to memory cell circuit 22 (Write operation) will be described. FIG. 7 shows an example of a timing chart in the write operation to memory cell circuit 22. When performing the write operation, the logical value of SA_BD signal remains "0", and NMOS transistors N1 and N2 are in the off state.

[0069] First, the data to be written to memory cell 21 is set in Write_reg30 in advance (refer to FIG. 7, timings t21 to t23).

[0070] At the rising timing t23 of the next clock signal CLK, the precharge operation of bit lines bit and bit_b is performed.

[0071] Subsequently, in synchronization with the falling timing t24 of the clock signal CLK, the precharge operation is terminated, the logical value of the WE signal is set to "1", and the NMOS transistors N4 and N6 are turned on. As a result, the data set in Write_reg30 is transmitted to the bit lines bit and bit_b.

[0072] Furthermore, as shown in FIG. 7, the logical value of the RW_EN signal is set to "1", and the logical value of the word line Local_WL m of the word (for example, word m) for which writing is to be performed is set to "1". As a result, the transistors TR1 and TR2 are turned on, the data on the bit line bit is transmitted to the memory node d, and the data on the bit line bit_b is transmitted to the memory node d_b, so that data with a logical value of "1" is written into the memory cell 21. At the falling timing t25 of the next clock signal CLK, the logical value of the WE signal is set to "0", and the NMOS transistors N4 and N6 are turned off. Also, the logical value of the RW_EN signal is set to "0", and by setting the logical product of the AND circuit AND1 to "0", the logical value of the word line Local_WL m is set to "0" to terminate the writing operation.

[0073] (Store operation mode) Next, the store operation mode in the memory cell circuit 22 will be described. The store operation mode includes the initialization operation of the MTJ elements MTJ1 and MTJ2 and the normal store operation.

[0074] (Store operation mode: Initialization operation of MTJ elements MTJ1 and MTJ2) First, the initialization operation of the MTJ elements MTJ1 and MTJ2 will be described. FIG. 8 shows an example of a timing chart in the initialization operation of the MTJ elements MTJ1 and MTJ2. Note that the timings t33 to t35 in FIG. 8 show the case where the logical value of the CTL signal is "0", and the timings t35 to t37 show the case where the logical value of the CTL signal is "1".

[0075] First, as a first step, perform the above-described writing operation, perform the writing operation of the memory cell 21 (see FIG. 7), and write the value (logical value) to be initialized for the MTJ elements MTJ1 and MTJ2 in the memory cell 21. When initializing the MTJ elements MTJ1 and MTJ2 to "0", write "0" in the memory cell 21. Also, when initializing the MTJ elements MTJ1 and MTJ2 to "1", write "1" in the memory cell 21.

[0076] Next, as a second step, read the data written in the memory cell 21, read the data held in the word m, and store it in Read_reg34 (refer to the period of timings t31 to t33 in the timing chart of FIG. 8). Note that if there is another means to directly set the data in Read_reg34, the value of Read_reg34 may be set by that means. In that case, the above first and second steps become unnecessary.

[0077] Next, as a third step, write (store) the data stored in Read_reg34 to the MTJ elements MTJ1 and MTJ2. As shown in the timings t33 to t37 of FIG. 8, set the logical values of the RW_EN signal, Glb_SR1 signal, Restore_all signal, and SA_BD signal to "0".

[0078] By setting the logical value of the RW_EN signal to "0", the logical product of the AND circuit AND1 becomes 0, and the logical value of Local_WL m becomes "0". Also, by setting the logical value of the Glb_SR1 signal to "0", the logical product of the AND circuit AND3 becomes 0, and the logical value of the signal line Local_SR1 becomes "0". Therefore, the NMOS transistors RstrTR1 and RstrTR2 are turned off. By setting the logical value of the Restore_all signal to "0", the logical sum of the OR circuits OR1 and OR2 becomes equal to the global word line Glb_WL m becomes equal. By setting the logical value of the SA_BD signal to "0", the NMOS transistors N1 and N2 are turned off.

[0079] Also, set the logical values of the SF signal and the Str_Burst signal to "1". By setting the logical value of the SF signal to "1", the logical sum of the OR circuit OR3 becomes "1", and the logical value of the TSEN signal becomes "1". Also, by setting the logic of the Str_Burst signal to "1", the negative logical sum of the NOR circuit NOR1 becomes "0", and the logical value of the signal line Local_SR2 becomes "0". Therefore, the PMOS transistors StrTR1 and StrTR2 are turned on.

[0080] As a result, the tri-state drivers TSDRV1 and TSDRV2 are activated, and since the PMOS transistors StrTR1 and StrTR2 are turned on, the data stored in Read_reg34 is written (stored) into the MTJ elements MTJ1 and MTJ2 via the bit lines bit and bit_b and the PMOS transistors StrTR1 and StrTR2.

[0081] (Store operation mode: normal store operation) Next, the normal store operation will be described. In the non-volatile memory circuit 16 of the present embodiment, the normal store operation is performed for each word. Set the logical value of the Str_Burst signal to "0". Here, it is assumed that some data is already stored in the MTJ elements MTJ1 and MTJ2, and also that some data is held in the memory cell circuit 22 after performing the writing operation (see Fig. 7) in the normal operation described above. The operation of storing the data held in the memory cell 21 of the memory cell circuit 22 in the MTJ elements MTJ1 and MTJ2 will be described with reference to Fig. 9. Fig. 9 shows an example of a timing chart in the store operation of the memory cell circuit 22.

[0082] First, as a first step, as shown in the timings t41 to t43 in Fig. 9, perform the above-described read operation of the memory cell 21 (see Fig. 6), read the data held in word m via the sense amplifier 32, and store it in Read_reg34. That is, the data held in the memory cell 21 is saved in Read_reg34.

[0083] Next, as a second step, as shown in timings t43 to t47 in FIG. 9, a restore operation is performed to read out the data stored in the MTJ elements MTJ1 and MTJ2 to the memory cell 21. In the restore operation, the transistors TR1 and TR2 and the PMOS transistors StrTR1 and StrTR2 are turned off, and the NMOS transistors RstrTR1 and RstrTR2 are turned on. Specifically, as shown in FIG. 9, in synchronization with the rising timing t43 of the clock signal CLK, the logical value of the GlB_SR1 signal is set to "1". Also, the logical value of the global word line Glb_WL m is set to "1". Therefore, the logical sum of the OR circuit OR2 becomes "1", and the logical product of the AND circuit AND3 becomes "1", so that the logical value of the signal line Local_SR1 of word m becomes "1", and the NMOS transistors RstrTR1 and RstrTR2 are turned on. As a result, a restore operation is performed in which the data stored in the MTJ elements MTJ1 and MTJ2 is read out to the memory cell 21. The details of the restore operation will be described later.

[0084] By performing the restore operation, the data stored in the MTJ elements MTJ1 and MTJ2 is read out and held in the memory cell 21. As a result, the data originally held in the memory cell 21 is corrupted. However, as described above, in this embodiment, since the data originally held in the memory cell 21 is saved in the first step, the data originally held in the memory cell 21 does not become unknown.

[0085] Next, as a third step, as shown in timings t47 to t49 in FIG. 9, the data stored in the MTJ elements MTJ1 and MTJ2 is stored in the sense amplifier 32. In this operation, the transistors TR1 and TR2 and the NMOS transistors N1 and N2 are turned on, and the NMOS transistors RstrTR1 and RstrTR2 and the PMOS transistors StrTR1 and StrTR2 are turned off. Specifically, as shown in FIG. 9, in synchronization with the rising timing t47 of the clock signal CLK, the logical values of the RW_EN signal and the global word line Glb_WL m are set to "1". As a result, the logical product of the AND circuit AND1 becomes "1", the logical value of the word line Local_WL m becomes "1", and the transistors TR1 and TR2 are turned on. Also, by setting the logical value of the SA_BD signal to "1", the NMOS transistors N1 and N2 are turned on. Further, by setting the logical value of the signal line Local_SR1 to "0", the NMOS transistors RstrTR1 and RstrTR2 are turned off. Also, by setting the logical value of the signal line Local_SR2 to "1", the PMOS transistors StrTR1 and StrTR2 are turned off.

[0086] As a result, the data of the MTJ elements MTJ1 and MTJ2 of the word m held in the memory cell 21 is read out to the bit lines bit and bit_b, sensed via the sense amplifier 32, and output as the sense amplifier output SAO of the sense amplifier 32. In other words, the value of the sense amplifier output SAO of the sense amplifier 32 is equivalent to the logical value of the data stored in the MTJ elements MTJ1 and MTJ2. The value of the sense amplifier output SAO is newly held until the sense amplifier 32 is activated. Note that the value of the sense amplifier output SAO is not stored in the Read_reg34. As an example, in this embodiment, by setting the logical value of the Update_EN1 signal to "0", the value of the sense amplifier output SAO is not stored in the Read_reg34.

[0087] Next, as the fourth step, as shown in the timings t49 to t413 in FIG. 9, compare the logical value of the output Q of Read_reg34 with the logical value of the sense amplifier output SAO of the sense amplifier 32. If the logical value of the output Q does not match the logical value of the sense amplifier output SAO, store the output Q of Read_reg34 in the MTJ elements MTJ1 and MTJ2. On the other hand, if the logical value of the output Q of Read_reg34 matches the logical value of the sense amplifier output SAO of the sense amplifier 32, do not store the output Q of Read_reg34 in the MTJ elements MTJ1 and MTJ2. Hereinafter, this storing method is referred to as Data-Aware Storing (DAS).

[0088] Here, the data held by the memory cell 21 is stored in Read_reg34 and output as Q. Also, the data stored in the MTJ elements MTJ1 and MTJ2 is stored in the sense amplifier 32 and output as the sense amplifier output SAO. Therefore, when the data held by the memory cell 21 does not match the data stored in the MTJ elements MTJ1 and MTJ2, the data held by the memory cell 21 is stored in the MTJ elements MTJ1 and MTJ2. On the other hand, when the data held by the memory cell 21 matches the data stored in the MTJ elements MTJ1 and MTJ2, the data held by the memory cell 21 is not stored in the MTJ elements MTJ1 and MTJ2.

[0089] Hereinafter, this operation will be specifically described. In this operation, the transistors TR1 and TR2, the NMOS transistors N1 and N2, and the NMOS transistors RstrTR1 and RstrTR2 are turned off, and the PMOS transistors StrTR1 and StrTR2 are turned on.

[0090] Specifically, as shown in FIG. 9, in synchronization with the rising timing t49 of the clock signal CLK, the logical value of the SA_BD signal is set to "0", and the NMOS transistors N1 and N2 are turned off. Also, the logical value of the Glb_SR2 signal is set to "1". As a result, the logical product of the AND circuit AND5 becomes the logical value of the sense amplifier output SAO of the sense amplifier 32. That is, the logical product of the AND circuit AND5 becomes the logical value of the data stored in the MTJ elements MTJ1 and MTJ2. On the other hand, the logical product of the AND circuit AND6 becomes the logical value of the output Q of Read_reg34. That is, the logical product of the AND circuit AND6 becomes the logical value of the data held in the memory cell 21.

[0091] The XOR circuit XOR1 compares whether the logical value of the sense amplifier output SAO is the same as the logical value of the output Q, and outputs the comparison result. That is, the XOR circuit XOR1 compares the logical value of the data stored in the MTJ elements MTJ1 and MTJ2 with the logical value of the data held in the memory cell 21, and outputs the comparison result.

[0092] When the logical value of the sense amplifier output SAO is different from the logical value of the output Q, that is, when the logical value of the data stored in the MTJ elements MTJ1 and MTJ2 is different from the logical value of the data held in the memory cell 21, the exclusive logical sum of the XOR circuit XOR1 becomes "1". As a result, the logical sum of the OR circuit OR3 becomes "1" and the logical value of the TSEN signal becomes "1", activating the tri-state drivers TSDRV1 and TSDRV2. Also, the output Q of Read_reg34 is input to the tri-state driver TSDRV1. Further, the inverted value QB of the output Q of Read_reg34 is input to the tri-state driver TSDRV2. On the other hand, since the logical value of the Glb_SR2 signal is "1", the logical value of the Str_Burst signal is "0", but the negative logical product of the NOR circuit NOR1 becomes "0", and since the logical value of the signal line Local_SR2 becomes "0", the PMOS transistors StrTR1 and StrTR2 are turned on. As a result, via the bit lines bit and bit_b, the output Q of Read_reg34, which is the data held in the memory cell 21, is stored in the MTJ elements MTJ1 and MTJ2 of word m.

[0093] On the other hand, when the logical value of the sense amplifier output SAO is the same as the logical value of the output Q, that is, when the logical value of the data stored in the MTJ elements MTJ1 and MTJ2 is the same as the logical value of the data held in the memory cell 21, the exclusive logical sum of the XOR circuit XOR1 becomes "0". At this time, the logical value of the SF signal is "0". As a result, the logical sum of the OR circuit OR3 becomes "0" and the logical value of the TSEN signal becomes "0", so the tri-state drivers TSDRV1 and TSDRV2 are not activated. Therefore, the bit lines bit and bit_b are not driven, and the output Q of Read_reg34, which is the data held in the memory cell 21, is not stored in the MTJ elements MTJ1 and MTJ2 of word m.

[0094] Note that in this case, the potential (logical value) states remaining in the bit lines bit and bit_b from the previous step (the third step) cause the PMOS transistors StrTR1 and StrTR2 to turn on, but no problem occurs. As described above, in the third step, the data of the MTJ elements MTJ1 and MTJ2 of the word m held in the memory cell 21 is read out to the bit lines bit and bit_b. Since the data of the bit lines bit and bit_b is the same as the data of the MTJ elements MTJ1 and MTJ2, the data of the MTJ elements MTJ1 and MTJ2 is not rewritten.

[0095] Thus, in the non-volatile memory circuit 16 of the present embodiment, when the data held in the memory cell 21 is the same as the data stored in the MTJ elements MTJ1 and MTJ2, it is possible to suppress storing the data held in the memory cell 21 in the MTJ elements MTJ1 and MTJ2.

[0096] By repeating the operations of the first to fourth steps for each word to be stored, as described above, the storing operation of the data held in the memory cell 21 to the MTJ elements MTJ1 and MTJ2 is performed.

[0097] (Power-off mode) In the power-off mode, as described above, the control signal V PG is set to "1", the power switch 14 is turned off, and the supply of the VVDD voltage to the memory cell circuit 22 and the peripheral circuit 24 is cut off. In the non-volatile memory circuit 16, this reduces the power consumption due to the leakage current.

[0098] (Restore operation mode) Next, the restore operation mode in the memory cell circuit 22 will be described. FIG. 10 shows an example of a timing chart in the restore operation. Note that before performing the restore operation, the power switch 14 is turned on to start the supply of the VVDD voltage to the memory cell circuit 22 and the peripheral circuit 24.

[0099] Synchronize with the rising timing t51 of the clock signal CLK and set the logic value of the Restore_All signal to "1". As a result, the logical sum of the OR circuits OR1 and OR2 becomes "1". Also, set the logic value of the Glb_LPG signal to "1". Thereby, the logical product of the AND circuit AND2 becomes "1", the logic value of the signal line Local_LPG becomes "1", and the PMOS transistors P4 and P5 are turned off.

[0100] Furthermore, by setting the logic value of the GlB_SR1 signal to "1", the output of the AND circuit AND3 becomes "1", the logic value of the signal line Local_SR1 becomes "1", and the RstrTR1 and RstrTR2 are turned on. Since the logic value of the CTRL signal is "0", the memory nodes d and d_b become "0".

[0101] Next, synchronize with the rising timing t53 of the clock signal CLK and set the logic value of the Local_LPG signal to "0". Thereby, the logical product of the AND circuit AND2 becomes "0", the logic value of the signal line Local_LPG becomes "0", and the PMOS transistors P4 and P5 are turned on.

[0102] Due to the difference in resistance between the MTJ element MTJ1 and the MTJ element MTJ2, a slight potential difference occurs between the memory node d and the memory node d_b. This potential difference is amplified by the inverter loop composed of the inverters INV1 and INV2, and the potentials of the memory nodes d and d_b are determined. As a result, the data stored in the MTJ elements MTJ1 and MTJ2 is read out (restored) to the memory cell 21.

[0103] Note that this restore operation is performed simultaneously and in parallel for all bits of all words without passing through the bit lines bit and bit_b, so the return from the power-off mode is performed at high speed.

[0104] As described above, the non-volatile memory circuit 16 of the present embodiment includes a memory cell 21 and a memory cell circuit 22 for enabling the memory cell 21 to be used as a non-volatile memory. Specifically, the non-volatile memory circuit 16 includes a memory cell 21 that holds 1-bit data, a pair of bit lines bit and bit_b for writing data to or reading data from the memory cell 21, and MTJ elements MTJ1 and MTJ2 that store the data held by the memory cell 21. Further, the non-volatile memory circuit 16 causes the data currently held by the memory cell 21 to be stored in Read_reg34, causes the data currently stored in the MTJ elements MTJ1 and MTJ2 to be stored in the sense amplifier 32, and when the data stored in Read_reg34 is different from the data stored in the sense amplifier 32, causes the data stored in Read_reg34 to be written to the MTJ elements MTJ1 and MTJ2 via the pair of bit lines bit and bit_b, and when the data stored in Read_reg34 is the same as the data stored in the sense amplifier 32, does not cause the data stored in Read_reg34 to be written to the MTJ elements MTJ1 and MTJ2.

[0105] Thus, in the present embodiment, when the data held in the memory cell 21 is the same as the data stored in the MTJ elements MTJ1 and MTJ2, the store for writing the data held in the memory cell 21 to the MTJ elements MTJ1 and MTJ2 is not performed. Therefore, according to the non-volatile memory circuit 16 using the memory cell circuit 22 of the present embodiment, the power consumption required for writing the data held in the memory cell 21 to the MTJ elements MTJ1 and MTJ2 can be suppressed, and low power consumption can be achieved.

[0106] Also, for example, in the techniques described in Non-Patent Documents 1 and 2, when reading the data stored in the MTJ element, the data stored in the MTJ element is read into the memory cell of the SRAM. Therefore, in the techniques described in Non-Patent Documents 1 and 2, the data originally held by the memory cell of the SRAM is broken, and it has been difficult to determine the identity between the data held in the memory cell of the SRAM and the data stored in the MTJ element.

[0107] In contrast, the non-volatile memory circuit 16 of the present embodiment reads the data stored in the MTJ elements MTJ1 and MTJ2 into the memory cell 21 after saving the data originally held by the memory cell 21 in the Read_reg34. By reading the data stored in the MTJ elements MTJ1 and MTJ2 into the memory cell 21, the data held by the memory cell 21 will be overwritten by the data stored in the MTJ elements MTJ1 and MTJ2. However, in the non-volatile memory circuit 16 of the present embodiment, by using the data originally held in the memory cell 21 saved in the Read_reg34, it is possible to easily determine the identity between the data held by the memory cell 21 and the data stored in the MTJ elements MTJ1 and MTJ2.

[0108] [Second Embodiment] In the present embodiment, since some configurations and operations of the non-volatile memory circuit 16 are different from those of the non-volatile memory circuit 16 (see FIG. 3) of the first embodiment, different configurations and operations will be described.

[0109] When a non-volatile memory is used in applications such as image processing and machine learning, a method has been proposed and its effectiveness has been suggested in which the upper bits of the data to be stored perform the storage operation over a sufficiently long time, while the lower bits perform the storage in a short time (see Non-Patent Documents 3 and 4). [Non-Patent Document 3] Y. Ono, K. Usami, “Energy Efficient Approximate Storing of Image Data for MTJ Based Non-volatile Memory”, The 9th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA 2020), Korea, Aug. 20, 2020. [Non-Patent Document 4] Y. Ono, K. Usami, “Energy Efficient Approximate Storing to MRAM for Deep Neural Network Tasks in Edge Computing”, The 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2021), Hirosaki, Japan, Mar. 29 - 30, 2021.

[0110] This method is a development form of Approximate Computing (AC), and situations where the lower bits of data cannot be stored accurately occur probabilistically. However, the lower bits have a lower importance compared to the upper bits of the data. Therefore, even when an incorrect value is stored, it has been reported that the degradation of image data cannot be recognized by the human eye (see Non - Patent Document 3), or the accuracy in machine learning does not degrade significantly (see Non - Patent Document 4). The energy consumption during storage is determined by the product of the power consumption and the storage time. Therefore, by controlling to store the lower bits in a shorter time compared to the upper bits, the energy consumption during storage can be reduced compared to the case of storing all bits in a sufficiently long time.

[0111] On the other hand, Non - Patent Documents 3 and 4 also suggest that the optimal bit widths for storing for a long time and for a short time vary depending on the application. The boundary between the bits stored for a long time (upper bits) and the bits stored for a short time (lower bits) within one word to be stored is called the Bit Split Position (BSP). When the application to be executed switches during operation, it is necessary to dynamically change the BSP, but Non - Patent Documents 3 and 4 do not suggest any specific implementation methods for this.

[0112] Therefore, in the present embodiment, a non-volatile memory circuit 16 capable of dynamically changing the BSP will be described. FIG. 11 shows a circuit diagram of an example of the non-volatile memory circuit 16 of the present embodiment. As shown in FIG. 11, the configuration of the peripheral circuit 24 of the present embodiment is different from that of the peripheral circuit 24 (see FIG. 3) of the first embodiment. The peripheral circuit 24 of the present embodiment further includes an AND circuit AND7, an OR circuit OR4, and an AC (Approximate Computing) control register (AC_reg) 36. The AND circuit AND7, the OR circuit OR4, and the AC_reg36 of the present embodiment are examples of the storage time control unit of the present disclosure, and the AC_reg36 of the present embodiment is an example of the setting unit of the present disclosure.

[0113] The clock signal CLK and the Update_EN2 signal are input to the AC_reg36 from the control circuit 12. Further, an AC_MSK signal is input to the non-volatile memory circuit 16 from the control circuit 12. The output Q of the AC_reg36 and the AC_MSK signal are input to the OR circuit OR4. Further, the logical sum of the OR circuit OR4 and the exclusive logical sum of the XOR1 are input to the AND circuit AND7, and the logical product of the AND circuit AND7 is input to the OR circuit OR3.

[0114] As an example, in the present embodiment, it is assumed that the storage time can be switched in clock cycle units. The short-time storage is performed in N_short cycles, and the long-time storage is performed in N_long (N_short < N_long) cycles. The N_short cycle of the present embodiment is an example of the second time of the present disclosure, and the N_long of the present embodiment is an example of the first time of the present disclosure.

[0115] Next, the operation of the non-volatile memory circuit 16 of the present embodiment will be described. The operation of the non-volatile memory circuit 16 of the present embodiment is different from the normal storage operation in the storage operation mode of the non-volatile memory circuit 16 of the first embodiment (see FIG. 9) in part of the normal storage operation in the storage operation mode. Therefore, the normal storage operation in the storage operation mode will be described.

[0116] (Store operation mode: Normal store operation) Similar to the first embodiment, here, it is assumed that some data is already stored in the MTJ elements MTJ1 and MTJ2, and also that some data is held in the memory cell circuit 22 by performing the write operation (see Fig. 7) in the normal operation described above. Fig. 12 shows an example of a timing chart in the store operation of the memory cell circuit 22.

[0117] First, as the first step, as shown in timings t61 to t63 in Fig. 12, in response to the Update_EN2 signal, a value corresponding to the store time is set in AC_reg36. For the AC_reg36 of the peripheral circuit 24 corresponding to the memory cell circuit 22 of the bit to be stored for a long time, "1" is set. Also, for the AC_reg36 of the peripheral circuit 24 corresponding to the memory cell circuit 22 of the bit to be stored for a short time, "0" is set. For example, when the data to be stored is 1 word, n bits, and the lower k (k < n) bits among the n bits are stored in a short time, "0" is set in the AC_reg36 of the peripheral circuit 24 corresponding to the memory cell circuit 22 of the lower k bits. On the other hand, since the upper n - k bits are stored for a long time, "1" is set in the AC_reg36 of the peripheral circuit 24 corresponding to the memory cell circuit 22 of the upper n - k bits.

[0118] Note that the method of determining the number of lower bits n to be stored in a short time or the number of upper bits n - k to be stored in a long time is not limited. For example, it may be determined automatically according to the type of data processed in the internal circuit 18 of the semiconductor integrated circuit 10 or the desired data accuracy, or in a form determined according to the user's desire. In this embodiment, the number of lower bits n or the number of upper bits n - k is instructed by the control circuit 12.

[0119] Next, as a second step, as shown in timings t63 to t65 in FIG. 12, a read operation of the memory cell 21 is performed to read the data held in word m and store it in Read_reg34. This operation is the same as the first step of the normal store operation (see FIG. 9) in the store operation mode of the non-volatile memory circuit 16 of the first embodiment.

[0120] Next, as a third step, as shown in timings t65 to t69 in FIG. 12, a restore operation is performed to read the data stored in the MTJ elements MTJ1 and MTJ2 into the memory cell 21. This operation is the same as the second step of the normal store operation (see FIG. 9) in the store operation mode of the non-volatile memory circuit 16 of the first embodiment.

[0121] Next, as a fourth step, as shown in timings t69 to t611 in FIG. 12, the data stored in the MTJ elements MTJ1 and MTJ2 is stored in the sense amplifier 32. This operation is the same as the third step of the normal store operation (see FIG. 9) in the store operation mode of the non-volatile memory circuit 16 of the first embodiment.

[0122] Next, as a fifth step, as shown in timings t611 to t619 in FIG. 12, the logical value of the output Q of Read_reg34 is compared with the logical value of the sense amplifier output SAO of the sense amplifier 32. When the logical value of the output Q and the logical value of the sense amplifier output SAO do not match, the output Q of Read_reg34 is stored in the MTJ elements MTJ1 and MTJ2. On the other hand, when the logical value of the output Q of Read_reg34 matches the logical value of the sense amplifier output SAO of the sense amplifier 32, the output Q of Read_reg34 is not stored in the MTJ elements MTJ1 and MTJ2.

[0123] This operation compares the logical value of the output Q of Read_reg34 with the logical value of the sense amplifier output SAO of the sense amplifier 32 by the XOR circuit XOR1 in the same manner as the fourth step of the normal store operation (see FIG. 9) in the store operation mode of the non-volatile memory circuit 16 of the first embodiment.

[0124] When the logical value of the output Q of Read_reg34 is different from the logical value of the sense amplifier output SAO of the sense amplifier 32, during the period of the N_short cycle, the logical value of the AC_MSK signal is set to "1", and the store operation is performed as described above.

[0125] First, during the period of the N_short cycle, the logical value of the AC_MSK signal becomes "1". In FIG. 12, the periods from timing t611 to t613 and from timing t615 to 617 correspond to the period of the N_short cycle. Since the logical value of the AC_MSK signal is "1", the logical sum of the OR circuit OR4 becomes "1". Here, since the exclusive logical sum of the XOR circuit XOR1 is "1" as described above, the logical product of the AND circuit AND7 becomes "1". Therefore, the tri-state drivers TSDRV1 and TSDRV2 are activated, and the output Q of Read_reg34 is stored in the MTJ elements MTJ1 and MTJ2.

[0126] When the period of the N_short cycle ends, immediately, the logical value of the AC_MSK signal becomes "0". The store operation is continued for a period of clock cycles corresponding to the difference between the N_long cycle and the N_short cycle (N_long cycle - N_short cycle).

[0127] Here, in the peripheral circuit 24 of the bit where "1" is set in AC_reg36, as described above, the tri-state drivers TSDRV1 and TSDRV2 are activated, and the output Q of Read_reg34 is stored in the MTJ elements MTJ1 and MTJ2.

[0128] On the other hand, in the peripheral circuit 24 of the bit where "0" is set in AC_reg36, the logical sum of the OR circuit OR4 becomes "0", the logical product of the AND circuit AND7 becomes "0", the logical sum of the OR circuit OR3 becomes "0", and the logical value of the TSEN signal becomes "0". Therefore, the tri-state drivers TSDRV1 and TSDRV2 are not activated, and the output Q of Read_reg34 is not stored in the MTJ elements MTJ1 and MTJ2.

[0129] Therefore, for the bits where '1' is set in AC_reg36, during the N_long cycle period, the output Q of Read_reg34 is stored in the MTJ elements MTJ1 and MTJ2. On the other hand, for the bits where '0' is set in AC_reg36, the output Q of Read_reg34 is stored in the MTJ elements MTJ1 and MTJ2 only during the N_shot cycle period.

[0130] When changing the position of the BSP, in other words, when changing the setting of the bits with a short storage time and the bits with a long storage time, it is only necessary to change the value set in AC_reg36. For example, for 8-bit data, to set the storage time of the lower 5 bits to a short time, set '11100000' in AC_reg36. After setting like this, when changing the storage time of the lower 2 bits to a short time due to a change in the application or the like, it is only necessary to set '11111100' in AC_reg36. Since the change of the value set in AC_reg36 can be performed by the above-described first step, the BSP can be dynamically changed during execution.

[0131] As described above, similar to the non-volatile memory circuit 16 of the first embodiment, in the non-volatile memory circuit 16 of the present embodiment, when the data held in the memory cell 21 is the same as the data stored in the MTJ elements MTJ1 and MTJ2, the store for writing the data held in the memory cell 21 to the MTJ elements MTJ1 and MTJ2 is not performed. Therefore, also in the non-volatile memory circuit 16 using the memory cell circuit 22 of the present embodiment, the power consumption required for writing the data held in the memory cell 21 to the MTJ elements MTJ1 and MTJ2 can be suppressed, and low power consumption can be realized.

[0132] Further, according to the non-volatile memory circuit 16 of the present embodiment, since the position of the BSP can be set and changed during operation with a simple configuration, more power consumption can be reduced.

[0133] In each of the above embodiments, an example of the non-volatile memory unit is the form using the MTJ elements MTJ1 and MTJ2, but the present form is not limited thereto. The non-volatile memory unit is not particularly limited as long as it is a memory unit in which the stored data does not disappear (non-volatile) even after the supply of the VVDD voltage is cut off by the power switch 14.

[0134] Also, in each of the above embodiments, an example of the first storage unit is the form using Read_reg34, but the first storage unit is not limited to this form. The first storage unit may be a register or a semiconductor memory circuit. Also, in each of the above forms, an example of the second storage unit is the form using the sense amplifier 32, but the second storage unit is not limited to this form. The second storage unit may be a semiconductor circuit having a function of detecting the potentials of the bit lines bit and bit_b when reading the data stored in the memory cell 21 and determining the logical value of the data read from the memory cell 21 based on the detected potential difference, and a function of storing the read data.

[0135] Also, in each of the above forms, the form of outputting the data held in the non-volatile memory circuit 16 of the non-volatile memory circuit group 15 to the internal circuit 18 has been described, but the present invention is not limited to this form, and the data held in the non-volatile memory circuit 16 of the non-volatile memory circuit group 15 may be output to the outside of the semiconductor integrated circuit 10.

[0136] Also, the configurations and operations of the semiconductor integrated circuit 10, the non-volatile memory circuit 16, etc. described in each of the above embodiments are examples, and it goes without saying that they can be changed according to the situation without departing from the gist of the present invention.

Explanation of Reference Numerals

[0137] 10 Semiconductor integrated circuit 12 Control circuit 14 Power switch 15 Non-volatile memory circuit group 16 Non-volatile memory circuit 20 Address Decoder 21 Memory Cell 22 Memory Cell Circuit 24 Peripheral Circuit 30 Write_reg 32 Sense Amplifier 34 Read_reg 36 AC Control Register (AC_reg) AND1~AND7 AND Circuit bit, bit_b Bit Lines d, d_b Memory Nodes Glb_WL m Global Word Line INV1, INV2, IV1~IV4 Inverters Local_WL m Word Line Local_LPG, Local_SR1, Local_SR2 Signal Lines MTJ1, MTJ2 MTJ Elements NOR1 NOR Circuit OR1~OR4 OR Circuits RstrTR1, RstrTR2, TR1, TR2, N1~N11 NMOS Transistors StrTR1, StrTR2, P1~P14 PMOS Transistors TSDRV1, TSDRV2 Tri-State Drivers XOR1 XOR Circuit

Claims

1. A memory cell for holding 1-bit data, A pair of bit lines for writing data to or reading data from the memory cell, A non-volatile memory unit for storing the data held by the memory cell, A write control unit that causes the data currently held by the memory cell to be stored in a first storage unit, causes the data currently stored in the non-volatile memory unit to be stored in a second storage unit, and when the data stored in the first storage unit is different from the data stored in the second storage unit, causes the data stored in the first storage unit to be written to the non-volatile memory unit via the pair of bit lines, and when the data stored in the first storage unit is the same as the data stored in the second storage unit, does not cause the data stored in the first storage unit to be written to the non-volatile memory unit; A semiconductor device comprising the above.

2. The second storage unit detects a potential difference between the pair of bit lines and outputs, to the first storage unit, a determination result of determining a logical value of the data read from the memory cell based on the potential difference. The semiconductor device according to claim 1.

3. The write control unit A first switch that is turned on when storing the data held by the memory cell in the non-volatile memory unit and is turned off when writing the data stored in the non-volatile memory unit to the memory cell, and connects the non-volatile memory unit and the second storage unit; A second switch that is turned off when storing the data held by the memory cell in the non-volatile memory unit and is turned on when writing the data stored in the non-volatile memory unit to the memory cell, and connects the non-volatile memory unit and the memory cell, and includes The semiconductor device according to claim 1 or claim 2.

4. The data read from the memory cell is stored in the first storage unit via the second storage unit. The semiconductor device according to any one of claims 1 to 3.

5. Further comprising a store time control unit that performs control to set a store time for storing the data held in the memory cell in the non-volatile memory unit to either a first time or a second time shorter than the first time. The semiconductor device according to any one of claims 1 to 4.

6. The store time control unit includes a setting unit in which different logical values are set for the first time and the second time, and stores the data held in the memory cell in the non-volatile memory unit according to the logical value provided in the setting unit and the logical value of a store time control signal that controls the first time and the second time. The semiconductor device according to claim 5.

7. The store time control unit performs control to set the first time when the data held in the memory cell is a predetermined upper bit among a plurality of bits of data, and performs control to set the second time when the data is a predetermined lower bit among the plurality of bits of data. The semiconductor device according to claim 5 or claim 6.

8. The non-volatile memory unit is a magnetic tunnel junction element. The semiconductor device according to any one of claims 1 to 7.

9. A memory cell that holds 1-bit data. A pair of bit lines for writing data to or reading data from the memory cell. A non-volatile memory unit that stores the data held by the memory cell. A first switch that connects the non-volatile memory unit and the bit line, which is turned on when storing the data held in the memory cell in the non-volatile memory unit and turned off when writing the data stored in the non-volatile memory unit to the memory cell. A second switch that is turned off when storing the data held in the memory cell in the non-volatile memory unit and is turned on when writing the data stored in the non-volatile memory unit to the memory cell, and the non-volatile memory unit and the memory cell are connected Memory cell circuit.

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