Semiconductor device

Abstract

This semiconductor device, which can provide a semiconductor device that uses a gallium nitride layer, comprises: an amorphous glass substrate; an oriented metal layer having crystalline orientation and being provided on the amorphous glass substrate; a first gallium nitride layer having a first type of conductivity, which is disposed on the oriented metal layer; a second gallium nitride layer having a second type of conductivity, which is connected to the first gallium nitride layer on the first gallium nitride layer, which has a higher conductivity than the first gallium nitride layer, and which comprises, facing each other, a source side second gallium nitride layer and a drain side second gallium nitride layer; a gate electrode facing the first gallium nitride layer; and a gate insulating layer between the first gallium nitride layer and the gate electrode. In cross-sectional view, the gate insulating layer is located between the source side second gallium nitride layer and the drain side second gallium nitride layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using gallium nitride.

Background Art

[0002] Gallium nitride (GaN) is a direct-transition semiconductor with a large bandgap. Utilizing this characteristic of gallium nitride, light-emitting diodes (LEDs) using gallium nitride have already been put into practical use. Gallium nitride has the characteristics of high electron saturation mobility and high breakdown voltage. In recent years, taking advantage of these characteristics of gallium nitride, the development of transistors (semiconductor devices) for applications such as high-frequency power devices has been underway. Generally, the gallium nitride layer used in a light-emitting diode or a transistor is formed on a sapphire substrate at a high temperature of 800°C to 1000°C using MOCVD (Metal Organic Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy).

[0003] Furthermore, in recent years, as next-generation display devices, the development of so-called micro-LED display devices or mini-LED display devices in which minute light-emitting diode chips are mounted within pixels of a circuit board has been underway. Micro-LED display devices or mini-LED display devices have high efficiency, high brightness, and high reliability. Such micro-LED display devices or mini-LED display devices are manufactured by transferring LED chips onto a backplane on which transistors using an oxide semiconductor or low-temperature polysilicon or the like are formed (see, for example, Patent Document 1). On the other hand, a method of forming a transistor and a light-emitting diode containing gallium nitride on the same substrate has also been studied (see, for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] The manufacturing method of a micro-LED display device by transferring an LED chip has a high manufacturing cost, and it is difficult to manufacture a micro-LED display device at a low cost. If a transistor using gallium nitride can be formed together with a light-emitting diode on a large-area substrate such as an amorphous glass substrate, the manufacturing cost can be reduced. However, as described above, since the gallium nitride layer is formed at a high temperature, it is difficult to directly form a transistor including gallium nitride on an amorphous glass substrate.

[0006] One embodiment of the present invention aims to provide a semiconductor device using a gallium nitride layer in view of the above problems.

Means for Solving the Problems

[0007] A semiconductor device according to an embodiment of the present invention includes an amorphous glass substrate, an orientation metal layer provided on the amorphous glass substrate and having crystal orientation, a first gallium nitride layer of a first conductivity type provided on the orientation metal layer, a second gallium nitride layer of a second conductivity type including a source-side second gallium nitride layer and a drain-side second gallium nitride layer that are connected to the first gallium nitride layer on the first gallium nitride layer and have higher conductivity than the first gallium nitride layer and face each other, a gate electrode facing the first gallium nitride layer, and a gate insulating layer between the first gallium nitride layer and the gate electrode, and the gate insulating layer is located between the source-side second gallium nitride layer and the drain-side second gallium nitride layer in a cross-sectional view.

[0008] A semiconductor device according to an embodiment of the present invention includes an amorphous glass substrate, an oriented metal layer provided on the amorphous glass substrate and including a separated first oriented metal layer and a second oriented metal layer, the oriented metal layer having crystal orientation, a first gallium nitride layer of a first conductivity type provided on the oriented metal layer, a second gallium nitride layer of a second conductivity type provided on the oriented metal layer and connected to the first gallium nitride layer, the second gallium nitride layer having higher conductivity than the first gallium nitride layer and including a source-side second gallium nitride layer and a drain-side second gallium nitride layer facing each other, a gate electrode facing the first gallium nitride layer, and a gate insulating layer between the first gallium nitride layer and the gate electrode, and a portion separating the first oriented metal layer and the second oriented metal layer crosses between the source-side second gallium nitride layer and the drain-side second gallium nitride layer.

[0009] A semiconductor device according to an embodiment of the present invention includes an amorphous glass substrate, an oriented metal layer provided on the amorphous glass substrate and having crystal orientation, an oriented insulating layer provided on the oriented metal layer, a first gallium nitride layer of a first conductivity type provided on the oriented insulating layer, a second gallium nitride layer of a second conductivity type provided on the oriented insulating layer and connected to the first gallium nitride layer, the second gallium nitride layer having higher conductivity than the first gallium nitride layer and including a source-side second gallium nitride layer and a drain-side second gallium nitride layer facing each other, a gate electrode facing the first gallium nitride layer, and a gate insulating layer between the first gallium nitride layer and the gate electrode.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are naturally included in the scope of the present invention. The drawings may be schematically represented in terms of the width, thickness, shape, etc. of each part compared to the actual aspect in order to make the explanation clearer. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, for elements that are the same as those described above in the previously presented figures, an alphabet may be appended after the same reference numeral, and detailed explanations may be omitted as appropriate.

[0012] In each embodiment of the present invention, the direction from the substrate toward the gate electrode is referred to as up or upward. Conversely, the direction from the gate electrode toward the substrate is referred to as down or downward. Thus, for the sake of convenience in explanation, the terms up or downward are used for explanation. However, for example, the substrate and the gate electrode may be arranged such that their vertical relationship is reversed from that shown in the drawing. In the following description, for example, the expression a gate electrode on a substrate merely explains the vertical relationship between the substrate and the gate electrode as described above, and other members may be arranged between the substrate and the gate electrode. Up or downward means the stacking order in a structure in which a plurality of layers are stacked. When expressing a pixel electrode above a transistor, the positional relationship may be such that the transistor and the pixel electrode do not overlap in plan view. On the other hand, when expressing a pixel electrode directly above the transistor in the vertical direction, it means the positional relationship in which the transistor and the pixel electrode overlap in plan view.

[0013] In this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", "α includes one selected from the group consisting of A, B, and C", etc. do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0014] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0015] [1. First Embodiment] [1-1. Configuration of Semiconductor Device 10] With reference to FIG. 1, a semiconductor device 10 according to the first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 10 includes a substrate 100, an alignment metal layer 110, a first gallium nitride layer 120, a gate electrode 130, a gate insulating layer 140, a second gallium nitride layer 150 (151, 153), and electrodes 160 (161, 163).

[0016] The substrate 100 is an amorphous substrate. For example, the substrate 100 is an amorphous glass substrate. However, the substrate 100 may be a resin substrate. As the resin substrate, a flexible substrate such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate is used.

[0017] The alignment metal layer 110 is provided on the substrate 100. The alignment metal layer 110 has crystal orientation (for example, c-axis orientation). Specifically, the surface of the alignment metal layer 110 is a surface having six-fold rotational symmetry. For example, the alignment metal layer 110 has a (0001) plane in a hexagonal close-packed structure or a (111) plane in a face-centered cubic structure. As the alignment metal layer 110, for example, titanium or aluminum is used. Since the alignment metal layer 110 has the above characteristics, when a gallium nitride layer is grown on the alignment metal layer 110, a gallium nitride layer having high crystallinity can be obtained. For example, when the alignment metal layer 110 is c-axis oriented with respect to the substrate 100, a c-axis oriented gallium nitride layer grows on the alignment metal layer 110.

[0018] The alignment metal layer 110 is formed, for example, by sputtering. The film formation method of the alignment metal layer 110 may be other physical vapor deposition methods (Physical Vapor Deposition: PVD method). For example, the alignment metal layer 110 may be formed by vacuum evaporation or electron beam evaporation. An underlying insulating layer may be provided between the substrate 100 and the alignment metal layer 110. As the underlying insulating layer, a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, an aluminum nitride layer, and a laminate thereof are used. For example, a laminate of [silicon nitride layer / silicon oxide layer / silicon nitride layer] may be used as the underlying insulating layer.

[0019] The first gallium nitride layer 120 is in contact with the orientation metal layer 110 from above the orientation metal layer 110. The first gallium nitride layer 120 is formed, for example, by a sputtering method. The crystal growth of the first gallium nitride layer 120 is controlled by the orientation metal layer 110. As a result, the first gallium nitride layer 120 has a crystallinity (or orientation) that reflects the crystallinity (or orientation) of the orientation metal layer 110. As described above, when the orientation metal layer 110 is c-axis oriented, a c-axis oriented first gallium nitride layer 120 is obtained.

[0020] The first gallium nitride layer 120 is, for example, a p-type gallium nitride layer. In this case, as the first gallium nitride layer 120, for example, a gallium nitride layer doped with magnesium, zinc, cadmium, beryllium, or selenium is used.

[0021] The gate electrode 130 is provided on the first gallium nitride layer 120 and faces the first gallium nitride layer 120. A gate insulating layer 140 is provided between the first gallium nitride layer 120 and the gate electrode 130. The gate insulating layer 140 is in contact with each of the first gallium nitride layer 120 and the gate electrode 130. As the gate electrode 130, a general metal is used. For example, as the gate electrode 130, aluminum, titanium, platinum, nickel, tantalum, and alloys thereof are used in a single layer or in a stacked manner. As the gate insulating layer 140, a metal oxide, a metal nitride, or an organic material is used. For example, as the gate insulating layer 140, a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, an aluminum nitride layer, gallium oxide, titanium oxide, titanium nitride, and a laminate thereof are used. When the semiconductor device 10 is configured to use a Schottky barrier at the interface between the first gallium nitride layer 120 and the gate electrode 130, the gate insulating layer 140 may be omitted.

[0022] The second gallium nitride layer 150 is in contact with the first gallium nitride layer 120 from above the first gallium nitride layer 120. The second gallium nitride layer 150 includes a source-side second gallium nitride layer 151 provided on the source side of the semiconductor device 10 and a drain-side second gallium nitride layer 153 provided on the drain side of the semiconductor device 10. The source-side second gallium nitride layer 151 and the drain-side second gallium nitride layer 153 are separated and opposed to each other, and a gate electrode 130 is provided therebetween. The conductivity of the second gallium nitride layer 150 is higher than that of the first gallium nitride layer 120. That is, the resistivity of the second gallium nitride layer 150 is lower than the resistivity of the first gallium nitride layer 120.

[0023] The second gallium nitride layer 150 is formed by a sputtering method in the same manner as the first gallium nitride layer 120. The crystal growth of the second gallium nitride layer 150 is controlled by the first gallium nitride layer 120. As a result, the second gallium nitride layer 150 has a crystallinity (or orientation) that reflects the crystallinity (or orientation) of the first gallium nitride layer 120. As described above, when the first gallium nitride layer 120 is c-axis oriented, a c-axis oriented second gallium nitride layer 150 is obtained.

[0024] The second gallium nitride layer 150 is, for example, an n-type gallium nitride layer. In this case, as the second gallium nitride layer 150, for example, a gallium nitride layer doped with silicon or germanium is used.

[0025] In this embodiment, a configuration in which the first gallium nitride layer 120 has a p-type conductivity type and the second gallium nitride layer 150 has an n-type conductivity type is illustrated, but the present invention is not limited to this configuration. The first gallium nitride layer 120 may have an n-type conductivity type and the second gallium nitride layer 150 may have a p-type conductivity type. As an expression including the above two configurations, there is a case where the first gallium nitride layer 120 has a first conductivity type and the second gallium nitride layer 150 has a second conductivity type.

[0026] As will be described in detail later, the second gallium nitride layer 150 is formed by processing a matrix gallium nitride layer formed over the entire surface. The gate insulating layer 140 and the gate electrode 130 are provided in a region where the matrix gallium nitride layer has been removed by the processing of the second gallium nitride layer 150. Accordingly, the gate insulating layer 140 and the gate electrode 130 are positioned between the second gallium nitride layers 150 (in the case of FIG. 1, the source-side second gallium nitride layer 151 and the drain-side second gallium nitride layer 153) facing each other in a cross-sectional view. In other words, in a cross-sectional view, the distance h1 from the upper surface of the substrate 100 to the upper surface of the gate insulating layer 140 is smaller than the distance h2 from the upper surface of the substrate 100 to the upper surface of the second gallium nitride layer 150. In other words, in a cross-sectional view, a line segment 159 connecting the upper surface 155 of the source-side second gallium nitride layer 151 and the upper surface 157 of the drain-side second gallium nitride layer 153 crosses the gate electrode 130 or the gate insulating layer 140. In FIG. 1, the line segment 159 crosses the gate insulating layer 140.

[0027] Since the first gallium nitride layer 120 and the second gallium nitride layer 150 are formed by a sputtering method, process gas used in the sputtering process remains in these gallium nitride layers. For example, when argon gas is used in the sputtering process for forming the first gallium nitride layer 120 and the second gallium nitride layer 150, these gallium nitride layers contain argon. The argon can be detected, for example, by an analysis method such as secondary ion mass spectrometry (SIMS) for these gallium nitride layers.

[0028] The electrode 160 is in contact with the second gallium nitride layer 150 from above the second gallium nitride layer 150. The electrode 160 includes a source-side electrode 161 provided on the source side of the semiconductor device 10 and a drain-side electrode 163 provided on the drain side of the semiconductor device 10. The source-side electrode 161 is connected to the source-side second gallium nitride layer 151. The drain-side electrode 163 is connected to the drain-side second gallium nitride layer 153. As the electrode 160, a general metal is used. For example, as the electrode 160, aluminum, titanium, platinum, nickel, tantalum, and alloys thereof are used in a single layer or in a stacked layer.

[0029] When a predetermined voltage (ON voltage) is supplied to the gate electrode 130, carriers are generated in the first gallium nitride layer 120 (a channel is formed) in the vicinity of the interface between the first gallium nitride layer 120 and the gate insulating layer 140. In this state, when a potential difference is applied between the source-side second gallium nitride layer 151 and the drain-side second gallium nitride layer 153, a current flows from the source-side second gallium nitride layer 151 to the drain-side second gallium nitride layer 153 through the channel.

[0030] [1-2. Manufacturing method of the semiconductor device 10] An oriented metal layer 110 is formed on a substrate 100 which is an amorphous glass substrate. As described above, the oriented metal layer 110 is formed, for example, by a sputtering method. A first gallium nitride layer 120 and a second gallium nitride layer 150 are formed on the oriented metal layer 110. These gallium nitride layers are formed, for example, by a sputtering method. The formation of the oriented metal layer 110, the first gallium nitride layer 120, and the second gallium nitride layer 150 is preferably carried out continuously. For example, the formation of these layers may be carried out while maintaining a vacuum in a sputtering apparatus equipped with a plurality of chambers for forming each layer. By forming the above layers in this way, contamination at the interface between the oriented metal layer 110 and the first gallium nitride layer 120 and at the interface between the first gallium nitride layer 120 and the second gallium nitride layer 150 can be reduced, and defects in the first gallium nitride layer 120 and the second gallium nitride layer 150 can be reduced. As a result, a first gallium nitride layer 120 and a second gallium nitride layer 150 having good crystallinity can be obtained.

[0031] Subsequently, as shown in FIG. 1, the second gallium nitride layer 150 formed in the region where the gate electrode 130 and the gate insulating layer 140 are later provided is removed, and the first gallium nitride layer 120 in the region is exposed.

[0032] Subsequently, the gate insulating layer 140 and the gate electrode 130 are formed. The gate insulating layer 140 and the gate electrode 130 are formed on each of the first gallium nitride layer 120 and the second gallium nitride layer 150. Thereafter, as shown in FIG. 1, the gate insulating layer 140 and the gate electrode 130 are patterned. Subsequently, the electrode 160 is formed over the entire surface and patterned as shown in FIG. 1.

[0033] As described above, since the formation of the oriented metal layer 110, the first gallium nitride layer 120, and the second gallium nitride layer 150 is carried out continuously, a first gallium nitride layer 120 and a second gallium nitride layer 150 having good crystallinity can be obtained. As a result, good electrical characteristics of the semiconductor device 10 can be obtained.

[0034] In the above description, a manufacturing method in which the electrode 160 is formed after the patterns of the gate insulating layer 140 and the gate electrode 130 are formed has been exemplified, but the manufacturing method is not limited thereto. For example, the electrode 160 may be formed immediately after the second gallium nitride layer 150 is formed, and the patterns of the gate insulating layer 140 and the gate electrode 130 may be formed after the patterning of the electrode 160 and the patterning of the second gallium nitride layer 150 are performed.

[0035] [1-3. Film formation methods for the first gallium nitride layer 120 and the second gallium nitride layer 150] The film formation of the gallium nitride layer using sputtering will be described.

[0036] In the vacuum chamber of the sputtering apparatus, a substrate 100 such as an amorphous glass substrate is disposed at a position facing the gallium nitride target. The composition ratio of gallium nitride in the gallium nitride target is preferably 0.7 or more and 2 or less in terms of the ratio of gallium to nitrogen. In addition to the sputtering gas (such as argon or krypton), nitrogen gas is supplied to the vacuum chamber. In that case, the composition ratio of gallium nitride in the gallium nitride target is preferably a ratio in which gallium is more than nitrogen. For example, nitrogen may be supplied by a nitrogen radical supply source. The sputtering power supply may be any of a DC power supply, an RF power supply, or a pulsed DC power supply.

[0037] In the vacuum chamber, the substrate 100 may be heated. For example, the substrate 100 may be heated at a temperature of room temperature or higher and less than 600 °C, preferably 100 °C or higher and 400 °C or lower. With this heating temperature, a heat treatment can be applied to an amorphous glass substrate with low heat resistance. This heating temperature is lower than the heating temperature of the metalorganic chemical vapor deposition method (MOCVD) or the hydride vapor phase epitaxy method (HVPE).

[0038] After the inside of the vacuum chamber in which the substrate 100 is disposed is sufficiently evacuated, a sputtering gas is supplied. By applying a voltage between the substrate 100 and the gallium nitride target at a predetermined pressure to generate a plasma, a gallium nitride layer is formed.

[0039] The configuration of the sputtering apparatus or the sputtering conditions can be appropriately changed. If an aluminum gallium nitride target is used instead of the gallium nitride target, an aluminum gallium nitride layer can be formed.

[0040] [2. Second Embodiment] With reference to FIGS. 2A and 2B, a semiconductor device 10A according to a second embodiment of the present invention will be described. The semiconductor device 10A is similar to the semiconductor device 10 according to the first embodiment. In the following description, the description of the configuration of the semiconductor device 10A that is the same as that of the semiconductor device 10 of the first embodiment will be omitted, and mainly the differences from the semiconductor device 10 will be described. In the following description, when describing the same configuration as that of the first embodiment, reference is made to FIG. 1, and the reference numerals shown in FIG. 1 are appended with the alphabet "A" for description.

[0041] [2-1. Configuration of Semiconductor Device 10A] As shown in FIG. 2A, the orientation metal layer 110A includes a first orientation metal layer 111A, a second orientation metal layer 113A, and a third orientation metal layer 115A. The first orientation metal layer 111A, the second orientation metal layer 113A, and the third orientation metal layer 115A are separated from each other by a separation portion 119A. In the present embodiment, in the separation portion 119A, a first gallium nitride layer 120A is embedded in a region where the pattern of the orientation metal layer 110A does not exist. Even when an ON voltage is supplied to the gate electrode 130A, the first gallium nitride layer 120A in the separation portion 119A has a higher resistance than the orientation metal layer 110A.

[0042] As shown in FIG. 2B, the separation portion 119A extends in the D3 direction intersecting the direction of the current flowing in the semiconductor device 10A. The separation portion 119A crosses the first gallium nitride layer 120A in the D3 direction between the source-side second gallium nitride layer 151A and the drain-side second gallium nitride layer 153A. That is, the separation portion 119A suppresses the current supplied to the source-side second gallium nitride layer 151A from flowing to the drain-side second gallium nitride layer 153A through the alignment metal layer 110A.

[0043] Referring to FIG. 2B, in plan view, the first alignment metal layer 111A overlaps the source-side second gallium nitride layer 151A. Similarly, in plan view, the second alignment metal layer 113A overlaps the drain-side second gallium nitride layer 153A. Referring to FIGS. 2A and 2B, in plan view, the third alignment metal layer 115A overlaps the first gallium nitride layer 120A in the region between the source-side second gallium nitride layer 151A and the drain-side second gallium nitride layer 153A. More specifically, in plan view, the region (channel region 129A) where the first gallium nitride layer 120A and the gate electrode 130A overlap is provided inside the third alignment metal layer 115A.

[0044] As described above, the configuration in which the first gallium nitride layer 120A is provided in the separation portion 119A is exemplified, but the present embodiment is not limited to this configuration. An insulator such as a metal oxide may be embedded in the separation portion 119A so that the first alignment metal layer 111A, the second alignment metal layer 113A, and the third alignment metal layer 115A are insulated from each other. Alternatively, the alignment metal layer 110A in the region corresponding to the separation portion 119A may be oxidized to increase its resistance or insulate it.

[0045] In the present embodiment, the second gallium nitride layer 150A is formed so as to be embedded in the first gallium nitride layer 120A, and a configuration in which the upper surface 121A of the first gallium nitride layer 120A and the upper surfaces 155A and 157A of the second gallium nitride layer 150A are substantially at the same position in the D2 direction is exemplified, but the present embodiment is not limited to this configuration. For example, as shown in FIG. 1, a configuration in which the second gallium nitride layer 150 is provided above the first gallium nitride layer 120 may be employed.

[0046] As described in the first embodiment, since the oriented metal layer 110A is provided under the first gallium nitride layer 120A, the first gallium nitride layer 120A having good crystallinity can be obtained. On the other hand, since the oriented metal layer 110A has higher conductivity than the first gallium nitride layer 120A, a leakage current may flow from the source-side second gallium nitride layer 151A to the drain-side second gallium nitride layer 153A through the oriented metal layer 110A. Even in such a case, at least the first oriented metal layer 111A and the second oriented metal layer 113A are separated by the separation portion 119A, so that the leakage current can be suppressed.

[0047] As described above, in plan view, since the first oriented metal layer 111A and the source-side second gallium nitride layer 151A overlap, the source-side second gallium nitride layer 151A having good crystallinity can be obtained. Similarly, in plan view, since the second oriented metal layer 113A and the drain-side second gallium nitride layer 153A overlap, the drain-side second gallium nitride layer 153A having good crystallinity can be obtained. Similarly, in plan view, since the third oriented metal layer 115A and the first gallium nitride layer 120A corresponding to the channel region 129A overlap, the first gallium nitride layer 120A having good crystallinity in the channel region 129A can be obtained.

[0048] [2-2. Modification of the semiconductor device 10A] Figs. 3 and 4 show a modification of the semiconductor device 10A according to the second embodiment. In the example shown in Fig. 3, only one separation portion 119A is provided between the first oriented metal layer 111A and the second oriented metal layer 113A. The separation portion 119A is provided between the gate electrode 130A and the drain-side second gallium nitride layer 153A in plan view, and the first oriented metal layer 111A overlaps the source-side second gallium nitride layer 151A and the gate electrode 130A. By providing the separation portion 119A at the above position, the first gallium nitride layer 120A having good crystallinity can be obtained in the channel region 129A. As a result, good electrical characteristics of the semiconductor device 10A can be obtained.

[0049] When only one separation part 119A is provided, the position of the separation part 119A is not limited to the above configuration. As described above, if the leakage current flowing from the source-side second gallium nitride layer 151A to the drain-side second gallium nitride layer 153A can be suppressed, the separation part 119A can be provided at any position.

[0050] In the example shown in FIG. 4, the number of separation parts 119A is larger than the number of separation parts 119 shown in FIG. 3. As shown in FIG. 4, the separation part 119A may be provided in a region overlapping with the channel region 129A, the source-side second gallium nitride layer 151A, and the drain-side second gallium nitride layer 153A. The separation part 119A may separate the alignment metal layer 110A in a lattice shape. Regarding the size, shape, and number of the separation parts 119A, it is possible to appropriately change them in the channel region 129A, directly below the electrode 160A, and the region between the channel region 129A and the electrode 160A. The positions where a plurality of separation parts 119A are provided may be equally spaced, or may be irregular. The crystallinity required for the first gallium nitride layer 120A and the interval between the separation parts 119A may be different according to the electrical specifications required for the semiconductor device 10A.

[0051] [3. Third Embodiment] With reference to FIG. 5, a semiconductor device 10B according to the third embodiment of the present invention will be described. The semiconductor device 10B is similar to the semiconductor device 10A according to the second embodiment. In the following description, among the configurations of the semiconductor device 10B, mainly the points different from the semiconductor device 10A will be described. In the following description, when describing the same configuration as the above embodiment, refer to FIG. 1 and describe it by attaching the alphabet "B" after the reference numeral shown in FIG. 1.

[0052] [3-1. Configuration of Semiconductor Device 10B] As shown in FIG. 5, an oriented metal layer 110B and a gate electrode 130B are provided on a substrate 100B. The oriented metal layer 110B and the gate electrode 130B are separated by a separation portion 119B. A second gallium nitride layer 150B is provided on the oriented metal layer 110B. A gate insulating layer 140B is provided on the gate electrode 130B. The gate insulating layer 140B is provided so as to fill the separation portion 119B. A first gallium nitride layer 120B is provided on the gate insulating layer 140B and the second gallium nitride layer 150B. The second gallium nitride layer 150B is in contact with the oriented metal layer 110B. The gate insulating layer 140B is in contact with the gate electrode 130B. The first gallium nitride layer 120B is in contact with the second gallium nitride layer 150B and the gate insulating layer 140B. In other words, the gate electrode 130B and the gate insulating layer 140B are provided between the first gallium nitride layer 120B and the substrate 100B. The second gallium nitride layer 150B is provided between the oriented metal layer 110B and the first gallium nitride layer 120B.

[0053] In this embodiment, the gate electrode 130B and the gate insulating layer 140B have the same crystal orientation as the oriented metal layer 110B. The gate electrode 130B may be the same layer as the oriented metal layer 110B. That is, the gate electrode 130B and the oriented metal layer 110B may have the same material and film thickness.

[0054] According to the semiconductor device 10B of this embodiment, since the separation portion 119B is provided between the oriented metal layer 110B and the source-side second gallium nitride layer 151B, leakage current can be suppressed in the same manner as the semiconductor device 10A of the second embodiment. If the gate electrode 130B is formed of the same layer as the oriented metal layer 110B, the process for forming the gate electrode can be omitted.

[0055] [4. Fourth Embodiment] Referring to FIG. 6, a semiconductor device 10C according to a fourth embodiment of the present invention will be described. The semiconductor device 10C is similar to the semiconductor device 10B according to the third embodiment. In the following description, among the configurations of the semiconductor device 10C, mainly the points different from the semiconductor device 10B will be described. In the following description, when describing the same configuration as in the above embodiment, refer to FIG. 1 and add the alphabet "C" after the reference numeral shown in FIG. 1 for the description.

[0056] [4-1. Configuration of Semiconductor Device 10C] As shown in FIG. 6, a gallium nitride layer 170C is provided between the gate electrode 130C and the gate insulating layer 140C. The conductivity of the gallium nitride layer 170C is higher than that of the gallium nitride layer 120C. That is, the gallium nitride layer 170C has a lower resistance than the gallium nitride layer 120C. The conductivity of the gallium nitride layer 170C is higher than that of the gallium nitride layer 150C. That is, the gallium nitride layer 170C has a lower resistance than the gallium nitride layer 150C.

[0057] When the gate electrode 130C is formed in the same layer as the oriented metal layer 110C, its film thickness may be limited. For example, in order to obtain an oriented metal layer 110C having good orientation, an upper limit value may be provided for the film thickness of the oriented metal layer 110C. When the upper limit of the film thickness of the oriented metal layer 110C is limited, the electrical resistance of the gate electrode 130C is also limited. Therefore, it may not be possible to obtain the characteristics required for circuit operation.

[0058] In such a case, since the gallium nitride layer 170C is provided on the gate electrode 130C, the laminated structure of the gate electrode 130C and the gallium nitride layer 170C can be used as a gate electrode. Therefore, the electrical resistance of the gate electrode of the laminated structure can be reduced.

[0059] [5. Fifth Embodiment] Referring to FIG. 7, a semiconductor device 10D according to a fifth embodiment of the present invention will be described. The semiconductor device 10D is similar to the semiconductor device 10A according to the second embodiment. In the following description, among the configurations of the semiconductor device 10D, mainly the differences from the semiconductor device 10A will be described. In the following description, when describing the same configurations as those in the above embodiments, reference is made to FIG. 1, and the description is made by adding the alphabet "D" after the reference numerals shown in FIG. 1.

[0060] [5-1. Configuration of Semiconductor Device 10D] As shown in FIG. 7, the first gallium nitride layer 120D provided on the third oriented metal layer 115D is patterned. The first oriented metal layer 111D and the second oriented metal layer 113D are provided in the region where the first gallium nitride layer 120D is removed. A second gallium nitride layer 150D is provided on the first oriented metal layer 111D and the second oriented metal layer 113D. The first gallium nitride layer 120D is in contact with the third oriented metal layer 115D. The source-side second gallium nitride layer 151D is in contact with the first oriented metal layer 111D. The drain-side second gallium nitride layer 153D is in contact with the second oriented metal layer 113D.

[0061] As described above, since both the first gallium nitride layer 120D and the second gallium nitride layer 150D are in contact with the oriented metal layer 110D, a gallium nitride layer having good crystallinity can be obtained.

[0062] [5-2. Modification Example of Semiconductor Device 10D] Modification examples of the semiconductor device 10D are shown in FIGS. 8 to 10. In the following modification examples, the same effects as those of the above semiconductor device 10D can be obtained.

[0063] In the modification shown in FIG. 8, the first gallium nitride layer 120D is riding on the second gallium nitride layer 150D. That is, the first gallium nitride layer 120D is formed on a part of the upper surface of the second gallium nitride layer 150D. For example, after forming the orientation metal layer 110D, first the second gallium nitride layer 150D is formed, and then the first gallium nitride layer 120D is formed, whereby the structure shown in FIG. 8 can be obtained.

[0064] In the modification shown in FIG. 9, similar to FIG. 8, the first gallium nitride layer 120D is formed on a part of the upper surface of the second gallium nitride layer 150D. On the other hand, different from FIG. 8, in the region corresponding to the third orientation metal layer 115D, a concave portion is formed on the upper surface of the first gallium nitride layer 120D. The gate insulating layer 140D and the gate electrode 130D are provided in the concave portion.

[0065] In the modification shown in FIG. 10, the second gallium nitride layer 150D is riding on the first gallium nitride layer 120D. That is, the second gallium nitride layer 150D is formed on a part of the upper surface of the first gallium nitride layer 120D. For example, after forming the orientation metal layer 110D, first the first gallium nitride layer 120D is formed, and then the second gallium nitride layer 150D is formed, whereby the structure shown in FIG. 10 can be obtained.

[0066] [6. Sixth Embodiment] Referring to FIG. 11, a semiconductor device 10E according to the sixth embodiment of the present invention will be described. The semiconductor device 10E is similar to the semiconductor device 10A according to the second embodiment. In the following description, among the configurations of the semiconductor device 10E, mainly the points different from the semiconductor device 10A will be described. In the following description, when describing the same configurations as those in the above embodiments, reference is made to FIG. 1, and the description is made by attaching the alphabet "E" after the reference numerals shown in FIG. 1.

[0067] [6-1. Configuration of Semiconductor Device 10E] As shown in FIG. 11, an orientation insulating layer 180E is provided between the orientation metal layer 110E and the first gallium nitride layer 120E. The orientation insulating layer 180E is in contact with the orientation metal layer 110E and the first gallium nitride layer 120E. The orientation insulating layer 180E has crystal orientation (for example, c-axis orientation). Specifically, the surface of the orientation insulating layer 180E is a surface having six-fold rotational symmetry. For example, the orientation insulating layer 180E has a (0001) plane in a hexagonal close-packed structure or a (111) plane in a face-centered cubic structure. As the orientation insulating layer 180E, for example, aluminum nitride, gallium oxide, titanium nitride, or titanium oxide is used. The orientation insulating layer 180E is formed by a sputtering method in the same manner as the orientation metal layer 110E. However, the orientation insulating layer 180E may be formed by other PVD methods or CVD methods.

[0068] Since the orientation insulating layer 180E is in contact with the orientation metal layer 110E, an orientation insulating layer 180E having better orientation can be obtained compared to the orientation insulating layer 180E formed on a layer having no orientation. Further, since the first gallium nitride layer 120E is in contact with the orientation insulating layer 180E, a first gallium nitride layer 120E having good crystallinity can be obtained. Further, since the orientation insulating layer 180E electrically insulates the orientation metal layer 110E and the first gallium nitride layer 120E, the leakage current flowing from the source-side second gallium nitride layer 151E to the drain-side second gallium nitride layer 153E through the orientation metal layer 110E can be suppressed. When the orientation insulating layer 180E is provided, the orientation metal layer 110E may be omitted.

[0069] [7. Seventh Embodiment] With reference to FIGS. 12 to 14, a display device 20J according to the seventh embodiment of the present invention will be described. FIG. 12 is a schematic diagram showing the configuration of a display device according to an embodiment of the present invention. FIG. 13 is a circuit diagram (pixel circuit) of a pixel of a display device according to an embodiment of the present invention. FIG. 14 is a cross-sectional view of a pixel of a display device according to an embodiment of the present invention.

[0070] [7-1. Outline of the Configuration of the Display Device 20J] FIG. 12 is a schematic diagram showing the configuration of a display device 20J according to an embodiment of the present invention. The display device 20J has a display unit 1020J, a drive circuit unit 1030J, and a terminal unit 1040J on a substrate 100J. The drive circuit unit 1030J is provided around the display unit 1020J and controls the display unit 1020J. The drive circuit unit 1030J includes, for example, a scanning drive circuit. The terminal unit 1040J is provided at an end of the substrate 100J and supplies signals and power from the outside to the display device 20J. The terminal unit 1040J includes, for example, a terminal 1041J. The terminal 1041J is connected to a flexible printed circuit board 1050J. A driver IC 1060J is provided on the flexible printed circuit board 1050J.

[0071] The display unit 1020J can display an image or video and includes a plurality of pixels 1021J arranged in a matrix. However, the arrangement of the plurality of pixels 1021J is not limited to a matrix. The plurality of pixels 1021J may be arranged, for example, in a staggered pattern.

[0072] [7-2. Configuration of Pixel 1021J] FIG. 13 is a circuit diagram (pixel circuit) of a pixel 1021J of a display device 20J according to an embodiment of the present invention. The pixel 1021J includes a first transistor 200J-1, a second transistor 200J-2, a light-emitting diode 300J, and a capacitive element 400J.

[0073] The first transistor 200J-1 functions as a selection transistor. That is, the conduction state of the first transistor 200J-1 is controlled by a scanning line 1110J. In the first transistor 200J-1, the gate, source, and drain are electrically connected to the scanning line 1110J, a signal line 1120J, and the gate of the second transistor 200J-2, respectively.

[0074] The second transistor 200J-2 functions as a driving transistor. That is, the second transistor 200J-2 controls the emission luminance of the light-emitting diode 300J. In the second transistor 200J-2, the gate, source, and drain are electrically connected to the drain of the first transistor 200J-1, the driving power supply line 1140J, and the anode (p-type electrode) of the light-emitting diode 300J, respectively.

[0075] One of the capacitive electrodes of the capacitive element 400J is electrically connected to the gate of the second transistor 200J-2 and the drain of the first transistor 200J-1. The other capacitive electrode of the capacitive element 400J is electrically connected to the driving power supply line 1140J.

[0076] The anode of the light-emitting diode 300J is connected to the drain of the second transistor 200J-2. The cathode (n-type electrode) of the light-emitting diode 300J is connected to the reference power supply line 1160J.

[0077] [7-3. Cross-sectional Structure of Display Device 20J] Referring to FIG. 14, the layer structure of the pixel 1021J will be described. In the description of FIG. 14, the first transistor 200J-1 and the second transistor 200J-2 are not particularly distinguished and are described as the transistor 200J.

[0078] FIG. 14 is a cross-sectional view of the pixel 1021J cut along the line A1-A2 shown in FIG. 12. As shown in FIG. 14, the display device 20J includes a substrate 100J, an underlayer 105J, an alignment metal layer 110J, a transistor 200J, a light-emitting diode 300J, a light-shielding wall 500J, a light-shielding layer 600J, an interlayer film 270J, a conductive layer 280J, and a transparent conductive layer 290J. The underlayer 105J, the alignment metal layer 110J, the transistor 200J, the light-emitting diode 300J, the light-shielding wall 500J, the interlayer film 270J, the conductive layer 280J, and the transparent conductive layer 290J are provided on the first surface 101J side of the substrate 100J. The light-shielding layer 600J is provided on the second surface 102J side opposite to the first surface 101J of the substrate 100J.

[0079] The substrate 100J is a support substrate for the transistor 200J and the light-emitting diode 300J. As the substrate 100J, an amorphous glass substrate or the like can be used as described above.

[0080] The underlayer 105J is provided on the substrate 100J. The underlayer 105J can prevent the diffusion of impurities from the substrate 100J or external impurities (e.g., moisture or sodium). As the underlayer 105J, for example, a silicon nitride layer, or a laminate of a silicon oxide layer and a silicon nitride layer may be used.

[0081] The alignment metal layer 110J is provided on the underlayer 105J. By providing the alignment metal layer 110J, the crystallinity of the first gallium nitride layer 120J of the transistor 200J formed on the alignment metal layer 110J can be improved, and the crystallinity of the gallium nitride layer 310J of the light-emitting diode 300J formed on the alignment metal layer 110J can be improved. The first gallium nitride layer 120J and the gallium nitride layer 310J are formed in the same layer and have the same film thickness and physical properties.

[0082] When the alignment metal layer 110J contains a nitrogen compound (e.g., titanium nitride), the underlayer 105J may not be provided. Since the nitrogen contained in the nitrogen compound has a high electronegativity, it can trap the impurities contained in the substrate 100J.

[0083] The transistor 200J includes a first gallium nitride layer 120J, a gate electrode 130J, a gate insulating layer 140J, a source electrode 250J, and a drain electrode 260J. The source electrode 250J corresponds to, for example, the source-side second gallium nitride layer 151 and the source-side electrode 161 in FIG. 1. The drain electrode 260J corresponds to, for example, the drain-side second gallium nitride layer 153 and the drain-side electrode 163 in FIG. 1.

[0084] The first gallium nitride layer 120J is provided on the orientation metal layer 110J. As described above, since the first gallium nitride layer 120J is in contact with the orientation metal layer 110J, the crystal growth of the first gallium nitride layer 120J is controlled by the orientation metal layer 110J. As a result, the first gallium nitride layer 120J is c-axis oriented with respect to the substrate 100J.

[0085] The transistor 200J is a so-called MOS transistor, but may also be a HEMT (High Electron Mobility Transistor).

[0086] The light-emitting diode 300J is provided on the orientation metal layer 110J. The light-emitting diode 300J includes a gallium nitride layer 310J, an n-type semiconductor layer 320J, a light-emitting layer 330J, a p-type semiconductor layer 340J, an n-type electrode 350J, and a p-type electrode 360J.

[0087] The gallium nitride layer 310J is provided on the orientation metal layer 110J. As the gallium nitride layer 310J, for example, a gallium nitride layer or the like is used. Since the gallium nitride layer 310J is in contact with the orientation metal layer 110J, the crystal growth of the gallium nitride layer 310J is controlled by the orientation metal layer 110J. As a result, the gallium nitride layer 310J is c-axis oriented with respect to the substrate 100J.

[0088] The n-type semiconductor layer 320J is provided on the gallium nitride layer 310J. As the n-type semiconductor layer 320J, for example, a gallium nitride layer doped with silicon or the like is used.

[0089] The light-emitting layer 330J is provided on the n-type semiconductor layer 320J. As the light-emitting layer 330J, for example, a layer in which an indium gallium nitride layer and a gallium nitride layer are alternately laminated is used.

[0090] The p-type semiconductor layer 340J is provided on the light-emitting layer 330J. As the p-type semiconductor layer 340J, for example, a gallium nitride layer doped with magnesium is used.

[0091] The n-type electrode 350J and the p-type electrode 360J are provided on the n-type semiconductor layer 320J and the p-type semiconductor layer 340J, respectively. As the n-type electrode 350J, for example, a metal such as indium is used. As the p-type electrode 360J, for example, a metal such as palladium or gold is used.

[0092] The light-emitting diode 300J is a so-called micro-LED or mini-LED formed by sputtering on the substrate 100J which is an amorphous substrate, but is not limited thereto. A micro-LED is an LED with a size of 100 μm or less on one side. A mini-LED is an LED with a size of more than 100 μm on one side.

[0093] Although not shown, a protective layer may be provided as needed to cover the transistor 200J or the light-emitting diode 300J. As the protective layer, silicon nitride, or a laminate of a silicon oxide layer and a silicon nitride layer may be used.

[0094] The light-shielding wall 500J is provided between the transistor 200J and the light-emitting diode 300J. The light-shielding wall 500J can block the light emitted from the light-emitting diode 300J and prevent the transistor 200J from being irradiated with light. As the light-shielding wall 500J, for example, an acrylic resin (resin black) added with carbon can be used.

[0095] The light-shielding layer 600J is provided on the second surface 102J of the substrate 100J. The light-shielding layer 600J can block the light from the outside and prevent the transistor 200J from being irradiated with light. As the light-shielding layer 600J, for example, an acrylic resin (resin black) added with carbon may be used.

[0096] The interlayer film 270J is provided so as to cover the transistor 200J, the light-emitting diode 300J, and the light-shielding wall 500J. The interlayer film 270J can planarize the unevenness formed by the transistor 200J, the light-emitting diode 300J, and the light-shielding wall 500J. As the interlayer film 270J, for example, an organic insulating film such as an acrylic resin film or a polyimide resin film is used. The interlayer film 270J may be a single layer or a laminate. When the interlayer film 270J is a laminate, the interlayer film 270J may include not only an organic insulating layer but also an inorganic insulating layer such as a silicon oxide layer or a silicon nitride layer.

[0097] The conductive layer 280J and the transparent conductive layer 290J are provided on the interlayer film 270J. The conductive layer 280J is electrically connected to the gate electrode 130J through an opening provided in the interlayer film 270J. The transparent conductive layer 290J electrically connects the drain electrode 260J and the p-type electrode 360J through an opening provided in the interlayer film 270J. The light emitted from the light-emitting layer 330J of the light-emitting diode 300J passes through the transparent conductive layer 290J and is emitted to the outside. As the conductive layer 280J, for example, a laminate of aluminum and titanium (for example, Ti / Al / Ti) can be used. As the transparent conductive layer 290J, for example, a transparent conductive layer such as an indium tin oxide (ITO) film or an indium zinc oxide (IZO) film can be used.

[0098] Each of the embodiments described above as embodiments of the present invention can be implemented in appropriate combination as long as they do not conflict with each other. Based on each embodiment, those in which those skilled in the art appropriately add, delete, or change the design of components, or add, omit, or change the conditions of processes, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0099] Even other operational effects different from the operational effects brought about by each of the above-described embodiments, those that are obvious from the description of this specification or can be easily predicted by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0100] 10: Semiconductor device, 20J: Display device, 100: Substrate, 101J: First surface, 102J: Second surface, 105J: Underlayer, 110: Alignment metal layer, 111A: First alignment metal layer, 113A: Second alignment metal layer, 115A: Third alignment metal layer, 119A: Separation part, 120: First gallium nitride layer, 121A: Upper surface, 129A: Channel region, 130: Gate electrode, 140: Gate insulating layer, 150: Second gallium nitride layer, 151: Source-side second gallium nitride layer, 153: Drain-side second gallium nitride layer, 155: Upper surface, 157: Upper surface, 159: Line segment, 160: Electrode, 161: Source-side electrode, 163: Drain-side electrode, 170C: Third gallium nitride layer, 180E: Alignment insulating layer, 200J: Transistor, 250J: Source electrode, 260J: Drain electrode, 270J: Interlayer film, 280J: Conductive layer, 290J: Transparent conductive layer, 300J: Light-emitting diode, 310J: Gallium nitride layer, 320J: n-type semiconductor layer, 330J: Light-emitting layer, 340J: p-type semiconductor layer, 350J: n-type electrode, 360J: p-type electrode, 400J: Capacitor element, 500J: Light-shielding wall, 600J: Light-shielding layer, 1020J: Display part, 1021J: Pixel, 1030J: Driving circuit part, 1040J: Terminal part, 1041J: Terminal, 1050J: Flexible printed circuit board, 1110J: Scanning line, 1120J: Signal line, 1140J: Driving power supply line, 1160J: Reference power supply line

Claims

1. An amorphous glass substrate, An oriented metal layer provided on the amorphous glass substrate and having crystal orientation, A first gallium nitride layer of a first conductivity type provided on the oriented metal layer, A second gallium nitride layer of a second conductivity type, which is connected to the first gallium nitride layer on the first gallium nitride layer, has higher conductivity than the first gallium nitride layer, and includes a source-side second gallium nitride layer and a drain-side second gallium nitride layer facing each other, A gate electrode facing the first gallium nitride layer, And a gate insulating layer between the first gallium nitride layer and the gate electrode. The gate insulating layer is located between the source-side second gallium nitride layer and the drain-side second gallium nitride layer in a cross-sectional view. A semiconductor device.

2. In a cross-sectional view, the distance from the upper surface of the amorphous glass substrate to the upper surface of the gate insulating layer is smaller than the distance from the upper surface of the amorphous glass substrate to the upper surface of the second gallium nitride layer. The semiconductor device according to claim 1.

3. The first gallium nitride layer is in contact with the oriented metal layer, The second gallium nitride layer and the gate insulating layer are in contact with the first gallium nitride layer. The semiconductor device according to claim 1.

4. An amorphous glass substrate, An oriented metal layer provided on the amorphous glass substrate, including a separated first oriented metal layer and a second oriented metal layer, and having crystal orientation, A first gallium nitride layer of a first conductivity type provided on the oriented metal layer, A second gallium nitride layer of a second conductivity type, which is connected to the first gallium nitride layer on the oriented metal layer, has higher conductivity than the first gallium nitride layer, and includes a source-side second gallium nitride layer and a drain-side second gallium nitride layer facing each other, A gate electrode facing the first gallium nitride layer, It has a gate insulating layer between the first gallium nitride layer and the gate electrode. A semiconductor device in which a portion separating the first oriented metal layer and the second oriented metal layer crosses between the source-side second gallium nitride layer and the drain-side second gallium nitride layer.

5. In plan view, The first oriented metal layer overlaps with the source-side second gallium nitride layer. The semiconductor device according to claim 4, wherein the second oriented metal layer overlaps with the drain-side second gallium nitride layer.

6. The oriented metal layer further includes a third oriented metal layer separated from the first oriented metal layer and the second oriented metal layer. In plan view, The first oriented metal layer overlaps with the source-side second gallium nitride layer. The second oriented metal layer overlaps with the drain-side second gallium nitride layer. The semiconductor device according to claim 4, wherein the third oriented metal layer overlaps with the first gallium nitride layer between the source-side second gallium nitride layer and the drain-side second gallium nitride layer.

7. The first gallium nitride layer is in contact with the oriented metal layer. The semiconductor device according to claim 4, wherein the second gallium nitride layer is in contact with the first gallium nitride layer from above the first gallium nitride layer.

8. The gate electrode is provided between the first gallium nitride layer and the amorphous glass substrate and has crystal orientation. The semiconductor device according to claim 4, wherein the gate insulating layer has crystal orientation.

9. The semiconductor device according to claim 8, wherein the second gallium nitride layer is provided between the oriented metal layer and the first gallium nitride layer.

10. The second gallium nitride layer is in contact with the oriented metal layer. The gate insulating layer is in contact with the gate electrode, The semiconductor device according to claim 8, wherein the first gallium nitride layer is in contact with the gate insulating layer.

11. The semiconductor device according to claim 8, further comprising a third gallium nitride layer provided between the gate electrode and the gate insulating layer and having higher conductivity than the second gallium nitride layer.

12. The alignment metal layer is provided between the first alignment metal layer and the second alignment metal layer, and further includes a third alignment metal layer separated from the first alignment metal layer and the second alignment metal layer by a separation portion, The first gallium nitride layer is in contact with the third alignment metal layer, The source-side second gallium nitride layer is in contact with the first alignment metal layer, The drain-side second gallium nitride layer is in contact with the second alignment metal layer, The semiconductor device according to claim 4, wherein the gate electrode is provided on the first gallium nitride layer.

13. The semiconductor device according to claim 1, further comprising an alignment insulating layer provided between the alignment metal layer and the amorphous glass substrate.

14. An amorphous glass substrate, An alignment metal layer provided on the amorphous glass substrate and having crystal orientation, An alignment insulating layer provided on the alignment metal layer, A first gallium nitride layer of a first conductivity type provided on the alignment insulating layer, A second gallium nitride layer of a second conductivity type, which is connected to the first gallium nitride layer on the alignment insulating layer, has higher conductivity than the first gallium nitride layer, and includes a source-side second gallium nitride layer and a drain-side second gallium nitride layer facing each other, A gate electrode facing the first gallium nitride layer, And a gate insulating layer between the first gallium nitride layer and the gate electrode.

15. The semiconductor device according to claim 14, wherein the first gallium nitride layer is in contact with the alignment insulating layer.

16. The semiconductor device according to any one of claims 1 to 15, wherein the alignment metal layer has a plane with six-fold rotational symmetry.

17. The semiconductor device according to any one of claims 1 to 15, wherein the alignment metal layer has a (0001) plane in a hexagonal close-packed structure or a (111) plane in a face-centered cubic structure.

18. The semiconductor device according to any one of claims 13 to 15, wherein the alignment insulating layer has a plane with six-fold rotational symmetry.

19. The semiconductor device according to any one of claims 13 to 15, wherein the alignment insulating layer has a (0001) plane in a hexagonal close-packed structure or a (111) plane in a face-centered cubic structure.

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