Display device

Abstract

To provide a display device capable of improving its image quality.SOLUTION: The display device has a plurality of pixel blocks in a display area, and the pixel block includes one first circuit and a plurality of second circuits. The first circuit has a function of adding plural pieces of data supplied from a source driver. The second circuit includes a display element and a function of performing displaying according to the added data. One pixel is configured to include one second circuit and an element of the first circuit shared. Sharing the first circuit with the plurality of pixels improves a numerical aperture.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, their operating methods, or their manufacturing methods, as an example.

[0003] Note that in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. Also, storage devices, display devices, imaging devices, and electronic devices may have semiconductor devices.

Background Art

[0004] Techniques for constructing transistors using metal oxides formed on a substrate have attracted attention. For example, techniques for using transistors using zinc oxide or In-Ga-Zn-based oxides as switching elements for pixels of display devices are disclosed in Patent Document 1 and Patent Document 2.

[0005] Also, a storage device having a configuration in which a transistor with an extremely low off-current is used for a memory cell is disclosed in Patent Document 3.

[0006] ​​​​​In addition, various improvements and applications have been attempted in liquid crystal display devices. For example, a transparent display that performs display by field sequential operation is disclosed in Patent Document 4. [Prior Art Documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119674 [Patent Document 4] Japanese Patent Application Laid-Open No. 2018-21974 [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] In display devices, the resolution is increasing, and hardware that can perform display at a resolution of 8K4K (number of pixels: 7680×4320) or higher has been developed. In addition, the introduction of HDR (High Dynamic Range) display technology to improve image quality by adjusting brightness is also progressing.

[0009] To perform clear gradation display, it is desirable to widen the range of data potentials that can be supplied to the display elements. On the other hand, for example, the output voltage of a source driver for a liquid crystal display device is about 15V, and a high-output source driver must be used to supply a voltage higher than that to the display elements. A high-output source driver also has high power consumption, and it may be necessary to develop a new driver IC.

[0010] In addition, in order to display moving images more smoothly, it is required to increase the frame frequency. However, as the number of pixels increases, the horizontal period becomes shorter, making it difficult to increase the frame frequency. By realizing a configuration that makes it easy to increase the frame frequency, it becomes easier to apply to display devices using the field sequential liquid crystal method and the like.

[0011] While it is desired to solve the above problems, when the components of the pixel circuit increase, the aperture ratio decreases. Therefore, it is preferable to configure the pixel circuit with fewer elements.

[0012] Therefore, one of the objects of one aspect of the present invention is to provide a display device capable of improving image quality. Or, one of the objects is to provide a display device capable of supplying a voltage equal to or higher than the output voltage of the source driver to the display element. Or, one of the objects is to provide a display device capable of increasing the luminance of the displayed image. Or, one of the objects is to provide a display device capable of increasing the frame frequency. Or, one of the objects is to provide a display device capable of increasing the aperture ratio of the pixel. Or, one of the objects is to provide a display device with low power consumption.

[0013] Or, one of the objects is to provide a highly reliable display device. Or, one of the objects is to provide a novel display device or the like. Or, one of the objects is to provide a driving method for the above display device. Or, one of the objects is to provide a novel semiconductor device or the like.

[0014] Note that the description of these problems does not prevent the existence of other problems. Note that one Aspects are not required to solve all of these problems. Other problems will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0015] One aspect of the present invention relates to a display device capable of improving image quality.

[0016] One aspect of the present invention is a display device having a plurality of pixel blocks, the pixel blocks having a first circuit and a plurality of second circuits, the first circuit and the second circuits being electrically connected, the first circuit having a function of adding first data and second data to generate third data, and the second circuit having a function of holding the third data and a function of performing display according to the third data.

[0017] The first circuit has a first transistor, a second transistor, and a first capacitor element, one of the source or drain of the first transistor being electrically connected to one electrode of the first capacitor element, and the other electrode of the first capacitor element being electrically connectable to the other of the source or drain of the second transistor.

[0018] Furthermore, it has a third transistor, one of the source or drain of the third transistor being electrically connected to the other electrode of the first capacitor element, and the other of the source or drain of the first transistor and the other of the source or drain of the second transistor may be electrically connected.

[0019] The second circuit has a third transistor and a third circuit. One of the source or drain of the third transistor is electrically connected to one of the source or drain of the first transistor. The other of the source or drain of the third transistor is electrically connected to the third circuit, and the third circuit can have a display element. One of the source or drain is electrically connected to one of the source or drain of the first transistor. The other of the source or drain of the third transistor is electrically connected to the third circuit. The third circuit can have a display element.

[0020] The third circuit has a fourth transistor, a second capacitive element, and a light-emitting element that functions as a display element. The gate of the fourth transistor is electrically connected to the other of the source or drain of the third transistor. The other of the source or drain of the fourth transistor is electrically connected to one electrode of the light-emitting element. One electrode of the light-emitting element is electrically connected to one electrode of the second capacitive element. The other electrode of the second capacitive element is electrically connected to the gate of the fourth transistor. The gate of the fourth transistor is electrically connected to the other of the source or drain of the third transistor. The other of the source or drain of the fourth transistor is electrically connected to one electrode of the light-emitting element. One electrode of the light-emitting element is electrically connected to one electrode of the second capacitive element. The other electrode of the second capacitive element is electrically connected to the gate of the fourth transistor. It can be configured in this way.

[0021] Furthermore, it has a fifth transistor. One of the source or drain of the fifth transistor is electrically connected to one electrode of the light-emitting element. The other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the fourth transistor. The other of the source or drain of the fifth transistor may be electrically connected to one electrode of the second capacitive element. One of the source or drain of the fifth transistor is electrically connected to one electrode of the light-emitting element. The other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the fourth transistor. The other of the source or drain of the fifth transistor is electrically connected to one electrode of the second capacitive element. It may be electrically connected.

[0022] Alternatively, the third circuit has a liquid crystal element as a display element. One electrode of the liquid crystal element is electrically connected to one of the source or drain of the third transistor. It may be configured in this way. Furthermore, it has a third capacitive element. One electrode of the third capacitive element may be electrically connected to one electrode of the liquid crystal element. It may be electrically connected.

[0023] Furthermore, it may have a fourth circuit and a fifth circuit. The fourth circuit has a function of controlling the first circuit and the fifth circuit can have a function of controlling the second circuit.

[0024] The pixel block has a plurality of pixels, and any one of the plurality of pixels has a plurality of elements of the first circuit and the pixel having a plurality of elements of the first circuit may have a greater vertical length than other pixels.

[0025] The transistor included in the pixel block has a metal oxide in the channel formation region, and the metal oxide preferably contains In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

Advantages of the Invention

[0026] By using one aspect of the present invention, it is possible to provide a display device capable of improving image quality or a display device capable of supplying a voltage equal to or higher than the output voltage of the source driver to the display element. Or a display device capable of increasing the luminance of the displayed image can be provided. Or a display device capable of increasing the frame frequency can be provided. Or a display device capable of increasing the aperture ratio of the pixel can be provided.

[0027] Or a display device with low power consumption can be provided. Or a highly reliable display device can be provided. Or a novel display device or the like can be provided. Or a method of operating the above display device can be provided. Or a novel semiconductor device or the like can be provided ​​It can be used for.

Brief Description of Drawings

[0028]

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Embodiments for Carrying Out the Invention

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description content of the following embodiments. In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having the same function among different drawings. It will not be limited, and it can be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description content of the following embodiments. In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having the same function among different drawings. It will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description content of the following embodiments. In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having the same function among different drawings. It will not be limited, and it can be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description content of the following embodiments. In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having the same function among different drawings. Among the configurations of the invention described below, the same reference numerals are used for the same parts or parts having the same function among different drawings. It is used and the repeated description may be omitted. Note that the matching of the same elements constituting the figure may be appropriately omitted or changed between different drawings. There are cases where the matching may be appropriately omitted or changed between different drawings.

[0030] Also, even if an element is illustrated as a single element on the circuit diagram, if there is no functional inconvenience, the element may be composed of a plurality of elements. For example, transistors operating as switches may be connected in series or in parallel in some cases. Also, there are cases where capacitors are divided and arranged at a plurality of positions.

[0031] Also, there are cases where one conductor has a plurality of functions such as wiring, electrodes, and terminals, and in this specification, a plurality of names may be used for the same element. Also, even if it is illustrated on the circuit diagram that elements are directly connected, actually, there are cases where the elements are connected via a plurality of conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0032] (Embodiment 1) In this embodiment, a display device which is one aspect of the present invention will be described with reference to the drawings.

[0033] One aspect of the present invention is a display device having a plurality of pixel blocks in a display area. The pixel blocks have a first circuit and a plurality of second circuits electrically connected to the first circuit. The first circuit has a function of adding a plurality of data supplied from a source driver. Therefore, a voltage higher than the output of the source driver can be generated.

[0034] Also, the second circuit has a display element and has a function of performing display according to the added data. It is configured such that one pixel includes one second circuit and elements of a shared first circuit. The first circuit has more components (including wiring) and a larger occupied area than the second circuit. Therefore, by sharing the first circuit among a plurality of pixels, the aperture ratio can be improved.

[0035] FIG. 1 is a diagram for explaining a display device according to an aspect of the present invention. The display device includes a pixel block 12, a source driver 13, gate drivers 14a and 14b, and a circuit 15. Also, although an example in which two gate drivers are provided is shown, one gate driver may be used.

[0036] The display area is composed of a plurality of regularly arranged pixel blocks 12. The pixel block 1 2 has a circuit 11 and n (n is a natural number of 2 or more) circuits 10. The circuit 11 is electrically connected to each of the circuits 10. The circuit 11 and one circuit 10 function as one pixel. That is, the circuit 11 is configured to be shared among a plurality of pixels.

[0037] The circuit 10 has a function of adding second data to first data by capacitive coupling to generate third data. The circuit 10 has a display element and has a function of holding the third data and a function of performing display on the display element according to the third data.

[0038] The n circuits 10 included in one pixel block 12 can be arranged in the direction in which the source line extends (vertical direction). The larger the number of circuits 10, the more the elements of the circuit 11 can be dispersed in the occupied area of each pixel, thereby improving the aperture ratio.

[0039] The larger the number of circuits 10 included in the pixel block 12, the higher the aperture ratio, but the writing of image data Considering the time, it is preferable to arrange a plurality of pixel blocks per line. .

[0040] In the case of a display device with high resolution, it is necessary to perform writing in a short horizontal period. If the number of circuits 10 is too large, the capacitance of the wiring connecting circuit 11 and circuit 10 will increase, resulting in a defect that writing cannot be completed within the horizontal period. Therefore, it is preferable that the number of circuits 10 in the pixel block is set to an appropriate number considering a plurality of conditions such as the aperture ratio, resolution (horizontal period), and capacitance of the wiring connecting circuit 11 and circuit 10. When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000. When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000. When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000. When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000.

[0041] When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000. When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000. When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000. When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000. When it is desired to efficiently increase the aperture ratio, from the simulation results described later, n is 5 or more and 100 or less, preferably 10 or more and 50 or less, more preferably 20 or more and 40 or less. When n is within this range, it is estimated that the capacitance of the wiring connecting circuit 11 and circuit 10 is sufficiently small, so the influence of the horizontal period can be ignored. In addition, when a sufficient horizontal period can be ensured, n may be set to about 100 to 1000.

[0042] Fig. 2 shows a specific example of pixel block 12. Pixel block 12 has circuit 11 and a plurality of circuits 10 (circuits 10[1] to [n]). Here, the regions where any one of circuits 10[1] to [n] is arranged are defined as pixels 20[1] to [n]. Fig. 2 shows a specific example of pixel block 12. Pixel block 12 has circuit 11 and a plurality of circuits 10 (circuits 10[1] to [n]). Here, the regions where any one of circuits 10[1] to [n] is arranged are defined as pixels 20[1] to [n]. Fig. 2 shows a specific example of pixel block 12. Pixel block 12 has circuit 11 and a plurality of circuits 10 (circuits 10[1] to [n]). Here, the regions where any one of circuits 10[1] to [n] is arranged are defined as pixels 20[1] to [n].

[0043] Circuit 11 can be configured to have transistor 101, transistor 102, and capacitor element 104. One of the source or drain of transistor 101 is electrically connected to one electrode of capacitor element 104. The other electrode of capacitor element 104 is connected to the source or drain of transistor 102. Circuit 11 can be configured to have transistor 101, transistor 102, and capacitor element 104. One of the source or drain of transistor 101 is electrically connected to one electrode of capacitor element 104. The other electrode of capacitor element 104 is connected to the source or drain of transistor 102. Circuit 11 can be configured to have transistor 101, transistor 102, and capacitor element 104. One of the source or drain of transistor 101 is electrically connected to one electrode of capacitor element 104. The other electrode of capacitor element 104 is connected to the source or drain of transistor 102. It is electrically connected to one of the source or drain of the transistor 102.

[0044] The circuit 10 can be configured to include a transistor 103 and a circuit block 110. The circuit block 110 can be configured to include transistors, capacitor elements, display elements, etc. One of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 101. One of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 101. The other of the source or drain of the transistor 103 is electrically connected to the circuit block 110.

[0045] Here, a wiring connecting one of the source or drain of the transistor 101, one of the electrodes of the capacitor element 104, and one of the source or drain of the transistor 103 is defined as node NM. Here, a wiring connecting one of the source or drain of the transistor 101, one of the electrodes of the capacitor element 104, and one of the source or drain of the transistor 103 is defined as node NM. Also, a wiring connecting the other of the source or drain of the transistor 103 and the circuit block 110 is defined as node NP. Node NP can be floating, and the display element included in the circuit block 110 operates according to the potential of node NP. Node NP can be floating, and the display element included in the circuit block 110 operates according to the potential of node NP.

[0046] The connection between the elements included in the circuit 10 and the circuit 11 and various wirings will be described. The gate of the transistor 101 is electrically connected to the wiring 121. The gate of the transistor 102 is electrically connected to the wiring 122. The gate of the transistor 103 is electrically connected to the wiring 123. The other of the source or drain of the transistor 101 is electrically connected to the wiring 125. The other of the source or drain of the transistor 102 is electrically connected to the wiring 126.

[0047] The wirings 121, 122, 123 (123[1] to [n]) have the function as gate lines. For example, the wirings 121 and 122 are electrically connected to the gate driver 14a. The wiring 123 is electrically connected to the gate driver 14b. It has a function as a source line and is electrically connected to the source driver 13 via the circuit 15. (See Figure 1.)

[0048] The circuit 15 can be configured as shown in FIG. The potential input from the source driver 13 is output to the wiring 125 or the wiring 126. In addition, the wiring 126 can be connected to a potential “V ref (For example, a base such as 0V The output control of each potential is performed by the transistors connected to each wiring. Transistor to signal V ref By controlling _EN, 125_EN, and 126_EN In addition, the circuit 15 may not be provided.

[0049] In the circuit 11, first, the first data (weight: W) is written to the node NM. The other electrode of the capacitance element 104 is connected to “V ref " is supplied to the capacitance element 104, and "WV re f Next, the node NM is set to a floating state, and the other potential of the capacitance element 104 is set to a low level. When the second data (data: D) is supplied to the node NM, the potential of the node NM becomes WV ref +D”.

[0050] Here, “W” = “D”, “V ref ”=0V, and the capacitance of node NM is sufficiently small. If the potential of the node NM is “2D” or “2W”, the output of the source driver 13 It will be possible to output a potential approximately twice as high to node NM. Therefore, even when using a general-purpose driver IC it can be used for applications that require a high voltage (for example, liquid crystal elements that require a high voltage for gradation control such as). Or, since the voltage supplied from the source driver 13 can be made approximately 1 / 2 for driving general liquid crystal elements, light-emitting elements, etc., the power consumption of the display device can be reduced.

[0051] Also, correction data may be supplied as the first data (weight: W). For example, by adding the luminance correction data to the image data, it is possible to correct the variation in luminance specific to the display device. Or, since the luminance can be corrected for each pixel, it may be used for HDR display. Also, when a light-emitting element is used as the display element, since the display quality is affected by the variation in the threshold voltage of the driving transistor, the threshold voltage correction data of the transistor may be supplied as the first data (weight: W) to improve the display quality. Note that the first data (weight: W) and the second data (data: D) may be interchanged.

[0052] In one aspect of the present invention, in accordance with the operation of adding the above-described potential, the transistor 103 of the specific circuit 10 is turned on to determine the potential of node NP (= the potential of node NM). By sequentially performing such an operation from circuit 10[1] to circuit 10[n], the potential of node NP of each circuit 10 can be determined. That is, different image data can be supplied to each pixel.

[0053] Nodes NM and NP act as storage nodes. The transistors connected to each node By making the switch conductive, data can be written to each node. Also, by making the transistor non-conductive, the data can be held at each node. By using a transistor with an extremely low off-current in the transistor, the leakage current can be suppressed, and the potential of each node can be held for a long time. For the transistor, for example, a transistor using a metal oxide in the channel formation region (hereinafter, OS transistor) can be used. Specifically, it is preferable to apply an OS transistor to transistors 101, 102, and 103. Also, an OS transistor may be applied to the elements included in circuit block 110. When operating within an acceptable range of leakage current, a transistor having Si in the channel formation region (hereinafter, Si transistor) may be applied. Or, an OS transistor and an Si transistor may be used in combination. Note that examples of the Si transistor

[0054] include a transistor having amorphous silicon, a transistor having crystalline silicon (typically, low-temperature polysilicon, single-crystalline silicon), and the like. As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, it is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal and is suitable for transistors that emphasize reliability. Also, CAC-OS exhibits high mobility characteristics and is suitable for transistors that perform high-speed driving. For example, include a transistor having amorphous silicon, a transistor having crystalline silicon (typically, low-temperature polysilicon, single-crystalline silicon), and the like. As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably

[0055] 2.5 eV or more, more preferably 3 eV or more can be used. Typically, it is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal and is suitable for transistors that emphasize reliability. Also, CAC-OS exhibits high mobility characteristics and is suitable for transistors that perform high-speed driving. For example, include a transistor having amorphous silicon, a transistor having crystalline silicon (typically, low-temperature polysilicon, single-crystalline silicon), and the like. As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, it is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal and is suitable for transistors that emphasize reliability. Also, CAC-OS

[0056] Since the energy gap of the semiconductor layer in the OS transistor is large, it exhibits an extremely low off-current characteristic of several yA / μm (the current value per 1 μm channel width). In addition, the OS transistor has characteristics different from those of Si transistors, such as no impact ionization, avalanche breakdown, and short-channel effect, and can form a highly reliable circuit. Also, the OS transistor is less likely to have variations in electrical characteristics due to the non-uniformity of crystallinity, which is a problem in Si transistors.

[0057] The semiconductor layer of the OS transistor can be a film represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and M (metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0058] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In :M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4. 1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5: 1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target. ​​​​​​​​​

[0059] The semiconductor layer is made of an oxide semiconductor having a low carrier density. Carrier density is 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Further details are below. Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 The following is further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a high-purity intrinsic or This is called a substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and is stable. It can be said that the oxide semiconductor has stable characteristics.

[0060] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer are determined. It is preferable to appropriately set the density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. stomach.

[0061] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase and the semiconductor layer becomes n-type. The concentrations of cations and carbon (obtained by secondary ion mass spectrometry) were calculated using a ratio of 2×10 18 atom s / cm 3 Less than or equal to 2×1017 atoms / cm 3 Shall be as follows.

[0062] In addition, when an alkali metal and an alkaline earth metal combine with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. For this reason, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration obtainable by secondary ion mass spectrometry) shall be 1×10 atoms / cm or less, preferably 2×10 atoms / cm or less. atoms / cm 18 atoms / cm 3 or less, preferably 2×10 16 a toms / cm 3 or less.

[0063] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (the concentration obtainable by secondary ion mass spectrometry) shall preferably be 5×10 atoms / cm or less. atoms / cm atoms / cm 18 atoms / cm 3 or less.

[0064] In addition, when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen that binds to metal atoms to become water, and thus oxygen vacancies may be formed in the oxide semiconductor. When oxygen vacancies are contained in the channel formation region in the oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies function as donors, and carriers, i.e., electrons, may be generated. Also, a part of hydrogen may combine with oxygen that binds to metal atoms to generate carriers, i.e., electrons. Therefore, when a large amount of hydrogen is contained, the transistor may have normally-on characteristics. atoms / cm characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies function as donors, and carriers, i.e., electrons, may be generated. Also, a part of hydrogen may combine with oxygen that binds to metal atoms to generate carriers, i.e., electrons. Therefore, when a large amount of hydrogen is contained, the transistor may have normally-on characteristics. characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies function as donors, and carriers, i.e., electrons, may be generated. Also, a part of hydrogen may combine with oxygen that binds to metal atoms to generate carriers, i.e., electrons. Therefore, when a large amount of hydrogen is contained, A transistor using an oxide semiconductor tends to have normally-on characteristics.

[0065] Defects in which oxygen vacancies are filled with hydrogen can function as donors in the oxide semiconductor. However it is difficult to quantitatively evaluate such defects. Therefore, in the oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used. That is, the "carrier concentration" described in this specification and the like may be able to be paraphrased as "donor concentration".

[0066] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Io n Mass Spectrometry) is less than 1×10 20 a toms / cm 3 less than, preferably less than 1×10 19 atoms / cm 3 less than, more preferably less than 5×10 18 atoms / cm 3 less than, even more preferably less than 1×10 18 atoms / c m 3 less than. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0067] Also, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure has, for example, crystals oriented along the c-axis and has CAAC-OS (C-Axis Aligned Crystalli ne Oxide Semiconductor), polycrystalline structure, microcrystalline structure, or non crystalline structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAA C-OS has the lowest density of defect levels.

[0068] The oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide film with an amorphous structure has, for example, a completely amorphous structure and no crystal part. None.

[0069] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC -OS region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.

[0070] Hereinafter, the configuration of CAC (Cloud-Aligned C omposite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0071] CAC-OS refers to, for example, a composition in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Note that hereinafter, in the oxide semiconductor, one or more metal elements are unevenly distributed, and the region having the metal element is in a mixed state in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof, and is also referred to as a mosaic state or a patch state. None. None.

[0072] Note that the oxide semiconductor preferably contains at least indium. In particular, indium and Preferably contains yttrium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included. trium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, ger manium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc., may be included.

[0073] For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-G a-Zn oxide may be particularly referred to as CAC-IGZO.) refers to indium oxide (hereinafter, InO X1 (where X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (where X2, Y2, and Z2 are real numbers greater than 0) ), and gallium oxide (hereinafter, GaO X3 (where X3 is a real number greater than 0) ), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are real numbers greater than 0).), etc., and the materials are separated to form a mosaic shape, and the mosaic-shaped InO , or In X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film configuration (hereinafter, also referred to as cloud-like).

[0074] That is, CAC-OS is a region where GaO X3 is the main component, and In X2 Zn Y2 O Z2 , or InO X1 ​A composite oxide semiconductor having a structure in which a region having a main component and a region are mixed is. In this specification, for example, the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region, and the first region is the first Compared with the second region, it is assumed that the concentration of In is high.

[0075] Note that IGZO is a general term and refers to one compound of In, Ga, Zn, and O in some cases. As a representative example, InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number) represents a crystalline compound. is mentioned.

[0076] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane .

[0077] On the other hand, CAC-OS relates to the material composition of the oxide semiconductor. CAC-OS refers to a structure in which, in a material composition containing In, Ga a, Zn, and O, a region observed in the form of nanoparticles mainly composed of Ga in part and a region observed in the form of nanoparticles mainly composed of In in part are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element. is.

[0078] Note that CAC-OS does not include a laminated structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga is not included None.

[0079] In addition, for the region where GaO X3 is the main component and the region where In X2 Zn Y2 O Z2 or InO X1 is the main component, it may not be possible to observe a clear boundary.

[0080] In addition, when one or more selected from aluminum, yttrium, copper, vanadium, beryllium , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium such as sodium are included, CAC-OS is observed in part in a region in the form of nanoparticles with the metal element as the main component and in part in a region in the form of nanoparticles with In as the main component randomly dispersed in a mosaic pattern. That is.

[0081] CAC-OS can be formed by sputtering, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by sputtering, as the film-forming gas one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used. Also, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, it is preferable to set the flow rate ratio of oxygen gas to 0% or more and less than 30%, preferably 0% or more and 10% or less. Preferably, it is preferably 0% or more and 10% or less. Preferably, it is preferably 0% or more and 10% or less.

[0082] CAC-OS is measured by X-ray diffraction (XRD) measurement method When measured using θ / 2θ scanning by the out-of-plane method, which is as follows , it has the characteristic that distinct peaks are not observed. That is, from the X-ray diffraction measurement, it can be seen that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region.

[0083] Also, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, from the electron diffraction pattern , it can be seen that the crystal structure of CAC-OS has no orientation in the plane direction and the cross-sectional direction and has a nc (nano-crystal) structure.

[0084] Also, for example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy-dispersive X -ray spectroscopy (EDX: Energy Dispersive X-ray spectro scopy), regions where GaO X3 is the main component and regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are unevenly distributed and have a mixed structure.

[0085] CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IG ZO compound. That is, CAC-OS has regions where, for example, GaO X3 and the like are the main components and regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component, and they are mutually It is phase-separated and has a structure in which regions mainly composed of each element are mosaic-shaped.

[0086] Here, In X2 Zn Y2 O Z2 , or InO X1 The region mainly composed of is a region with higher conductivity compared to the region mainly composed of GaO X3 and the like. That is, In X2 Zn Y 2O Z2 , or InO X1 When the region mainly composed of is the carrier flows, the conductivity as an oxide semiconductor is exhibited. Therefore, In Zn X2 O Y2 , or In Z2 O When the region mainly composed of is distributed in a cloud shape in the oxide semiconductor, a high field X1 effect mobility (μ) can be realized.

[0087] On the other hand, the region mainly composed of GaO X3 and the like is a region with higher insulating property compared to the region mainly composed of In X2 Zn Y2 O Z2 , or InO X 1. That is, when the region mainly composed of GaO X3 and the like is distributed in the oxide semiconductor, the leakage current is suppressed, and a good switching operation can be realized.

[0088] Therefore, when CAC-OS is used in a semiconductor device, the insulating property X3 caused by GaO and the conductivity X2 Zn Y2 O Z2 , or InO X1 caused by act complementarily to achieve a high on-current (Ion ) and can achieve a high field-effect mobility (μ). It is possible.

[0089] In addition, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0090] Note that in FIG. 2, a configuration in which the circuit 11 is arranged in the pixel 20[1] is illustrated, but it may be arranged in other pixels. Alternatively, as shown in FIG. 4, the elements of the circuit 11 may be distributed and arranged in a plurality of regions.

[0091] For example, the transistor 101 can be arranged in the pixel 20[1], the transistor 102 in the pixel 20[2], and the capacitor element 104 divided into the pixels 20[n - 1] and 20[n] can be arranged. By thus distributing and arranging the elements of the circuit 11, the number and occupied area of elements such as transistors and capacitor elements provided in each pixel can be reduced, and the aperture ratio can be increased. It is possible.

[0092] Note that although not shown in FIG. 4, there may be pixels in which the elements of the circuit 11 are not arranged. Also moreover, a plurality of such elements may be arranged in one pixel. Also, the capacitor element may not be divided and may be arranged in one pixel. Alternatively, the number of divisions of the capacitor element may be increased and it may be divided and arranged in three or more pixels.

[0093] Next, the operation method of the pixel block 12 shown in FIG. 2 or FIG. 4 will be described using the timing chart shown in FIG. 5. In the following description, a high potential is represented by “H” and a low potential by “L”. Also, the weight supplied to the pixel 20[1] is “W[1]” and the image data is “D[1] . ”, the weight supplied to pixel 20[2] is “W[2]”, the image data is “D[2]”, and pixel 2 0[n - 1] is “W[n - 1]”, the image data is “D[n - 1]”, and pixel 20[n] is “W[n]”, and the image data is “D[n]”. ”V re f ” can be, for example, 0V, GND potential, or a specific reference potential.

[0094] Here, in the potential distribution, connection, or loss, detailed changes due to the circuit configuration, operation timing, etc. are not considered. Also, the potential change due to capacitive coupling using a capacitive element depends on the capacitance ratio between the capacitive element and the load connected to the capacitive element. For clarity of explanation, the capacitance value of circuit block 110 is assumed to be a sufficiently small value.

[0095] First, the write operation of “W[1]” in pixel 20[1] will be described.

[0096] At time T1, “W[1]” is supplied to wiring 125 and “V ref ” is supplied to wiring 121, 122, and 123[1] are set to “H”. Then, transistor 102 conducts, and the potential of the other electrode of capacitive element 104 becomes “V ref ”. This operation is a reset operation for the subsequent addition operation ( capacitive coupling operation).

[0097] Also, transistors 101 and 103 conduct, and the potential of wiring 125 is written to node NP[1]. This operation is the weight write operation, and the potential of node NP[1] becomes “W[1 ”.

[0098] At time T2, the potentials of wirings 121 and 122 are set to “L” and the potential of wiring 123[1] is set to “H” Then, transistors 101 and 102 become non-conductive. At this time, “W[1]” is held at node NP[1]. Also, “W[1] - V ” is held in capacitor element 104. Up to this point is the write operation of “W[1]” in pixel 20[1]. ref ” is held Here is the write operation of “W[1]” in pixel 20[1].

[0099] Next, the addition operation of “D[1]” in pixel 20[1] will be described.

[0100] At time T3, when “D[1]” is supplied to wiring 126, the potential of wiring 121 is set to “L”, and the potentials of wirings 122 and 123[1] are set to “H”, transistors 102 and 103 become conductive . At this time, the potential of the other electrode of capacitor element 104 becomes “D[1]”, and “D[1]” is added to the potential of node NP[1] by capacitive coupling. This operation is an addition operation, and the potential of node NP[1] becomes “W[1] - V + D[1]”. At this time, if “V ref ” = 0, the potential of node NP[1] becomes “W[1] + D[1]”. The potential of node N ref ” = 0, the potential of node NP[1] becomes “W[1] + D[1]”. The potential of node NP[1] is supplied to the display element and display is performed. P[1] is supplied to the display element and display is performed.

[0101] At time T4, when the potentials of wirings 121, 122, and 123[1] are set to “L”, transistor 103 becomes non-conductive, the potential of node NP[1] is held, and display continues until the operation of the next frame. The above is the operation explanation of pixel 20[1]. The above is the operation explanation of pixel 20[1].

[0102] Next, the write operation of “W[2]” in pixel 20[2] will be described.

[0103] At time T5, “W[2]” is supplied to wiring 125, “V ref ” is supplied to wiring 126, and wiring If the potentials of 121, 122, and 123[2] are set to “H”, the transistor 102 conducts, and the potential of the other electrode of the capacitor element 104 becomes “V ref ”.

[0104] Also, the transistors 101 and 103 conduct, and the potential of the wiring 125 is written into the node NP[2]. This operation is the weight writing operation, and the potential of the node NP[2] becomes “W[2 ”.

[0105] At time T6, if the potentials of the wirings 121 and 122 are set to “L” and the potential of the wiring 123[2] is set to “H” , the transistors 101 and 102 become non - conductive. At this time, “W[2]” is held at the node NP[2]. Also, in the capacitor element 104, “W[2] - V ” is held ref . This is the writing operation of “W[2]” in the pixel 20[2].

[0106] Next, the addition operation of “D[2]” in the pixel 20[2] will be described.

[0107] At time T7, if “D[2]” is supplied to the wiring 126, the potential of the wiring 121 is set to “L”, and the potentials of the wirings 122 and 123[1] are set to “H”, the transistors 102 and 103 conduct . At this time, the potential of the other electrode of the capacitor element 104 becomes “D[2]”, and “D[2]” is added to the potential of the node NP[1] by capacitive coupling. This operation is the addition operation, and the potential of the node NP[1] becomes “W[2] - V + D[2]”. At this time, if “V ref ” = 0, the potential of the node NP[2] becomes “W[2]+D[2]”. The potential of the node N ref P[2] is supplied to the display element and display is performed.

[0108] ​​When the potentials of wirings 121, 122, and 123[2] are set to “L” at time T8, the transistor 103 becomes non-conductive, the potential of node NP[2] is retained, and the display continues until the operation of the next frame. The above is the operation explanation of pixel 20[2].

[0109] The potential of node NP[2] is supplied to the display element and the display is performed. The above is the operation explanation of pixel 20[2] Applying the same operation to pixel 20[n - 1] at times T9 to T12 enables pixel 20[n - 1] to perform a display according to “W[n - 1]+D[n - 1]”. Also, applying the same operation to pixel 20[n] at times T13 to T16 enables pixel 20[n] to perform a display according to “W[n]+D[n]”.

[0110] The pixel block 12 can be operated as described above.

[0111] Note that the circuit 11 may have the configuration shown in FIG. 6(A). The circuit 11 shown in FIG. 6(A) differs from the circuit 11 shown in FIG. 2 or FIG. 4 in that it has the transistor 105 and has one source line.

[0112] The gate of the transistor 105 is electrically connected to the wiring 122. One of the source or drain of the transistor 105 is electrically connected to the other electrode of the capacitor element 104. The other of the source or drain of the transistor 105 is electrically connected to a wiring capable of supplying “V ref ”. The other of the source or drain of the transistor 101 and the other of the source or drain of the transistor 102 are electrically connected to the wiring 125. ​​​​​​​

[0113] In the configuration of the circuit 11 shown in FIG. 2 or FIG. 4, data (D) and “V ref " In the configuration of the circuit 11 shown in FIG. 6(A), ref " In order to supply data from a dedicated path, the weight (W) and data (D) are switched from the wiring 125. This allows the number of source lines to be reduced by one.

[0114] Operation when the circuit 11 shown in FIG. 6(A) is used in the pixel block 12 shown in FIG. 2 or FIG. The operation will be explained with reference to the timing chart shown in FIG.

[0115] At time T1, “W[1]” is supplied to the wiring 125, and the potential of the wirings 121 and 123[1] When the potential of the other electrode of the capacitor 104 is set to "H", the transistor 105 is turned on. "V ref This operation is a reset for the subsequent addition operation (capacitive coupling operation). It is an action.

[0116] In addition, the transistors 101 and 103 are turned on, and the potential of the wiring 125 is written to the node NP[1]. This operation is a weight write operation, and the potential of node NP[1] becomes “W[1 ]”

[0117] At time T2, if the potential of the wiring 121 is “L” and the potential of the wiring 123[1] is “H”, At this time, the node NP[1] receives “W[1 In addition, the capacitance element 104 holds “W[1]-V ref " is retained. This completes the write operation of "W[1]" in pixel 20[1].

[0118] At time T3, supply "D[1]" to wiring 125, set the potential of wiring 121 to "L", and the potentials of wirings 122 and 123[1] to "H", then transistors 102 and 103 conduct. At this time, the potential of the other electrode of capacitor element 104 becomes "D[1]", and due to capacitive coupling, "D[1]" is added to the potential of node NP[1]. This operation is an addition operation, and the potential of node NP[1] becomes "W[1] - V ref + D[1]". At this time, if "V ref " = 0, the potential of node NP[1] becomes "W[1] + D[1]". The potential of node N P[1] is supplied to the display element, and display is performed.

[0119] At time T4, if the potentials of wirings 121, 122, and 123[1] are set to "L", then transistor 103 becomes non - conductive, the potential of node NP[1] is held, and display continues until the operation of the next frame. The above is the operation explanation of pixel 20[1].

[0120] By applying the same operation to pixel 20[2] at times T5 to T8, pixel 20[2] can perform display according to "W[2] + D[2]". Also, by applying the same operation to pixel 20[n - 1] at times T9 to T12, pixel 20[n - 1] can perform display according to "W[n - 1] + D[n - 1]". Also, by applying the same operation to pixel 20[n] at times T13 to T16, pixel 20[n] can perform display according to "W[n] + D[n]". "W[n] + D[n]".

[0121] Also, circuit 11 may have the configuration shown in Fig. 6(B). Circuit 11 shown in Fig. 6(B) differs from the circuit 11 shown in Fig. 2 or Fig. 4 in that it has transistor 106 and capacitor element 107. is different from

[0122] One electrode of the capacitive element 107 is electrically connected to the node NM. The other electrode of the capacitive element 107 is electrically connected to one of the source or drain of the transistor 106. The gate of the transistor 106 is electrically connected to the wiring 127 having a function as a gate line. The other of the source or drain of the transistor 106 is electrically connected to the wiring 128 having a function as a source line.

[0123] The circuit 11 shown in FIG. 6(B) has two capacitive elements connected in parallel to the node NM and can perform various operations. For example, correction data of the threshold voltage of the driving transistor of the light-emitting element can be written into one capacitive element, and luminance correction data can be written into the other capacitive element for image correction or the like. Alternatively, in an operation using a liquid crystal element, by selectively using capacitive elements according to the polarity of a signal corresponding to an inversion operation, the polarity of the charges accumulated on both electrodes of the capacitive element can always be made constant. Therefore, the amount of charge supplied during the inversion operation can be reduced, and the power consumption of the display device can be suppressed.

[0124] FIGS. 8(A) to (C) can be applied to the circuit block 110 and are examples of configurations including a light-emitting element as a display element.

[0125] The configuration shown in FIG. 8(A) includes a transistor 111, a capacitive element 113, and a light-emitting element 114. One of the source or drain of the transistor 111 is electrically connected to one electrode of the light-emitting element 114. One electrode of the light-emitting element 114 is one electrode of the capacitive element 113. is electrically connected to the pole. The other electrode of the capacitor element 113 is the gate of the transistor 111 and is electrically connected thereto. The gate of the transistor 111 is electrically connected to the node NP .

[0126] The other of the source or drain of the transistor 111 is electrically connected to the wiring 128 . The other electrode of the light-emitting element 114 is electrically connected to the wiring 129. The wirings 128 and 12 9 have the function of supplying power. For example, the wiring 128 can supply a high-potential power source . Also, the wiring 129 can supply a low-potential power source

[0127] In the configuration shown in FIG. 8(A), when the potential of the node NM becomes equal to or higher than the threshold voltage of the transistor 111 , a current flows through the light-emitting element 114. Therefore, when the weight (W) is written to the node NP , the light emission of the light-emitting element 114 may start, and the application may be limited .

[0128] Alternatively, as shown in FIG. 8(B), one electrode of the light-emitting element 114 may be electrically connected to the wiring 128 , and the other electrode of the light-emitting element 114 may be electrically connected to the other of the source or drain of the transistor 111 . The said configuration can also be applied to other circuit blocks 1 10 having the light-emitting element 114

[0129] FIG. 8(C) shows a configuration in which the transistor 112 is added to the configuration of FIG. 8(A). One of the source or drain of the transistor 112 is electrically connected to one of the source or drain of the transistor 111 . The other of the source or drain of the transistor 112 is electrically connected to the light-emitting element 114. The gate of the transistor 112 is electrically connected to the wiring 127 It is connected pneumatically. The wiring 127 can function as a signal line for controlling the conduction of the transistor 112. It can have a function.

[0130] In this configuration, when the potential of the node NP is equal to or higher than the threshold voltage of the transistor 111 and the transistor 112 is conducting, a current flows through the light-emitting element 114. Therefore, the light emission of the light-emitting element 114 can be started at an arbitrary timing after the addition operation of the weight ( W) and the data (D). It can be done. It can be done.

[0131] FIG. 8(D) shows a configuration in which a transistor 115 is added to the configuration of FIG. 8(C). One of the source or drain of the transistor 115 is electrically connected to one of the source or drain of the transistor 111. The other of the source or drain of the transistor 115 is electrically connected to the wiring 131. The gate of the transistor 115 is electrically connected to the wiring 132. The wiring 132 can function as a signal line for controlling the conduction of the transistor 115. One of the source or drain of the transistor 115 is electrically connected to one of the source or drain of the transistor 111. The other of the source or drain of the transistor 115 is electrically connected to the wiring 131. The other of the source or drain of the transistor 115 is electrically connected to the wiring 131. The gate of the transistor 115 is electrically connected to the wiring 132. The wiring 132 can function as a signal line for controlling the conduction of the transistor 115. It can have a function. It can have a function.

[0132] The wiring 131 can be electrically connected to a source of a specific potential such as a reference potential. By supplying a specific potential from the wiring 131 to one of the source or drain of the transistor 111, the writing of the image data can also be stabilized. By supplying a specific potential from the wiring 131 to one of the source or drain of the transistor 111, the writing of the image data can also be stabilized. It can also be done.

[0133] Also, the wiring 131 can be connected to the circuit 120 and can also function as a monitor line. The circuit 120 can have one or more of the functions of supplying the above specific potential source, obtaining the electrical characteristics of the transistor 111, and generating correction data. It can also be done. The circuit 120 can have one or more of the functions of supplying the above specific potential source, obtaining the electrical characteristics of the transistor 111, and generating correction data. It can have a function.

[0134] Figures 9(A) through (D) are examples of configurations applicable to circuit block 110 and including a liquid crystal element as a display element. This is an example of a configuration.

[0135] The configuration shown in FIG. 9(A) has a capacitor element 116 and a liquid crystal element 117. One electrode of the liquid crystal element 11 7 is electrically connected to one electrode of the capacitor element 116. One electrode of the capacitor element 116 is electrically connected to node NP.

[0136] The other electrode of the capacitor element 116 is electrically connected to wiring 133. The other electrode of the liquid crystal element 117 is electrically connected to wiring 134. The wirings 133 and 134 have a function of supplying power. For example, the wirings 133 and 134 can supply a reference potential such as GND or 0V or an arbitrary potential. For example, the wirings 133 and 134 can supply a reference potential such as GND or 0V or an arbitrary potential. can be supplied.

[0137] Note that a configuration in which the capacitor element 116 is omitted as shown in FIG. 9(B) may be used. As described above, an OS transistor can be used for the transistor connected to node NP. Since the OS transistor has an extremely small leakage current, the display can be maintained for a relatively long time even if the capacitor element 116 that functions as a holding capacitor is omitted. Also, not limited to the configuration of the transistor, when the display period can be shortened by high-speed operation such as field sequential driving it is also effective to omit the capacitor element 116. By omitting the capacitor element 116, the aperture ratio can be improved or the transmittance of the pixel can be improved. or the transmittance of the pixel can be improved. In the configurations of FIGS. 9(A) and (B), the operation of the liquid crystal element 117 starts when the potential of node NP is determined to be equal to or higher than the operation threshold of the liquid crystal element 117. Therefore, a weight is written to node NP. or the transmittance of the pixel can be improved.

[0138] In the configurations of FIGS. 9(A) and (B), the operation of the liquid crystal element 117 starts when the potential of node NP is determined to be equal to or higher than the operation threshold of the liquid crystal element 117. Therefore, a weight is written to node NP. is determined, the operation of the liquid crystal element 117 starts. Therefore, a weight is written to node NP. There may be cases where the display operation starts at the stage of being written in, and the applications may be limited. However, In the case of a transmissive liquid crystal display device, by combining operations such as turning off the backlight until the timing when the addition operation of the weight (W) and the data (D) is completed, it is possible to suppress visual recognition even if an unnecessary display operation is performed.

[0139] FIG. 9(C) shows a configuration in which a transistor 118 is added to the configuration of FIG. 9(A). One of the source or drain of the transistor 118 is electrically connected to one electrode of the capacitive element 116. The other of the source or drain of the transistor 118 is electrically connected to the node NP. The gate of the transistor 118 is electrically connected to the wiring 130. The wiring 1 30 can function as a signal line for controlling the conduction of the transistor 118.

[0140]

[0141] In this configuration, the potential of the node NP is applied to the liquid crystal element 117 with the conduction of the transistor 118. Therefore, the operation of the liquid crystal element can be started at an arbitrary timing after the addition operation of the weight (W) and the data (D).

[0142] Note that, since the potentials supplied to the capacitive element 116 and the liquid crystal element 117 are continuously held in the state where the transistor 118 is non-conductive, it is preferable to reset the potentials supplied to the capacitive element 116 and the liquid crystal element 117 before rewriting the image data. The reset can be performed, for example, by supplying a reset potential to the source line (for example, wirings 125, 126, etc.) to which the pixel is connected and simultaneously turning on the transistors 101 and 118.​​​​​​​​​FIG. 9(D) shows a configuration in which a transistor 119 is added to the configuration of FIG. 9(C). One of the source or drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source or drain of the transistor 119 is electrically connected to the wiring 131. The gate of the transistor 119 is electrically connected to the wiring 132. The wiring 132 can function as a signal line for controlling the conduction of the transistor 119. The circuit 120 electrically connected to the wiring 131 is the same as the description of FIG. 8(C) described above. In addition, it may have a function of resetting the potentials supplied to the capacitor element 116 and the liquid crystal element 117.

[0143]

[0144] FIGS. 10(A) to (C) are diagrams showing an example of a wiring system for supplying “V ref ”. As shown in FIG. 10(A), when a light-emitting element is used as the display element, the wiring 128 can be applied to the wiring for supplying “V ”. Since “V ” is preferably 0V, GND, or a low potential, the wiring 128 also has a function of supplying at least one of those potentials. At the timing of writing data to the node NP, “V ref ” is supplied to the wiring 128, and a high-potential power supply may be supplied at the timing of causing the light-emitting element 114 to emit light. Alternatively, as shown in FIG. 10(B), the wiring 129 for supplying a low potential may be applied as the wiring for supplying “V re f ”. ref Also, as shown in FIG. 10(C), when a liquid crystal element is used as the display element, “V ref ” may be supplied.

[0145] ref ​​​​​​​​​​ Wiring 133 can be applied to the wiring for supplying “”. Or, wiring 134 can be applied. Note that, regardless of the type of display element, a dedicated common ref wiring for supplying “V” may be provided.

[0146] Also, in one aspect of the present invention, as illustrated in FIGS. 11(A) and (B), a configuration may be adopted in which a back gate is provided for the transistor included in pixel block 12. FIG. 11(A) shows a configuration in which the back gate is electrically connected to the front gate and has the effect of increasing the on-current. FIG. 11(B) shows a configuration in which the back gate is electrically connected to wiring 135 capable of supplying a fixed potential, and

[0147] the threshold voltage of the transistor can be controlled. Also, as shown in the timing chart of FIG. 4 and the like, for circuit 10, the gate signal “H” is input while being shifted at regular intervals. On the other hand, for circuit 11, it is necessary to input the gate signal “H” or “L” in

[0148] accordance with the operation period of one circuit 10. Also, this operation is repeated the number of times of the circuits 10 included in pixel block 12. Therefore, as shown in FIG. 1, it is preferable to provide a gate driver 14a for controlling circuit 11 and a gate driver 14b for controlling circuit 10. By providing the gate drivers for controlling circuit 10 and circuit 11

[0149] ​For example, FIG. 12 is a diagram showing input / output signals of gate drivers 14a and 14b. Note that here, the number of pixel rows is 1280, and the number of pixels (circuits 10) in pixel block 12 is 4 is assumed.

[0150] The signals input to gate driver 14a can be SPL (start pulse signal for gate driver 14a), CLK[1:4]L (clock signal for gate driver 14a), PWC1, PWC2 (pulse width control signal for gate signal), and its output can be applied to certain GL1[1] to GL1

[0320] , and GL2[1] to GL2

[0320] through gate lines. Here, GL1 corresponds to wiring 125, and GL2 corresponds to wiring 126. Also, 320 is the same as the number of pixel blocks 12 provided in the vertical direction.

[0151] The signals input to gate driver 14b can be SPR (start pulse signal for gate driver 14b), CLK[1:4]R (clock signal for gate driver 14b), and its output can be applied to GL3[1] to GL3

[1280] which are gate lines. Here, GL3 corresponds to wiring 123. Also, 1280 is the same as the number of pixels 20 provided in the vertical direction. is assumed.

[0152] FIG. 13 is an example of a block diagram of gate driver 14a. Gate driver 14a includes a shift register circuit composed of a plurality of set / reset flip-flops, and a buffer circuit (BuF). One stage of the shift register circuit is represented by "SR", and the dummy stage is represented by "DUM". RES is a reset signal, and when a "H" input is applied, all outputs of the shift register circuit can be set to "L".

[0153] "BuF" has an AND circuit and outputs a signal to the gate lines (GL1 and / or GL2) using the output signal (SROUT signal) of "SR", the PWC1 signal and the PWC2 signal. It can do so.

[0154] "SR" can be configured as, for example, the block diagram shown in FIG. 15(A) and the circuit diagram shown in FIG. 15(B). Here, LIN is the shift signal input from the previous-stage "SR", FO is the output signal that controls the transistors of "Buf", and RIN represents the reset signal input from the subsequent-stage "SR". The input clock signal can be, for example, a combination of CLK[1]L and CLK[3]L, or a combination of CLK[2]L and CLK[4]L. The input clock signal can be, for example, a combination of CLK[1]L and CLK[3]L, or a combination of CLK[2]L and CLK[4]L. signal, FO is the output signal that controls the transistors of "Buf", and RIN represents the reset signal input from the subsequent-stage "SR". The input clock signal can be, for example, a combination of CLK[1]L and CLK[3]L, or a combination of CLK[2]L and CLK[4]L. Note that the input clock signal can be, for example, a combination of CLK[1]L and CLK[3]L, or a combination of CLK[2]L and CLK[4]L. K[1]L and CLK[3]L, or a combination of CLK[2]L and CLK[4]L. combination.

[0155] Also, the buffer circuit (BuF) can be configured as the block diagram shown in FIG. 16(A) and the circuit diagram shown in FIG. 16(B). Here, FN represents the signal (FO) input from "SR", and LN represents the signal (SROUT) input from "SR". Note that the input clock signal can be, for example, a combination of CLK[1]L and CLK[3]L, or a combination of CLK[2]L and CLK[4]L. (FO), LN represents the signal (SROUT) input from "SR".

[0156] FIG. 14 is an example of the block diagram of the gate driver 14b. It has a shift register circuit composed of a plurality of set-reset flip-flops. One stage of the shift register circuit is represented by "SR", and the dummy stage is represented by "DUM". "SR" can be configured as, for example, the block diagram shown in FIG. 17(A) and the circuit diagram shown in FIG. 17(B). It has a shift register circuit composed of a plurality of set-reset flip-flops. One stage of the shift register circuit is represented by "SR", and the dummy stage is represented by "DUM". "SR" can be configured as, for example, the block diagram shown in FIG. 17(A) and the circuit diagram shown in FIG. 17(B). is represented by "SR", and the dummy stage is represented by "DUM". "SR" can be configured as, for example, the block diagram shown in FIG. 17( A) and the circuit diagram shown in FIG. 17(B).

[0157] Next, the simulation results regarding the pixel block 12 will be described. The simulation is shown in FIG. 18 Shows the configuration of the pixel block 12 used in the simulation. The timing chart used in the simulation is shown in FIG. 19. The number of pixels of the pixel block 12 is 4, and the circuit block 110 has the configuration shown in FIG. 9(A) (liquid crystal element and capacitance element). The simulation was performed on the voltage change of the node NP when the operation was sequentially performed for each pixel.

[0158] The parameters used in the simulation are as follows. The transistor size is L / W = 4μm / 4μm (transistor of the pixel block 12), the capacitance value of the capacitance element C1 is 500 fF, the capacitance value of the capacitance element Cs is 100 fF, and the capacitance value of the liquid crystal element Clc is 100 fF . The common electrodes VCOM and TCOM are set to 0V. Also, the voltage applied to the gate of the transistor is +15V for “H” and -10V for “L”. Note that SPICE was used for the circuit simulation software. Here, the parasitic capacitance of the wiring PL shown in FIG. 18 is excluded from the parameters.

[0159] FIG. 19 is the timing chart used in the simulation. Here, the weights (W [1] to [4]) and the data (D[1] to [4]) are all set to 5V. Also, “V re f ” is set to 0V.

[0160] FIG. 20(A) shows the simulation results when all the weights (W[1] to [4]) and the data (D[1] to [4]) are set to 5V and “V ” is set to 0V. The horizontal axis is time ref and the vertical axis is the voltage of the node NP. It was confirmed that the weights (W) and the data (D) are added according to the capacitance ratio at each node NP.

[0161] Figure 20(B) shows the simulation results when the weights (W[1]) and data (D[2]) are set to 5V, the weights (W[2]) and data (D[2]) are set to 2.5V, the weights (W[3]) and data (D[3]) are set to - 2.5V, the weights (W[4]) and data (D[4]) are set to -5V, and "V ref " is set to 0V. At each node NP, it was confirmed that the weights (W) and data (D) are added according to the capacitance ratio. Also, since the addition operation can be performed regardless of the polarity of the weights and data within the same pixel block 12, it was confirmed that the application of gate line inversion driving is also possible.

[0162] Therefore, it was confirmed that the pixel block 12, which is one aspect of the present invention, can perform the addition operation of the weights (W) and data (D) normally within a range where the parasitic capacitance of the wiring PL has no influence.

[0163] Next, the simulation results regarding the pixel layout will be described. FIG. 21 shows an example of the layout of three pixels in the vertical direction, with the pixel block 12 shown in FIG. 18 as the basic configuration, for the m-th column and the m +1-th column.

[0164] In the layout shown in FIG. 21, Cs is omitted, and the pixel electrode PE corresponding to the node NP is illustrated. As an example of the transistor, a bottom gate type (back gate type) is illustrated.

[0165] The transistors Tr1 and Tr2 are arranged to be included in the pixels of the first row of the pixel block 12. Therefore, the number of transistors in each row is three in total, namely Tr1, T r2, and Tr3 in the first row, and one transistor Tr3 in the rows after the second row. Note that The sizes of transistors Tr1 and Tr2 are L / W = 4 μm / 30 μm, and the size of transistor Tr 3 is assumed to be L / W = 4 μm / 10 μm. The pixel pitch is assumed to be about 136 μm (different for the first row and the subsequent rows).

[0166] C1 uses a conductive layer formed in the same process as the gate wiring and a conductive layer formed in the same process as the source wiring as a pair of electrodes. The two conductive layers are arranged in parallel with the source lines SL1 and SL2 and have an overlapping region via an insulating layer (e.g., a gate insulating film) in each pixel. That is, one capacitive element is provided in each pixel. Also, since the capacitive elements are connected in parallel, they are equivalent to one large capacitive element. That is, since the capacitive element C1 is divided and arranged, the aperture ratio and transmittance of the pixel can be improved . For the electrical connection between the conductive layers on one side constituting the capacitive element, it is preferable to use a connection wiring BR that bridges the gate wiring. As the connection wiring BR , for example, it can be formed in the same process as the source wiring.

[0167] Here, since the transistors Tr1, Tr2 and their driving gate lines are provided in the pixels of the first row, the number of elements is larger than that of the pixels in other rows. As shown in type 1 of FIG. 22(A), when the vertical length of all pixels is unified to A, the pixel electrode PE1 becomes smaller than the pixel electrodes P E2 and PE3. Therefore, the display in the first column may be visually recognized as a dark line . Therefore, as in type 2 shown in FIG. 22(B), when the vertical length of all pixel electrodes is

[0168] Here, since the transistors Tr1, Tr2 and their driving gate lines are provided in the pixels of the first row, the number of elements is larger than that of the pixels in other rows. As shown in type 1 of FIG. 22(A), when the vertical length of all pixels is unified to A, the pixel electrode PE1 becomes smaller than the pixel electrodes P E2 and PE3. Therefore, the display in the first column may be visually recognized as a dark line . As shown in type 1 of FIG. 22(A), when the vertical length of all pixels is unified to A, the pixel electrode PE1 becomes smaller than the pixel electrodes P E2 and PE3. Therefore, the display in the first column may be visually recognized as a dark line .

[0169] Therefore, as in type 2 shown in FIG. 22(B), when the vertical length of all pixel electrodes is Unify it to B, and the vertical length of the pixels in the first row may be made larger than the vertical length of the pixels after the second row. Or, the vertical length of each pixel may be adjusted so that the pixel electrode PE1 is larger than the pixel electrodes PE2 and PE3. With such a configuration, it is possible to suppress the display of the first row from being visually recognized as a dark line. Also, the vertical length of each pixel may be adjusted so that the pixel electrode PE1 is larger than the pixel electrodes PE2 and PE3. With such a configuration, it is possible to suppress the display of the first row from being visually recognized as a dark line. from being visually recognized as a dark line.

[0170] The calculated aperture ratio values when applying the pixel block of type 1 or type 2 shown in FIG. 22 to the display area are shown in FIG. 23. The aperture ratio shown here is (the area of all pixel electrodes in the pixel block) / (the area of the pixel block). In the calculation, the number of pixels in the pixel block was set to 1 to 4000. Note that it is assumed that all the pixels of type 1 are square pixels with a side length of 136 μm. Also, in type 2, when the number of pixels is 1, it is a square pixel with a side length of 136 μm, and when the number of pixels is 2 or more, the vertical length is adjusted so that the pixel electrodes have the same size. Note that the vertical length of the pixel block is the same as that when using square pixels with a side length of 136 μm so that it can be compared with type 1. The calculated aperture ratio values when applying the pixel block of type 1 or type 2 shown in FIG. 22 to the display area are shown in FIG. 23. The aperture ratio shown here is (the area of all pixel electrodes in the pixel block) / (the area of the pixel block). In the calculation, the number of pixels in the pixel block was set to 1 to 4000. Note that it is assumed that all the pixels of type 1 are square pixels with a side length of 136 μm. In the calculation, the number of pixels in the pixel block was set to 1 to 4000. Note that it is assumed that all the pixels of type 1 are square pixels with a side length of 136 μm. Also, in type 2, when the number of pixels is 1, it is a square pixel with a side length of 136 μm, and when the number of pixels is 2 or more, the vertical length is adjusted so that the pixel electrodes have the same size. Also, in type 2, when the number of pixels is 1, it is a square pixel with a side length of 136 μm, and when the number of pixels is 2 or more, the vertical length is adjusted so that the pixel electrodes have the same size. Note that the vertical length of the pixel block is the same as that when using square pixels with a side length of 136 μm so that it can be compared with type 1. Note that the vertical length of the pixel block is the same as that when using square pixels with a side length of 136 μm so that it can be compared with type 1.

[0171] As shown in FIG. 23, for both type 1 and type 2, when the number of pixels in the pixel block is up to about 10, the aperture ratio rises rapidly and reaches 81% at about 20. After that, it also rises gently and approaches nearly 82% at 100. Therefore, when emphasizing the aperture ratio, it can be said that it is preferable to make the number of pixels in the pixel block as large as possible. However, considering the efficient effect due to the pixel layout, about 5 to 100 is preferable, about 10 to 50 is more preferable, and about 20 to 40 is even more preferable. the aperture ratio rises rapidly and reaches 81% at about 20. After that, it also rises gently and approaches nearly 82% at 100. Therefore, when emphasizing the aperture ratio, it can be said that it is preferable to make the number of pixels in the pixel block as large as possible. the aperture ratio rises rapidly and reaches 81% at about 20. After that, it also rises gently and approaches nearly 82% at 100. Therefore, when emphasizing the aperture ratio, it can be said that it is preferable to make the number of pixels in the pixel block as large as possible. However, considering the efficient effect due to the pixel layout, about 5 to 100 is preferable, about 10 to 50 is more preferable, and about 20 to 40 is even more preferable. However, considering the efficient effect due to the pixel layout, about 5 to 100 is preferable, about 10 to 50 is more preferable, and about 20 to 40 is even more preferable.

[0172] From the above simulation results, the effect of one embodiment of the present invention could be confirmed.

[0173] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0174] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal element and a configuration example of a display device using a light emitting element will be described. A configuration example will be described. In this embodiment, the display device described in the first embodiment will be Descriptions of the elements, operations and functions of the device are omitted.

[0175] 24A to 24C show the structure of a display device in which one embodiment of the present invention can be used. FIG.

[0176] In FIG. 24A, a display unit 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display unit 215 is disposed between the sealant 4005 and the second substrate 4. Sealed by 006.

[0177] The display unit 215 can be provided with the pixel block 12 described in the first embodiment and the like. The scanning line driving circuit described below is a gate driver, and the signal line driving circuit is a source driver. Equivalent to ba.

[0178] In FIG. 24A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline The common line driving circuit 241a is formed of a semiconductor. It has a function of supplying a specified potential to 129, 132, 133, 135, etc.

[0179] The various signals and potentials supplied to the scanning line drive circuit 221a, the common line drive circuit 241a, the signal line drive circuit 231a, and the signal line drive circuit 232a are supplied via an FPC (FPC: Flexible printed circuit) 4018.

[0180] The integrated circuit 4042 included in the scanning line drive circuit 221a and the common line drive circuit 241a has a function of supplying a selection signal to the display unit 215. The integrated circuit 4042 included in the signal line drive circuit 231a and the signal line drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0181] Note that the connection method of the integrated circuit 4042 is not particularly limited, and wire bonding method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, COF (Chip On Film) method, etc. can be used.

[0182] FIG. 24(B) shows an example of mounting the integrated circuit 4042 included in the signal line drive circuit 231a and the signal line drive circuit 232a by the COG method. Also, a part or all of the drive circuit can be integrally formed on the same substrate as the display unit 215 to form a system-on-panel.

[0183] In FIG. 24(B), the scanning line drive circuit 221a and the common line drive circuit 241a are shown in the display unit 2 An example of forming on the same substrate as 15 is shown. By forming the drive circuit at the same time as the pixel circuit in the display unit 215, the number of components can be reduced. Therefore, productivity can be increased.

[0184] Also, in FIG. 24(B), a sealing material 4005 is provided so as to surround the display unit 215 provided on the first substrate 4001, the scanning line drive circuit 221a, and the common line drive circuit 241a. Further, a second substrate 4006 is provided on the display unit 215, the scanning line drive circuit 221a, and the common line drive circuit 241a. Therefore, the display unit 215, the scanning line drive circuit 221a, and the common line drive circuit 241a are sealed together with the display elements by the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0185] Also, in FIG. 24(B), an example is shown in which the signal line drive circuits 231a and 232a are separately formed and mounted on the first substrate 4001, but the configuration is not limited to this. The scanning line drive circuit may be separately formed and mounted, or a part of the signal line drive circuit or a part of the scanning line drive circuit may be separately formed and mounted. Further, as shown in FIG. 24(C), the signal line drive circuits 231a and 232a may be formed on the same substrate as the display unit 215.

[0186] Further, the display device may include a panel in a state where the display element is sealed, and a module in a state where an IC or the like including a controller is mounted on the panel.

[0187] Also, the display unit and the scanning line drive circuit provided on the first substrate have a plurality of transistors. is possible. As the transistor, the transistor shown in the above embodiment can be applied. This is possible.

[0188] The structure of the transistor included in the peripheral drive circuit and the structure of the transistor included in the pixel circuit of the display unit may be the same or different. All of the transistors included in the peripheral drive circuit may be transistors having the same structure, or may have transistors of two or more types of structures. Similarly, all of the transistors included in the pixel circuit may be transistors having the same structure, or may have transistors of two or more types of structures.

[0189] In addition, an input device 4200 can be provided on the second substrate 4006. The configuration in which the input device 4200 is provided in the display device shown in FIGS. 24(A) to (C) can function as a touch panel. This is possible.

[0190] There is no limitation on the detection element (also referred to as a sensor element) included in the touch panel according to one aspect of the present invention. Various sensors capable of detecting the proximity or contact of a detected object such as a finger or a stylus can be applied as the detection element.

[0191] As the sensor method, for example, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used.

[0192] In the present embodiment, a touch panel having a capacitance-type detection element will be described as an example. This is possible.

[0193] As the capacitance method, there are a surface capacitance method, a projected capacitance method, etc. Further, the projected As the capacitance type, there are self-capacitance type, mutual-capacitance type, etc. Using the mutual-capacitance type is preferable because it enables simultaneous multi-point detection.

[0194] The touch panel according to one aspect of the present invention has a configuration in which a separately manufactured display device and a detection element are bonded together or a configuration in which electrodes and the like constituting the detection element are provided on one or both of the substrate supporting the display element and the counter substrate, and various configurations can be applied.

[0195] Figs. 25(A) and (B) show an example of a touch panel. Fig. 25(A) is a perspective view of the touch panel 4 210. Fig. 25(B) is a schematic perspective view of the input device 4200. For clarity, only typical components are shown.

[0196] The touch panel 4210 has a configuration in which a separately manufactured display device and a detection element are bonded together .

[0197] The touch panel 4210 has an input device 4200 and a display device, and these are provided so as to overlap each other.

[0198] The input device 4200 has a substrate 4263, electrodes 4227, electrodes 4228, a plurality of wirings 4237 , a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. Also, the electrode 4228 can be electrically connected to the wiring 4239. The FPC 4272b is electrically connected to each of the plurality of wirings 4237 and the plurality of wirings 4238. An IC 427 3b can be provided on the FPC 4272b.

[0199] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case of providing a touch sensor between the first substrate 4001 and the second substrate 4006, in addition to the capacitance type touch sensor, an optical touch sensor using a photoelectric conversion element may also be applied.

[0200] FIGS. 26(A) and (B) are cross-sectional views of the portion indicated by the chain line N1-N2 in FIG. 24(B). The display device shown in FIGS. 26(A) and (B) has an electrode 4015, and the electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. Also, in FIGS. 26(A) and (B), the electrode 4015 is electrically connected to the wiring 4014 at the opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

[0201] The electrode 4015 is formed of the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed of the same conductive layer as the source electrode and the drain electrode of the transistors 4010 and 4011.

[0202] Also, the display unit 215 and the scanning line driving circuit 221a provided on the first substrate 4001 have a plurality of transistors. In FIGS. 26(A) and (B), the transistors 4010 included in the display unit 215 and the transistors 4011 included in the scanning line driving circuit 221a are exemplified. Note that, in FIGS. 26(A) and (B), bottom gate type transistors are exemplified as the transistors 4010 and 4011, but top gate type transistors may also be used.

[0203] ​​​​​​In FIGS. 26(A) and (B), an insulating layer 4112 is provided on transistors 4010 and 4011. Also, in FIG. 26(B), a partition wall 451 0 is formed on the insulating layer 4112.

[0204] Also, transistors 4010 and 4011 are provided on the insulating layer 4102 and are formed on the insulating layer 4111 and have an electrode 4017 formed thereon. The electrode 4017 can function as a back gate electrode .

[0205] Also, the display device shown in FIGS. 26(A) and (B) has a capacitor element 4020. The capacitor element 4 020 has an electrode 4021 formed in the same process as the gate electrode of the transistor 4010 and an electrode formed in the same process as the source electrode and the drain electrode. Each electrode overlaps via the insulating layer 4103.

[0206] Generally, the capacitance of the capacitor element provided in the pixel portion of the display device is set so that it can hold charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion and so on. The capacitance of the capacitor element may be set in consideration of the off-current of the transistor and so on.

[0207] The transistor 4010 provided in the display unit 215 is electrically connected to the display element. FIG. 26 (A) is an example of a liquid crystal display device using a liquid crystal element as the display element. In FIG. 26(A), the liquid crystal element 4013, which is the display element, includes a first electrode layer 4030, a second electrode layer 40 31, and a liquid crystal layer 4008. Note that the insulating layer 4032 that functions as an alignment film, the insulating Layer 4033 is provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 therebetween.

[0208] As the liquid crystal element 4013, a liquid crystal element to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an A SM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Bend) mode, an F LC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an EC B (Electrically Controlled Birefringence) mode, a VA-IPS mode, a guest-host mode, etc., a liquid crystal element to which these modes are applied can be used.

[0209] In addition, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be applied to the liquid crystal display device shown in this embodiment. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignme nt) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, etc. can be used.

[0210] ​​Note that a liquid crystal element is an element that controls the transmission or non - transmission of light by the optical modulation action of liquid crystal. There is. The optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). As the liquid crystal used in the liquid crystal element, thermotropic liquid crystal, low - molecular liquid crystal, high - molecular liquid crystal, polymer - dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

[0211] In FIG. 26, an example of a liquid crystal display device having a vertical - electric - field - type liquid crystal element was shown. However, in one aspect of the present invention , a liquid crystal display device having a horizontal - electric - field - type liquid crystal element can be applied. When adopting the horizontal - electric - field method, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid - crystal phases. When the cholesteric liquid crystal is heated, it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid - crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid - crystal layer 40 08 in order to improve the temperature range. The liquid - crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. Also, the liquid - crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has a small viewing - angle dependence. Also, since an alignment film does not need to be provided, no rubbing treatment is required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced.

[0212] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0213] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. In addition, the above-mentioned backlight and sidelight may be used. Micro LEDs or the like may be used as the light.

[0214] In the display device shown in FIG. 26A, a light-shielding layer is provided between the substrate 4006 and the second electrode layer 4031. 4132, a coloring layer 4131, and an insulating layer 4133 are provided.

[0215] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, etc. Examples of the material for the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. In addition, the light-shielding layer may be a laminated film of a film containing the material of the colored layer. A film containing a material for a colored layer that transmits light of a certain color and a material for a colored layer that transmits light of a different color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0216] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, or dyes. Examples include the resin material obtained. The light-shielding layer and the colored layer can be formed, for example, by an inkjet method or the like.

[0217] In addition, the display device shown in FIGS. 26(A) and (B) has an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, an insulating layer that hardly transmits impurity elements is used. By sandwiching the semiconductor layer of the transistor with the insulating layer 4111 and the insulating layer 4104, intrusion of impurities from the outside can be prevented.

[0218] In addition, a light-emitting element can be used as the display element included in the display device. As the light-emitting element, for example, an EL element utilizing electroluminescence can be applied. The EL element has a layer containing a light-emitting compound (also referred to as an "EL layer") between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected from the anode side and electrons are injected from the cathode side into the EL layer. The injected electrons and holes recombine in the EL layer, and the light-emitting substance contained in the EL layer emits light.

[0219] In addition, the EL element is classified depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0220] In the organic EL element, by applying a voltage, electrons are injected from one electrode and holes are injected from the other electrode into the EL layer, respectively. Then, when these carriers (electrons and holes) recombine, a light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is a current-excited type light-emitting element. ​​​​​​​​It is called a child.

[0221] In addition, the EL layer may contain, in addition to the light-emitting compound, a substance with high hole injection properties, a substance with high hole transport properties , a hole blocking material, a substance with high electron transport properties, a substance with high electron injection properties, or a bipolar substance (a substance with high electron transport and hole transport properties).

[0222] The EL layer can be formed by any method such as vapor deposition (including vacuum vapor deposition), transfer method, printing method, inkjet method, coating method .

[0223] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. Dispersed inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder , and the light-emitting mechanism is donor-acceptor recombination emission that utilizes donor levels and acceptor levels. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers , and further sandwiched between electrodes, and the light-emitting mechanism is localized emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used as the light-emitting element for explanation.

[0224] For the light-emitting element, at least one of the pair of electrodes may be transparent in order to extract light. Then, a transistor and a light-emitting element are formed on a substrate, and top emission (top emission) in which light is extracted from the surface opposite to the substrate , bottom emission (bottom emission) in which light is extracted from the surface on the substrate side , and dual emission (dual emission) in which light is extracted from both sides There are light-emitting elements with structures, and light-emitting elements with any emission structure can be applied.

[0225] FIG. 26(B) shows an example of a light-emitting display device (also referred to as an "EL display device") using a light-emitting element as a display element. The light-emitting element 4513, which is the display element, is electrically connected to a transistor 4010 provided in the display unit 215. The structure of the light-emitting element 4513 is a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, but it is not limited to this structure. The structure of the light-emitting element 4513 can be appropriately changed according to the direction of light extracted from the light-emitting element 4513 and the like. The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 and to form the side surface of the opening as an inclined surface having a continuous curvature. The light-emitting layer 4511 may be composed of a single layer or a plurality of stacked layers. The light-emitting color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, yellow, or the like depending on the material constituting the light-emitting layer 4511. As a method for realizing color display, there are a method of combining a light-emitting element 4513 having a white light-emitting color with a coloring layer and a method of providing light-emitting elements 4513 having different light-emitting colors for each pixel. The former method has higher productivity than the latter method. On the other hand, in the latter method, since it is necessary to separately produce the light-emitting layer 4511 for each pixel, the productivity is inferior to the former method. However, in the latter method, a light-emitting color with higher color purity can be obtained than in the former method. In addition to the latter method, the light emission

[0226]

[0227]

[0228]

[0229] By imparting a microcavity structure to the element 4513, the color purity can be further enhanced. This can be achieved.

[0230] Note that the light-emitting layer 4511 may contain an inorganic compound such as a quantum dot. For example, by using a quantum dot in the light-emitting layer, it can also function as a light-emitting material. This can be achieved.

[0231] A protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not penetrate into the light-emitting element 4513. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (Diamond Like Carbon), etc. can be formed. In addition, a filling material 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4 005. In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to package (encase) it with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. 005. 005. As the filling material 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or

[0232] EVA (ethylene vinyl acetate), etc. can be used. Further, the filling material 4514 may contain a desiccant.

[0233] The sealing material 4005 includes glass materials such as glass frit and conventional It is possible to use resin materials such as thermosetting resins, photocurable resins, and thermosetting resins that cure at low temperatures. Also, the sealing material 4005 may contain a desiccant.

[0234] Also, if necessary, an optical film such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. may be appropriately provided. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection.

[0235] Also, by forming the light-emitting element into a microcavity structure, light with high color purity can be extracted. Also, by combining the microcavity structure and the color filter, the reflection can be reduced and the visibility of the display image can be improved.

[0236] In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) to which a voltage is applied to the display element, the light extraction direction, the location where the electrode layer is provided, and the light transmittance and reflectivity may be selected according to the pattern structure of the electrode layer.

[0237] The first electrode layer 4030 and the second electrode layer 4031 can use a conductive material having light transmittance such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. It is possible to use.

[0238] ​In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed using one or more of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), and other metals , or alloys thereof, or metal nitrides thereof. .

[0239] In addition, as the first electrode layer 4030 and the second electrode layer 4031, a conductive composition containing a conductive polymer (also referred to as a conductive polymer) can be used. As the conductive polymer , so-called π-electron conjugated system conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives , or copolymers or derivatives thereof composed of two or more of aniline, pyrrole, and thiophene can be mentioned.

[0240] In addition, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element.

[0241] Note that, as shown in FIG. 27, a stack structure having a region where transistors and capacitor elements overlap in the height direction may be used. For example, by stacking the transistor 4011 and the transistor 4022 constituting the drive circuit, a display device with a narrow border can be obtained. Also, the transistor 4010, the transistor 4023, and the capacitor element 402 constituting the pixel circuit If they are arranged so as to have an overlapping region even partially, such as 0, the aperture ratio and resolution can be improved. This can be achieved. In FIG. 27, an example in which a stack structure is applied to the liquid crystal display device shown in FIG. 26(A) is shown, but it may also be applied to the EL display device shown in FIG. 26(B).

[0242] Also, in the pixel circuit, by using a transparent conductive film having high light transmittance with respect to visible light for electrodes and wirings, the light transmittance within the pixel can be increased, and substantially the aperture ratio can be improved. In addition, when using an OS transistor, since the semiconductor layer also has light transmittance, the aperture ratio can be further increased. These are effective even when the transistor or the like is not in a stack structure.

[0243] Also, a display device may be configured by combining a liquid crystal display device and a light emitting device.

[0244] The light emitting device is arranged on the reverse side of the display surface or at the end of the display surface. The light emitting device has a function of supplying light to the display element. The light emitting device can also be called a backlight.

[0245] Here, the light emitting device can have a plate-shaped or sheet-shaped light guide part (also referred to as a light guide plate) and a plurality of light emitting elements that exhibit different colors of light. When the light emitting elements are arranged near the side surface of the light guide part, light can be emitted from the side surface of the light guide part to the inside. The light guide part has a mechanism for changing the optical path ( also referred to as a light extraction mechanism), and thereby, the light emitting device can uniformly irradiate the pixel part of the display panel with light. Alternatively, a configuration may be adopted in which the light guide part is not provided and the light emitting device is arranged directly below the pixel.

[0246] The light emitting device preferably has light emitting elements of three colors: red (R), green (G), and blue (B). Yes. Furthermore, it may have a white (W) light-emitting element. As these light-emitting elements, light-emitting diodes (LEDs) are preferably used. Yes. Furthermore, it may have a white (W) light-emitting element. As these light-emitting elements, light-emitting diodes (LEDs) are preferably used. .

[0247] Furthermore, the light-emitting element preferably has a full width at half maximum (FWHM) of its emission spectrum of 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, which is a light-emitting element with extremely high color purity. Note that the full width at half maximum of the emission spectrum can be, for example, 1 nm or more. This allows for a vivid display with high color reproducibility when performing color display. at Half Maximum) of 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, which is a light-emitting element with extremely high color purity. Note that the full width at half maximum of the emission spectrum can be, for example, 1 nm or more. This allows for a vivid display with high color reproducibility when performing color display. Furthermore, the light-emitting element preferably has a full width at half maximum (FWHM) of its emission spectrum of 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, which is a light-emitting element with extremely high color purity. Note that the full width at half maximum of the emission spectrum can be, for example, 1 nm or more. This allows for a vivid display with high color reproducibility when performing color display. Furthermore, the light-emitting element preferably has a full width at half maximum (FWHM) of its emission spectrum of 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, which is a light-emitting element with extremely high color purity. Note that the full width at half maximum of the emission spectrum can be, for example, 1 nm or more. This allows for a vivid display with high color reproducibility when performing color display. Furthermore, the light-emitting element preferably has a full width at half maximum (FWHM) of its emission spectrum of 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, which is a light-emitting element with extremely high color purity. Note that the full width at half maximum of the emission spectrum can be, for example, 1 nm or more. This allows for a vivid display with high color reproducibility when performing color display. Furthermore, the light-emitting element preferably has a full width at half maximum (FWHM) of its emission spectrum of 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less, which is a light-emitting element with extremely high color purity. Note that the full width at half maximum of the emission spectrum can be, for example, 1 nm or more. This allows for a vivid display with high color reproducibility when performing color display.

[0248] Also, for the red light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 625 nm or more and 650 nm or less. For the green light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 515 nm or more and 540 nm or less. For the blue light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 445 nm or more and 470 nm or less. Also, for the red light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 625 nm or more and 650 nm or less. For the green light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 515 nm or more and 540 nm or less. For the blue light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 445 nm or more and 470 nm or less. Also, for the red light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 625 nm or more and 650 nm or less. For the green light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 515 nm or more and 540 nm or less. For the blue light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 445 nm or more and 470 nm or less. Also, for the red light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 625 nm or more and 650 nm or less. For the green light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 515 nm or more and 540 nm or less. For the blue light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 445 nm or more and 470 nm or less. Also, for the red light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 625 nm or more and 650 nm or less. For the green light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 515 nm or more and 540 nm or less. For the blue light-emitting element, it is preferable to use an element whose peak wavelength of the emission spectrum is in the range of 445 nm or more and 470 nm or less.

[0249] The display device can perform color display based on the sequential addition color mixing method by sequentially turning on and off the three-color light-emitting elements and driving the pixels in synchronization therewith. This driving method can also be called field sequential driving. The display device can perform color display based on the sequential addition color mixing method by sequentially turning on and off the three-color light-emitting elements and driving the pixels in synchronization therewith. This driving method can also be called field sequential driving. The display device can perform color display based on the sequential addition color mixing method by sequentially turning on and off the three-color light-emitting elements and driving the pixels in synchronization therewith. This driving method can also be called field sequential driving.

[0250] With field sequential driving, a vivid color image can be displayed. Also , a smooth moving image can be displayed. Also, by using the above driving method, it is not necessary to configure one pixel with a plurality of sub-pixels of different colors, and the effective reflection area (also referred to as the effective display area and aperture ratio) of one pixel can be increased, so that a bright display can be performed. Furthermore, since it is not necessary to provide a color filter for the pixel, the transmittance of the pixel can also be improved, and a brighter display can be further performed. Also, the manufacturing process can be simplified and the manufacturing cost can be reduced. It is not necessary to configure one pixel with a plurality of sub-pixels of different colors, and the effective reflection area (also referred to as the effective display area and aperture ratio) of one pixel can be increased, so that a bright display can be performed. Furthermore, since it is not necessary to provide a color filter for the pixel, the transmittance of the pixel can also be improved, and a brighter display can be further performed. Also, the manufacturing process can be simplified and the manufacturing cost can be reduced. Furthermore, since it is not necessary to provide a color filter for the pixel, the transmittance of the pixel can also be improved, and a brighter display can be further performed. Also, the manufacturing process can be simplified and the manufacturing cost can be reduced. Furthermore, since it is not necessary to provide a color filter for the pixel, the transmittance of the pixel can also be improved, and a brighter display can be further performed. Also, the manufacturing process can be simplified and the manufacturing cost can be reduced. Furthermore, since it is not necessary to provide a color filter for the pixel, the transmittance of the pixel can also be improved, and a brighter display can be further performed. Also, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0251] FIGS. 28(A) and (B) are schematic cross-sectional views of a display device capable of field sequential driving. On the substrate 4001 side of the display device, a backlight unit capable of emitting light of RGB colors is provided. In field sequential driving, since colors are expressed by time-division emission of RGB colors, a color filter is not required. On the substrate 4001 side of the display device, a backlight unit capable of emitting light of RGB colors is provided. In field sequential driving, since colors are expressed by time-division emission of RGB colors, a color filter is not required. On the substrate 4001 side of the display device, a backlight unit capable of emitting light of RGB colors is provided. In field sequential driving, since colors are expressed by time-division emission of RGB colors, a color filter is not required.

[0252] The backlight unit 4340a shown in FIG. 28(A) has a configuration in which a plurality of light emitting elements 4342 are provided via a diffusion plate 4352 directly below the pixels. The diffusion plate 4352 has a function of diffusing the light emitted from the light emitting elements 4342 toward the substrate 4001 side and equalizing the luminance within the display portion. A polarizing plate may be provided between the light emitting elements 4342 and the diffusion plate 4352 as needed. Also, if the diffusion plate 4352 is not necessary, it may not be provided. Also, a configuration in which the light shielding layer 4132 is omitted may be used. The backlight unit 4340a shown in FIG. 28(A) has a configuration in which a plurality of light emitting elements 4342 are provided via a diffusion plate 4352 directly below the pixels. The diffusion plate 4352 has a function of diffusing the light emitted from the light emitting elements 4342 toward the substrate 4001 side and equalizing the luminance within the display portion. A polarizing plate may be provided between the light emitting elements 4342 and the diffusion plate 4352 as needed. Also, if the diffusion plate 4352 is not necessary, it may not be provided. Also, a configuration in which the light shielding layer 4132 is omitted may be used. The backlight unit 4340a shown in FIG. 28(A) has a configuration in which a plurality of light emitting elements 4342 are provided via a diffusion plate 4352 directly below the pixels. The diffusion plate 4352 has a function of diffusing the light emitted from the light emitting elements 4342 toward the substrate 4001 side and equalizing the luminance within the display portion. A polarizing plate may be provided between the light emitting elements 4342 and the diffusion plate 4352 as needed. Also, if the diffusion plate 4352 is not necessary, it may not be provided. Also, a configuration in which the light shielding layer 4132 is omitted may be used. The backlight unit 4340a shown in FIG. 28(A) has a configuration in which a plurality of light emitting elements 4342 are provided via a diffusion plate 4352 directly below the pixels. The diffusion plate 4352 has a function of diffusing the light emitted from the light emitting elements 4342 toward the substrate 4001 side and equalizing the luminance within the display portion. A polarizing plate may be provided between the light emitting elements 4342 and the diffusion plate 4352 as needed. Also, if the diffusion plate 4352 is not necessary, it may not be provided. Also, a configuration in which the light shielding layer 4132 is omitted may be used. The backlight unit 4340a shown in FIG. 28(A) has a configuration in which a plurality of light emitting elements 4342 are provided via a diffusion plate 4352 directly below the pixels. The diffusion plate 4352 has a function of diffusing the light emitted from the light emitting elements 4342 toward the substrate 4001 side and equalizing the luminance within the display portion. A polarizing plate may be provided between the light emitting elements 4342 and the diffusion plate 4352 as needed. Also, if the diffusion plate 4352 is not necessary, it may not be provided. Also, a configuration in which the light shielding layer 4132 is omitted may be used. The backlight unit 4340a shown in FIG. 28(A) has a configuration in which a plurality of light emitting elements 4342 are provided via a diffusion plate 4352 directly below the pixels. The diffusion plate 4352 has a function of diffusing the light emitted from the light emitting elements 4342 toward the substrate 4001 side and equalizing the luminance within the display portion. A polarizing plate may be provided between the light emitting elements 4342 and the diffusion plate 4352 as needed. Also, if the diffusion plate 4352 is not necessary, it may not be provided. Also, a configuration in which the light shielding layer 4132 is omitted may be used.

[0253] Since the backlight unit 4340a can mount a large number of light emitting elements 4342, a bright display is possible. Also, a light guide plate is not required, and there is an advantage that the light efficiency of the light emitting elements 4342 is hardly impaired. If necessary, a lens 43 for light diffusion may be provided for the light emitting elements 4342. Since the backlight unit 4340a can mount a large number of light emitting elements 4342, a bright display is possible. Also, a light guide plate is not required, and there is an advantage that the light efficiency of the light emitting elements 4342 is hardly impaired. If necessary, a lens 43 for light diffusion may be provided for the light emitting elements 4342. Since the backlight unit 4340a can mount a large number of light emitting elements 4342, a bright display is possible. Also, a light guide plate is not required, and there is an advantage that the light efficiency of the light emitting elements 4342 is hardly impaired. If necessary, a lens 43 for light diffusion may be provided for the light emitting elements 4342. 44 may be provided.

[0254] The backlight unit 4340b shown in FIG. 28(B) has a diffusion plate 4352 directly under the pixels. The light guide plate 4341 is provided at the end of the light guide plate 4341. The light guide plate 4341 has an uneven shape on the side opposite to the diffusion plate 4352. The guided light can be scattered by the uneven surface and emitted in the direction of the diffusion plate 4352.

[0255] The light emitting element 4342 can be fixed to a printed circuit board 4347. ), the light emitting elements 4342 of each color of R, G, and B are illustrated overlapping each other, but The light emitting elements 4342 of the respective colors B and B can be arranged side by side. A reflective layer 4348 that reflects visible light is provided on the side opposite to the light emitting element 4342. It is okay.

[0256] The backlight unit 4340b can reduce the number of light-emitting elements 4342. It can be made low cost and thin.

[0257] The liquid crystal element may be a light scattering type liquid crystal element. It is preferable to use an element having a composite material of a liquid crystal and a polymer. For example, a polymer dispersed liquid crystal Alternatively, a polymer network liquid crystal (PNLC) A liquid crystal (LC) network element may also be used.

[0258] The light-scattering liquid crystal element is a liquid crystal layer in a three-dimensional network structure of a resin part sandwiched between a pair of electrodes. The liquid crystal portion is made of a material such as nematic liquid crystal. It can be used. Further, a photocurable resin can be used as the resin part. The photocurable resin , for example, monofunctional monomers such as acrylate and methacrylate, diacrylate, tri acrylate, polyfunctional monomers such as dimethacrylate and trimethacrylate, or a polymerizable compound obtained by mixing these can be used.

[0259] The light-scattering type liquid crystal element utilizes the anisotropy of the refractive index of the liquid crystal material to transmit or scatter light to perform display. Further, the resin part may also have anisotropy of the refractive index. When the liquid crystal molecules are aligned in a certain direction according to the voltage applied to the light-scattering type liquid crystal element , a direction in which the difference in refractive index between the liquid crystal part and the resin part becomes small is generated, and the light incident along the direction is scattered by the liquid crystal part and transmits without being scattered. Therefore, the light-scattering type liquid crystal element is visually recognized as a transparent state from the direction . On the other hand, when the alignment of the liquid crystal molecules becomes random according to the applied voltage, since a large change does not occur in the difference in refractive index between the liquid crystal part and the resin part , the incident light is scattered by the liquid crystal part. Therefore, the light-scattering type liquid crystal element becomes an opaque state regardless of the viewing direction .

[0260] FIG. 29(A) shows a configuration in which the liquid crystal element 4013 of the display device in FIG. 28(A) is replaced with a light-scattering type liquid crystal element 401 6. The light-scattering type liquid crystal element 4016 has a composite layer 4009 having a liquid crystal part and a resin part, and electrode layers 4030 and 4031 . The elements related to field-sequential driving are the same as those in FIG. 28(A), but when the light-scattering type liquid crystal element 4016 is used , the alignment film and the polarizing plate become unnecessary. Note that the spacer 4035 is shown in a spherical form in the figure , but it may be columnar .

[0261] FIG. 29(B) shows a configuration in which the liquid crystal element 4013 of the display device in FIG. 28(B) is replaced with a light-scattering liquid crystal element 401 6. In the configuration of FIG. 28(B), it is preferably configured to operate in a mode in which light is transmitted when no voltage is applied to the light-scattering liquid crystal element 4016 and light is scattered when a voltage is applied. By adopting such a configuration, a transparent display device can be obtained in the normal state (a state where display is not performed). In this case, color display can be performed when the operation of scattering light is performed. )

[0262] Modifications of the display device shown in FIG. 29(B) are shown in FIGS. 30(A) to (E). In FIGS. 30( A) to (E), for clarity, some elements of FIG. 29(B) are used and other elements are omitted and shown.

[0263] FIG. 30(A) shows a configuration in which the substrate 4001 has a function as a light guide plate. An uneven shape may be provided on the outer surface of the substrate 4001. In this configuration, since there is no need to separately provide a light guide plate, the manufacturing cost can be reduced. In addition, since there is no attenuation of light due to the light guide plate, the light emitted from the light-emitting element 4342 can be efficiently utilized.

[0264] FIG. 30(B) shows a configuration in which light is incident from the vicinity of the end of the composite layer 4009. Total reflection at the interface between the composite layer 400 9 and the substrate 4006 and at the interface between the composite layer 4009 and the substrate 4001 is utilized to emit light from the light-scattering liquid crystal element to the outside. A material having a refractive index larger than that of the substrate 4001 and the substrate 4006 is used for the resin portion of the composite layer 4009.

[0265] Note that the light-emitting element 4342 is not only provided on one side of the display device, but also as shown in FIG. 30(C) It may be provided on two sides facing each other. Further, it may be provided on three sides or four sides. The light-emitting element 43 By providing the 42 on a plurality of sides, light attenuation can be compensated for, and it is possible to cope with a large-area display element as well.

[0266] FIG. 30(D) shows a configuration in which the light emitted from the light-emitting element 4342 is guided to the display device via the mirror 4345 With this configuration, it is easy to guide light to the display device at a certain angle so that total reflection light can be obtained efficiently.

[0267] FIG. 30(E) shows a configuration having a stack of the layer 4003 and the layer 4004 on the composite layer 4009 One of the layer 4003 and the layer 4004 is a support such as a glass substrate, and the other can be formed of an inorganic film, an organic resin coating film, or a film. A material having a refractive index larger than that of the layer 4004 is used for the resin portion of the composite layer 40 09. Also, a material having a refractive index larger than that of the layer 4003 is used for the layer 4004 .

[0268] A first interface is formed between the composite layer 4009 and the layer 4004, and a second interface is formed between the layer 4004 and the layer 400 3. With this configuration, the light that has passed through without being totally reflected at the first interface can be totally reflected at the second interface and returned to the composite layer 4009. Therefore the light emitted from the light-emitting element 4342 can be used efficiently.

[0269] Note that the configurations in FIGS. 29(B) and 30(A) to (E) can be combined with each other .

[0270] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like . ​

[0271] (Embodiment 3) In this embodiment, an example of a transistor that can be used in place of each transistor shown in the above embodiment will be described with reference to the drawings.

[0272] The display device according to one aspect of the present invention can be manufactured using various types of transistors such as bottom gate type transistors and top gate type transistors. Therefore, it is possible to easily replace the material of the semiconductor layer and the transistor structure to be used according to the existing manufacturing line.

[0273] 〔Bottom Gate Type Transistor〕 FIG. 31(A1) is a cross-sectional view of a channel protection type transistor 810, which is a type of bottom gate type transistor, in the channel length direction. In FIG. 31(A1), the transistor 810 is formed on a substrate 771. Further, the transistor 810 has an electrode 746 via an insulating layer 772 on the substrate 771. Further, a semiconductor layer 742 is provided on the electrode 746 via an insulating layer 726. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.

[0274] Further, an insulating layer 741 is provided on the channel formation region of the semiconductor layer 742. Further, in contact with a part of the semiconductor layer 742, electrodes 744a and 744b are provided on the insulating layer 726. The electrode 744a can function as one of the source electrode or the drain electrode. The electrode 744b can function as the other of the source electrode or the drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741.

[0275] ​​​​​​​​​​​​​The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs during the formation of the electrode 744a and the electrode 744b is suppressed. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor having good electrical characteristics can be realized.

[0276] The transistor 810 includes an insulating layer 741 and an electrode 744a. A layer 728 is provided, and an insulating layer 729 is provided on the insulating layer 728 .

[0277] When an oxide semiconductor is used for the semiconductor layer 742, at least At least in the portion in contact with the semiconductor layer 742, oxygen is taken from a portion of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material capable of generating oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, which makes it n-type, and the region is called an n-type region (n + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742 to fill the oxygen vacancies. Examples of materials that can produce this include tungsten and titanium. do.

[0278] The source region and the drain region are formed in the semiconductor layer 742, whereby the electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0279] When using a semiconductor such as silicon for the semiconductor layer 742, between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b, it is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. The layer that functions as an n-type semiconductor or a p-type semiconductor can function as the source region or the drain region of a transistor.

[0280] The insulating layer 729 is preferably formed using a material having a function of preventing or reducing the diffusion of impurities from the outside into the transistor. Note that the insulating layer 729 can be omitted if necessary.

[0281] The transistor 811 shown in Fig. 31(A2) is different from the transistor 810 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729. The electrode 723 can be formed by the same materials and methods as the electrode 746.

[0282] Generally, the back gate electrode is formed of a conductive layer and is arranged so as to sandwich the channel formation region of the semiconductor layer between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as the potential of the gate electrode or may be a ground potential (GND potential) or an arbitrary potential. Also, by changing the potential of the back gate electrode independently without linking it to the potential of the gate electrode, the threshold voltage of the transistor can be changed. Furthermore, both the electrode 746 and the electrode 723 can function as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 each function as a gate insulating

[0283] layer. ​ It can function as a layer. Note that the electrode 723 is between the insulating layer 728 and the insulating layer 729 and may be provided there.

[0284] When one of the electrode 746 or the electrode 723 is referred to as the "gate electrode", the other is referred to as the "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as the "gate electrode" the electrode 746 is referred to as the "back gate electrode". Also, when the electrode 723 is used as the "gate electrode", the transistor 811 can be considered as a type of top-gate transistor. Also, either one of the electrode 746 and the electrode 723 may be referred to as the "first gate electrode" and the other as the "second gate electrode". By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, and further by setting the electrode 74

[0285] 6 and the electrode 723 to the same potential, the region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction, so the amount of carrier movement increases. As a result, the on-current of the transistor 811 increases and the field-effect mobility becomes higher. Therefore, the transistor 811 is a transistor having a large on-current with respect to the occupied area. That is, the occupied area of the transistor 811 can be made smaller with respect to the required on-current. According to one aspect of the present invention, the occupied area of the transistor can be made smaller.

[0286] Thus, according to one aspect of the present invention, a semiconductor device with a high degree of integration can be realized.

[0287]

[0287] Also, since the gate electrode and the back gate electrode are formed of a conductive layer, outside the transistor It has a function of preventing the generated electric field from acting on the semiconductor layer where the channel is formed (especially an electric field shielding function against static electricity etc.). Note that by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be enhanced .

[0288] Also, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the side of the back gate electrode. Therefore, it is possible to prevent light deterioration of the semiconductor layer and prevent deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor .

[0289] According to one aspect of the present invention, a transistor with good reliability can be realized. Also, a semiconductor device with good reliability can be realized.

[0290] FIG. 31(B1) is a cross-sectional view of the channel protection type transistor 82 0 in the channel length direction having a configuration different from that of FIG. 31(A1). The transistor 820 has substantially the same structure as the transistor 810, but is different in that the insulating layer 741 covers the end of the semiconductor layer 742 . Also, in the opening formed by selectively removing a part of the insulating layer 729 overlapping the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a are electrically connected. Also, in another opening formed by selectively removing a part of the insulating layer 729 overlapping the semiconductor layer 7 42, the semiconductor layer 742 and the electrode 744b are electrically connected. The region of the insulating layer 729 overlapping the channel formation region can function as a channel protection layer.

[0291] The transistor 821 shown in FIG. 31(B2) has a back gate electrode on the insulating layer 729 ​The point that it has the functional electrode 723 is different from the transistor 820.

[0292] By providing the insulating layer 729, it is possible to prevent the exposure of the semiconductor layer 742 that occurs when forming the electrodes 744a and 744b. Therefore, it is possible to prevent the thinning of the semiconductor layer 742 when forming the electrodes 744a and 744b. Moreover, the distance between the electrode 744a and the electrode 746, and the distance between the electrode 744b and the electrode 746 are longer than those of the transistors 810 and 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Also, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized.

[0293] Also, the transistors 820 and 821 have a longer distance between the electrode 744a and the electrode 746, and a longer distance between the electrode 744b and the electrode 746 than the transistors 810 and 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Also, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized. Moreover, the distance between the electrode 744a and the electrode 746, and the distance between the electrode 744b and the electrode 746 are longer than those of the transistors 810 and 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Also, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized. Moreover, the distance between the electrode 744a and the electrode 746, and the distance between the electrode 744b and the electrode 746 are longer than those of the transistors 810 and 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Also, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized. Moreover, the distance between the electrode 744a and the electrode 746, and the distance between the electrode 744b and the electrode 746 are longer than those of the transistors 810 and 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Also, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized. Moreover, the distance between the electrode 744a and the electrode 746, and the distance between the electrode 744b and the electrode 746 are longer than those of the transistors 810 and 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Also, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized.

[0294] The transistor 825 shown in FIG. 31(C1) is a cross-sectional view in the channel length direction of the channel etching type transistor 825 which is one of the bottom gate type transistors. The transistor 825 forms the electrodes 744a and 744b without using the insulating layer 729. Therefore, a part of the semiconductor layer 742 exposed when forming the electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 729 is not provided, the productivity of the transistor can be increased. Therefore, a part of the semiconductor layer 742 exposed when forming the electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 729 is not provided, the productivity of the transistor can be increased. Therefore, a part of the semiconductor layer 742 exposed when forming the electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 729 is not provided, the productivity of the transistor can be increased. Therefore, a part of the semiconductor layer 742 exposed when forming the electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 729 is not provided, the productivity of the transistor can be increased. Therefore, a part of the semiconductor layer 742 exposed when forming the electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 729 is not provided, the productivity of the transistor can be increased.

[0295] The transistor 825 shown in FIG. 31(C2) is different from the transistor 820 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729. The point that it has the functional electrode 723 is different from the transistor 820.

[0296] FIG. 32(A1) to (C2) respectively show cross-sectional views in the channel width direction of transistors 810, 811, 820, 821, 825, 826.

[0297] In the structures shown in FIGS. 32(B2) and (C2), the gate electrode and the back gate electrode are connected , and the potentials of the gate electrode and the back gate electrode become the same potential. Further, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0298] The length of each of the gate electrode and the back gate electrode in the channel width direction is longer than the length of the semiconductor layer 74 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is covered by the gate electrode or the back gate electrode with insulating layers 726, 741, 728, 729 interposed therebetween. That is the configuration.

[0299] With this configuration, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric fields of the gate electrode and the back gate electrode.

[0300] A device structure of a transistor in which a semiconductor layer 742 in which a channel formation region is formed is electrically surrounded by the electric fields of a gate electrode and a back gate electrode, such as transistor 821 or transistor 826, can be called a Surrounded channel (S-channel) structure. By adopting the S-channel structure, an electric field for inducing a channel by one or

[0301] both of the gate electrode and the back gate electrode can be effectively applied to the semiconductor layer 742, so that the current driving ability of the transistor is improved and high on-current characteristics can be obtained. ​​It becomes possible. Also, since it is possible to increase the on-current, it is possible to miniaturize the transistor. It becomes possible. Also, by adopting an S-channel structure, the mechanical strength of the transistor can be enhanced.

[0302] 〔Top-Gate Transistor〕 The transistor 842 illustrated in FIG. 33(A1) is one of the top-gate transistors. The transistor 842 is different from the transistor 830 and the transistor 840 in that the electrodes 744a and 7 44b are formed after the insulating layer 729 is formed. The electrodes 744a and 744b are electrically connected to the semiconductor layer 742 at the openings formed in the insulating layer 728 and the insulating layer 729.

[0303] Also, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and impurities 755 are introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask, so that impurity regions can be formed self-alignedly in the semiconductor layer 742. The transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 into which the impurities 755 are introduced through the insulating layer 726 is lower than that in the region into which the impurities 755 are introduced without passing through the insulating layer 726. The semiconductor layer 74 2 has an LDD (Lightly Doped Drain ) region formed in a region that does not overlap with the electrode 746.

[0304] The transistor 843 shown in FIG. 33(A2) is different from the transistor 84 2 in that it has an electrode 723. The transistor 843 has an electrode 723 formed on the substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. can function as a back gate electrode.

[0305] In addition, the transistor 844 shown in FIG. 33B1 and the transistor shown in FIG. As in the case of the electrode 845, the insulating layer 726 may be entirely removed from areas that do not overlap with the electrode 746. In addition, the transistor 846 shown in FIG. 33(C1) and the transistor shown in FIG. Insulating layer 726 may be left behind, as may layer 847.

[0306] After forming the electrode 746, the transistors 842 to 847 are also As a result, the semiconductor layer 742 is doped with impurities 755 using the mask. According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner. According to one aspect of the present invention, a transistor having good integration properties can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0307] In FIG. 34(A1) to (C2), transistors 842, 843, 844, 845, 846, 847 are cross-sectional views in the channel width direction.

[0308] The transistors 843, 845, and 847 are The S-channel structure described above is the same as that described above. However, the present invention is not limited to this. 3. The transistors 845 and 847 are not of S-channel structure. This is also fine.

[0309] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0310] (Embodiment 4) As an electronic device that can use the display device according to an aspect of the present invention, a display device, a personal computer, an image storage device or an image playback device equipped with a recording medium, a mobile phone, a mobile game machine including a portable type, a portable data terminal, an e-book terminal, a video camera, a digital still camera such as a camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction machine, a cash dispenser (ATM), a self- service vending machine, etc. are exemplified. Specific examples of these electronic devices are shown in FIG. 35.

[0311] FIG. 35(A) is a digital camera, which has a housing 961, a shutter button 962, a microphone 9 63, a speaker 967, a display unit 965, operation keys 966, a zoom lever 968, a lens 9 69, etc. By using the display device of an aspect of the present invention for the display unit 965, various images can be displayed.

[0312] FIG. 35(B) is a digital signage, which has a large display unit 922. For example, it is attached to the side surface of a pillar 9 21. By using the display device of an aspect of the present invention for the display unit 922 , a display with high display quality can be performed.

[0313] FIG. 35(C) is an example of a mobile phone, which has a housing 951, a display unit 952, operation buttons 953 , an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone is provided with a touch sensor on the display unit 952. When making a call or entering characters Any operation such as applying force is performed by touching the display unit 952 with a finger, a stylus, or the like. Also, the housing 901 and the display unit 952 are flexible and can be bent and used as shown in the figure. By using the display device according to an aspect of the present invention for the display unit 952, various images can be displayed.

[0314] FIG. 35(D) is a video camera and includes a first housing 901, a second housing 902, a display unit 903, operation keys 904, a lens 905, a connection part 906, a speaker 907, and the like. The operation keys 9 04 and the lens 905 are provided on the first housing 901, and the display unit 903 is provided on the second housing 9 02. By using the display device according to an aspect of the present invention for the display unit 903, various images can be displayed.

[0315] FIG. 35(E) is a television and includes a housing 971, a display unit 973, operation keys 974, a speaker 9 75, a communication connection terminal 976, a light sensor 977, and the like. A touch sensor is provided for the display unit 973, and an input operation can also be performed. By using the display device according to an aspect of the present invention for the display unit 973, various images can be displayed.

[0316] FIG. 35(F) is a portable data terminal and includes a housing 911, a display unit 912, a speaker 913, a camera 919, and the like. Input and output of information can be performed by the touch panel function of the display unit 912. By using the display device according to an aspect of the present invention for the display unit 912, various images can be displayed.

[0317] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like. It is possible.

Explanation of Reference Numerals

[0318] 10: Circuit, 11: Circuit, 12: Pixel block, 13: Source driver, 14a: Gate Driver, 14b: Gate driver, 15: Circuit, 20: Pixel, 101: Transistor, 102: Transistor, 103: Transistor, 104: Capacitor element, 105: Trans istor, 106: Transistor, 107: Capacitor element, 110: Circuit block, 111: Trans istor, 112: Transistor, 113: Capacitor element, 114: Light emitting element, 115: Trans istor, 116: Capacitor element, 117: Liquid crystal element, 118: Transistor, 119: Trans istor, 120: Circuit, 121: Wiring, 122: Wiring, 123: Wiring, 125: Wiring, 1 26: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 130: Wiring, 131: Wiring 、132: Wiring, 133: Wiring, 134: Wiring, 135: Wiring, 215: Display unit, 221 a: Scanning line drive circuit, 231a: Signal line drive circuit, 232a: Signal line drive circuit, 241a : Common line drive circuit, 723: Electrode, 726: Insulating layer, 728: Insulating layer, 729: Insulating layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 755: Impurity, 771: Substrate, 772: Insulating layer, 810: Transistor, 811: Trans istor, 820: Transistor, 821: Transistor, 825: Transistor, 82 6: Transistor, 830: Transistor, 840: Transistor, 842: Trans istor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Trans istor, 847: Transistor, 901: Housing, 902: Housing, 903: Display unit, 9 04: Operation key, 905: Lens, 906: Connection part, 907: Speaker, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Column, 922: Display unit, 9 51: Housing, 952: Display unit, 953: Operation button, 954: External connection port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter button , 963: Microphone, 965: Display unit, 966: Operation key, 967: Speaker, 968: Zoom lever, 969: Lens, 971: Housing, 973: Display unit, 974: Operation key, 97 5: Speaker, 976: Communication connection terminal, 977: Optical sensor, 4001: Substrate, 4003 : Layer, 4004: Layer, 4005: Sealing material, 4006: Substrate, 4008: Liquid crystal layer, 400 9: Composite layer, 4010: Transistor, 4011: Transistor, 4013: Liquid crystal element, 4014: Wiring, 4015: Electrode, 4016: Light-scattering type liquid crystal element, 4017: Electrode, 40 18: FPC, 4019: Anisotropic conductive layer, 4020: Capacitor element, 4021: Electrode, 402 2: Transistor, 4023: Transistor, 4030: Electrode layer, 4031: Electrode layer, 4 032: Insulating layer, 4033: Insulating layer, 4035: Spacer, 4041: Printed circuit board, 4 042: Integrated circuit, 4102: Insulating layer, 4103: Insulating layer, 4104: Insulating layer, 4110 : Insulating layer, 4111: Insulating layer, 4112: Insulating layer, 4131: Coloring layer, 4132: Light-shielding layer , 4133: Insulating layer, 4200: Input device, 4210: Touch panel, 4227: Electrode, 4228: Electrode, 4237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate, 4272b: FPC, 4273b: IC, 4340a: Backlight unit, 4340 b: Backlight unit, 4341: Light guide plate, 4342: Light-emitting element, 4344: Lens , 4345: Mirror, 4347: Printed circuit board, 4348: Reflective layer, 4352: Diffusion plate, 4510: Partition wall, 4511: Light-emitting layer, 4513: Light-emitting element, 4514: Filling material

Claims

1. A source driver; a pixel block electrically connected to the source driver; the pixel block includes a first circuit, a second circuit, and a third circuit; the first circuit includes a first transistor, a second transistor, and a first capacitance element; the second circuit includes a third transistor electrically connected to the first circuit, and a first circuit block electrically connected to the third transistor; the third circuit includes a fourth transistor electrically connected to the first circuit and a second circuit block electrically connected to the fourth transistor; the first circuit block includes a fifth transistor having a gate electrically connected to one of a source or a drain of the third transistor, a second capacitance element electrically connected between the gate and the other of the source or the drain of the fifth transistor, and a first light-emitting element electrically connected to the other of the source or the drain of the fifth transistor; the second circuit block includes a sixth transistor having a gate electrically connected to one of a source or a drain of the fourth transistor, a third capacitance element electrically connected between the gate and the other of the source or the drain of the sixth transistor, and a second light-emitting element electrically connected to the other of the source or the drain of the sixth transistor; the first transistor has a first gate and a second gate having an area overlapping the first gate; the second transistor has a third gate and a fourth gate having a region overlapping with the third gate; one of a source and a drain of the first transistor is electrically connected to the source driver; the other of the source and the drain of the first transistor is electrically connected to a first electrode of the first capacitance element; one of a source and a drain of the second transistor is electrically connected to a second electrode of the first capacitance element; The display device, wherein the first circuit has a function of adding second data to first data supplied from the source driver by capacitive coupling using the first capacitor.

2. A source driver; a pixel block electrically connected to the source driver; the pixel block includes a first circuit, a second circuit, and a third circuit; the first circuit includes a first transistor, a second transistor, and a first capacitance element; the second circuit includes a third transistor electrically connected to the first circuit, and a first circuit block electrically connected to the third transistor; the third circuit includes a fourth transistor electrically connected to the first circuit and a second circuit block electrically connected to the fourth transistor; the first circuit block includes a fifth transistor having a gate electrically connected to one of a source or a drain of the third transistor, a second capacitance element electrically connected between the gate and the other of the source or the drain of the fifth transistor, and a first light-emitting element electrically connected to the other of the source or the drain of the fifth transistor; the second circuit block includes a sixth transistor having a gate electrically connected to one of a source or a drain of the fourth transistor, a third capacitance element electrically connected between the gate and the other of the source or the drain of the sixth transistor, and a second light-emitting element electrically connected to the other of the source or the drain of the sixth transistor; the first transistor has a first front gate and a first back gate; the second transistor has a second front gate and a second back gate; one of a source and a drain of the first transistor is electrically connected to the source driver; the other of the source and the drain of the first transistor is electrically connected to a first electrode of the first capacitance element; one of a source and a drain of the second transistor is electrically connected to a second electrode of the first capacitance element; The display device, wherein the first circuit has a function of adding second data to first data supplied from the source driver by capacitive coupling using the first capacitor.

3. In claim 1 or 2, The display device, wherein the first light-emitting element has a function of performing display based on data obtained by adding second data to the first data.

4. In any one of claims 1 to 3, The second light-emitting element has a function of performing display based on data obtained by adding second data to the first data.

5. In any one of claims 1 to 4, each of the first transistor to the sixth transistor has a metal oxide in a channel formation region; The display device, wherein the metal oxide contains In.

6. In any one of claims 1 to 5, each of the first transistor to the sixth transistor has a metal oxide in a channel formation region; The display device, wherein the metal oxide comprises In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

Images