Semiconductor device

Abstract

To provide a semiconductor device having a structure capable of suppressing deterioration of electric characteristics which becomes noticeable at the time of miniaturization.SOLUTION: A semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film on the second oxide film, and a gate electrode in contact with the gate insulating film, and the upper end portion of the oxide semiconductor film in the channel width direction has a curved surface.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] A technology for constructing transistors using a semiconductor thin film formed on a substrate with an insulating surface. The transistor is being used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices such as the following: Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention as other materials. It is being done.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. is.

[0005] In addition, a technique for improving carrier mobility by forming an oxide semiconductor film into a stacked structure is also known. are disclosed in Patent Documents 2 and 3. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2006-165528 A [Patent Document 2] JP 2011-124360 A [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-138934

Summary of the Invention

Problems to be Solved by the Invention

[0007] Generally, in the high integration of circuits, miniaturization of transistors is an essential technology. On the other hand, when a transistor is miniaturized, it is known that the electrical characteristics of transistors such as on-current, threshold voltage, and S-value (sub-threshold value) deteriorate.

[0008] For example, in a transistor using silicon, when the channel length is shortened, short-channel effects such as deterioration of the sub-threshold coefficient (S-value) and variation of the threshold voltage to the negative side occur. It is known.

[0009] On the other hand, a transistor using an oxide semiconductor is a transistor (also referred to as an accumulation-type transistor) having an accumulation layer with electrons as majority carriers as a channel. Therefore, compared with a transistor (also referred to as an inversion-type transistor) having an inversion layer such as silicon as a channel, DIBL (Drain-Induced Barrier Lowering) in a short channel is less likely to occur. In other words, it can be said that a transistor using an oxide semiconductor has resistance to short-channel effects.

[0010] In addition, when the channel width of a transistor is reduced, a decrease in on-current is a concern. For the purpose of improving the on-current, a method of thickening the active layer so that a channel is also formed on the side surface of the active layer is also known. However, since the surface area where the channel is formed increases, carrier scattering increases at the interface between the channel formation region and the gate insulating film. Therefore, it is not easy to expect sufficient improvement in on-current. ​​​​​

[0011] Accordingly, one object of the present invention is to provide a semiconductor device having a configuration capable of suppressing a decrease in electrical characteristics that becomes significant with miniaturization. Or, one object is to provide a semiconductor device with a high degree of integration. Or, one object is to provide a semiconductor device with reduced deterioration of the on-current. Or, one object is to provide a semiconductor device with low power consumption. Or, one object is to provide a highly reliable semiconductor device. Or, one object is to provide a semiconductor device that retains data even when the power supply is cut off. Or, one object is to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc.

[0012] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0013] One aspect of the present invention relates to a semiconductor device having a stacked oxide semiconductor film.

[0014] One aspect of the present invention includes a first oxide film, an oxide semiconductor film on the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film on the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film on the second oxide film, and a gate electrode in contact with the gate insulating film. The upper end portion of the oxide semiconductor film in the channel width direction has a curved surface. A semiconductor device characterized by having the following structure.

[0015] Note that ordinal numbers such as "first" and "second" in this specification are used to avoid confusion between components, and it should be noted that they are not numerically limiting. For the purpose of avoiding confusion between components, and it should be noted that they are not numerically limiting.

[0016] Also, in the above structure, the upper surface of the oxide semiconductor film may have a flat portion.

[0017] Also, in the above structure, the radius of curvature r (when there are two end portions, r1 and r2 of each radius of curvature) of the end portion in the channel width direction of the oxide semiconductor film is greater than 0 and not more than half of the channel width W (0 < r (or r1, r2) ≤ W / 2). (0 < r (or r1, r2) ≤ W / 2).

[0018] Also, in the above structure, the upper end portion of the second oxide film may coincide with the lower end portion of the gate insulating film, and the upper end portion of the gate insulating film may coincide with the lower end portion of the gate electrode.

[0019] Also, in the above structure, the first oxide film and the second oxide film preferably have an energy of the lower end of the conduction band closer to the vacuum level in the range of 0.05 eV or more and 2 eV or less than that of the oxide semiconductor film. than that of the oxide semiconductor film, and the energy of the lower end of the conduction band is preferably in the range of 0.05 eV or more and 2 eV or less closer to the vacuum level. is preferable.

[0020] Also, in the above structure, a barrier film may be provided in contact with and covering the first oxide film, the oxide semiconductor film, the source electrode, the drain electrode, the second oxide film, the gate insulating film, and the gate electrode. covering the first oxide film, the oxide semiconductor film, the source electrode, the drain electrode, the second oxide film, the gate insulating film, and the gate electrode. may be provided.

[0021] Also, in the above structure, a first sidewall insulating film may be provided on the sidewalls of the first oxide film, the oxide semiconductor film, the source electrode, and the drain electrode via the barrier film. on the sidewalls of the first oxide film, the oxide semiconductor film, the source electrode, and the drain electrode via the barrier film.

[0022] Also, in the above configuration, a second sidewall insulating film provided on the sidewalls of the second oxide film, the gate insulating film, and the gate electrode via a barrier film may be provided.

Advantages of the Invention

[0023] By using one aspect of the present invention, it is possible to provide a semiconductor device having a configuration capable of suppressing a decrease in electrical characteristics that becomes significant with miniaturization. Or, it is possible to provide a semiconductor device with a high degree of integration. Or, it is possible to provide a semiconductor device with reduced deterioration of the on-current. Or, it is possible to provide a low-power consumption semiconductor device. Or, it is possible to provide a highly reliable semiconductor device. Or, it is possible to provide a semiconductor device that retains data even when the power supply is cut off. Or, it is possible to provide a novel semiconductor device. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0024]

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Embodiments for Carrying Out the Invention

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be varied in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same part or parts having the same or similar functions in different drawings, and the repeated description thereof may be

[0026] (Embodiment 1) In this embodiment, a semiconductor device according to an aspect of the present invention will be described with reference to the drawings.

[0027] FIGS. 1(A) to 1(C) are a top view and a cross-sectional view of a transistor according to an aspect of the present invention. FIG. 1(A) is a top view, and the cross-section along the dashed-dotted line A-B shown in FIG. 1(A) corresponds to FIG. 1(B), and the cross-section along the dashed-dotted line C-D corresponds to FIG. 1(C). In the top view of FIG. 1(A), some elements are omitted for clarity of the drawing. Also, the direction of the dashed-dotted line A-B may be referred to as the channel length direction, and the direction of the dashed-dotted line C-D may be referred to as the channel width direction. The channel length refers to the length in the direction in which carriers flow in the channel formation region. And the channel width refers to the length of the channel formation region in the direction perpendicular to the channel length direction.

[0028] The transistor 450 shown in FIGS. 1(A) to 1(C) includes a base insulating film 402 on a substrate 400, a first oxide film 404a and an oxide semiconductor film 404b on the base insulating film 402, source electrodes 406a and drain electrodes 406b on the first oxide film 404a and the oxide semiconductor film 404b, a second oxide film 404c on the oxide semiconductor film 404b, the source electrodes 406a, and the drain electrodes 406b, a gate insulating film 408 on the second oxide film 404c, a gate electrode 410 on the gate insulating film 408, and an oxide insulating film 412 on the source electrodes 406a, the drain electrodes 406b, and the gate electrode 410. The first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are collectively referred to as a multilayer film 404.

[0029] Also, when the channel length and channel width of the transistor are miniaturized, a resist mask ​There are cases where the ends of electrodes, semiconductor films, etc. to be processed have rounded (curved surfaces). The shape of the oxide semiconductor film 404b of the present embodiment has a rounded upper end when viewed from the cross-section, and is semi- circular. With such a configuration, the covering properties of the gate insulating film 408, the gate electrode 410, and the oxide insulating film 412 formed on the oxide semiconductor film 404b can be improved. Moreover, the electric field concentration that may occur at the ends of the source electrode 406a and the drain electrode 406b can be alleviated, and the deterioration of the transistor can be suppressed.

[0030] Note that the oxide semiconductor film 404b has a curvature composed of a contact circle with a radius of curvature of r. Note that the radius of curvature is equal to the radius of the contact circle of the curve. Also, the oxide semiconductor film 404b may have curvatures composed of different contact circles at two or more locations.

[0031] Specifically, the oxide semiconductor film 404b shown in FIG. 1 has a radius of curvature r1 at the upper end in the channel width direction, and a radius of curvature r2 at the upper end in the channel width direction that is separated from the upper end having the radius of curvature r1 by the channel width W. It is preferable that r1 and r2 are greater than 0 and less than or equal to half of the channel width W (0 < r1, r2 ≦ W / 2 ). Also, as shown in FIG. 6(C), when there is no flat portion on the upper surface of the oxide semiconductor film 404b in the channel width direction, it is preferable that the radius of curvature r3 of the upper end is greater than 0 and less than or equal to half of the channel width W (0 < r3 ≦ W / 2).

[0032] Note that the functions of "source" and "drain" of the transistor may be interchanged when different polarities of transistors are adopted, or when the direction of current changes in the circuit operation. exists. Therefore, in this specification, terms such as "source" and "drain" can be used interchangeably.

[0033] The substrate 400 is not limited to a mere support material and may be a substrate on which other devices such as other transistors are formed. In this case, at least one of the gate electrode 410, source electrode 406a, and drain electrode 406b of the transistor 450 may be electrically connected to the above-mentioned other devices.

[0034] The underlying insulating film 402 not only serves to prevent the diffusion of impurities from the substrate 400 but can also play a role in supplying oxygen to the multilayer film 404. Therefore, the underlying insulating film 402 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. Further, as described above, when the substrate 400 is a substrate on which other devices are formed, the underlying insulating film 402 also has a function as an interlayer insulating film. In that case, since irregularities are formed on the surface of the underlying insulating film 402, it is preferable to perform a planarization treatment by a method such as CMP (Chemical Mechanical Polishing) so that the surface becomes flat. ical Mechanical Polishing) method or the like.

[0035] Also, it is preferable to use an aluminum oxide film capable of supplying oxygen for the underlying insulating film 402. The aluminum oxide film can not only supply oxygen but also has a blocking effect on hydrogen, water, and oxygen. Note that an aluminum oxide film containing silicon oxide formed by using a target in which aluminum oxide and silicon oxide are mixed can also be used. At this time, the content of silicon oxide is 0.1 wt% or more and 30 wt% or less. ​​​​​​​​​​​​​is preferable.

[0036] Also, in the region where the channel of the transistor 450 is formed, the multilayer film 404 is formed on the substrate 400 side with a structure in which a first oxide film 404a, an oxide semiconductor film 404b, and a second oxide film 404 c are laminated. Further, the oxide semiconductor film 404b has a structure surrounded by the first oxide film 4 04a and the second oxide film 404c. Also, as shown in FIG. 1 (C), the gate electrode 410 has a structure that electrically surrounds the oxide semiconductor film 40 4b in the channel width direction.

[0037] Here, as an example, the oxide semiconductor film 404b uses an oxide semiconductor having a higher electron affinity (energy from the vacuum level to the lower end of the conduction band) than the first oxide film 404a and the second oxide film 404c. The electron affinity can be obtained as a value obtained by subtracting the energy difference (energy gap) between the lower end of the conduction band and the upper end of the valence band from the energy difference (ionization potential) between the vacuum level and the upper end of the valence band. The first oxide film 404a and the second oxide film 404c contain one or more metal elements constituting the oxide semiconductor film 404b. For example, the energy of the lower end of the conduction band is higher than that of the oxide semiconductor film 4 04b by any one of 0.05 eV, 0.07 eV, 0.1 eV, 0.15 eV or more and is preferably formed of an oxide semiconductor close to the vacuum level in the range of any one of 2 eV, 1 eV, 0.5 eV, 0.4 eV or less.

[0038] When an electric field is applied to the gate electrode 410 in such a structure, among the multilayer films 404 the first oxide film 404a and the second oxide film 404c contain one or more metal elements constituting the oxide semiconductor film 404b. For example, the energy of the lower end of the conduction band is higher than that of the oxide semiconductor film 4 04b by any one of 0.05 eV, 0.07 eV, 0.1 eV, 0.15 eV or more and is preferably formed of an oxide semiconductor close to the vacuum level in the range of any one of 2 eV, 1 eV, 0.5 eV, 0.4 eV or less. In such a structure, when an electric field is applied to the gate electrode 410, among the multilayer films 404

[0039] When an electric field is applied to the gate electrode 410 in such a structure, among the multilayer films 404 A channel is formed in the oxide semiconductor film 404b having the lowest energy at the lower end of the conduction band. . That is, since the second oxide film 40 4c is formed between the oxide semiconductor film 404b and the gate insulating film 408, the channel of the transistor is not in contact with the gate insulating film. It becomes a structure.

[0040] In addition, since the first oxide film 404a is composed of one or more metal elements constituting the oxide semiconductor film 404b, when the oxide semiconductor film 404b is in contact with the underlying insulating film 402, Compared with the interface, it is difficult to form interface levels at the interface between the oxide semiconductor film 404b and the first oxide film 404a. Since the interface levels may form a channel, The threshold voltage of the transistor may fluctuate. Therefore, by providing the first oxide film 404a, Variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0041] In addition, since the second oxide film 404c is composed of one or more metal elements constituting the oxide semiconductor film 404b, when the oxide semiconductor film 404b is in contact with the gate insulating film 408, Compared with the interface in this case, carrier scattering is less likely to occur at the interface between the oxide semiconductor film 404b and the second oxide film 404c. Therefore, by providing the second oxide film 404c, The field-effect mobility of the transistor can be increased.

[0042] The first oxide film 404a and the second oxide film 404c contain, for example, Al, Ti, G a, Ge, Y, Zr, Sn, La, Ce, or Hf at a higher concentration than the oxide semiconductor film 404b. Materials containing them in an atomic ratio can be used. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more. Since the above-mentioned elements strongly bond with oxygen, they have a function of suppressing the occurrence of oxygen deficiency in the oxide semiconductor film. That is, the first oxide film 404a and the second oxide film 404c can be said to be less likely to have oxygen deficiency than the oxide semiconductor film 404b.

[0043] In addition, when the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are In-M-Zn oxides containing at least indium, zinc, and M (metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), if the first oxide film 404a is In:M:Zn = x1:y1:z1 [atomic ratio], the oxide semiconductor film 404b is In:M:Zn = x2:y2:z2 [atomic ratio], and the second oxide film 404c is In:M: Zn = x 3: y 3: z3 [atomic ratio], it is preferable that y1 / x1 and y3 / x3 are larger than y2 / x 2. y1 / x1 and y3 / x3 are 1 .5 times or more, preferably 2 times or more, more preferably 3 times or more than y2 / x2. At this time, in the oxide semiconductor film 404b, when y2 is equal to or greater than x2, the electrical characteristics of the transistor can be stabilized. However, when y2 is 3 times or more of x2, the field-effect mobility of the transistor decreases, so it is preferable that y2 is less than 3 times of x2.

[0044] The atomic ratio of In to M excluding Zn and O in the first oxide film 404a and the second oxide film 404c is preferably less than 50 atomic% for In and 50 atomic % for M. ​​More than %, more preferably, In is less than 25 atomic% and M is 75 atomic% or more is set. Further, the atomic ratio of In to M excluding Zn and O in the oxide semiconductor film 404b is preferably such that In is 25 atomic% or more and M is less than 75 atomic%, more preferably such that In is 34 atomic% or more and M is less than 66 atomic%.

[0045] The thicknesses of the first oxide film 404a and the second oxide film 404c are 3 nm or more and 100 n m or less, preferably 3 nm or more and 50 nm or less. Further, the thickness of the oxide semiconductor film 404b is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50 nm or less.

[0046] For the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, for example, an oxide semiconductor containing indium, zinc, and gallium can be used. In particular, when indium is included in the oxide semiconductor film 404b, it is preferable because the carrier mobility increases .

[0047] Note that in order to impart stable electrical characteristics to a transistor having an oxide semiconductor film as a channel, it is effective to reduce the impurity concentration in the oxide semiconductor film and make the oxide semiconductor film intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor film is less than 1×10 17 / cm 3 , preferably less than 1×10 15 / cm 3 , and more preferably less than 1×10 13 / cm 3 .

[0048] ​In addition, part of hydrogen in the oxide semiconductor film is captured by oxygen vacancies, and the oxide semiconductor film becomes an n-type Therefore, the oxide semiconductor film containing a large amount of hydrogen becomes a highly purified intrinsic oxide semiconductor. The Fermi level (Ef) is closer to the conduction band edge (Ec) than the conductive film, The field effect mobility of the oxide semiconductor film is expected to be improved. Then, the Fermi energy of the oxide semiconductor film is the mid-gap (energy of the oxide semiconductor film) In this case, the oxidation There is concern that a decrease in the number of carriers contained in the semiconductor film may result in a decrease in field effect mobility.

[0049] However, in the transistor of one embodiment of the present invention, In addition to the gate field from the top, a gate field is applied from the side. A gate electric field is applied to the entire semiconductor film, and a current flows through the entire oxide semiconductor film. This allows the transistor to be manufactured while suppressing the fluctuation of electrical characteristics due to the high purity of the intrinsic material. It is possible to improve the field effect mobility of the sta.

[0050] In addition, in the oxide semiconductor film, hydrogen, nitrogen, carbon, silicon, and gold other than the main component are For example, hydrogen and nitrogen contribute to the formation of donor levels and carrier In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor film. The impurity levels become traps and may degrade the electrical characteristics of a transistor. Therefore, the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 4 It is preferable to reduce the impurity concentration in the 04c film and at the respective interfaces.

[0051] In order to make the oxide semiconductor film intrinsic or substantially intrinsic, a secondary ionization mass spectrometry (SIMS) method is used. In the case of the ion mass spectrometry (IMS) analysis, for example, oxide The silicon concentration at a certain depth in the conductor film or in a certain region of the oxide semiconductor film 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Not yet More preferably, 1×10 18 atoms / cm 3 The amount is less than the amount of the The hydrogen concentration is preferably, for example, at a certain depth in the oxide semiconductor film or In a certain region of the oxide semiconductor film, 20 atoms / cm 3 Hereinafter, preferably 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 It has the following parts: The nitrogen concentration is preferably, for example, at a certain depth in the oxide semiconductor film or , 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 It has the following parts: It is preferred.

[0052] In addition, when the oxide semiconductor film contains crystals, if silicon or carbon is contained at a high concentration, it may reduce the crystallinity of the oxide semiconductor film. In order not to reduce the crystallinity of the oxide semiconductor film, for example, at a certain depth of the oxide semiconductor film or in a certain region of the oxide semiconductor film, the silicon concentration is less than 1×10 atoms / cm , preferably less than 5×10 atoms / cm 19 , more preferably less than 1×10 3 atoms / cm 18 . It suffices to have a portion that is less than this. Also, for example, at a certain depth of the oxide semiconductor film or in a certain region of the oxide semiconductor film, the carbon concentration is less than 1×10 3 atoms / cm 18 , preferably less than 5×10 3 atoms / cm , more preferably less than 1×10 atoms / cm 19 . It suffices to have a portion that is less than this. 3 not satisfied, preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 a toms / cm 3 .

[0053] In addition, the off-current of a transistor using the oxide semiconductor film purified as described above in the channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm. Since an insulating film containing silicon is often used as the gate insulating film of the transistor, for the above reasons, it can be said that a structure in which the region serving as the channel of the multilayer film does not contact the gate insulating film is preferable as in the transistor of one aspect of the present invention. Also, the gate insulating film

[0054] ​ When a channel is formed at the interface with the multilayer film, carrier scattering occurs at this interface, and the field-effect mobility of the transistor may decrease. From this perspective as well, it can be said that the region that becomes the channel of the multilayer film is preferably separated from the gate insulating film. Therefore, by forming the multilayer film 404 into a stacked structure of a first oxide film 404a, an oxide semiconductor film 404b, and a second oxide film 404c, a channel can be formed in the oxide semiconductor film 404b, and a transistor having high field-effect mobility and stable electrical characteristics can be formed. Next, the band structure of the multilayer film 404 will be described. The analysis of the band structure is carried out by fabricating a stack corresponding to the multilayer film 404 using In-Ga-Zn oxide with an energy gap of 3.5 eV as the layers corresponding to the first oxide film 404a and the second oxide film 404c, and In-Ga-Zn oxide with an energy gap of 3.15 eV as the layer corresponding to the oxide semiconductor film 404b.

[0055] The film thicknesses of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are each 10 nm, and the energy gaps were measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300). Also, the energy difference between the vacuum level and the valence band top was measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus (PHI VersaProbe).

[0056]

[0057]

[0058] ​​​​​​​​​​​​​​Fig. 2(A) shows the energy difference between the vacuum level and the upper end of the valence band, and the energy difference (electron affinity) between the vacuum level and the lower end of the conduction band calculated as the difference from the energy gap of each layer, schematically showing a part of the band structure. Fig. 2(A) is a band diagram when a silicon oxide film is provided in contact with the first oxide film 404a and the second oxide film 404c. Here, Ev is the energy of the vacuum level, EcI1 and EcI2 are the energies of the lower ends of the conduction bands of the silicon oxide film, EcS1 is the energy of the lower end of the conduction band of the first oxide film 404a, EcS2 is the energy of the lower end of the conduction band of the oxide semiconductor film 404b, and EcS3 is the energy of the lower end of the conduction band of the second oxide film 404c. As shown in Fig. 2(A), in the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, the energies of the lower ends of the conduction bands change continuously. This can also be understood from the fact that since the compositions of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are approximated and oxygen diffuses easily among them. Therefore, although the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are laminated bodies of layers with different compositions, it can be said that they are physically continuous, and in the drawing, the respective interfaces of the laminate are represented by dotted lines. The multilayer film 404 laminated with a common main component is fabricated not simply by laminating each layer but by continuous bonding (here, a U-shaped well structure (U Shape Well) in which the energy of the lower end of the conduction band changes continuously between layers is formed). That is, there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of each layer. Here, Ev is the energy of the vacuum level, EcI1 and EcI2 are the energies of the lower ends of the conduction bands of the silicon oxide film, EcS1 is the energy of the lower end of the conduction band of the first oxide film 404a, EcS2 is the energy of the lower end of the conduction band of the oxide semiconductor film 404b, and EcS3 is the energy of the lower end of the conduction band of the second oxide film 404c. Here, Ev is the energy of the vacuum level, EcI1 and EcI2 are the energies of the lower ends of the conduction bands of the silicon oxide film, EcS1 is the energy of the lower end of the conduction band of the first oxide film 404a, EcS2 is the energy of the lower end of the conduction band of the oxide semiconductor film 404b, and EcS3 is the energy of the lower end of the conduction band of the second oxide film 404c. Here, Ev is the energy of the vacuum level, EcI1 and EcI2 are the energies of the lower ends of the conduction bands of the silicon oxide film, EcS1 is the energy of the lower end of the conduction band of the first oxide film 404a, EcS2 is the energy of the lower end of the conduction band of the oxide semiconductor film 404b, and EcS3 is the energy of the lower end of the conduction band of the second oxide film 404c. Here, Ev is the energy of the vacuum level, EcI1 and EcI2 are the energies of the lower ends of the conduction bands of the silicon oxide film, EcS1 is the energy of the lower end of the conduction band of the first oxide film 404a, EcS2 is the energy of the lower end of the conduction band of the oxide semiconductor film 404b, and EcS3 is the energy of the lower end of the conduction band of the second oxide film 404c. Here, Ev is the energy of the vacuum level, EcI1 and EcI2 are the energies of the lower ends of the conduction bands of the silicon oxide film, EcS1 is the energy of the lower end of the conduction band of the first oxide film 404a, EcS2 is the energy of the lower end of the conduction band of the oxide semiconductor film 404b, and EcS3 is the energy of the lower end of the conduction band of the second oxide film 404c.

[0059] As shown in Fig. 2(A), in the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, the energies of the lower ends of the conduction bands change continuously. This can also be understood from the fact that since the compositions of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are approximated and oxygen diffuses easily among them. Therefore, although the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are laminated bodies of layers with different compositions, it can be said that they are physically continuous, and in the drawing, the respective interfaces of the laminate are represented by dotted lines. As shown in Fig. 2(A), in the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, the energies of the lower ends of the conduction bands change continuously. This can also be understood from the fact that since the compositions of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are approximated and oxygen diffuses easily among them. Therefore, although the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are laminated bodies of layers with different compositions, it can be said that they are physically continuous, and in the drawing, the respective interfaces of the laminate are represented by dotted lines. As shown in Fig. 2(A), in the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, the energies of the lower ends of the conduction bands change continuously. This can also be understood from the fact that since the compositions of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are approximated and oxygen diffuses easily among them. Therefore, although the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are laminated bodies of layers with different compositions, it can be said that they are physically continuous, and in the drawing, the respective interfaces of the laminate are represented by dotted lines. As shown in Fig. 2(A), in the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, the energies of the lower ends of the conduction bands change continuously. This can also be understood from the fact that since the compositions of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are approximated and oxygen diffuses easily among them. Therefore, although the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are laminated bodies of layers with different compositions, it can be said that they are physically continuous, and in the drawing, the respective interfaces of the laminate are represented by dotted lines. As shown in Fig. 2(A), in the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, the energies of the lower ends of the conduction bands change continuously. This can also be understood from the fact that since the compositions of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are approximated and oxygen diffuses easily among them. Therefore, although the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are laminated bodies of layers with different compositions, it can be said that they are physically continuous, and in the drawing, the respective interfaces of the laminate are represented by dotted lines. As shown in Fig. 2(A), in the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, the energies of the lower ends of the conduction bands change continuously. This can also be understood from the fact that since the compositions of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are approximated and oxygen diffuses easily among them. Therefore, although the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are laminated bodies of layers with different compositions, it can be said that they are physically continuous, and in the drawing, the respective interfaces of the laminate are represented by dotted lines. As shown in Fig. 2(A), in the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, the energies of the lower ends of the conduction bands change continuously. This can also be understood from the fact that since the compositions of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are approximated and oxygen diffuses easily among them. Therefore, although the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are laminated bodies of layers with different compositions, it can be said that they are physically continuous, and in the drawing, the respective interfaces of the laminate are represented by dotted lines.

[0060] The multilayer film 404 laminated with a common main component is fabricated not simply by laminating each layer but by continuous bonding (here, a U-shaped well structure (U Shape Well) in which the energy of the lower end of the conduction band changes continuously between layers is formed). That is, there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of each layer. The multilayer film 404 laminated with a common main component is fabricated not simply by laminating each layer but by continuous bonding (here, a U-shaped well structure (U Shape Well) in which the energy of the lower end of the conduction band changes continuously between layers is formed). That is, there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of each layer. The multilayer film 404 laminated with a common main component is fabricated not simply by laminating each layer but by continuous bonding (here, a U-shaped well structure (U Shape Well) in which the energy of the lower end of the conduction band changes continuously between layers is formed). That is, there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of each layer. The multilayer film 404 laminated with a common main component is fabricated not simply by laminating each layer but by continuous bonding (here, a U-shaped well structure (U Shape Well) in which the energy of the lower end of the conduction band changes continuously between layers is formed). That is, there are no impurities that form defect levels such as trap centers or recombination centers at the interfaces of each layer. A stacked structure is formed. If impurities are mixed between the layers of the stacked multilayer film, the continuity of the energy band is lost, and carriers disappear due to trapping or recombination at the interface.

[0061] In FIG. 2(A), the case where EcS1 and EcS3 are the same is shown, but they may be different from each other. For example, when EcS1 has a higher energy than EcS3, a part of the band structure is shown as in FIG. 2(B).

[0062] For example, when EcS1 = EcS3, In:Ga:Zn = 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1:9:6 (atomic ratio) is used for the first oxide film 404a and the second oxide film 404c, and In :Ga:Zn = 1:1:1 or 3:1:2 (atomic ratio) of In-Ga-Zn oxide or the like is used for the oxide semiconductor film 404b. Also, when EcS1 > EcS3, In:Ga:Zn = 1:6:4 or 1:9:6 (atomic ratio) is used for the first oxide film 404 a, In:Ga:Zn = 1:1:1, 1:1:1.2, 1:1:1.5 or 3:1: 2 (atomic ratio) is used for the oxide semiconductor film 40 4b, and In:Ga:Zn = 1:3:2, 1:3:3 , 1:3:4 (atomic ratio) of In-Ga-Zn oxide or the like is used for the second oxide film 404c.

[0063] From FIGS. 2(A) and 2(B), it can be seen that the oxide semiconductor film 404b in the multilayer film 404 becomes a well (well), and in a transistor using the multilayer film 404, a channel is formed in the oxide semiconductor film 404b. Note that the multilayer film 404 has an energy at the lower end of the conduction band ​Since it changes continuously, it can also be called a U-shaped well. Also, with such a configuration The formed channel can also be called an embedded channel.

[0064] Note that near the interfaces of the first oxide film 404a and the second oxide film 404c with an insulating film such as a silicon oxide film, trap levels caused by impurities and defects can be formed. Due to the presence of the first oxide film 404a and the second oxide film 404c, the oxide semiconductor film 4 04b can be separated from the trap levels. However, when the energy difference between EcS1 or EcS3 and EcS2 is small, electrons in the oxide semiconductor film 404b may reach the trap levels across the energy difference. When electrons are trapped at the trap levels negative fixed charges are generated at the insulating film interface, and the threshold voltage of the transistor shifts in the positive direction and ends up shifting. Therefore, in order to reduce the variation in the threshold voltage of the transistor, it is necessary to provide an energy difference between EcS1 and Ec

[0065] S3 and EcS2. Each such energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more. Note that the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c preferably contain a crystalline part. In particular, by using a crystal oriented along the c-axis, stable electrical characteristics can be imparted to the transistor.

[0066] When In-Ga-Zn oxide is used for the multilayer film 404, in order to prevent the diffusion of In into the gate insulating film, the second oxide film 404c contains less In than the oxide semiconductor film 404b. Preferably, a crystal part is included. In particular, by using a crystal oriented along the c-axis, stable electrical characteristics can be imparted to the transistor.

[0067] When In-Ga-Zn oxide is used for the multilayer film 404, in order to prevent the diffusion of In into the gate insulating film, the second oxide film 404c contains less In than the oxide semiconductor film 404b. In order to prevent the diffusion of In into the gate insulating film, the second oxide film 404c contains less In than the oxide semiconductor film 404b. ​It is preferably made into a composition that does not contain it.

[0068] For the source electrode 406a and the drain electrode 406b, it is preferable to use a conductive material that easily binds to oxygen. For example, Al, Cr, Cu, Ta, Ti, Mo, W, etc. can be used. Among the above materials, particularly Ti that easily binds to oxygen, and since the subsequent process temperature can be relatively high, it is more preferable to use W with a high melting point. Note that the conductive material that easily binds to oxygen also includes a material in which oxygen easily diffuses. When a conductive material that easily binds to oxygen is brought into contact with the multilayer film, a phenomenon occurs in which oxygen in the multilayer film diffuses to the side of the conductive material that easily binds to oxygen. This phenomenon occurs more prominently as the temperature is higher. Since there are several heating steps in the manufacturing process of the transistor, due to the above phenomenon, oxygen deficiency occurs in the region near the source electrode or drain electrode of the multilayer film in contact, and the hydrogen contained slightly in the film binds to the oxygen deficiency, causing the region to become n-type. Therefore, the n-type region can be made to act as the source or drain of the transistor.

[0069] When a conductive material that easily binds to oxygen is brought into contact with the multilayer film, a phenomenon occurs in which oxygen in the multilayer film diffuses to the side of the conductive material that easily binds to oxygen. This phenomenon occurs more prominently as the temperature is higher. Since there are several heating steps in the manufacturing process of the transistor, due to the above phenomenon, oxygen deficiency occurs in the region near the source electrode or drain electrode of the multilayer film in contact, and the hydrogen contained slightly in the film binds to the oxygen deficiency, causing the region to become n-type. Therefore, the n-type region can be made to act as the source or drain of the transistor.

[0070] The above n-type region is shown in the enlarged cross-sectional view (cross-section in the channel length direction) of the transistor in FIG. 3. The boundary 435 indicated by the dotted line in the oxide semiconductor film 404b is the boundary between the intrinsic semiconductor region and the n-type semiconductor region, and the region near the contact with the source electrode 406a or the drain electrode 406b in the oxide semiconductor film 404b becomes the n-type region. Note that the boundary 43 5 is schematically shown and may not be clear in actuality. Also, in FIG. 3, the state where the boundary 435 is located so as to extend horizontally in the oxide semiconductor film 404b is shown. 5 is schematically shown and may not be clear in actuality. Also, in FIG. 3, the state where the boundary 435 is located so as to extend horizontally in the oxide semiconductor film 404b is shown. ​​​​​​ Therefore, the entire thickness direction of the region sandwiched between the source electrode 406a or the drain electrode 406b of the oxide semiconductor film 404b and the first oxide film 404a may be n-type. Also, although not shown, an n-type region may also be formed in the first oxide film 404a or the second oxide film 404c.

[0071] In addition, when forming a transistor with an extremely short channel length, the n-type region generated by the occurrence of the above oxygen deficiency may extend in the channel length direction of the transistor. In this case, a state where the threshold voltage shifts and the on / off control cannot be performed with the gate voltage (conductive state) appears in the electrical characteristics of the transistor. Therefore, when forming a transistor with an extremely short channel length, it is not always preferable to use a conductive material that easily binds to oxygen for the source electrode and the drain electrode. In such a case, it is preferable to use a conductive material that is less likely to bind to oxygen than the above-described materials for the source electrode 406a and the drain electrode 406b. As the conductive material, for example, a material containing tantalum nitride, titanium nitride, or ruthenium can be used. When the conductive material comes into contact with the oxide semiconductor film 404b, the source electrode 40

[0072] 6a and the drain electrode 406b may be configured by laminating the conductive material and the conductive material that easily binds to oxygen described above. For the gate insulating film 408, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide,

[0073] For the gate insulating film 408, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, ​​​​​Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and the like, can be used as the insulating film. Further, the gate insulating film 408 may be a laminate of the above materials.

[0074] The gate electrode 410 can be formed of a conductive film such as Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, and W. Further, the gate electrode may be a laminate of the above materials. Further, a conductive film containing nitrogen may be used for the gate electrode 410.

[0075] An oxide insulating film 412 may be formed on the gate insulating film 408 and the gate electrode 410. The oxide insulating film 412 may contain one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Further, the oxide insulating film 412 may be a laminate of the above materials.

[0076] Here, the oxide insulating film 412 preferably has excess oxygen. The oxide insulating film containing excess oxygen refers to an oxide insulating film that can release oxygen by heat treatment or the like. Preferably, by temperature programmed desorption gas spectrometry analysis, the oxygen release amount in terms of oxygen atoms is 1.0 ×10 19 atoms / cm 3 or more. The oxygen released from the oxide insulating film diffuses into the channel formation region of the multilayer film 404 via the gate insulating film 408. Therefore, even when an oxygen deficiency is formed in the channel formation region, oxygen can be replenished. Thus, stable electrical characteristics of the transistor can be obtained.

[0077] In addition, it is preferable to use an aluminum oxide film for the oxide insulating film 412. The aluminum oxide film can not only supply oxygen but also has a blocking effect on hydrogen, water, and oxygen. Note that an aluminum oxide film containing silicon oxide formed by using a target in which aluminum oxide and silicon oxide are mixed can also be used. At this time, the content of silicon oxide is preferably 0.1 wt% or more and 30 wt% or less. When miniaturizing the semiconductor device, miniaturization of the transistor is essential. On the other hand, it is known that the electrical characteristics of the transistor deteriorate due to miniaturization of the transistor, and in particular, the decrease in the on-current directly caused by the reduction of the channel width is significant. FIGS. 4(A) and 4(B) are cross-sectional views in the channel width direction of a conventional transistor using an oxide semiconductor film. The transistor has a base insulating film 220 on a substrate 210, an oxide semiconductor film 230 formed on the base insulating film, a gate insulating film 260 formed on the oxide semiconductor film, and a gate electrode 270. FIG. 4(A) shows a transistor in which the length (W

[0078] In order to highly integrate the semiconductor device, miniaturization of the transistor is essential. On the other hand, it is known that the electrical characteristics of the transistor deteriorate due to miniaturization of the transistor, and in particular, the decrease in the on-current directly caused by the reduction of the channel width is significant. When miniaturizing the semiconductor device, miniaturization of the transistor is essential. On the other hand, it is known that the electrical characteristics of the transistor deteriorate due to miniaturization of the transistor, and in particular, the decrease in the on-current directly caused by the reduction of the channel width is significant. When miniaturizing the semiconductor device, miniaturization of the transistor is essential. On the other hand, it is known that the electrical characteristics of the transistor deteriorate due to miniaturization of the transistor, and in particular, the decrease in the on-current directly caused by the reduction of the channel width is significant.

[0079] FIGS. 4(A) and 4(B) are cross-sectional views in the channel width direction of a conventional transistor using an oxide semiconductor film. The transistor has a base insulating film 220 on a substrate 210, an oxide semiconductor film 230 formed on the base insulating film, a gate insulating film 260 formed on the oxide semiconductor film, and a gate electrode 270. FIG. 4(A) shows a transistor in which the length (W In FIG. 4(A), the transistor has a base insulating film 220 on a substrate 210, an oxide semiconductor film 230 formed on the base insulating film, a gate insulating film 260 formed on the oxide semiconductor film, and a gate electrode 270. In FIG. 4(A), the transistor has a base insulating film 220 on a substrate 210, an oxide semiconductor film 230 formed on the base insulating film, a gate insulating film 260 formed on the oxide semiconductor film, and a gate electrode 270.

[0080] In FIG. 4(A), the transistor has a base insulating film 220 on a substrate 210, an oxide semiconductor film 230 formed on the base insulating film, a gate insulating film 260 formed on the oxide semiconductor film, and a gate electrode 270. In FIG. 4(A), the transistor has a base insulating film 220 on a substrate 210, an oxide semiconductor film 230 formed on the base insulating film, a gate insulating film 260 formed on the oxide semiconductor film, and a gate electrode 270. T ) of the upper surface of the oxide semiconductor film in the channel width direction is sufficiently larger than the film thickness of the oxide semiconductor film 230. In this case, the channel width can be defined as W In FIG. 4(A), the transistor has a base insulating film 220 on a substrate 210, an oxide semiconductor film 230 formed on the base insulating film, a gate insulating film 260 formed on the oxide semiconductor film, and a gate electrode 270. T without any problem.

[0081] The electric field applied from the gate electrode 270 to the side surface of the oxide semiconductor film 230 does not reach the entire oxide semiconductor film 230. Therefore, the formation of a channel on the side surface of the oxide semiconductor film 230 is insufficient. Also, the length (W S1 、W S 2) of the side surface corresponding to the film thickness of the oxide semiconductor film 230 has a small ratio to the length (W T ) of its upper surface. Therefore, even if a channel is formed, its contribution is estimated to be small. Thus, it can be said that the smaller W is, that is, the more miniaturized T it is, the lower the on-current.

[0082] Also, as shown in FIG. 4(B), in the case of a transistor in which W T is reduced to the same level as the film thickness of the oxide semiconductor film 230, the electric field applied from the gate electrode 270 to the side surface of the oxide semiconductor film 230 reaches the entire oxide semiconductor film 230. Therefore, a channel is also formed on the side surface of the oxide semiconductor film 230. Thus, an improvement in the on-current is expected by thickening the oxide semiconductor film 230 or the like. However, in a conventional transistor, carriers are scattered at the interface between the channel formation layer (oxide semiconductor film 230) and the gate insulating film 260. Therefore, the on-current is not sufficiently improved.

[0083] Also, depending on the film formation method, the film thickness (T ) of the gate insulating film 260 covering the side surface of the oxide semiconductor film 230 tends to be thinner than the film thickness (T GI2 ) of the gate insulating film covering the upper surface of the oxide semiconductor film. Therefore, a portion with a low dielectric breakdown voltage may locally occur in the gate insulating film 260, which may reduce the reliability of the transistor. GI1

[0084] Also, TGI1 and T GI2 Since they are different, the electric field applied from the gate electrode 270 to the oxide semiconductor film 230 varies. Therefore, the on-current may vary.

[0085] On the other hand, in the transistor according to one embodiment of the present invention, as described above, a second oxide film 404c is formed between the oxide semiconductor film 404b in which the channel is formed and the gate insulating film 408 and has a structure. Therefore, scattering of carriers generated at the interface between the channel formation layer and the gate insulating film can be suppressed, and the field-effect mobility of the transistor can be increased.

[0086] Also, in the transistor according to one embodiment of the present invention, since the second oxide film 404c is formed so as to cover the oxide semiconductor film 404b in which the channel is formed, carrier scattering can be suppressed also on the side surface of the oxide semiconductor film 404b as well as on the upper surface. That is, the transistor according to one embodiment of the present invention can have a higher on-current than a conventional transistor.

[0087] Therefore, the transistor according to one embodiment of the present invention exhibits excellent effects particularly in a structure in which W is reduced to about the same thickness as or less than the thickness of the oxide semiconductor film 404b, as shown in FIGS. 5(A) and 5(B). T

[0088] In the case of the transistor as shown in FIGS. 5(A) and 5(B), since the electric field applied from the gate electrode 170 to the side surface of the oxide semiconductor film 404b extends over the entire oxide semiconductor film 404b a channel equivalent to the channel formed on the upper surface is also formed on the side surface of the oxide semiconductor film 404b. ​​​​​​​​​​​

[0089] When the channel region 137 as shown in FIG. 5(A) is formed in the transistor, the channe l width is W T 、W S1 、and W S2 can be defined as the sum, and an on-current corresponding to the channel width flows in the transistor.

[0090] Also, in the case of a transistor in which W T is extremely small as shown in FIG. 5(B), the channel region 138 may be formed over the entire W T direction of the oxide semiconductor film 404b. In this case, since current flows over the entire oxide semiconductor film 404b, an extremely high on-current flows in the transistor. Also, in the transistor as shown in FIG. 5(A), when W 、W T 、W S 1 is sufficiently small, current flows over the entire oxide semiconductor film 404b.

[0091] Also, one of the features of the transistor according to one aspect of the present invention is that T GI1 and T G I2 in the gate insulating film 160 are substantially equal. Therefore, there is no variation in the electric field applied from the gate electrode 170 to the oxide semiconductor film 404b, and a uniform channel is formed on the upper surface and side surfaces of the oxide semiconductor film 404b. Accordingly, when it is estimated that a channel is formed only on the upper surface when W 、W S1 、W S2 is equivalent to W T 、an on-current about three times as large can be obtained as compared with the case where a channel is formed only on the upper surface. Also, when W 、W is twice that of W S1 、W S2 is W T 、when it is estimated that a channel is formed only on the upper surface ​Compared with the case where it is estimated to be formed, an on-current approximately five times as large can be obtained.

[0092] In addition, in the transistor according to one aspect of the present invention, T in the gate insulating film 160 GI1 and T G I2 are substantially the same, so that a portion with a low dielectric breakdown voltage is not locally generated in the gate insulating film 260, and a highly reliable transistor can be formed.

[0093] Note that, in order to efficiently improve the on-current of the transistor, W T / W S1 (W S2 ) = 3 Hereinafter, preferably, W T / W S1 (W S2 ) is around 1. Specifically, W T / W S1 ( W S2 ) is set to 0.7 to 1.3. When W T / W S1 (W S2 ) is greater than 3, the S value and the off-current may increase.

[0094] Therefore, the transistor according to one aspect of the present invention can obtain a sufficiently high on-current even when the transistor is miniaturized. Such a structure of a transistor in which an oxide semiconductor film is electrically surrounded by a gate electrode and the on-current is increased is also referred to as a surrounded d channel (s-channel) structure. d channel (s-channel) structure. d channel (s-channel) structure.

[0095] In addition, the transistor according to one aspect of the present invention has an effect of making it difficult to form interface levels by forming the oxide semiconductor film 404b on the first oxide film 4 04a, and an effect of being able to eliminate the influence of impurity mixing from above and below by using the oxide semiconductor film 404b as an intermediate layer of a three-layer structure, etc. and the like can be combined. It has. Therefore, the oxide semiconductor film 404b has a structure surrounded by the first oxide film 404a and the second oxide film 404c. In addition to the improvement of the on-current of the transistor described above, it is possible to stabilize the threshold voltage and reduce the S value. Therefore, Icut (the current when the gate voltage VG is 0V) can be lowered, and the power consumption can be reduced. Also, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved.

[0096] Also, the transistor according to one aspect of the present invention may include a conductive film between the underlying insulating film 120 and the substrate 110. By using the conductive film as the second gate electrode, a further increase in the on-current and control of the threshold voltage can be achieved. To increase the on-current, for example, the gate electrode 170 and the conductive film may be set to the same potential and driven as a dual-gate transistor. To control the threshold voltage, a constant potential different from that of the gate electrode 170 may be supplied to the conductive film.

[0097] Also, a transistor 460 as shown in FIG. 6 can be used. FIGS. 6(A) to 6(C) are a top view and a cross-sectional view of the transistor 460. FIG. 6(A) is a top view, and the cross-section along the dashed-dotted line A-B shown in FIG. 6(A) corresponds to FIG. 6(B), and the cross-section along the dashed-dotted line C-D corresponds to FIG. 6(C). In the top view of FIG. 6(A), some elements are omitted for clarity of the drawing.

[0098] The difference between FIG. 6 and FIG. 1 is whether there is a flat portion on the upper surface of the oxide semiconductor film 404b in the channel width direction as shown in FIG. 1(C). ​​​​​​​​​​​​​​​

[0099] The transistor 450 shown in FIG. 1 and the transistor 460 shown in FIG. 6 are made of an oxide semiconductor. A multilayer structure in which a solid oxide film 404b is sandwiched between a first oxide film 404a and a second oxide film 404c. However, the present invention is not limited to this. For example, a first transistor such as a transistor 470 shown in FIG. The oxide film 404a and the second oxide film 404c are not included, and only the oxide semiconductor film 404b is included. It may be in a certain configuration.

[0100] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0101] (Embodiment 2) In this embodiment, a method for manufacturing the transistor 450 illustrated in FIG. This will be described with reference to FIG. 8 and FIG.

[0102] First, a base insulating film 402 is formed on a substrate 400 (see FIG. 8(A)).

[0103] The substrate 400 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor Substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator It is also possible to use a substrate such as a silicon insulator, and semiconductor elements can be mounted on these substrates. may be used.

[0104] The base insulating film 402 is formed by depositing aluminum oxide by plasma CVD or sputtering. , magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide Oxide insulating films such as mu and tantalum oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride and other nitride insulating films, or films mixed with the above materials can be used to form. Also, a laminate of the above materials may be used, and at least the upper layer in contact with the multilayer film 4 04 is preferably formed of a material containing excessive oxygen that can be a source of oxygen supply to the multilayer film 404.

[0105] In addition, oxygen may be added to the underlying insulating film 402 by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. Adding oxygen can further facilitate the supply of oxygen from the underlying insulating film 402 to the multilayer film 404.

[0106] Note that if the surface of the substrate 400 is an insulator and there is no influence on the impurity diffusion to the multilayer film 404 to be provided later, the underlying insulating film 402 may not be provided.

[0107] Next, the first oxide film 404a and the oxide semiconductor film 404b are formed on the underlying insulating film 402 by sputtering, CVD method, MBE method, ALD method or PLD method (see Fig. 8( B)). At this time, as shown in the figure, the underlying insulating film 402 may be etched slightly excessively. By etching the underlying insulating film 402 excessively, it is possible to easily cover the second oxide film 404c with the gate electrode 410 to be formed later.

[0108] Note that when forming the first oxide film 404a and the oxide semiconductor film 404b in an island shape, first, a film serving as a hard mask (for example, a tungsten film) and ​​​​​​A resist mask is provided, and a film serving as a hard mask is etched to form a hard mask. Thereafter, the resist mask is removed, and using the hard mask as a mask, the first oxide film 404a , and the oxide semiconductor film 404b are etched. Thereafter, the hard mask is removed. At this time , as the hard mask gradually shrinks as etching progresses, the edge of the hard mask naturally becomes rounded and has a curved surface. Along with this, the shape of the oxide semiconductor film 404b also has a rounded edge and a curved surface. With such a configuration, the coverage of the second oxide film 404c, the gate insulating film 408, the gate electrode 410, and the oxide insulating film 412 formed on the oxide semiconductor film 404b is improved, and the occurrence of shape defects such as steps can be prevented. Also , the electric field concentration that may occur at the edges of the source electrode 406a and the drain electrode 406b can be relaxed, and the deterioration of the transistor can be suppressed.

[0109] Also, in order to form a continuous junction in the stack including the first oxide film 404a, the stack of the oxide semiconductor film 404b, and the second oxide film 404c formed in subsequent processes, it is necessary to continuously stack each layer without exposing them to the atmosphere using a multi-chamber type film forming apparatus (for example, a sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus should be evacuated to a high vacuum (from 5×10 Pa to about 1×10 Pa) using an adsorption type vacuum exhaust pump such as a cryopump to remove impurities such as water that are impurities for the oxide semiconductor as much as possible, and the substrate to be film formed should be heated to 100°C or higher, preferably -7 Pa or more to -4 500°C or higher. Or, a turbo molecular pump and a cold pump It is preferable to combine traps to prevent the gas containing carbon components, moisture, etc. from flowing back from the exhaust system into the chamber. It is preferable to prevent this.

[0110] In order to obtain a high-purity true oxide semiconductor, not only the chamber needs to be evacuated to a high vacuum, but also the high-purity of the sputtering gas is necessary. The oxygen gas and argon gas used as the sputtering gas should have a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By using the gas purified to such a high purity, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor film as much as possible. It can be prevented as much as possible.

[0111] For the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c formed in the subsequent process, the materials described in Embodiment 1 can be used. For example, for the first oxide film 404a, an In-Ga-Zn oxide with In:Ga:Zn = 1:3:4 or 1:3:2 [atomic ratio], for the oxide semiconductor film 404b, an In-Ga-Zn oxide with In:Ga:Zn = 1:1:1 [atomic ratio], and for the second oxide film 404c, an In-Ga-Zn oxide with In:Ga:Zn = 1 :3:4 or 1:3:2 [atomic ratio] can be used. .

[0112] In addition, the oxide semiconductors that can be used for the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c preferably contain at least indium (In) or zinc (Zn). Or it is preferable to contain both In and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistors using the oxide semiconductor, it is preferable to contain a stabilizer together with them.

[0113] ​Examples of stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), etc. Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc.

[0114] For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide can be used.

[0115] Here, for example, In-Ga-Zn oxide means an oxide having In, Ga, and Zn as main components. Also, it may contain metal elements other than In, Ga, and Zn. In this specification, a film composed of In-Ga-Zn oxide is also called an IGZO film. Also, it may contain metal elements other than In, Ga, and Zn. In this specification, a film composed of In-Ga-Zn oxide is also called an IGZO film.

[0116] Also, a material represented by InMO3(ZnO) m (m > 0 and m is not an integer) may be used. Here, M represents one or more metal elements selected from Ga, Fe, Mn, and Co. Also, a material represented by In2SnO5(ZnO) (n > 0 and n is an integer) may be used. n (n > 0 and n is an integer) may be used.

[0117] However, as described in detail in Embodiment 1, the first oxide film 404a and the second oxide film 404c are selected such that their electron affinity is smaller than that of the oxide semiconductor film 404b.

[0118] For forming the oxide film and the oxide semiconductor film, it is preferable to use a sputtering method. As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, etc. can be used. In particular, it is preferable to use the DC sputtering method because it can reduce dust generated during film formation and make the film thickness distribution uniform.

[0119] When using In-Ga-Zn oxide for the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c, for example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:1.2, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:1.2, In:Ga:Zn = ​​​​​​​​​1:1:1.5, In:Ga:Zn = 2:2:1, In:Ga:Zn = 3:1:2, In :Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:4, In:Ga:Zn = 1:4 :3, In:Ga:Zn = 1:5:4, In:Ga:Zn = 1:6:6, In:Ga:Z n = 2:1:3, In:Ga:Zn = 1:6:4, In:Ga:Zn = 1:9:6, In :Ga:Zn = 1:1:4, In:Ga:Zn = 1:1:2, any of the materials, the electron affinity of the first oxide film 404a and the second oxide film 404c is made smaller than that of the oxide semiconductor film 40 4b.

[0120] Note that, for example, the composition of the oxide with the atomic ratio of In, Ga, Zn being In:Ga:Zn = a:b:c (a + b + c = 1) is in the vicinity of the composition of the oxide with the atomic ratio of In:Ga:Zn = A:B:C (A + B + C = 1) means that a, b, c satisfy (a - A) 2 + (b - B) 2 + (c - C) 2 ≦ r 2 For example, r may be 0.05. The same applies to other oxides. .

[0121] Also, the oxide semiconductor film 404b preferably has a higher indium content than the first oxide film 404a and the second oxide film 40 4c. In an oxide semiconductor, mainly the s orbital of heavy metals contributes to carrier conduction. By increasing the indium content, more s orbitals overlap. Therefore, an oxide with a composition having more indium than gallium has a higher mobility than an oxide with a composition having indium equal to or less than gallium. Thus, by using an oxide with a high indium content for the oxide semiconductor film 404b, a transistor with high mobility can be realized. ​ It can be done.

[0122] Hereinafter, the structure of the oxide semiconductor film will be described.

[0123] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0124] Also, in this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system. To express.

[0125] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Cry stalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, etc.

[0126] First, the CAAC-OS film will be described.

[0127] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction. .

[0128] When the CAAC-OS film is observed by a transmission electron microscope (TEM: Transmission Elec tron Microscope), it is not possible to confirm a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary). Therefore, C The AAC-OS film can be said to be less likely to cause a decrease in electron mobility due to crystal grain boundaries.

[0129] When the CAAC-OS film is observed by TEM from a direction approximately parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0130] On the other hand, when the CAAC-OS film is observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM observation), it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0131] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, when electron diffraction (also referred to as nano-beam electron diffraction) using an electron beam of, for example, 1 nm or more and 30 nm or less is performed on the upper surface of the CAAC-OS film, spots are observed (see Fig. 37(A)).

[0132] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation.

[0133] When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) device, for example, in the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, the diffraction angle (2θ) has a peak near 31°. ​​​​​​​​This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a roughly vertical direction.

[0134] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to Even when φ is fixed at around 56° and scanned, no clear peak appears.

[0135] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layers confirmed by the cross-sectional TEM observation mentioned above are aligned in the same direction. Each layer of metal atoms arranged in a lattice pattern is parallel to the ab plane of the crystal.

[0136] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. Orientation is parallel to the normal vector of the top surface. When the shape of the film is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the forming surface or the upper surface.

[0137] Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the surface to be formed. Further, when impurities are added to the CA AC-OS film, the crystallinity of the region where the impurities are added changes, and regions with locally different crystallinities may be formed.

[0138] In the out-of-plane analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. The peak at around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°.

[0139] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, deprive the oxide semiconductor film of oxygen, disturbing the atomic arrangement of the oxide semiconductor film and becoming a factor in reducing the crystallinity. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), and when contained inside the oxide semiconductor film, they disturb the atomic arrangement of the oxide semiconductor film and become a factor in reducing the crystallinity. Note that the impurities contained in the oxide semiconductor film The pure substance may serve as a carrier trap or a carrier generation source.

[0140] In addition, the CAAC-OS film is an oxide semiconductor film with a low density of defect levels. For example, oxygen deficiencies in the oxide semiconductor film may serve as carrier traps or may become carrier generation sources by capturing hydrogen. In addition, the CAAC-OS film is an oxide semiconductor film with a low density of defect levels. For example, oxygen deficiencies in the oxide semiconductor film may serve as carrier traps or may become carrier generation sources by capturing hydrogen. In addition, the CAAC-OS film is an oxide semiconductor film with a low density of defect levels. For example, oxygen deficiencies in the oxide semiconductor film may serve as carrier traps or may become carrier generation sources by capturing hydrogen.

[0141] A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. A low impurity concentration and a low density of defect levels (few oxygen deficiencies) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film rarely has electrical characteristics in which the threshold voltage becomes negative (also referred to as normally-on). In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film may take a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0142] In addition, a transistor using the CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. In addition, a transistor using the CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0143] Next, a polycrystalline oxide semiconductor film will be described.

[0144] The polycrystalline oxide semiconductor film can have its crystal grains confirmed by an observation image obtained by TEM. The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, in a grain size of 2 nm or more and 3 00 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less in an observation image obtained by TEM. This is often the case. Further, the polycrystalline oxide semiconductor film may have its crystal grain boundaries confirmed by an observation image obtained by TEM.

[0145] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientations may be different between the plurality of crystal grains. Further, when performing structure analysis on the polycrystalline oxide semiconductor film using an XRD apparatus, for example, in the out-of-plane method analysis of a polycrystalline oxide semiconductor film having InGaZnO4 crystals, peaks around 2θ of 31°, peaks around 2θ of 36°, or other peaks may appear.

[0146] Since the polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Therefore, a transistor using the polycrystalline oxide semiconductor film has high field-effect mobility. However, impurities may segregate at the crystal grain boundaries of the polycrystalline oxide semiconductor film. Also, the crystal grain boundaries of the polycrystalline oxide semiconductor film become defect levels. Since the crystal grain boundaries of the polycrystalline oxide semiconductor film may become carrier traps or carrier generation sources, a transistor using the polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics compared to a transistor using a CAAC-OS film and may be a transistor with low reliability.

[0147] Next, the microcrystalline oxide semiconductor film will be described.

[0148] In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal parts contained in the microcrystalline oxide semiconductor film often have a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, a nano crystal (nc: nanocryst tal) having a size of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is an oxide semiconductor film called an nc-OS (nanocrystalline O xide Semiconductor) film. Also, the nc-OS film may not be able to clearly confirm the crystal grain boundaries in the observation image by, for example, T EM. The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is seen in the whole film.

[0149] Therefore, depending on the analysis method, the nc-OS film may not be distinguishable from the amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating the crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron diffraction (also called limited-field electron diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film When performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating the crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron diffraction (also called limited-field electron diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. When performing nano-beam electron diffraction on the nc-OS film, spots are observed. When this is done, there are cases where a region with high luminance is observed to draw a circle (in a ring shape). Also when nano-beam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed within the ring-shaped region (see Fig. 37(B)).

[0150] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Therefore the nc-OS film has a lower density of defect levels than the amorphous oxide semiconductor film. However the nc-OS film does not show regularity in the crystal orientation between different crystal parts. Therefore, the nc- OS film has a higher density of defect levels than the CAAC-OS film.

[0151] Therefore, the carrier density of the nc-OS film may be higher than that of the CAAC-OS film. An oxide semiconductor film with a high carrier density may have a high electron mobility. Therefore a transistor using the nc-OS film may have a high field-effect mobility. Also since the nc-OS film has a higher density of defect levels than the CAAC-OS film, there may be more carrier traps. Therefore, a transistor using the nc-OS film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using the CAAC- OS film. However, since the nc-OS film can be formed even when it contains relatively many impurities it is easier to form than the CAAC-OS film and may be suitably used depending on the application. Therefore, a semiconductor device having a transistor using the nc-OS film may be manufactured with high productivity.

[0152]

[0153] Next, the amorphous oxide semiconductor film will be described.

[0153] An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

[0154] In the observation image by TEM, no crystal part can be confirmed in the amorphous oxide semiconductor film.

[0155] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. plane method, no peak indicating a crystal plane is detected. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. semiconductor film, a halo pattern is observed. Also, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. semiconductor film, no spot is observed and a halo pattern is observed. is observed.

[0156] An amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. Also, an amorphous oxide semiconductor film is an oxide semiconductor film having a high density of defect levels.

[0157] An oxide semiconductor film with a high impurity concentration and a high density of defect levels is an oxide semiconductor film with many carrier traps and carrier generation sources. is an oxide semiconductor film with many carrier traps and carrier generation sources.

[0158] Therefore, the amorphous oxide semiconductor film may have a higher carrier density than the nc-OS film. Therefore, a transistor using the amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Therefore, it may be suitably used for a transistor that requires normally-on electrical characteristics. Since the amorphous oxide semiconductor film has a high density of defect levels, there may be many carrier traps. Therefore, when using the amorphous oxide semiconductor film Therefore, a transistor using the amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Therefore, it may be suitably used for a transistor that requires normally-on electrical characteristics. Since the amorphous oxide semiconductor film has a high density of defect levels, there may be many carrier traps. Therefore, when using the amorphous oxide semiconductor film Therefore, it may be suitably used for a transistor that requires normally-on electrical characteristics. Since the amorphous oxide semiconductor film has a high density of defect levels, there may be many carrier traps. Therefore, when using the amorphous oxide semiconductor film suitable for a transistor that requires normally-on electrical characteristics. The amorphous oxide semiconductor film may have many carrier traps because it has a high density of defect levels. Therefore, when using the amorphous oxide semiconductor film suitable for a transistor that requires normally-on electrical characteristics. The amorphous oxide semiconductor film may have many carrier traps because it has a high density of defect levels. Therefore, when using the amorphous oxide semiconductor film The transistor in question becomes a transistor with large fluctuations in electrical characteristics and low reliability compared to transistors using CAAC-OS films or nc-OS films. It becomes a transistor with large fluctuations in electrical characteristics and low reliability.

[0159] Next, the single-crystalline oxide semiconductor film will be described.

[0160] The single-crystalline oxide semiconductor film is an oxide semiconductor film with a low impurity concentration and a low density of defect levels (low oxygen deficiency ). Therefore, the carrier density can be lowered. Thus, a transistor using a single- crystalline oxide semiconductor film is less likely to have normally-on electrical characteristics. Also, since the single-crystalline oxide semiconductor film has a low impurity concentration and a low density of defect levels, the number of carrier traps may be reduced. Therefore, a transistor using a single-crystalline oxide semiconductor film becomes a transistor with small fluctuations in electrical characteristics and high reliability.

[0161] Note that the density of the oxide semiconductor film increases when the number of defects is small. Also, the density of the oxide semiconductor film increases when the crystallinity is high. Further, the density of the oxide semiconductor film increases when the concentration of impurities such as hydrogen is low. The single-crystalline oxide semiconductor film has a higher density than the CAAC-OS film. Also the CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. Also, the polycrystalline oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. Further, the microcrystalline oxide semiconductor film has a higher density than the amorphous oxide semiconductor film.

[0162] Note that the oxide semiconductor film may be a laminated film having two or more of, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a C AAC-OS film.

[0163] When the oxide semiconductor film has a plurality of structures, the structure can be analyzed by using nano-beam electron diffraction. There may be cases where analysis is possible.

[0164] FIG. 38(A) shows a transmission electron diffraction measurement apparatus having an electron gun chamber 10, an optical system 12 below the electron gun chamber 10, a sample chamber 14 below the optical system 12, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, a camera 18 installed in the observation chamber 20, and a film chamber 22 below the observation chamber 20. The camera 18 is installed facing the inside of the observation chamber 20. Note that the film chamber 22 may not be provided. It is not necessary to have a film chamber 22.

[0165] Also, FIG. 38(B) shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. 38(A). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 10 are irradiated onto a substance 28 disposed in the sample chamber 14 through the optical system 12. The electrons that have passed through the substance 28 enter a fluorescent plate 32 installed inside the observation chamber 20 through the optical system 16. In the fluorescent plate 32, a pattern corresponding to the intensity of the incident electrons appears, and thus the transmission electron diffraction pattern can be measured. The camera 18 is installed facing the fluorescent plate 32 and can photograph the pattern that appears on the fluorescent plate 32. The angle formed by the straight line passing through the center of the lens of the camera 18 and the center of the fluorescent plate 32 and the upper surface of the fluorescent plate 32 is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera

[0166] The camera 18 is installed facing the fluorescent plate 32 and can photograph the pattern that appears on the fluorescent plate 32. The straight line passing through the center of the lens of the camera 18 and the center of the fluorescent plate 32 and the upper surface of the fluorescent plate 32 form an angle of, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 18. However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera photographed by the camera 18 has a greater distortion. However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. If the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera ​​In some cases, the camera 18 may be installed in the film chamber 22. For example, the camera 18 may be installed in the film chamber 22 so as to face the incident direction of the electrons 24. In this case, a transmission electron diffraction pattern with little distortion can be taken from the back surface of the fluorescent plate 32. The sample chamber 14 is provided with a holder for fixing the substance 28 as the sample. The holder has a structure that allows electrons passing through the substance 28 to pass through. The holder may, for example, have a function of moving the substance 28 in the X-axis, Y-axis, Z-axis, etc. The moving function of the holder may have an accuracy of moving in a range such as 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less. These ranges may be set to an optimal range according to the structure of the substance 28. Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described.

[0167] For example, as shown in FIG. 38(B), by changing (scanning) the irradiation position of the electrons 24, which are nano-beams in the substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 28 is a CAAC-OS film, a diffraction pattern as shown in FIG. 37(A) is observed. Or, if the substance 28 is an nc-OS film, a diffraction pattern as shown in FIG. 37(B) is observed. By the way, even if the substance 28 is a CAAC-OS film, it may be partially an nc-OS film or the like. The holder may have a function of moving the substance 28 in the X-axis, Y-axis, Z-axis, etc. The moving function of the holder may have an accuracy of moving in a range such as 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less. These ranges may be set to an optimal range according to the structure of the substance 28. For example, as shown in FIG. 38(B), by changing (scanning) the irradiation position of the electrons 24, which are nano-beams in the substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 28 is a CAAC-OS film, a diffraction pattern as shown in FIG. 37(A) is observed.

[0168] Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described. Or, if the substance 28 is an nc-OS film, a diffraction pattern as shown in FIG. 37(B) is observed.

[0169] For example, as shown in FIG. 38(B), by changing (scanning) the irradiation position of the electrons 24, which are nano-beams in the substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 28 is a CAAC-OS film, a diffraction pattern as shown in FIG. 37(A) is observed. Or, if the substance 28 is an nc-OS film, a diffraction pattern as shown in FIG. 37(B) is observed. By the way, even if the substance 28 is a CAAC-OS film, it may be partially an nc-OS film or the like. At this time, if the substance 28 is a CAAC-OS film, a diffraction pattern as shown in FIG. 37(A) is observed.

[0170] By the way, even if the substance 28 is a CAAC-OS film, it may be partially an nc-OS film or the like. Therefore, the quality of the CAAC-OS film can be judged by the following: , the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CAA For example, in a high-quality CAAC-OS film, If present, the CAAC ratio is 60% or more, preferably 80% or more, and more preferably 90% or more. The diffraction pattern is different from that of the CAAC-OS film. The percentage of areas where CAAC is observed is denoted as the non-CAAC rate.

[0171] As an example, immediately after deposition (denoted as-depo), after heat treatment at 350°C or after 450°C After the heat treatment at ℃, the top surface of each sample with the CAAC-OS film was scanned and the transmission The diffraction patterns were acquired by scanning at a speed of 5 nm / s for 60 seconds. The diffraction pattern is observed and converted into still images every 0.5 seconds. The CAAC rate was derived. Note that the electron beam was a nano-beam electron with a probe diameter of 1 nm. A sagittal line was used.

[0172] The CAAC ratio for each sample is shown in Figure 39. The comparison is as-is and after heat treatment at 350°C. In all cases, the CAAC conversion rate is higher after heat treatment at 450°C. Heat treatment at high temperatures (e.g., 400°C or higher) reduces the non-CAAC ratio (C Here, the diffraction pattern is different from that of the CAAC-OS film. Most of the diffraction patterns were similar to those of the nc-OS film. Therefore, the regions with the same structure as the nc-OS membrane are redistributed due to the influence of the structures of the neighboring regions. This suggests that the α-amino acids have been converted into CAAC.

[0173] By using such a measurement method, it may be possible to analyze the structure of an oxide semiconductor film having a plurality of structures. This may be the case.

[0174] The CAAC-OS film can be formed, for example, by using a target for sputtering an oxide semiconductor that is polycrystalline. When ions collide with the sputtering target, the crystal regions contained in the sputtering target may cleave from the a-b plane and peel off as flat plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a-b plane. In this case, since the flat plate-shaped or pellet-shaped sputtering particles are charged, they do not aggregate in the plasma and reach the substrate while maintaining the crystal state, and a CAAC-OS film can be formed. When ions collide with the sputtering target, the crystal regions contained in the sputtering target may cleave from the a-b plane and peel off as flat plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a-b plane. In this case, since the flat plate-shaped or pellet-shaped sputtering particles are charged, they do not aggregate in the plasma and reach the substrate while maintaining the crystal state, and a CAAC-OS film can be formed. In this case, since the flat plate-shaped or pellet-shaped sputtering particles are charged, they do not aggregate in the plasma and reach the substrate while maintaining the crystal state, and a CAAC-OS film can be formed. In this case, since the flat plate-shaped or pellet-shaped sputtering particles are charged, they do not aggregate in the plasma and reach the substrate while maintaining the crystal state, and a CAAC-OS film can be formed.

[0175] After the formation of the oxide semiconductor film 404b, a first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or a reduced pressure state. After the formation of the oxide semiconductor film 404b, a first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or a reduced pressure state. After the formation of the oxide semiconductor film 404b, a first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or a reduced pressure state. In addition, the atmosphere of the first heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere. In addition, the atmosphere of the first heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere. By the first heat treatment, the crystallinity of the oxide semiconductor film 404b can be enhanced, and furthermore, impurities such as hydrogen and water can be removed from the underlying insulating film 402 and the first oxide film 404a. By the first heat treatment, the crystallinity of the oxide semiconductor film 404b can be enhanced, and furthermore, impurities such as hydrogen and water can be removed from the underlying insulating film 402 and the first oxide film 404a. Note that the first heating step may be performed before the etching for forming the oxide semiconductor film 404b.

[0176] Next, a source electrode 406a is formed on the first oxide film 404a and the oxide semiconductor film 404b. ​And a first conductive film serving as the drain electrode 406b is formed. As the first conductive film, A l, Cr, Cu, Ta, Ti, Mo, W, or an alloy material mainly composed of these can be used For example, a 100 nm titanium film is formed by a sputtering method or the like. Also, C A tungsten film may be formed by CVD method.

[0177] Next, the first conductive film is etched so as to be segmented on the oxide semiconductor film 404b, and the source electrode 406a and the drain electrode 406b are formed (see FIG. 8(C)). At this time, Due to the over-etching of the first conductive film, a part of the underlying insulating film 402 may be etched into a shape.

[0178] Next, a second oxide film 403c is formed on the first oxide film 404a, the oxide semiconductor film 404b, the source electrode 406a, and the drain electrode 406b.

[0179] Note that a second heat treatment may be performed after forming the second oxide film 403c. The second heat treatment can be performed under the same conditions as the first heat treatment. By the second heat treatment, hydrogen, water, and other impurities can be removed from the second oxide film 403c. Also, hydrogen, water, and other impurities can be further removed from the first oxide film 404a and the oxide semiconductor film 404b can be removed.

[0180] Next, an insulating film 407 serving as the gate insulating film 408 is formed on the second oxide film 403c (see FIG. 9(A)). For the insulating film 407, aluminum oxide, magnesium oxide, silicon oxide con, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide Magnesium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. can be used. Note that the insulating film 407 may be a laminate of the above materials. The insulating film 407 can be formed using a sputtering method, CVD method, MBE method, ALD method, or PLD method, etc. Also, for the gate insulating film 408, the raw material, temperature, pressure, distance between electrodes, input power, etc. are adjusted, and conditions are used to improve the coating property GI1 such that T GI2 and T are substantially equal, as shown in FIG. 5(A). For example, within the range where the film quality as the gate insulating film can be maintained, the coating property can be improved by forming the film under high temperature and high pressure conditions.

[0181] Next, a second conductive film 409 that becomes the gate electrode 410 is formed on the insulating film 407 (see FIG. 9(B)). As the second conductive film 409, Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or an alloy material having these as the main component can be used. The second conductive film 409 can be formed by a sputtering method, CVD method, etc. Also, as the second conductive film 409, a conductive film containing nitrogen may be used, or a laminate of a conductive film containing the above materials and a conductive film containing nitrogen may be used.

[0182] Next, using a resist mask for forming the gate electrode 410, the second conductive film 409 is selectively etched to form the gate electrode 410 (see FIG. 9(C)).

[0183] Subsequently, using the above resist mask or the gate electrode 410 as a mask, the insulating film 407 is selectively etched to form the gate insulating film 408. ​​

[0184] Subsequently, using the resist mask or the gate electrode 410 as a mask, the second oxide film 4 03c is etched to form the second oxide film 404c.

[0185] That is, the upper end portion of the second oxide film 404c coincides with the lower end portion of the gate insulating film 408, and the upper end portion of the gate insulating film 408 coincides with the lower end portion of the gate electrode 410. Note that although the gate insulating film 408 and the second oxide film 404c are formed using the gate electrode 4 10 as a mask, this is not limited thereto, and the gate insulating film 408 and the second oxide film 404c may be formed before the formation of the second conductive film 409.

[0186] Next, an oxide insulating film 412 is formed on the source electrode 406a, the drain electrode 406b, and the gate electrode 410 (see Fig. 1(B)). The oxide insulating film 412 can be formed using the same materials and methods as the underlying insulating film 402. As the oxide insulating film 412, an aluminum oxide film, a magnesium oxide film, a silicon oxide film, a silicon oxynitride film, a nitrided silicon oxide film, a silicon nitride film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, or an oxide insulating film containing nitrogen may be used. The oxide insulating film 412 can be formed using a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method, and it is preferable that the film contains an excessive amount of oxygen so as to supply oxygen to the multilayer film 404.

[0187] Alternatively, oxygen may be added to the oxide insulating film 412 using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Adding oxygen ​ This enables easier supply of oxygen from the oxide insulating film 412 to the multilayer film 404. This can be achieved.

[0188] Next, a third heat treatment may be performed. The third heat treatment can be carried out under the same conditions as the first heat treatment. By the third heat treatment, excess oxygen is more easily released from the underlying insulating film 402, the gate insulating film 408, and the oxide insulating film 412, and the oxygen deficiency in the multilayer film 404 can be reduced. In the above steps, the transistor 450 shown in FIG. 1 can be fabricated. Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0189]

[0190]

[0191] (Embodiment 3) In this embodiment, a transistor having a structure different from that of the transistor described in Embodiment 1 will be described.

[0192] FIGS. 14(A) to 14(C) are a top view and a cross-sectional view of a transistor according to an aspect of the present invention. FIG. 14(A) is a top view, and the cross-section along the dashed line A - B shown in FIG. 14(A) corresponds to FIG. 14(B), and the cross-section along the dashed line C - D corresponds to FIG. 14(C). In the top view of FIG. 14(A), some elements are omitted for clarity of the drawing. Also, the direction of the dashed line A - B may be referred to as the channel length direction, and the direction of the dashed line C - D may be referred to as the channel width direction.

[0193] The transistor 550 shown in FIGS. 14(A) to 14(C) includes an underlying insulating film 402 on a substrate 400, a first oxide film 404a and an oxide semiconductor film 404 on the underlying insulating film 402. ​b, the source electrodes 406a on the first oxide film 404a and the oxide semiconductor film 404b, and the drain electrodes 406b, the second oxide film 404c on the oxide semiconductor film 404b, the source electrodes 406a, and the drain electrodes 406b, the gate insulating film 408 on the second oxide film 404c, the gate electrode 410 on the gate insulating film 408, the barrier film 414 on the source electrodes 406a, the drain electrodes 406b, the second oxide film 404c, and the gate electrode 410, the sidewall insulating film 416 that covers the sidewalls of the first oxide film 404a, the oxide semiconductor film 404b, the source electrodes 406a, and the drain electrodes 406b via the barrier film 414, the sidewall insulating film 418 that covers the sidewalls of the second oxide film 404c, the gate insulating film 408, and the gate electrode 410 via the barrier film 414, the oxide insulating film 412 on the source electrodes 406a, the drain electrodes 406b, the gate electrode 410, the sidewall insulating film 416, and the sidewall insulating film 418, the electrodes 419a and 419b that are embedded in the opening provided in the oxide insulating film 412 and are electrically connected to the source electrodes 406a and the drain electrodes 406b, and the wirings 420a and 420b that are electrically connected to the electrodes 419a and 419b. Also, the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are collectively referred to as the multilayer film 404.

[0194]

[0195] Also, the shape of the oxide semiconductor film 404b is such that the ends are rounded and it is shaped like a semicircle. With such a configuration, the coverage of the gate insulating film 408 and the gate electrode 410 formed on the oxide semiconductor film 404b can be improved.

[0195] ​​The barrier film 414 is preferably formed of an insulating film having a blocking effect on hydrogen, water, and oxygen, and is typically formed of an aluminum oxide film. The aluminum oxide film is an insulating film that can supply oxygen in addition to the blocking effect. Note that an aluminum oxide film containing silicon oxide formed by depositing a target mixture of aluminum oxide and silicon oxide can also be used. At this time, the content of silicon oxide is preferably 0.1 wt% or more and 30 wt% or less. In addition, since the coverage of the barrier film 414 in contact with the sidewalls of the multilayer film 404 and the gate electrode 410 may be poor, it is possible to block hydrogen, water, and oxygen by covering that portion with the sidewall insulating films 416 and 418. The sidewall insulating films 416 and 418 can be made of the same material as the underlying insulating film 402 and the gate insulating film 408. The electrodes 419a and 419b are electrically connected to the source electrode 406a and the drain electrode 406b. In addition, the wirings 420a and 420b are electrically connected to the electrodes 419a and 419b. When performing microfabrication, when openings are provided in the oxide insulating film 412 and the wirings 420a and 420b are to be formed so as to be electrically connected to the source electrode 406a and the drain electrode 406b through the openings, the wirings 420a and 420b do not reach the bottom of the openings and cannot be electrically connected. Therefore, first, the openings need to be filled with the electrodes 419a and 419b, and then the wirings 420a and 420b need to be formed. Note that the source electrode 406a and the drain electrode 406b are in contact with

[0196]

[0197] If wirings 420a and 420b are made of a material that enables this, electrodes 419a and there is no need to use electrode 419a.

[0198] Electrodes 419a, 419b, wirings 420a and 420b can use the same materials as source electrode 406a, drain electrode 406b and gate electrode 410.

[0199] Moreover, a configuration without sidewall insulating film 416 such as transistor 560 shown in Fig. 18(A) may be adopted. Also, a configuration without sidewall insulating film 416 and sidewall insulating film 418 such as transistor 570 shown in Fig. 18(B)

[0200] Furthermore, a configuration in which electrodes 419a and 41 9b reach source electrode 406a and drain electrode 406b such as transistor 580

[0201] shown in Fig. 18(C) may be adopted. Note that this embodiment can be appropriately combined with other embodiments

[0202] (Embodiment 4) In this embodiment, the method for manufacturing transistor 550 shown in Fig. 14 described in Embodiment 3 will be described with reference to Figs. 15 to 17.

[0203] First, an underlayer insulating film 402, a first oxide film 403a, and an oxide semiconductor film 403b are formed on substrate 400 (see Fig. 15(A)). The materials and manufacturing methods of substrate 400, underlayer insulating film 402, first oxide film 403a, and oxide semiconductor film 403b can refer to the previous

[0204] Next, a conductive film serving as a source electrode 406a and a drain electrode 406b is formed on the oxide semiconductor film 403b, and only the portion overlapping with the portion to be the channel region is etched to form a conductive film 405a and a conductive film 405b (see FIG. 15(B)). The material and manufacturing method of the conductive film serving as the source electrode 406a and the drain electrode 406b can refer to the previous embodiments. 405a and a conductive film 405b (see FIG. 15(B)). The material and manufacturing method of the conductive film serving as the source electrode 406a and the drain electrode 406b can refer to the previous embodiments. 405a and a conductive film 405b (see FIG. 15(B)). The material and manufacturing method of the conductive film serving as the source electrode 406a and the drain electrode 406b can refer to the previous embodiments. 405a and a conductive film 405b (see FIG. 15(B)). The material and manufacturing method of the conductive film serving as the source electrode 406a and the drain electrode 406b can refer to the previous embodiments.

[0205] Next, a resist mask is formed on the conductive film 405a and the conductive film 405b, and the first oxide film 403a, the oxide semiconductor film 403b, the conductive film 405a, and the conductive film 405b are selectively etched to form a first oxide film 404a, an oxide semiconductor film 404b, a source electrode 406 405a and a conductive film 405b (see FIG. 15(B)). The material and manufacturing method of the conductive film serving as the source electrode 406a and the drain electrode 406b can refer to the previous embodiments. a and a drain electrode 406b (see FIG. 15(B)). At this time, since the resist is thin and is formed finely so as to gradually shrink as etching progresses, the conductive film 4 05a and the conductive film 405b may naturally have rounded ends and a curved surface. By having such a configuration, the coverage of the second oxide film 404c, the gate insulating film 408, the gate electrode 410, and the oxide insulating film 412 formed on the source electrode 406a and the drain electrode 406b is improved, and the occurrence of shape defects such as steps can be prevented. 05a and the conductive film 405b may naturally have rounded ends and a curved surface. By having such a configuration, the coverage of the second oxide film 404c, the gate insulating film 408, the gate electrode 410, and the oxide insulating film 412 formed on the source electrode 406a and the drain electrode 406b is improved, and the occurrence of shape defects such as steps can be prevented. 412 formed on the source electrode 406a and the drain electrode 406b is improved, and the occurrence of shape defects such as steps can be prevented. 412 formed on the source electrode 406a and the drain electrode 406b is improved, and the occurrence of shape defects such as steps can be prevented.

[0206] Next, a second oxide film 403c and an insulating film 407 are formed on the first oxide film 404a, the oxide semiconductor film 404b, the source electrode 406a, and the drain electrode 406b (see FIG. 16(A)). The material and manufacturing method of the second oxide film 403c and the insulating film 407 can refer to the previous embodiments. 405a and a conductive film 405b (see FIG. 15(B)). The material and manufacturing method of the conductive film serving as the source electrode 406a and the drain electrode 406b can refer to the previous embodiments. 405a and a conductive film 405b (see FIG. 15(B)). The material and manufacturing method of the conductive film serving as the source electrode 406a and the drain electrode 406b can refer to the previous embodiments.

[0207] Note that a second heat treatment may be performed after forming the second oxide film 403c. The second heat treatment can be performed under the same conditions as the first heat treatment. By the second heat treatment, impurities such as hydrogen and water can be removed from the second oxide film 404c. Further, impurities such as hydrogen and water can be removed from the first oxide film 404a and the oxide semiconductor film 404b.

[0208] Next, a second conductive film that will become the gate electrode 410 is formed on the insulating film 407, and the second conductive film is selectively etched using a resist mask to form the gate electrode 410 (see FIG. 16(B)). The material and manufacturing method of the gate electrode 410 can refer to the previous embodiment.

[0209] Subsequently, the insulating film 407 is selectively etched using the resist mask or the gate electrode 410 as a mask to form the gate insulating film 408.

[0210] Subsequently, the second oxide film 403c is etched using the resist mask or the gate electrode 410 as a mask to form the second oxide film 404c.

[0211] Next, a barrier film 414 is formed on the base insulating film 402, the source electrode 406a, the drain electrode 406b, and the gate electrode 410 (see FIG. 16(C)).

[0212] Since the barrier film 414 is an insulating film having a blocking effect on hydrogen, water, and oxygen, it is possible to suppress the diffusion of oxygen contained in the multilayer film 404, the base insulating film 402, and the gate insulating film 408 to the outside, and efficiently supply oxygen to the oxide semiconductor film to adjust the oxygen deficiency amount. ​​​​​​​Therefore, the electrical characteristics are improved, and a highly reliable semiconductor device can be provided. It is possible.

[0213] Next, the insulating films that will become the sidewall insulating film 416 and the sidewall insulating film 418 are subjected to highly anisotropic etching. By performing the bonding process, the multilayer film 404, the source electrode 406a, A sidewall insulating film is formed on the side surfaces of the drain electrode 406b, the gate insulating film 408, and the gate electrode 410. 416, and a sidewall insulating film 418 can be formed (see FIG. 17(A)).

[0214] Next, the oxide insulating film 412 is formed over the barrier film 414 (see FIG. 17B). The above embodiment can be referred to for a material and a manufacturing method of the insulating film 412.

[0215] Next, a third heat treatment may be performed. The third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed under the following conditions. Therefore, excess oxygen is easily released from the oxide insulating film 412, and oxygen vacancies in the multilayer film 404 are reduced. It can be reduced.

[0216] Next, openings are formed in the oxide insulating film 412 and the barrier film 414, and The source electrode 406a and the drain electrode 406b are electrically connected to the opening. Electrodes 419a and 419b are formed corresponding to each other.

[0217] The electrodes 419a and 419b are embedded in the openings. As a means for embedding the electrode 419b, the electrode 41 is formed on the oxide insulating film 412 and in the opening. A conductive film that will become the electrodes 9a and 419b is formed, and the conductive film is subjected to a removal (polishing) process. Next, a part of the conductive film is removed so that the oxide insulating film 412 is exposed (see Fig. 17(C)). )

[0218] As a removal method, it is preferable to use a chemical mechanical polishing (CMP) process.

[0219] In this embodiment, the CMP process is used to remove a part of the conductive film, but other removal processes may be used. Alternatively, a polishing process such as the CMP process and an etching (dry etching, wet etching) process, a plasma process, etc. may be combined. For example, after the CMP process, a dry etching process or a plasma process (such as reverse sputtering) may be performed to improve the flatness of the processing surface. In the removal process, when an etching process, a plasma process, etc. are combined with the CMP process, the process order is not particularly limited and may be appropriately set according to the material, film thickness, and surface unevenness state of the conductive film. Also, most of the conductive film may be removed by the CMP process, and the remaining conductive film may be removed by a dry etching process or the like.

[0220] Note that the CMP process may be performed only once or multiple times. When performing the CMP process in multiple steps, it is preferable to perform a primary polishing with a high polishing rate first, and then a finishing polishing with a low polishing rate. By combining polishings with different polishing rates in this way, the flatness of the surface of the conductive film (electrodes 419a, 419b) can be further improved.

[0221] Next, wirings 420a and 420b that are electrically connected to the electrodes 419a and 419b are formed on the oxide insulating film 412, the electrodes 419a, and the electrodes 419b (see Fig. 14(B)). ​​​​​​​ ).

[0222] Through the above steps, a transistor 550 illustrated in FIG. 14 can be manufactured.

[0223] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0224] (Embodiment 5) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. The description will be given with reference to the surface.

[0225] 19(A) and 19(B) show circuit diagrams of the semiconductor device, and FIG. 19(C) and FIG. 19(C) and 19(D) show cross-sectional views of the semiconductor device. A cross-sectional view of the transistor 450 in the channel length direction is shown on the right, and a cross-sectional view in the channel width direction is shown on the left. In addition, the circuit diagram clearly shows that the transistor is made of an oxide semiconductor. In order to do so, the term "OS" is added.

[0226] The semiconductor device shown in FIG. 19(C) and FIG. 19(D) has a transistor using a first semiconductor material in the lower part. The transistor 2200 has a second semiconductor material on the upper side. In this embodiment, the transistor using the second semiconductor material is the transistor exemplified in the first embodiment. An example in which the resistor 450 is applied will be described.

[0227] Here, the first semiconductor material and the second semiconductor material have different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon, ruthenium, silicon germanium, silicon carbide, or gallium arsenide, etc.) The second semiconductor material can be the oxide semiconductor described in Embodiment 1. For a transistor using a material other than an oxide semiconductor such as single crystal silicon, high-speed operation is easy. On the other hand, a transistor using an oxide semiconductor has a low off-current. Here, although the transistor 2200 is described as being a p-channel type transistor, it goes without saying that different circuits can be configured using an n-channel type transistor. Also, other than using the transistor as shown in Embodiment 1 using an oxide semiconductor, the specific configuration of the semiconductor device such as the material used for the semiconductor device and the structure of the semiconductor device need not be limited to what is shown here. The configurations shown in FIGS. 19(A), 19(C), and 19(D) show an example of the configuration of a so-called CMOS circuit in which a p-channel type transistor and an n-channel type transistor are connected in series and their gates are connected. Since the on-current of the transistor to which the oxide semiconductor of one aspect of the present invention is applied is increased, high-speed operation of the circuit becomes possible. In the configuration shown in FIG. 19(C), a transistor 450 is provided above the transistor 2200 via an insulating film 2201. Also, a plurality of wirings 2202 are provided between the transistor 2200 and the transistor 450. Also, wirings and electrodes provided in the upper layer and the lower layer are electrically connected by a plurality of plugs 2203 embedded in various insulating films. Also, an insulating film 2204 covering the transistor 450 and a wiring on the insulating film 2204 For a transistor using a material other than an oxide semiconductor such as single crystal silicon, high-speed operation is easy. On the other hand, a transistor using an oxide semiconductor has a low off-current.

[0228] Here, although the transistor 2200 is described as being a p-channel type transistor, it goes without saying that different circuits can be configured using an n-channel type transistor. Also, other than using the transistor as shown in Embodiment 1 using an oxide semiconductor, the specific configuration of the semiconductor device such as the material used for the semiconductor device and the structure of the semiconductor device need not be limited to what is shown here.

[0229] The configurations shown in FIGS. 19(A), 19(C), and 19(D) show an example of the configuration of a so-called CMOS circuit in which a p-channel type transistor and an n-channel type transistor are connected in series and their gates are connected.

[0230] Since the on-current of the transistor to which the oxide semiconductor of one aspect of the present invention is applied is increased, high-speed operation of the circuit becomes possible.

[0231] In the configuration shown in FIG. 19(C), a transistor 450 is provided above the transistor 2200 via an insulating film 2201. Also, a plurality of wirings 2202 are provided between the transistor 2200 and the transistor 450. Also, a plurality of plugs 2203 embedded in various insulating films electrically connect the wirings and electrodes provided in the upper layer and the lower layer respectively. Also, an insulating film 2204 covering the transistor 450 and a wiring on the insulating film 2204 ​​Wiring formed by processing the same conductive film as the pair of electrodes of the transistor 450 and 2205 2206 is provided.

[0232] In this way, by stacking two transistors, the occupied area of the circuit is reduced, and a plurality of circuits can be arranged with higher density.

[0233] In FIG. 19(C), one of the source or drain of the transistor 450 and one of the source or drain of the transistor 2200 are electrically connected by the wiring 2202 or the plug 2203. Also, the gate of the transistor 450 is connected to the gate of the transistor 2200 electrically via the wiring 2205, the wiring 220 6, the plug 2203, the wiring 2202, etc. and is electrically connected.

[0234] In the configuration shown in FIG. 19(D), an opening for embedding the plug 2203 is provided in the gate insulating layer of the transistor 450, and the gate of the transistor 450 and the plug 2203 are in contact with each other. By adopting such a configuration, in addition to facilitating the integration of the circuit, the number and length of the wirings and plugs to be passed through can be reduced as compared with the configuration shown in FIG. 19(C), so that the circuit can operate at a higher speed.

[0235] Here, in the configurations shown in FIGS. 19(C) and 19(D), by varying the connection configurations of the electrodes of the transistor 450 and the transistor 2200, various circuits can be configured. For example, as shown in FIG. 19(B), by adopting a circuit configuration in which the source and drain of each transistor are connected, it can function as a so-called analog switch.

[0236] ​​​​ In addition, the transistor according to the above embodiment can be used to provide an image sensor for reading information about an object. A semiconductor device having a sensor function can be manufactured.

[0237] FIG. 24 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0238] The photodiode 602 has one electrode connected to a photodiode reset signal line 658. The other electrode is electrically connected to the gate of transistor 640. 0 indicates that either the source or the drain is connected to the photosensor reference signal line 672, The other end of the input terminal is electrically connected to one of the source and drain of the transistor 656 . The transistor 656 has a gate connected to a gate signal line 659 and the other of the source and drain connected to a floating gate. It is electrically connected to the photo sensor output signal line 671 .

[0239] The photodiode 602 includes, for example, a semiconductor layer having a p-type conductivity and a high-resistance ( A pin type in which a semiconductor layer having an i-type conductivity and a semiconductor layer having an n-type conductivity are stacked. A photodiode of the above type can be applied.

[0240] By detecting the light incident on the photodiode 602, information on the detected object is read. When reading the information of the detected object, a light source such as a backlight is used. There can be.

[0241] It should be noted that the transistor 640 and the transistor 656 may be any of the transistors according to the previous embodiments. A transistor in which a channel is formed in an oxide semiconductor, an example of which is shown in , can be used. In FIG. 24, the transistor 640 and the transistor 656 include an oxide semiconductor. To clearly identify this, the symbol of the transistor is appended with "OS".

[0242] Transistors 640 and 656 are the transistors shown as an example in the above embodiment, and preferably have a configuration in which an oxide semiconductor film is electrically surrounded by a gate electrode. Also, the shape of the oxide semiconductor film has a rounded upper end and a curved surface, which can improve the coverage of the film formed on the oxide semiconductor film. Further, it is possible to relieve the electric field concentration that may occur at the ends of the source electrode and the drain electrode, and suppress the deterioration of the transistor. Therefore, transistors 640 and 656 are electrically stable transistors with suppressed fluctuations in electrical characteristics. By including such transistors, a highly reliable semiconductor device having an image sensor function shown in FIG. 24 can be provided.

[0243] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0244] (Embodiment 6) In this embodiment, an example of a semiconductor device (memory device) that can retain stored content even when power is not supplied and has no limit on the number of write operations will be described with reference to the drawings, using a transistor which is an aspect of the present invention.

[0245] Circuit diagrams of semiconductor devices are shown in FIG. 20 respectively.

[0246] The semiconductor device shown in FIG. 20 includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor element 3400. Note that ​​​​​​​​​​​ As the transistor 3300, the transistor described in Embodiment 1 can be used. This is possible.

[0247] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 3300 has a small off-current, it is possible to hold the stored content for a longer period of time by using this transistor. That is, it is possible to configure a semiconductor memory device that does not require a refresh operation or requires a very low frequency of refresh operation, so that power consumption can be sufficiently reduced. In FIG. 20, the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. Further, the third wiring 3003 is electrically connected to one of the source electrode or the drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. Then, the gate electrode of the transistor 3200 and the other of the source electrode or the drain electrode of the transistor 3300 are electrically connected to one of the electrodes of the capacitor element 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor element 3400. In the semiconductor device shown in FIG. 20, by taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be held, writing, holding, and reading of information can be performed as follows. Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential higher than the threshold voltage of the transistor 3300, and the potential of the third wiring 3003 is set to a potential lower than the threshold voltage of the transistor 3300. Then, a voltage is applied between the first wiring 3001 and the second wiring 3002. As a result, electrons are injected from the source electrode of the transistor 3200 to the drain electrode through the channel, and some of the electrons are trapped in the semiconductor layer having the oxide semiconductor of the transistor 3300. At this time, the potential of the gate electrode of the transistor 3200 is held by the capacitor element 3400. Next, the potential of the fourth wiring 3004 is set to a potential lower than the threshold voltage of the transistor 3300, and the potential of the third wiring 3003 is set to a potential higher than the threshold voltage of the transistor 3300. Then, a voltage is applied between the first wiring 3001 and the second wiring 3002. As a result, holes are injected from the drain electrode of the transistor 3200 to the source electrode through the channel, and some of the holes are trapped in the semiconductor layer having the oxide semiconductor of the transistor 3300. At this time, the potential of the gate electrode of the transistor 3200 is held by the capacitor element 3400.

[0248] In FIG. 20, the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. Also, the third wiring 3003 is electrically connected to one of the source electrode or the drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. And the gate electrode of the transistor 3200, and the other of the source electrode or the drain electrode of the transistor 3300 are electrically connected to one of the electrodes of the capacitor element 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor element 3400. In the semiconductor device shown in FIG. 20, by taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be held, information can be written, held, and read as follows. Regarding the writing and holding of information, first, the potential of the fourth wiring 3004 is set to a potential higher than the threshold voltage of the transistor 3300, and the potential of the third wiring 3003 is set to a potential lower than the threshold voltage of the transistor 3300. Then, a voltage is applied between the first wiring 3001 and the second wiring 3002. As a result, electrons are injected from the source electrode of the transistor 3200 to the drain electrode through the channel, and some of the electrons are trapped in the semiconductor layer having the oxide semiconductor of the transistor 3300. At this time, the potential of the gate electrode of the transistor 3200 is held by the capacitor element 3400. Next, the potential of the fourth wiring 3004 is set to a potential lower than the threshold voltage of the transistor 3300, and the potential of the third wiring 3003 is set to a potential higher than the threshold voltage of the transistor 3300. Then, a voltage is applied between the first wiring 3001 and the second wiring 3002. As a result, holes are injected from the drain electrode of the transistor 3200 to the source electrode through the channel, and some of the holes are trapped in the semiconductor layer having the oxide semiconductor of the transistor 3300. At this time, the potential of the gate electrode of the transistor 3200 is held by the capacitor element 3400. The gate electrode of the transistor 3200, and the other of the source electrode or the drain electrode of the transistor 3300 are electrically connected to one of the electrodes of the capacitor element 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor element 3400. In the semiconductor device shown in FIG. 20, by taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be held, information can be written, held, and read as follows. Regarding the writing and holding of information, first, the potential of the fourth wiring 3004 is set to a potential higher than the threshold voltage of the transistor 3300, and the potential of the third wiring 3003 is set to a potential lower than the threshold voltage of the transistor 3300. Then, a voltage is applied between the first wiring 3001 and the second wiring 3002. As a result, electrons are injected from the source electrode of the transistor 3200 to the drain electrode through the channel, and some of the electrons are trapped in the semiconductor layer having the oxide semiconductor of the transistor 3300. At this time, the potential of the gate electrode of the transistor 3200 is held by the capacitor element 3400. Next, the potential of the fourth wiring 3004 is set to a potential lower than the threshold voltage of the transistor 3300, and the potential of the third wiring 3003 is set to a potential higher than the threshold voltage of the transistor 3300. Then, a voltage is applied between the first wiring 3001 and the second wiring 3002. As a result, holes are injected from the drain electrode of the transistor 3200 to the source electrode through the channel, and some of the holes are trapped in the semiconductor layer having the oxide semiconductor of the transistor 3300. At this time, the potential of the gate electrode of the transistor 3200 is held by the capacitor element 3400.

[0249] In the semiconductor device shown in FIG. 20, by taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be held, information can be written, held, and read as follows. By taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be held, the following describes how information can be written, held, and read.

[0250] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential higher than the threshold voltage of the transistor 3300, and the potential of the third wiring 3003 is set to a potential lower than the threshold voltage of the transistor 3300. Then, a voltage is applied between the first wiring 3001 and the second wiring 3002. As a result, electrons are injected from the source electrode of the transistor 3200 to the drain electrode through the channel, and some of the electrons are trapped in the semiconductor layer having the oxide semiconductor of the transistor 3300. At this time, the potential of the gate electrode of the transistor 3200 is held by the capacitor element 3400. Set the potential at which the transistor 3300 turns on to turn on the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and the capacitor element 3400. That is, a predetermined charge is applied to the gate electrode of the transistor 3200 (writing). Here, either one of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. After that, by setting the potential of the fourth wiring 3004 to the potential at which the transistor 3300 turns off and turning off the transistor 3300, the charge applied to the gate electrode of the transistor 3200 is held (holding). Since the off-current of the transistor 3300 is extremely small, the charge on the gate electrode of the transistor 3200 is held for a long time.

[0251]

[0252] Next, the reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 takes different potentials according to the amount of charge held on the gate electrode of the transistor 3200. Generally, when the transistor 3200 is an n-channel type, the apparent threshold voltage V when a High level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold voltage V when a Low level charge is applied to the gate electrode of the transistor 3200. t h_H This is because when a Low level charge is applied to the gate electrode of the transistor 3200. th_L Here, the apparent threshold voltage is the potential of the fifth wiring 3005 required to turn the transistor 3200 into the "on state". ​​​​Therefore, the potential of the fifth wiring 3005 is V th_H and V th _L By setting the potential V0 between For example, if a high-level charge is applied during writing, In this case, the potential of the fifth wiring 3005 is V0 (>V th_H ), then transistor 32 00 is in the "on state." When a low level charge is applied, the fifth wiring 3 The potential of 005 is V0( <V th_L ), transistor 3200 is in the "off state" Therefore, by determining the potential of the second wiring 3002, The information can be read out.

[0253] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 remains "on," that is, V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0254] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to extremely reduce the frequency of operation, sufficient power consumption reduction can be achieved. Also, even when there is no power supply (however, it is desirable that the potential is fixed), it is possible to retain the stored content over a long period of time.

[0255] In addition, in the semiconductor device shown in this embodiment, a high voltage is not required for writing information, and there is no problem of device degradation. For example, unlike conventional non-volatile memories, since it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized.

[0256] As described above, it is possible to provide a semiconductor device that realizes miniaturization and high integration and has high electrical characteristics.

[0257] (Embodiment 7) In this embodiment, the transistor described in the previous embodiment can be used, and a CPU including the memory device described in the previous embodiment will be described.

[0258] FIG. 21 is a block diagram showing a configuration example of a CPU using at least a part of the transistor described in Embodiment 1.

[0259] The CPU shown in FIG. 21 has an ALU 1191 (ALU: Arithme tic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing control ler 1195, register 1196, register controller 1197, bus interface 1198, rewritable ROM 1199, and ROM interface 1189. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. Rewritable able ROM 1199 and ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in Fig. 21 is just an example with a simplified configuration, and an actual CPU has various configurations depending on its application. For example, a configuration including the CPU shown in Fig. 21 or an arithmetic circuit is taken as one core, and a plurality of such cores are included, and each core may operate in parallel. Also, the number of bits handled by the CPU with its internal arithmetic circuit and data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0260] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the in terrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0261] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 controls the operation of the ALU1191 ​generates a signal for that purpose. Also, the interrupt controller 1194 interrupts requests from external input / output devices and peripheral circuits during the execution of the CPU's program and determines and processes them based on their priority and mask status. The register controller 1197 generates the address of the register 1196 and reads from and writes to the register 1196 according to the state of the CPU .

[0262] Also, the timing controller 1195 generates signals that control the operation timing of the ALU 1191, the ALU controller 11 92, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits described above .

[0263] In the CPU shown in FIG. 21, memory cells are provided in the register 1196. As the memory cells of the register 1196, the transistors shown in the previous embodiment can be used

[0264] In the CPU shown in FIG. 21, the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191. That is, in the memory cells of the register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, the supply of the power supply voltage to the memory cells in the register 1196 is performed ​​​​​​​​​​When data retention in the capacitive element is selected, data can be rewritten to the capacitive element, and the supply of the power voltage to the memory cell in the register 1196 can be stopped.

[0265] FIG. 22 is an example of a circuit diagram of a memory element that can be used as the register 1196. The memory element 700 includes a circuit 701 in which stored data is volatile when the power is cut off, a circuit 702 in which stored data is non-volatile when the power is cut off, a switch 703, a switch 704, a logic element 706, a capacitive element 707, and a circuit 720 having a selection function. The circuit 702 includes a capacitive element 708, a transistor 709, and a transistor 710. Note that the memory element 700 may further include other elements such as a diode, a resistive element, and an inductor as necessary.

[0266] Here, the storage device described in the previous embodiment can be used for the circuit 702. When the supply of the power voltage to the memory element 700 is stopped, a ground potential (0 V) or a potential at which the transistor 709 is turned off is input to the first gate of the transistor 709 in the circuit 702, and the configuration is continued. For example, the first gate of the transistor 709 is grounded via a load such as a resistor.

[0267] The switch 703 is configured using a transistor 713 of one conductivity type (e.g., n-channel type), and the switch 704 is configured using a transistor 714 of a conductivity type opposite to the one conductivity type (e.g., p-channel type). Here, the first terminal of the switch 703 corresponds to one of the source and drain of the transistor 713, and the second terminal of the switch 703 corresponds to the ​​​​​​​​​​​​​Corresponding to the other of the source and drain of transistor 713, switch 703 is connected to the gate of transistor 71 3, and the conduction or non-conduction (i.e., the on-state or off-state of transistor 713) between the first terminal and the second terminal is selected by the control signal RD input to the gate of transistor 713. The first terminal of switch 704 corresponds to one of the source and drain of transistor 714, and the second terminal of switch 704 corresponds to the other of the source and drain of transistor 714. Switch 704 is controlled by the control signal RD input to the gate of transistor 714 to select the conduction or non-conduction (i.e., the on-state or off-state of transistor 714) between the first terminal and the second terminal.

[0268] One of the source and drain of transistor 709 is electrically connected to one of the pair of electrodes of capacitor element 708 and to the gate of transistor 710. Here, let the connection point be node M2. One of the source and drain of transistor 710 is electrically connected to a wiring (e.g., GND line) capable of supplying a low power supply potential, and the other is electrically connected to the first terminal (one of the source and drain of transistor 713) of switch 703. The second terminal (the other of the source and drain of transistor 713) of switch 703 is electrically connected to the first terminal (one of the source and drain of transistor 714) of switch 704. The second terminal (the other of the source and drain of transistor 714) of switch 704 is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal (the other of the source and drain of transistor 713) of switch 703, the first terminal (one of the source and drain of transistor 714) of switch 704, and the input terminal of logic element 706 ​​​​​​​​​​​​​​ and is electrically connected to one of the pair of electrodes of the capacitive element 707. Here, the connection portion is designated as node M1. The other of the pair of electrodes of the capacitive element 707 can be configured to have a constant potential applied thereto. For example, it can be configured such that a low power supply potential (such as GND) or a high power supply potential ( such as VDD) is applied. The other of the pair of electrodes of the capacitive element 707 is electrically connected to a wiring (for example, a GND line) capable of supplying a low power supply potential . The other of the pair of electrodes of the capacitive element 708 can be configured to have a constant potential applied thereto. For example, it can be configured such that a low power supply potential (such as GND) or a high power supply potential (such as VDD) is applied . The other of the pair of electrodes of the capacitive element 708 is electrically connected to a wiring (for example, a GND line) capable of supplying a low power supply potential . Note that the capacitive elements 707 and 708 can also be omitted by positively utilizing the parasitic capacitances of transistors and wirings, etc.

[0269]

[0270] A control signal WE is input to the first gate (first gate electrode) of the transistor 709. The switches 703 and 704 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE, and when the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state .

[0271] A signal corresponding to the data held in the circuit 701 is input to the other of the source and drain of the transistor 709. In FIG. 22, the signal output from the circuit 701 is the transistor An example of input to the other side of the source and drain of the transistor 709 was shown. The second end of the switch 703 (the other side of the source and drain of the transistor 713) outputs a signal that becomes an inverted signal whose logical value is inverted by the logic element 7 06 and is input to the circuit 701 via the circuit 720.

[0272] In FIG. 22, an example of input to the circuit 701 via the logic element 706 and the circuit 720 was shown for the signal output from the second terminal of the switch 703 (the other side of the source and drain of the transistor 713), but it is not limited to this. The signal output from the second terminal of the switch 703 (the other side of the source and drain of the transistor 713) may be input to the circuit 701 without inverting its logical value. For example, when there is a node in the circuit 701 that holds a signal whose logical value is inverted from the signal input from the input terminal, the signal output from the second terminal of the switch 703 (the other side of the source and drain of the transistor 713) can be input to the said node. node. The transistor 709 in FIG. 22 can use the transistor described in Embodiment 1. Also, as described in Embodiment 3, it is preferable to have a configuration having a second gate (second gate electrode). A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal of a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709 and further reduces the Icut of the transistor 709. node. The transistor 709 in FIG. 22 can use the transistor described in Embodiment 1. Also, as described in Embodiment 3, it is preferable to have a configuration having a second gate (second gate electrode). A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal of a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709 and further reduces the Icut of the transistor 709. The transistor 709 in FIG. 22 can use the transistor described in Embodiment 1. Also, as described in Embodiment 3, it is preferable to have a configuration having a second gate (second gate electrode). A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal of a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709 and further reduces the Icut of the transistor 709. said node.

[0273] The transistor 709 in FIG. 22 can use the transistor described in Embodiment 1. Also, as described in Embodiment 3, it is preferable to have a configuration having a second gate (second gate electrode). A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal of a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709 and further reduces the Icut of the transistor 709. The transistor 709 in FIG. 22 can use the transistor described in Embodiment 1. Also, as described in Embodiment 3, it is preferable to have a configuration having a second gate (second gate electrode). A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal of a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709 and further reduces the Icut of the transistor 709. A control signal WE can be input to the first gate, and a control signal WE2 can be input to the second gate. The control signal WE2 may be a signal of a constant potential. For the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709 and further reduces the Icut of the transistor 709. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709 and further reduces the Icut of the transistor 709. is possible. Note that as the transistor 709, a transistor without a second gate can be used.

[0274] Also, in FIG. 22, among the transistors used in the memory element 700, the transis tors other than the transistor 709 can be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, it can be a transistor in which a channel is formed in a silicon layer or a silicon substrate. Also, all of the transistors used in the memory element 7 00 can be transistors in which a channel is formed of an oxide semiconductor film. Or, the memory element 700 may include, in addition to the transistor 709, a transis tor in which a channel is formed of an oxide semiconductor film, and the remaining transis tors can also be transistors in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor.

[0275] For the circuit 701 in FIG. 22, for example, a flip-flop circuit can be used. Also, as the logic element 706, for example, an inverter, a clocked inverter, or the like can be used.

[0276] In the semiconductor device according to one aspect of the present invention, while the power supply voltage is not supplied to the memory element 700, the data stored in the circuit 701 can be held by the capacitor element 708 provided in the circuit 702.

[0277] Also, a transistor in which a channel is formed in an oxide semiconductor film has an extremely small off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor film depends on the crystallinity. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Thus, by using the transistor as transistor 709, the signal held in capacitor 708 can be maintained for a long time even while the power supply voltage is not supplied to memory element 7 00. In this way, memory element 700 can hold the memory content (data) even while the supply of the power supply voltage is stopped.

[0278] Also, since it is a memory element characterized by performing a precharge operation by providing switch 703 and switch 704, after the resumption of the power supply voltage supply, the time until circuit 701 resumes holding the original data can be shortened.

[0279] In circuit 702, the signal held by capacitor 708 is input to the gate of transistor 7 10. Therefore, after the supply of the power supply voltage to memory element 700 is resumed, the signal held by capacitor 708 can be converted into the state (on state or off state) of transistor 710 and read out from circuit 702. Therefore, even if the potential corresponding to the signal held in capacitor 708 fluctuates somewhat, the original signal can be accurately read out.

[0280] By using such a memory element 700 in a memory device such as a register or a cache memory that a processor has, it is possible to prevent the loss of data in the memory device due to the stop of the power supply voltage supply. Also, after the resumption of the power supply voltage supply, it can return to the state before the power supply stop in a short time. Therefore, in the entire processor or one or a plurality of logic circuits constituting the processor, the power supply can be stopped even for a short time, so the power consumption can be reduced. ​​​​​​ It can be suppressed.

[0281] In this embodiment, although an example in which the memory element 700 is used as a CPU has been described, the memory element 7 00 can also be applied to a DSP (Digital Signal Processor), a custom LSI such as I, a PLD (Programmable Logic Device), an LSI such as an RF -ID (Radio Frequency Identification). It is possible.

[0282] This embodiment can be implemented in appropriate combination with other embodiments described in this specification. It can be done.

[0283] (Embodiment 8) In this embodiment, an example of an electronic device that can use the transistor described in Embodiment 1, the storage device described in Embodiments 5 and 6, or the CPU etc. (including DSP, custom LSI I, PLD, RF-ID) described in Embodiment 7 will be described. The transistor described in Embodiment 1, the storage device described in Embodiments 5 and 6, or the CPU etc. can be applied to various electronic devices (including gaming machines).

[0284] The transistor described in Embodiment 1, the storage device described in Embodiments 5 and 6, or the CPU etc. described in Embodiment 7 can be applied to various electronic devices (including gaming machines). Examples of electronic devices include display devices such as televisions and monitors, lighting devices, personal computers, word processors, image playback devices, portable audio players, radios, tape recorders, stereos, telephones, cordless telephones, mobile phones, car phones, transceivers, radios, gaming machines, calculators, portable information terminals, electronic notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, IC chips radios, tape recorders, stereos, telephones, cordless telephones, mobile phones, car phones, transceivers, radios, gaming machines, calculators, portable information terminals, electronic notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, IC chips transceivers, radios, gaming machines, calculators, portable information terminals, electronic notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, IC chips , high-frequency heating devices such as microwave ovens, rice cookers, washing machines, vacuum cleaners, air conditioners , air-conditioning equipment such as air conditioners, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators , freezers, electric freezers, electric refrigerator-freezers, DNA storage freezers, radiation measuring instruments, dialysis devices, X-ray diagnostic devices and other medical devices, etc. Also, smoke sensors, heat sensors, gas alarm devices, alarm devices such as security alarm devices. Furthermore, induction lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, industrial equipment such as power storage systems are also included . Also, engines using fuel, and mobile bodies propelled by electric motors using power from non-aqueous secondary batteries are also considered to be within the scope of electronic devices. As the above mobile bodies, for example , electric vehicles (EVs), hybrid vehicles (HEVs) having both an internal combustion engine and an electric motor, plug-in hybrid vehicles (PHEVs), tracked vehicles obtained by changing the tires of these vehicles to endless tracks, motorized bicycles including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, airplanes, rockets, artificial satellites, space exploration vehicles and planetary exploration vehicles, spacecraft. Specific examples of some of these electronic devices are shown in Fig. 23.

[0285] The television device 8000 shown in Fig. 23(A) has a display unit 8002 incorporated in a housing 8001, and can display images on the display unit 8002 and output sound from a speaker unit 8003. The transistors exemplified in the previous embodiments can be used for a drive circuit or pixels for operating the display unit 8002 incorporated in the housing 8001. .

[0286] The display unit 8002 can use a light-emitting element such as a liquid crystal display device or an organic EL element for each pixel. Devices, electrophoretic display devices, DMD (Digital Micromirror Devi ce), semiconductor display devices such as PDP (Plasma Display Panel), etc. can be used.

[0287] The television device 8000 may be provided with a receiver, a modem, etc. The television device 8000 can receive general television broadcasts by a receiver, and further connect to a wired or wireless communication network via a modem, thereby enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication. It is also possible.

[0288] In addition, the television device 8000 may be provided with a CPU 8004 and a memory for information communication. By using the transistors, storage devices, or CPUs shown in the previous embodiments in the CPU 8004 and the memory, power saving can be achieved.

[0289] The alarm device 8100 shown in Fig. 23(A) is a residential fire alarm, and is an example of an electronic device using a microcomputer 8101 and a smoke or heat detection unit 8102. The micro computer 8101 includes the transistors, storage devices, or CPUs shown in the previous embodiments. It includes a U.

[0290] In addition, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in Fig. 23(A) is an example of an electronic device including the transistors, storage devices, or CPUs, etc. shown in the previous embodiments. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, C etc. It has PU8203 etc. In Fig. 23(A), CPU8203 is exemplified as being provided in the indoor unit 8200 However, CPU8203 may be provided in the outdoor unit 8204 Or, CPU8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204 By using the transistor shown in the previous embodiment for the CPU of the air conditioner Power saving can be achieved.

[0291] Also, the electric refrigerator 8300 shown in Fig. 23(A) is an example of an electronic device including the transistor, memory device, or CPU etc. shown in the previous embodiment. Specifically, the electric refrigerator 8300 has a housing 8301, a refrigerator door 8302, a freezer door 8303, CPU83 04 etc. In Fig. 23(A), CPU8304 is provided inside the housing 8301 Power saving can be achieved by using the transistor shown in the previous embodiment for CPU830 4 of the electric refrigerator 8300. 4 of the electric refrigerator 8300.

[0292] Figs. 23(B) and 23(C) show an example of an electric vehicle which is an example of an electronic device. An electric vehicle 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is adjusted by a circuit 9702 and supplied to a drive device 9703. The circuit 9702 is controlled by a processing device 9704 having a ROM, RAM, CPU etc. (not shown). An electric vehicle 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is adjusted by a circuit 9702 and supplied to a drive device 9703. The circuit 9702 is controlled by a processing device 9704 having a ROM, RAM, CPU etc. (not shown). An electric vehicle 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is adjusted by a circuit 9702 and supplied to a drive device 9703. The circuit 9702 is controlled by a processing device 9704 having a ROM, RAM, CPU etc. (not shown). An electric vehicle 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is adjusted by a circuit 9702 and supplied to a drive device 9703. The circuit 9702 is controlled by a processing device 9704 having a ROM, RAM, CPU etc. (not shown). Power saving can be achieved by using the transistor shown in the previous embodiment for the CPU of the electric vehicle 9700 Power saving can be achieved by using the transistor shown in the previous embodiment for the CPU of the electric vehicle 9700

[0293] The drive device 9703 is a DC motor or an AC motor alone, or a combination of an electric motor and an internal combustion engine , which is composed by combining. The processing device 9704 is the operation of the driver of the electric vehicle 9700 information (such as acceleration, deceleration, stop, etc.) and information during driving (information such as uphill and downhill, load information applied to the driving wheels, etc.). Based on the input information, a control signal is output to the circuit 9702. The circuit 970 2 adjusts the electrical energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704 to control the output of the driving device 9703. When an AC motor is installed, although not shown in the figure, an inverter for converting DC to AC is also built-in. This embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0294] This embodiment can be implemented in appropriate combination with other embodiments described in this specification.

Example

[0295] In this example, as an example sample, a transistor having the same configuration as the transistor 460 shown in Fig. 6(A) was fabricated, and its cross-sectional shape was examined. In addition, the electrical characteristics of the fabricated transistor were evaluated.

[0296] First, the manufacturing method of the example sample is shown.

[0297] First, a silicon oxynitride (SiO N) film with a film thickness of 300 nm, which serves as an underlying insulating film, was formed on a silicon substrate. The silicon oxynitride film was formed by sputtering in an argon and oxygen (argon: oxygen = 25 sccm: 25 sccm) mixed atmosphere under a pressure of 0.4 P a and an applied power of 5.0 kW (power output). The film was formed under the conditions of a distance of 60 mm between the silicon substrate and the target and a substrate temperature of 100 °C.

[0298] After polishing the surface of the silicon oxynitride film, a first oxide film with a film thickness of 10 nm and a film thickness of 40 nm​​​ An oxide semiconductor film was formed by laminating. The film formation conditions were as follows: for the first oxide film, a sputtering method was used with an oxide target (IGZO(132)) having an atomic ratio of In:Ga:Zn =1:3:2 (atomic ratio) in an argon and oxygen (argon:oxygen = 30 sccm:15 sccm) mixed atmosphere. Under a pressure of 0.4 Pa and an applied power of 0.5 kW, the distance between the target and the substrate was set to 60 mm, and the substrate temperature was set to 200 °C for film formation. The oxide semiconductor film was formed using an oxide target (IGZO(111)) with an atomic ratio of In:Ga: Zn = 1:1:1 (atomic ratio) by a sputtering method in an argon and oxygen (argon:oxygen = 30 sccm:15 sccm ) mixed atmosphere. Under a pressure of 0.4 Pa and an applied power of 0.5 kW, the distance between the target and the substrate was set to 60 mm, and the substrate temperature was set to 300 °C for film formation. Note that the first oxide film and the oxide semiconductor film were continuously formed without exposure to the atmosphere. Next, heat treatment was performed. The heat treatment was carried out at 450 °C for 1 hour in a nitrogen atmosphere, and then at 450 °C for 1 hour in an oxygen atmosphere.

[0299] Next, a tungsten film serving as a hard mask was formed on the oxide semiconductor film to a thickness of 5 nm and etched to form a hard mask. The etching was performed by an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method in a carbon tetrafluoride

[0300] (CF4 = 100 sccm) atmosphere at a power of 2000 W, a bias power of 50 W, and a pressure of 0.67 Pa, and then in a mixed atmosphere of carbon tetrafluoride and oxygen (CF4:O2 = 60 sccm:4 0 sccm) at a power of 1000 W, a bias power of 25 W, and a pressure of 2.0 Pa . . ​​​

[0301] Next, the first oxide film and the oxide semiconductor film were processed into island-shaped first oxide film and oxide semiconductor film by ICP etching method in a mixed atmosphere of methane and argon (CH4:Ar = 16 sccm:32 sccm) at a power supply power of 6 00 W, a bias power of 100 W, a pressure of 1.0 Pa, and a substrate temperature of 70 °C.

[0302] Next, a tungsten (W) film serving as a source electrode and a drain electrode was formed on the first oxide film and the oxide semiconductor film with a film thickness of 10 nm. The film formation conditions were in an argon (argon 80 sccm) atmosphere by a sputtering method using a tungsten target at a pressure of 0.8 Pa and a power supply power (power supply output) of 1.0 kW, and the film was formed under the conditions of a distance of 60 mm between the silicon substrate and the target and a substrate temperature of 230 °C.

[0303] Next, a resist mask was formed on the tungsten film and etching was performed. The etching was performed by ICP etching method. The first etching was performed in a carbon tetrafluoride (CF4 = 100 sc cm) atmosphere at a power supply power of 2000 W, a bias power of 50 W, and a pressure of 0.67 Pa and then the second etching was performed in a mixed atmosphere of carbon tetrafluoride and oxygen (CF4:O2 = 60 sccm:40 s ccm) at a power supply power of 1000 W, a bias power of 25 W, and a pressure of 2.0 Pa to form the source electrode and the drain electrode.

[0304] Next, a second oxide film with a film thickness of 5 nm was formed on the oxide semiconductor film, the source electrode, and the drain electrode. The film formation conditions were by a sputtering method using an oxide target of In:Ga:Zn = 1:3:2 (atomic ratio) (IGZO(132)) with argon and oxygen (al gon​​​​​ Gon: Under an oxygen = 30 sccm: 15 sccm) mixed atmosphere, a pressure of 0.4 Pa and an electric source power of 0.5 kW were applied, and the distance between the target and the substrate was 60 mm, and the substrate temperature was 200 °C was set.

[0305] Next, a 10-nm silicon oxynitride film to be a gate insulating film was formed by the CVD method.

[0306] Next, a 10-nm titanium nitride film was formed on the silicon oxynitride film by sputtering method , under a nitrogen (N2 = 50 sccm) atmosphere, a pressure of 0.2 Pa and a source power of 12 kW were applied, the distance between the target and the substrate was 400 mm, and the substrate temperature was room temperature for film formation, and on it, a film thickness 10-nm tungsten film was formed by laminating under an argon (Ar = 100 sccm) atmosphere, a pressure of 2.0 P a, a source power of 4 kW was applied, the distance between the target and the substrate was 60 mm, and the substrate temperature was 230 °C.

[0307] Next, by the ICP etching method, a laminate of a 10-nm titanium nitride film and a 10-nm tungsten film was etched. The etching conditions were chlorine, carbon tetrafluoride and oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm) mixed atmosphere , a source power of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa for the first etching was performed, and after the first etching, boron trichloride and chlorine (BCl3:Cl2 = 150 sccm:50 sccm) mixed atmosphere, a source power of 1000 W, a bias power of 50 W, and a pressure of 0.67 Pa for the second etching was performed to form a gate electrode.

[0308] Next, by the ICP etching method, using the gate electrode as a mask, the gate insulating film, the second The oxide film stack was etched. The etching conditions were in a mixed atmosphere of methane and argon (CH4 :Ar = 16 sccm:32 sccm), with a power supply power of 600 W, a bias power of 100 W, a pressure of 1.0 Pa, and a substrate temperature of 70 °C for etching.

[0309] Next, an aluminum oxide film with a thickness of 20 nm was formed on the gate electrode by sputtering, and on top of that, a silicon oxynitride film with a thickness of 150 nm was formed by CVD. The cross-sectional STEM photograph of the example sample fabricated by the above method is shown in Fig. 10. Fig. 10(A

[0310] ) is a cross-sectional view in the channel length direction, and Fig. 10(B) is a cross-sectional view in the channel width direction. ) is a cross-sectional view in the channel length direction, and Fig. 10(B) is a cross-sectional view in the channel width direction.

[0311] As shown in Fig. 10(B), the cross-section of the IGZO(111) oxide semiconductor film in the channel width direction has rounded ends and is semi-circular. With such a configuration, the coverage of the second oxide film, gate insulating film, and gate electrode formed on the oxide semiconductor film is improved and it was confirmed that no shape defects such as steps occurred. and it was confirmed that no shape defects such as steps occurred. and it was confirmed that no shape defects such as steps occurred.

[0312] Also, the channel length of the fabricated transistor was 68 nm and the channel width was 34 nm.

[0313] Next, in the fabricated transistor, when the drain voltage (V d :[V]) was 0.1 V or 1 V, and the gate voltage (V g :[V]) was swept from -3 V to 3 V, the drain current (I d :[A]) was measured. The measurement results of the example transistor are shown in Fig. 29. In Fig. 29, the solid line is the measurement result when the drain voltage (V d :[V]) is 1 V, and the dots​​ The line is the measurement result when the drain voltage (V d :[V]) is 0.1 V. The horizontal axis is the gate voltage (V g :[V]), and the vertical axis is the drain current (I d :[A]). Note that "drain voltage (V d :[V])" is the potential difference between the drain and the source with the source as the reference, and "gate voltage (V (V g :[V])" is the potential difference between the gate and the source with the source as the reference.

[0314] As shown in Fig. 29, the on-current of the transistor fabricated in this example was 5.31 μA when the drain voltage (V d :[V]) was 1 V. Also, the field-effect mobility when the drain voltage was 0.1 V was 20.0 cm / Vs. Also, the shift value when the drain voltage was 1 V was 0.13 A. Here, the value of the gate voltage at which the drain current is 1×10 2 A is defined as the shift value. Also, the threshold voltage when the drain voltage was 1 V was 0.65 V. Also, the S value when the drain voltage was 0.1 V was 113.1 mV / dec. Also, the off-current when the drain voltage was 1 V was below the measurement lower limit -12 A . From the above, it was shown that the transistor of this example is a transistor with high electrical characteristics.

Example

[0315] In this example, the temperature dependence of the transistor fabricated in Example 1 was evaluated.

[0316]

[0317] The evaluation was performed under three conditions of -25°C, 50°C, and 150°C for the drain voltage (V

[0317] (V d:[V]) is 1 V, the gate voltage (V g :[V]) was swept from -3 V to 3 V, the drain current ( I d :[A]) and the field-effect mobility (μFE) were measured. For the transistor of the example The measurement results are shown in FIG. 30. In FIG. 30, the horizontal axis is the gate voltage (V g :[V]), and the vertical axis on the left is the drain current (I d :[A]), and the vertical axis on the right is the field-effect mobility (μFE: cm 2 / Vs) is shown.

[0318] As shown in FIG. 30, it was confirmed that for the transistor fabricated in Example 1, the on-current and the field-effect mobility did not change much due to temperature change.

[0319] Also, the temperature dependence of the threshold voltage is shown in FIG. 31.

[0320] It was confirmed that the value of the threshold voltage did not change much due to temperature change.

[0321] From the above, it is shown that the transistor of this example is a transistor having temperature tolerance.

Example

[0322] In this example, the reliability of the transistor fabricated in Example 1 was evaluated.

[0323] As the stress test conditions, the source voltage (Vs: [V]) and the drain voltage ( Vd: [V]) were set to 0 V, the gate voltage was set to -1.8 V, and they were applied at 150 °C for 1 hour, and the drain current (Id: [A]) was measured. The measurement results of the transistor of the example are shown in FIG. 32(A). In FIG. 32(A), when the drain voltage (Vd: [V]) is 0.1 V and 1 V ​These are the measurement results. The horizontal axis represents the gate voltage (Vg: [V]), and the vertical axis represents the drain current (Id: A).

[0324] Also, as the stress test conditions, the source voltage (Vs: [V]) and the gate voltage (Vg : [V]) were set to 0 V, the drain voltage was set to 1.8 V, and they were applied at 150 °C for 1 hour. Then, the drain current ( Id: [A]) was measured. The measurement results of the transistor of the example are shown in Fig. 32(B). In Fig. 32(B), these are the measurement results when the drain voltage (Vd: [V]) is 0.1 V and 1 V. The horizontal axis represents the gate voltage (Vg: [V]), and the vertical axis represents the drain current (Id: [A] ) .

[0325] Note that the solid line in the figure represents the measurement result before the stress test, and the dotted line represents the measurement result after the stress test. As shown in Fig. 32(A) and Fig. 32(B), the change amount ΔVth of the threshold voltage when the drain voltage (Vd: [V]) of the transistor fabricated in Example 1 is 1 V is 0.03 V in Fig. 32(A) and 0.11 V in Fig. 32(B), showing a small change amount .

[0326] Also, Fig. 33 (the rectangle in the figure) shows the change amount of the threshold voltage with the source voltage (Vs: [V]) and the gate voltage (Vg : [V]) set to 0 V, at 125 °C for 0.01 year (87.6 hours), and the drain voltage (Vd: V]) applied at 1.8 V

[0327] Also, Fig. 33 (the diamond in the figure) shows the change amount of the threshold voltage with the source voltage (Vs: [V]) and the drain voltage (V d: [V]) set to 0 V, at 125 °C for 0.01 year (87.6 hours), and the gate voltage (Vg: V]) applied at -1.8 V

[0328] ​As shown in FIG. 33, the change amount of the threshold voltage of the transistor fabricated in Example 1 was 0. It was confirmed that the change amount was small even after 0.01 years had passed.

[0329] From the above, it was shown that the transistor of this example is a transistor having high electrical stability.

Example

[0330] In this example, the electrical characteristics of the transistor fabricated in Example 1 were evaluated with respect to the channel width.

[0331] First, the on-current (I d :[A]) with respect to the channel width was measured when the drain voltage (V on :[V]) was 1 V. The measurement results of the example transistor are shown in FIG. 34(A). In FIG. 34(A), the horizontal axis represents the channel length [nm], and the vertical axis represents the on-current (I on :[A]) is shown. Note that the diamonds in the figure indicate the measurement results when the channel width is 40 nm, the triangles indicate the measurement results when the channel width is 100 nm, and the squares indicate the measurement results when the channel width is 500 nm.

[0332] From FIG. 34(A), it was confirmed that the on-current I on is high even when the channel width is narrow.

[0333] Next, the field-effect d mobility with respect to the channel width was measured when the drain voltage (V :[V]) was 0.1 V. The measurement results of the example transistor are shown in FIG. 34(B). In FIG. 34( B), the horizontal axis represents the channel length [nm], and the vertical axis represents the field-effect mobility (μFE: cm 2 / V s). Note that the diamonds in the figure indicate the measurement results when the channel width is 40 nm, the triangles indicate the measurement results when the channel width is 100 n ​​​m. The measurement results when the channel width is 500 nm are shown for the four corners.

[0334] From Fig. 34(B), it was confirmed that the mobility is higher when the channel width is narrower.

[0335] Next, the threshold voltage d with respect to the channel width when the drain voltage (V :[V]) is 1 V was measured. The measurement results of the example transistors are shown in Fig. 34(C). In Fig. 34(C), the horizontal axis represents the channel length [nm], and the vertical axis represents the threshold voltage (V th :[V]). Also, the diamonds in the figure represent the measurement results when the channel width is 40 nm, the triangles represent when the channel width is 100 nm, and the squares represent the measurement results when the channel width is 500 nm. From Fig. 34(C), it was confirmed that the threshold voltage did not change much.

[0336]

[0337] Next, the shift value with respect to the channel width when the drain voltage (V d :[V]) is 1 V was measured. The shift value refers to the rising voltage, and is defined as the gate voltage (V when the drain current (I d :[A] ) is 1E - 12 A. The measurement results of the example transistors g are shown in Fig. 34(D). In Fig. 34(D), the horizontal axis represents the channel length [nm], and the vertical axis represents the shift value [V]. Also, the diamonds in the figure represent the measurement results when the channel width is 40 nm, the triangles represent when the channel width is 100 nm, and the squares represent

[0338] the measurement results when the channel width is 500 nm. From Fig. 34(D), it was confirmed that the change in the shift value is smaller when the channel width is narrower.

[0339]

[0339] Next, the drain voltage (V d ​: [V]) when the S value with respect to the channel width was measured when it was 0.1V. The measurement was performed. The measurement results of the example transistors are shown in Fig. 35(A). In Fig. 35(A), the horizontal axis represents the channel length [nm], and the vertical axis represents the S value [mV / dec.]. Note that the diamond shape in the figure indicates the measurement result when the channel width is 40 nm, the triangle indicates the measurement result when the channel width is 100 nm, and the square indicates the measurement result when the channel width is 50 0 nm.

[0340] From Fig. 35(A), it was confirmed that the smaller the channel width, the lower the S value.

[0341] Next, the measurement of DIBL with respect to the channel width was performed. The drain voltage (V d : [V]) is subtracted from the threshold voltage when the drain voltage (V d : [V]) is 1V, and the value obtained by dividing it by 0.9 is defined as DIBL. The measurement results of the example transistors are shown in Fig. 35(B). In Fig. 35(B), the horizontal axis represents the channel length [nm , and the vertical axis represents the DIBL value [V / V.]. Note that the diamond shape in the figure indicates the measurement result when the channel width is 40 nm , the triangle indicates the measurement result when the channel width is 100 nm, and the square indicates the measurement result when the channel width is 500 nm.

[0342] From Fig. 35(B), it was confirmed that as the channel width becomes narrower, DIBL decreases.

[0343] From the above, it was shown that the transistor of this example is a transistor having higher electrical characteristics as the channel width becomes narrower.

Example

[0344] In this example, as an example sample, a configuration similar to the transistor 460 shown in Fig. 6(A) The transistor was fabricated and its electrical characteristics were evaluated.

[0345] First, the method for fabricating the example sample will be described.

[0346] The method for fabricating the example sample can refer to Example 1. Note that, unlike Example 1, the first oxide film in this example has a film thickness of 10 nm, and the film formation conditions are as follows: An oxide target (IGZO(134)) with In:Ga:Zn = 1:3:4 (atomic ratio) was used to deposit the film by sputtering in an argon and oxygen (argon:oxygen = 30 sccm: 15 sccm) mixed atmosphere. A pressure of 0.4 Pa and a power supply power of 0.5 kW were applied, and the film was formed with a distance of 60 mm between the target and the substrate and a substrate temperature of 200 °C.

[0347] In addition, an example transistor with a channel length of 70 nm and a channel width of 40 nm was fabricated.

[0348] Next, in the fabricated transistor, the drain voltage (V d :[V]) was set to 1 V, and the gate voltage (V g :[V]) was swept from -3 V to 3 V, and the drain current (I d :[A ) was measured. Also, the field-effect mobility (μFE) was measured when the drain voltage was 0.1 V. The measurement results of the example transistor are shown in Fig. 11. In Fig. 11, it is the measurement result when the drain voltage (V d :[V]) is 1 V. The horizontal axis is the gate voltage (V g : V]), the left vertical axis is the drain current (I d :[A]), and the right vertical axis is the field-effect mobility (μ FE:cm 2 / Vs).

[0349] As shown in FIG. 11, the on-current of the transistor fabricated in this example was 5.08 μA when the drain voltage (V d :[V]) was 1 V. Also, the field-effect mobility when the drain voltage was 0.1 V was 17.0 cm / Vs. 2

[0350] From the above, it was shown that the transistor of this example is a transistor having high electrical characteristics.

Example

[0351] In this example, as an example sample, a transistor having the same configuration as the transistor 460 shown in FIG. 6(A) was fabricated, and the electrical characteristics with respect to the channel width were evaluated.

[0352] First, the manufacturing method of the example sample will be shown.

[0353] For the manufacturing method of the example sample, Example 1 can be referred to. The sample used in Example 1 ( The first oxide film is IGZO (132) with a film thickness of 10 nm, and the oxide semiconductor film is IGZO (111) with a film thickness of 40 nm was sample A, and the sample used in Example 5 (the first oxide film is IGZO (134) with a film thickness of 10 nm and the oxide semiconductor film is IGZO (111) with a film thickness of 40 nm) was sample B , and sample C was fabricated in which the first oxide film is IGZO (132) with a film thickness of 20 nm and the oxide semiconductor film is IGZO (111) with a film thickness of 15 nm and the other configurations are the same as those of sample A. Note that the film formation conditions of sample C are such that the first oxide film is formed by sputtering using an oxide target (IGZO (132)) with In:Ga:Zn = 1:3:2 (atomic ratio) in an argon and oxygen (argon:oxygen = 30 sccm:15 sccm) mixed atmosphere at a pressure of 0.4 ​​​​​Pa, a power supply power of 0.5 kW was applied, the distance between the target and the substrate was 60 mm, and the substrate temperature was set to 200 °C to form a film, and the oxide semiconductor film had an In:Ga:Zn = 1:1:1 (atomic ratio) oxide target (IGZO(111)). By sputtering method, argon and oxygen (argon:oxygen = 30 sccm:15 sccm) were used. In a mixed atmosphere, the pressure was 0 .4 Pa, a power supply power of 0.5 kW was applied, the distance between the target and the substrate was 60 mm, and the substrate temperature was set to 300 °C to form a film.

[0354] In addition, an example transistor with a channel length of 40 nm was fabricated.

[0355] Next, in the fabricated transistor, the drain voltage (V d :[V]) was 1 V, and the measurement of the on-current (I :[A]) with respect to the channel width W was performed. In this example, on the on-current was defined as the current value when the gate voltage was the threshold voltage + 1 V. The measurement results of the example transistor are shown in FIGS. 12 and 13. In FIGS. 12 and 13, the horizontal axis represents the channel width (W:[nm]), and the vertical axis represents the on-current (I :[A]). on

[0356] According to FIG. 12, for sample C with an oxide semiconductor film thickness of 15 nm, as the channel width W decreased, the on-current I on decreased. On the other hand, for samples A and B with an oxide semiconductor film thickness of 40 nm, even when the channel width W decreased, no decrease in the on-current I on was observed.

[0357] As the oxide semiconductor film becomes thicker, the electric field of the lateral gate electrode in the case of a short channel width becomes stronger, and the on-current I onis presumed to have been improved.

[0358] Also, FIG. 13(A) shows the characteristics of the transistor of Sample A, FIG. 13(B) shows the characteristics of the transistor of Sample B, and FIG. 13(C) shows the characteristics of the transistor of Sample C. From FIG. 13, it was confirmed that in any condition of Sample A, Sample B, and Sample C, as the channel width W becomes longer, the on-current I tends to increase. on

Example

[0359] In this example, as an example sample, a transistor having the same configuration as the transistor 460 shown in FIG. 6(A) was fabricated, and the electrical characteristics of the fabricated transistor were evaluated. First, a silicon oxynitride (SiO

[0360] N) film with a film thickness of 300 nm, which serves as an underlying insulating film, was formed on a silicon substrate. The silicon oxynitride film was formed by sputtering in a mixed atmosphere of argon and oxygen (argon: oxygen = 25 sccm: 25 sccm) under a pressure of 0.4 P

[0361] a and a power supply power (power supply output) of 5.0 kW applied, with a distance between the silicon substrate and the target of 60 mm and a substrate temperature of 100°C. (argon: oxygen = 25 sccm: 25 sccm) mixed atmosphere, a pressure of 0.4 P a, a power supply power (power supply output) of 5.0 kW was applied, and the film was formed under the conditions of a distance between the silicon substrate and the target of 60 mm and a substrate temperature of 100°C.

[0362] After polishing the surface of the silicon oxynitride film, a first oxide film with a film thickness of 20 nm and an oxide semiconductor film with a film thickness of 20 nm were laminated and formed. The film formation conditions were as follows: for the first oxide film, a sputtering ring method using an oxide target (IGZO(134)) with an In:Ga:Zn = 1:3:4 (atomic ratio) in a mixed atmosphere of argon and oxygen (argon: oxygen = 40 sccm: 5 sccm) ​​Under an atmosphere, a pressure of 0.4 Pa and a power supply power of 0.5 kW were applied, and film formation was carried out with the distance between the target and the substrate being 60 mm and the substrate temperature being 200 °C. The oxide semiconductor film was formed using an oxide target (IGZO(111)) with In:Ga:Z n = 1:1:1 (atomic ratio) by sputtering method with argon and oxygen (argon:oxygen = 30 sccm:15 sccm) under a mixed atmosphere. A pressure of 0.4 Pa and a power supply power of 0.5 kW were applied, and film formation was carried out with the distance between the target and the sub strate being 60 mm and the substrate temperature being 300 °C. Note that the first oxide film and the oxide semiconductor film were continuously formed without exposure to the atmosphere. Next, heat treatment was performed. The heat treatment was carried out at 450 °C for 1 hour in a nitrogen atmosphere, and then at 450 °C for 1 hour in an oxygen atmosphere.

[0363] Next, a tungsten film serving as a source electrode and a drain electrode was formed on the oxide semiconductor film to a thickness of 1 50 nm. The film formation conditions were as follows: by sputtering method using a tungsten target, in an argon (argon 80 sccm) atmosphere, a pressure of 0.8 Pa and a power supply power (power supply output) of 1.0 kW were applied, and film formation was carried out under the conditions of a distance of 60 mm between the silicon substrate and the target and a substrate

[0364] temperature of 230 °C. Next, a resist mask was formed on the tungsten film and etching was performed. The etching was carried out by ICP etching method. The first etching was carried out in a mixed atmosphere of chlorine, carbon tetrafluoride and oxygen (C l2:CF4:O2 = 45 sccm:55 sccm:55 sccm) at a power supply power of 3000 W, a bias power of 110 W and a pressure of 0.67 Pa. Then, the second etching was carried out. Next, a resist mask was formed on the tungsten film and etching was performed. The etching was carried out by ICP etching method. The first etching was carried out in a mixed atmosphere of chlorine, carbon tetrafluoride and oxygen (C

[0365] Next, a resist mask was formed on the tungsten film and etching was performed. The etching was carried out by ICP etching method. The first etching was carried out in a mixed atmosphere of chlorine, carbon tetrafluoride and oxygen (C l2:CF4:O2 = 45 sccm:55 sccm:55 sccm) at a power supply power of 3000 W, a bias power of 110 W and a pressure of 0.67 Pa. Then, the second etching was carried out in a mixed atmosphere of chlorine, carbon tetrafluoride and oxygen (C l2:CF4:O2 = 45 sccm:55 sccm:55 sccm) at a power supply power of 3000 W, a bias power of 110 W and a pressure of 0.67 Pa. Etching was performed in an oxygen (O2 = 100 sccm) atmosphere at a power supply power of 2000 W, a bias power of 0 W, and a pressure of 3.0 Pa. Further, the third etching was performed in a mixed atmosphere of chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm) at a power supply power of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa, and source electrodes and drain electrodes were formed.

[0366] Next, a resist mask was formed on the oxide semiconductor film, and the first oxide film and the oxide semiconductor film were processed into island-shaped first oxide films and oxide semiconductor films by the ICP etching method in a boron trichloride (BCl3 = 80 sccm) atmosphere at a power supply power of 450 W, a bias power of 100 W, a pressure of 1.2 Pa, and a substrate temperature of 70 °C.

[0367] Next, a second oxide film with a thickness of 5 nm was formed on the oxide semiconductor film, the source electrode, and the drain electrode. The film formation conditions were argon and oxygen (argon:oxygen = 30 sccm:15 sccm) in a mixed atmosphere using an oxide target of In:Ga:Zn = 1:3:2 (atomic ratio) (IGZO(132)) by sputtering method, at a pressure of 0.4 Pa and an applied power supply power of 0.5 kW, with a distance between the target and the substrate of 60 mm and a substrate temperature of 200 °C.

[0368] Next, a 20-nm silicon oxynitride film serving as a gate insulating film was formed by the CVD method.

[0369] Next, a 30-nm tantalum nitride film was formed by sputtering on the silicon oxynitride film in an atmosphere of tantalum nitride and argon (TaN:Ar = 50 sccm:10 sccm). , a pressure of 0.6 Pa and a power supply power of 1 kW were applied, and the distance between the target and the substrate was 60 mm. The film was formed with the substrate temperature at room temperature, and on it, a tungsten film with a thickness of 135 nm was formed in an argon (Ar = 100 sccm) atmosphere with a pressure of 2.0 Pa and a power supply power of 4 kW applied, and the distance between the target and the substrate was 60 mm, and the film was formed by laminating with the substrate temperature at 230 °C.

[0370] Next, by the ICP etching method, the laminate of the tantalum nitride film with a thickness of 30 nm and the tungsten film with a thickness of 135 n m was etched. The etching conditions were as follows: in a mixed atmosphere of chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm), at a power supply power of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa, the first etching was performed. After the first etching, in a chlorine (Cl2 = 100 sccm) atmosphere, at a power supply power of 1000 W, a bias power of 50 W, and a pressure of 0.67 Pa, the second etching was performed to form the gate electrode.

[0371] Next, by the ICP etching method, the laminate of the gate insulating film and the second oxide film was etched. The etching conditions were as follows: in a boron trichloride (BCl3 = 80 sccm) atmosphere, at a power supply power of 4 50 W, a bias power of 100 W, a pressure of 1.2 Pa, and a substrate temperature of 70 °C, the etching was performed.

[0372] Next, an aluminum oxide film with a thickness of 140 nm was formed on the gate electrode by sputtering method, and on it, a silicon oxynitride film with a thickness of 300 nm was formed by CVD method.

[0373] The channel length of the fabricated transistor was 0.48 μm and the channel width was 0.5 μm. .

[0374] Next, the temperature dependence of the fabricated transistor was evaluated.

[0375] The evaluation was performed under six conditions of 25°C, 50°C, 100°C, 150°C, 200°C, and 250°C, with the drain voltage (V :[V]) being 1 V and the gate voltage (V d :[V]) being swept from -3 V to 3 V. The drain current (I g :[A]) per 1 μm channel width was measured when swept. The measurement results of the transistor of the example are shown in FIG. 40(A). In FIG. 40(A), the horizontal axis is the gate voltage (V d :[V]), and the vertical axis is the drain current (I :[A]). The arrows in the figure indicate that the temperature increases from the base to the tip of the arrow. is the gate voltage (V g :[V]), and the vertical axis is the drain current (I d :[A]). Note that the arrows in the figure indicate that the temperature increases from the base to the tip of the arrow. It was confirmed that the on-current of the transistor fabricated in this example does not change significantly with temperature changes.

[0376] As shown in FIG. 40, it was confirmed that the on-current of the transistor fabricated in this example does not change significantly with temperature changes.

[0377] Also, the temperature dependencies of the threshold voltage and the S value are shown in FIGS. 40(B) and 40(C ).

[0378] It was confirmed that the values of the threshold voltage and the S value do not change significantly with temperature changes.

[0379] From the above, it was shown that the transistor of this example is a transistor with temperature tolerance.

Example

[0380] In this example, the difference in electrical characteristics due to the shape of the oxide semiconductor film was simulated and evaluated.

[0381] First, the structure of the transistor will be described.

[0382] FIG. 25(A) is a cross-sectional view in the channel width direction of a transistor (hereinafter also referred to as a transistor with a square structure) in which the upper end portion of the oxide semiconductor film is angular. W in the figure indicates the channel width, and the film thickness of the oxide semiconductor film is set to be W / 2. FIG. 25(A) is a cross-sectional view in the channel width direction of a transistor (hereinafter also referred to as a transistor with a square structure) in which the upper end portion of the oxide semiconductor film is angular. W in the figure indicates the channel width, and the film thickness of the oxide semiconductor film is set to be W / 2. FIG. 25(A) is a cross-sectional view in the channel width direction of a transistor (hereinafter also referred to as a transistor with a square structure) in which the upper end portion of the oxide semiconductor film is angular. W in the figure indicates the channel width, and the film thickness of the oxide semiconductor film is set to be W / 2.

[0383] Further, FIG. 25(B) is a cross-sectional view in the channel width direction of a transistor (hereinafter also referred to as a transistor with a semi-circular structure) in which the upper end portion of the oxide semiconductor film has a curved surface, which is a structure of one embodiment of the present invention. r in the figure indicates the radius of curvature, and it is set to be r = W / 2. Further, FIG. 25(B) is a cross-sectional view in the channel width direction of a transistor (hereinafter also referred to as a transistor with a semi-circular structure) in which the upper end portion of the oxide semiconductor film has a curved surface, which is a structure of one embodiment of the present invention. r in the figure indicates the radius of curvature, and it is set to be r = W / 2. Further, FIG. 25(B) is a cross-sectional view in the channel width direction of a transistor (hereinafter also referred to as a transistor with a semi-circular structure) in which the upper end portion of the oxide semiconductor film has a curved surface, which is a structure of one embodiment of the present invention. r in the figure indicates the radius of curvature, and it is set to be r = W / 2.

[0384] In the square structure and the semi-circular structure, the effective channel width of each is 2W obtained by adding the side surface and the upper surface in the square structure, and πr = πW / 2 = 1.57W in the circumferential portion in the semi-circular structure. The ratio of the effective channel width W at this time is 0.785. In the square structure and the semi-circular structure, the effective channel width of each is 2W obtained by adding the side surface and the upper surface in the square structure, and πr = πW / 2 = 1.57W in the circumferential portion in the semi-circular structure. The ratio of the effective channel width W at this time is 0.785. In the square structure and the semi-circular structure, the effective channel width of each is 2W obtained by adding the side surface and the upper surface in the square structure, and πr = πW / 2 = 1.57W in the circumferential portion in the semi-circular structure. The ratio of the effective channel width W at this time is 0.785.

[0385] Also, the cross-sectional views in the channel length direction of the transistors shown in FIGS. 25(A) and 25(B) are both as shown in FIG. 26. L in the figure indicates the channel length. Also, the cross-sectional views in the channel length direction of the transistors shown in FIGS. 25(A) and 25(B) are both as shown in FIG. 26. L in the figure indicates the channel length.

[0386] Next, the calculation conditions will be described.

[0387] For the calculation, Sentaurus of Synopsys was used, and simulations were performed under the conditions shown in Table 1. For the calculation, Sentaurus of Synopsys was used, and simulations were performed under the conditions shown in Table 1.

[0388] [Table 1]

[0389] In FIG. 27, the drain voltage (Vd : [V]) when it is 0.1V of I d -V g characteristics and mobility, In FIG. 28, the drain voltage (V d : [V]) when it is 1V of I d -V g characteristics and mobility are shown.

[0390] From FIGS. 27 and 28, the I of the semicircular structure d -V g characteristics have a better turn-on voltage compared to the square structure. Also, the mobility calculated using the effective channel width W is larger for the semicircular structure than that of the square structure.

[0391] Also, Table 2 shows a comparison of various characteristic values obtained from FIGS. 27 and 28.

[0392]

Table 2

[0393] From Table 2, it can be seen that the semicircular structure is superior to the square structure in characteristics other than the on-current. Also, regarding the on-current, the ratio is 0.892, which is larger than the ratio of the effective channel width W of 0 .785. That is, it can be said that electrons are more easily induced in the channel part of the semicircular structure .

[0394] One reason why electrons are more easily induced in the channel part of the semicircular structure is considered to be the relationship between the effective channel width W and the on-current. The on-current is considered to be proportional to the capacitance of the gate insulating film (hereinafter also referred to as the GI capacitance), but in the semicircular structure, the GI capacitance is not expressed by the formula of a parallel plate and is approximately expressed by the following formula. GI capacitance) and is considered to be proportional. However, in the semicircular structure, the GI capacitance is not represented by the formula of a parallel plate and is approximately represented by the following formula.

[0395]

Equation

[0396] C r is the GI capacitance per unit channel length of the semi-circular structure, ε is the dielectric constant of the gate insulating film, t GI is the thickness of the gate insulating film, t OS represents the thickness of the oxide semiconductor film.

[0397] In the case of the semi-circular structure, the GI capacitance is not proportional to the effective channel width W(πt OS ), and the on current cannot be discussed in terms of the ratio of the effective channel width W as described above.

[0398] On the other hand, the GI capacitance per unit channel length of the rectangular structure is approximately expressed by the following formula.

[0399]

Equation

[0400] To obtain the on-current, it is necessary to consider the ratio of the GI capacitances. Taking the ratio of the GI capacitance of the rectangular structure obtained from Equation 2 and the GI capacitance of the semi-circular structure obtained from Equation 1, C / C r / C s = 0.9 68 or so, which is larger than the ratio of the effective channel width W of 0.785. This estimate is approximate and does not match the ratio of the calculation results by simulation, but it can be said that the semi-circular structure is more likely to induce electrons in the channel part. <Reference Example>

[0401] In this reference example, the resistance of the transistor using the CAAC-OS film to the short-channel effect will be explained in terms of its sufficiency.

[0402] As an index of the resistance to the short-channel effect, the characteristic length (Characteristic Length) is widely used. The characteristic length is an index of the "bending way" of the potential in the channel region. The shorter the characteristic length, the steeper the potential rises, so the short-channel effect is stronger.

[0403] The transistor using the CAAC-OS film is an accumulation-type transistor. The reason why the transistor using the CAAC-O S film is strong in the short-channel effect is considered to be due to the fact that the characteristic length of the accumulation-type transistor is shorter than the characteristic length of the inversion-type transistor.

[0404] This will be described in detail with reference to the schematic diagram of the transistor structure in FIG. 36. Note that ε S is the dielectric constant of the semiconductor film, ε is the dielectric constant of the gate insulating film, t OX is the thickness of the semiconductor film, t S is the thickness of the semiconductor film, t OX is the thickness of the gate insulating film is.

[0405] First, assume an n-channel inversion-type transistor and solve its Poisson equation to analyze the potential in the channel region. Note that by applying Gauss's law to the minute section x to x + dx in the semiconductor film that becomes the channel region, which is shown by hatching in the figure, the following equation was derived. Here, φ(x) is the potential (surface potential) at position x, φ(x + dx

[0406]

Equation

[0407] is the potential (surface potential) at position x + dx, V ) is the potential (surface potential) at position x + dx, V G is the gate voltage, V F B is the flat-band voltage, e is the elementary charge, and N A is the acceptor density.

[0408] Rearranging the above Equation 3 gives the following.

[0409]

Equation

[0410] Here, Equation 5 below was substituted into Equation 4 to obtain Equation 6.

[0411]

Equation

[0412]

Equation

[0413] Furthermore, the general solution of Equation 6 was obtained using Equation 7 below to obtain Equation 8.

[0414]

Equation

[0415]

Equation

[0416] Furthermore, the potential φ(x) satisfies the following boundary conditions.

[0417]

Equation

[0418] The coefficients A and B were obtained and rearranged so as to satisfy the above boundary conditions, and the particular solution of the differential equation was obtained, and the potential φ(x) is as follows.

[0419]

Equation

[0420] Actually, by substituting x = 0 or x = L into the equation respectively, it can be easily verified that Equation 10 satisfies the boundary conditions of Equation 9.

[0421] Here, l in the formula is the characteristic length, which serves as an index of the ease of potential bending. The shorter the length is, the more steeply the potential in the channel portion of the FET changes.

[0422] Therefore, the characteristic length of the inversion-type transistor is as follows.

[0423]

Equation

[0424] Next, the same consideration is made for the accumulation-type transistor including the transistor using the CAAC-OS film, and the characteristic lengths are compared. Similarly, by applying Gauss's law to the minute section x to x + dx in the semiconductor film serving as the channel portion, the following equation is derived.

[0425]

Equation

[0426] Here, n i is the intrinsic carrier density, k B is the Boltzmann constant, and φ F is the Fermi potential barrier.

[0427] When the above equation is rearranged, it becomes as follows.

[0428]

Equation

[0429] ​ However, l is equal to the channel length of the depletion-mode transistor.

[0430] The right side of Equation 13 was expanded using the following approximate equation (Equation 14) in the above equation to obtain Equation 15. and obtained.

[0431]

Equation

[0432]

Equation

[0433] Here, n1 is the electron density at position x1. Furthermore, the following Equations 16 and 17 were substituted into Equation 15 to obtain Equation 18.

[0434]

Equation

[0435]

Equation

[0436]

Equation

[0437] Furthermore, Equation 18 was rearranged using the following Equation 19 to obtain Equation 20.

[0438]

Equation

[0439]

Equation

[0440] The above formula is only valid in the vicinity of point x1.

[0441] From the above discussion, the characteristic length of the accumulation-type transistor in the vicinity of point x1 is as follows as follows.

[0442]

Number

[0443]

Number

[0444] From the above formula, it can be seen that l(inv) > l(acc).

[0445] Note that the value of the characteristic length l(acc) of the accumulation-type transistor calculated by point x1 varies, but in any case it is shorter than that of the depletion-type transistor. Furthermore, since the electron density increases near the source / drain, the potential rises more steeply . .

[0446] As described above, it is shown that the characteristic length of the accumulation-type transistor is shorter than that of the depletion-type transistor. .

Explanation of Signs

[0447] 110 Substrate 120 Underlying insulating film 137 Channel region 138 Channel region 160 Gate insulating film 170 gate electrode 210 substrate 220 underlayer insulating film 230 oxide semiconductor film 260 gate insulating film 270 gate electrode 400 substrate 402 underlayer insulating film 403a first oxide film 403b oxide semiconductor film 403c second oxide film 404 multilayer film 404a first oxide film 404b oxide semiconductor film 404c second oxide film 405a conductive film 405b conductive film 406a source electrode 406b drain electrode 407 insulating film 408 gate insulating film 409 conductive film 410 gate electrode 412 oxide insulating film 414 barrier film 416 sidewall insulating film 418 sidewall insulating film 419a electrode 419b electrode 420a wiring 420b wiring 435 boundary 450 transistor 460 transistor 470 transistor 550 transistor 560 transistor 570 transistor 580 transistor 602 photodiode 640 transistor 656 transistor 658 photodiode reset signal line 659 gate signal line 672 Photo Sensor Reference Signal Line 700 Memory Element 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic Element 707 Capacitor Element 708 Capacitor Element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 1189 ROM Interface 1190 Substrate 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 Transistor 2201 Insulating Film 2202 Wiring 2203 Plug 2204 Insulating Film 2205 Wiring 2206 Wiring 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitor Element 8000 Television Device 8001 Housing 8002 Display Unit 8003 Speaker Unit 8004 CPU 8100 Alarm device 8101 Microcomputer 8102 Detection unit 8200 Indoor unit 8201 Housing 8202 Air outlet 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Door for refrigerator compartment 8303 Door for freezer compartment 8304 CPU 9700 Electric vehicle 9701 Secondary battery 9702 Circuit 9703 Driving device 9704 Processing device

Claims

1. A first insulating film; an oxide film disposed above the first insulating film; an oxide semiconductor film disposed above the oxide film and having a channel formation region of a first transistor; a source electrode and a drain electrode of the first transistor, the source electrode and the drain electrode being electrically connected to the oxide semiconductor film and having a region in contact with the oxide semiconductor film; a gate insulating film of the first transistor having a region disposed above the oxide semiconductor film; a gate electrode of the first transistor, the gate electrode being disposed above the gate insulating film and having a region in contact with the gate insulating film; a second insulating film having a region disposed above a gate electrode of the first transistor; an interconnection having a region disposed above the second insulating film; a gate electrode of a second transistor disposed under the first insulating film; a channel formation region of the second transistor disposed below a gate electrode of the second transistor; When nanobeam electron diffraction is performed on the oxide semiconductor film, a plurality of spots are observed within a ring-shaped region, a channel formation region of the second transistor includes silicon; a gate electrode of the first transistor has a region in which a bottom surface of the gate electrode of the first transistor is located below a bottom surface of the oxide semiconductor film; the first insulating film has a first region that does not overlap with the oxide film and a second region that overlaps with the oxide film; The thickness of the first region is smaller than the thickness of the second region, a source electrode or a drain electrode of the first transistor is electrically connected to a source region or a drain region of the second transistor through a first contact hole penetrating the first region; a gate electrode of the first transistor is electrically connected to the wiring; the wiring is electrically connected to a gate electrode of the second transistor via a second contact hole that penetrates the first region.

2. In claim 1, the first transistor is an n-channel type; the second transistor is a p-channel transistor, The first transistor and the second transistor constitute an inverter.

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