Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide a silicon carbide semiconductor device and a manufacturing method of the silicon carbide semiconductor device capable of improving the trade-off between Vth and carrier mobility.SOLUTION: A silicon carbide semiconductor device 70 includes a first conductivity type silicon carbide semiconductor substrate 1, a first conductivity type first semiconductor layer 2, a second conductivity type second semiconductor layer 6, a first conductivity type first semiconductor region 7, a trench 16, a gate insulating film 9, and a gate electrode 10. The silicon carbide semiconductor device 70 has a minimum S value of 0.24 V / dec. or more and 0.3 V / dec. or less in a subthreshold region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device.

Background Art

[0002] Silicon carbide (SiC) is expected as a next-generation semiconductor material to replace silicon (Si). A semiconductor device using silicon carbide as a semiconductor material (hereinafter referred to as a silicon carbide semiconductor device) has various advantages compared with a conventional semiconductor device using silicon as a semiconductor material, such as being able to reduce the resistance of the device in the on state to one several hundredth, and being usable in an environment at a higher temperature (200°C or higher). This is due to the characteristics of the material itself that the bandgap of silicon carbide is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly one order of magnitude larger than that of silicon.

[0003] To date, as silicon carbide semiconductor devices, a Schottky Barrier Diode (SBD), a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a planar gate structure or a trench gate structure have been commercialized.

[0004] The planar gate structure is a MOS gate structure in which a planar MOS gate is provided on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed in a direction perpendicular to the front surface of the semiconductor substrate along the side wall of the trench. Therefore, compared with the planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, the unit cell (the constituent unit of the device) density per unit area can be increased, and the current density per unit area can be increased, which is advantageous in terms of cost.

[0005] Also, the interface between the epitaxial layer and the gate insulating film is 5×1011 cm -2 eV -1 By setting the interface state density to less than a certain value, a large channel mobility can be more reliably obtained, and by setting the S value to 200 mV / decade or less, a silicon carbide semiconductor device with steep switching characteristics is known (for example, see Patent Document 1 below).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] Here, in conventional silicon carbide MOSFETs, there is a problem of a trade-off that generally, as the threshold voltage Vth increases, the carrier mobility decreases, and as the carrier mobility is improved, the threshold voltage Vth decreases. The higher the threshold voltage, the lower the possibility of accidental turn-on due to electromagnetic noise or the like, and the higher the carrier mobility, the lower the on-resistance (RonA). For example, if the threshold voltage Vth is set to 5 to 6 V, which is comparable to that of a silicon IGBT, the carrier mobility becomes too low.

[0008] An object of this invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can improve the trade-off between Vth and carrier mobility in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0009] In order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate of the first conductivity type. A second semiconductor layer of a second conductivity type is provided on the surface of the first semiconductor layer opposite to the side of the silicon carbide semiconductor substrate. A first semiconductor region of the first conductivity type is selectively provided in the surface layer of the second semiconductor layer opposite to the side of the silicon carbide semiconductor substrate. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. A gate electrode is provided in the trench via a gate insulating film. A first electrode is provided on the surfaces of the second semiconductor layer and the first semiconductor region. A second electrode is provided on the back surface of the silicon carbide semiconductor substrate. The minimum value of the S value in the subthreshold region is 0.24 V / dec. or more and 0.3 V / dec. or less. The threshold voltage is 5.9 V or higher. In the region where the second semiconductor layer faces the first semiconductor region in the depth direction, the impurity concentration is uniform.

[0010] Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the minimum value of the S value in the subthreshold region is 1.1 times or more and 1.4 times or less of the value at which the S value saturates with nitridation when forming the gate insulating film.

[0011] In order to solve the above problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is performed on the front surface of the silicon carbide semiconductor substrate of the first conductivity type. Next, a second step of forming a second semiconductor layer of a second conductivity type is performed on the surface of the first semiconductor layer opposite to the side of the silicon carbide semiconductor substrate. Next, a third step of selectively forming a first semiconductor region of a first conductivity type in the surface layer of the second semiconductor layer opposite to the side of the silicon carbide semiconductor substrate is performed. Next, a fourth step of forming a gate insulating film in contact with the second semiconductor layer is performed. Next, a fifth step of performing post-annealing on the gate insulating film with a gas containing nitrogen is performed. Next, a sixth step of forming a gate electrode on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer is performed. Next, a seventh step of forming a first electrode on the surfaces of the second semiconductor layer and the first semiconductor region is performed. Next, an eighth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate is performed. In the fifth step, the annealing time of the post-annealing is 8 minutes or more and 12 minutes or less, or the concentration of nitric oxide in the post-annealing is 3% or more and 7% or less. Before the fourth step, the method includes a step of forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. In the fourth step, a gate insulating film is formed inside the trench. In the sixth step, a gate electrode is formed inside the trench via the gate insulating film, and no sacrificial oxidation is performed on the trench.

[0013] According to the above-described invention, the minimum value of the S value in the subthreshold region is 0.24 V / dec. or more and 0.3 V / dec. or less. This is because by setting the annealing time of the NO-PDA to 8 minutes or more and 12 minutes or less, or setting the NO concentration of the NO-PDA to 3% or more and 7% or less, the above S value can be realized, whereby the carrier mobility can be made comparable to that of a conventional trench-type MOSFET, the Vth can be increased, and the trade-off between Vth and carrier mobility can be improved.

Effect of the Invention

[0014] According to the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention, there is an effect that the trade-off between Vth and carrier mobility can be improved.

Brief Description of the Drawings

[0015]

Figure 1

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Figure 13

Embodiments for Carrying Out the Invention

[0016] With reference to the accompanying drawings below, a silicon carbide semiconductor device and a preferred embodiment of the silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in the case of a layer or region preceded by n or p, it means that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layer or region to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. Further, in this specification, in the notation of Miller indices, "-" means a bar attached to the immediately following index, and a negative index is represented by attaching "-" before the index. And the description of the same or equivalent shall preferably include within 5% in consideration of variations in manufacturing.

[0017] (Embodiment) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as the wide bandgap semiconductor will be described by taking the trench type MOSFET 70 as an example. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. In FIG. 1, only the active region through which the main current of the trench type MOSFET 70 flows is shown.

[0018] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment has an n + type silicon carbide substrate (a silicon carbide semiconductor substrate of the first conductivity type) 1 on the first main surface (front surface), for example, the (0001) surface (Si surface), an n - type silicon carbide epitaxial layer (a first semiconductor layer of the first conductivity type) 2 is deposited.

[0019] n + type silicon carbide substrate 1 is a single crystal silicon carbide substrate. n -The n-type silicon carbide epitaxial layer 2 has an impurity concentration lower than that of the n + -type silicon carbide substrate 1, and is, for example, a low-concentration n-type drift layer. The n - -type silicon carbide epitaxial layer 2 may have an n-type high-concentration region 5 provided on the surface opposite to the side of the n + -type silicon carbide substrate 1. The n-type high-concentration region 5 is a high-concentration n-type drift layer having an impurity concentration lower than that of the n + -type silicon carbide substrate 1 and higher than that of the n - -type silicon carbide epitaxial layer 2.

[0020] n - On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the side of the n + -type silicon carbide substrate 1, a p-type base layer (a second semiconductor layer of the second conductivity type) 6 is provided. Hereinafter, the n + -type silicon carbide substrate 1, the n - -type silicon carbide epitaxial layer 2, the n-type high-concentration region 5, and the p-type base layer 6 are combined to form a silicon carbide semiconductor substrate (a semiconductor substrate made of silicon carbide) 18.

[0021] n + On the second main surface (the back surface, that is, the back surface of the silicon carbide semiconductor substrate 18) of the n-type silicon carbide substrate 1, a drain electrode serving as a back surface electrode 13 is provided. On the surface of the back surface electrode 13, a drain electrode pad (not shown) is provided.

[0022] On the first main surface side (the p-type base layer 6 side) of the silicon carbide semiconductor substrate 18, a trench structure is formed. Specifically, the trench 16 penetrates the p-type base layer 6 from the surface on the side opposite to the side of the n + -type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate 18) and reaches the n-type high-concentration region 5 (when the n-type high-concentration region 5 is not provided, the n -The type silicon carbide epitaxial layer 2 (hereinafter simply referred to as (2)) is reached. Along the inner wall of the trench 16, a gate insulating film 9 is formed on the bottom and side walls of the trench 16, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 16. The gate electrode 10 is insulated from the n-type high-concentration region 5(2) and the p-type base layer 6 by the gate insulating film 9. A part of the gate electrode 10 may protrude from above the trench 16 (the side where the source electrode 12 described later is provided) toward the source electrode 12 side.

[0023] n of the n-type high-concentration region 5(2) + On the surface layer on the side opposite to the type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate 18), a first p-type base region 3 is provided between the trenches 16. + Also, a second p-type base region 4 in contact with the bottom of the trench 16 is provided in the n-type high-concentration region 5(2). + The second p-type base region 4 + is provided at a position facing the bottom of the trench 16 in the depth direction (the direction from the source electrode 12 to the drain electrode 13). The width of the second p-type base region 4 is the same as or wider than the width of the trench 16. The bottom of the trench 16 may reach the second p-type base region 4, or may be located in the n-type high-concentration region 5(2) sandwiched between the p-type base layer 6 and the second p-type base region 4. + The width of the second p-type base region 4 is the same as or wider than the width of the trench 16. The bottom of the trench 16 may reach the second p-type base region 4, or may be located in the n-type high-concentration region 5(2) sandwiched between the p-type base layer 6 and the second p-type base region 4. + The bottom of the trench 16 may reach the second p-type base region 4, or may be located in the n-type high-concentration region 5(2) sandwiched between the p-type base layer 6 and the second p-type base region 4. + is located in the n-type high-concentration region 5(2) sandwiched between the p-type base layer 6 and the second p-type base region 4.

[0024] Also, an n-type region 17 having a peak impurity concentration higher than that of the n-type high-concentration region 5(2) is provided in the type silicon carbide epitaxial layer 2 at a position deeper than the first p-type base region 3 between the trenches 16. Note that the deep position means a position closer to the drain electrode 13 than the first p-type base region 3. - In the type silicon carbide epitaxial layer 2, an n-type region 17 having a peak impurity concentration higher than that of the n-type high-concentration region 5(2) is provided at a position deeper than the first p-type base region 3 between the trenches 16. + In the type silicon carbide epitaxial layer 2, an n-type region 17 having a peak impurity concentration higher than that of the n-type high-concentration region 5(2) is provided at a position deeper than the first p-type base region 3 between the trenches 16. + Note that the deep position means a position closer to the drain electrode 13 than the first p-type base region 3. + is a position closer to the drain electrode 13 than the first p-type base region 3.

[0025] Inside the p-type base layer 6, an n-type region is provided on the first main surface side of the silicon carbide semiconductor substrate 18. +The n-type source region (the first semiconductor region of the first conductivity type) 7 is selectively provided. Also, a p + type contact region 8 may be selectively provided. Also, an n + type source region 7 and a p + type contact region 8 are in contact with each other.

[0026] The interlayer insulating film 11 is provided so as to cover the gate electrode 10 embedded in the trench 16 over the entire surface on the first main surface side of the silicon carbide semiconductor substrate 18. The source electrode 12 is connected to the n + type source region 7 and the p-type base layer 6 through a contact hole opened in the interlayer insulating film 11. Also, when a p + type contact region 8 is provided, the source electrode 12 is connected to the n + type source region 7, the p-type base layer 6, and the p + type contact region 8. The source electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. A barrier metal 14 for preventing diffusion of metal atoms from the source electrode 12 toward the gate electrode 10 may be provided between the source electrode 12 and the interlayer insulating film 11.

[0027] Here, in the trench type MOSFET 70 according to the embodiment, the minimum value of the S value in the subthreshold region is 0.24 V / decade (hereinafter, abbreviated as V / dec.) or more and 0.3 V / dec. or less.

[0028] As described below, as the nitriding time after forming the gate insulating film 9 increases, the S value decreases, and after a certain time (for example, 10 minutes) or more, the value of the S value saturates at a substantially constant value without increasing. In the trench-type MOSFET 70 according to the embodiment, the minimum value of the S value in the subthreshold region is preferably 1.1 times or more and 1.4 times or less the value at which the S value saturates with nitriding when forming the gate insulating film 9. For example, the value at which the S value of the current trench-type MOSFET 70 saturates is about 0.21 V / dec. In this case, it falls within the above range (0.24 V / dec. ≤ S value ≤ 0.3 V / dec.).

[0029] Here, the S value is

Number

[0030] Also, the subthreshold region is the state of the MOSFET when the gate-source voltage is equal to or less than the threshold voltage Vth. In this state, Id and Vg are approximately in a proportional relationship, but not in a perfect proportional relationship. Therefore, the measurement results of the S value are not necessarily the same throughout the subthreshold region.

[0031] Therefore, the S value in the subthreshold region in the embodiment is preferably the measurement result in the region where Vg is 70% or less of Vth (Vg ≤ 0.7Vth), and more preferably the measurement result in the region where Vg is 50% or less of Vth (Vg ≤ 0.5Vth).

[0032] As described below, when the minimum value of the S value in the subthreshold region is within the above range, the trench-type MOSFET 70 according to the embodiment can increase Vth while keeping the carrier mobility at the same level as that of the conventional trench-type MOSFET, and can improve the trade-off between Vth and carrier mobility.

[0033] (Method for manufacturing silicon carbide semiconductor device according to embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. FIGS. 2 to 6 are cross-sectional views showing states during the manufacture of the silicon carbide semiconductor device according to the embodiment.

[0034] First, an n + -type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Then, on the first main surface of this n + -type silicon carbide substrate 1, a lower n - -type silicon carbide epitaxial layer 2a made of silicon carbide is epitaxially grown to a thickness of about 30 μm while doping with an n-type impurity, for example, nitrogen atoms (N). The state up to this point is shown in FIG. 2.

[0035] Next, on the surface of the lower n - -type silicon carbide epitaxial layer 2a, a mask (not shown) having a desired opening is formed, for example, with an oxide film, by photolithography technology. Then, an n-type impurity, for example, nitrogen atoms, may be ion-implanted using this oxide film as a mask by the ion implantation method. As a result, an n - -type region 17 is formed inside the lower n + -type silicon carbide epitaxial layer 2a.

[0036] Next, the mask used during the ion implantation for forming the n + -type region 17 is removed. Next, an ion implantation mask having a predetermined opening is formed, for example, with an oxide film, by photolithography technology. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p + -type base region 3a and a second p + -type base region 4. When the n + -type region 17 is formed, on the surface of the n + -type region 17 on the side opposite to the n + -type silicon carbide substrate 1, the lower first p + -type base region 3a is formed so as to overlap the n + -type region 17.

[0037] Next, a part of the mask for ion implantation is removed, and n-type impurities such as nitrogen are ion-implanted into the opening, and the lower n - type silicon carbide epitaxial layer 2a, a lower n-type high-concentration region 5a with a depth of about 0.5 μm, for example, may be formed in a part of the surface region. The impurity concentration of the lower n-type high-concentration region 5a is, for example, 1×10 17 / cm 3 is set to about. The state up to here is described in FIG. 3.

[0038] Next, on the surface of the lower n - type silicon carbide epitaxial layer 2a, an upper n - type silicon carbide epitaxial layer 2b doped with n-type impurities such as nitrogen is formed with a thickness of about 0.5 μm. The impurity concentration of the upper n - type silicon carbide epitaxial layer 2b is set to be about 3×10 15 / cm 3 or so. Thereafter, the lower n - type silicon carbide epitaxial layer 2a and the upper n - type silicon carbide epitaxial layer 2b are combined to form an n - type silicon carbide epitaxial layer 2.

[0039] Next, on the surface of the upper n - type silicon carbide epitaxial layer 2b, a mask for ion implantation having a predetermined opening is formed, for example, with an oxide film by photolithography. Then, p-type impurities such as aluminum are implanted into the opening of the oxide film, and an upper first p + type base region 3b with a depth of about 0.5 μm is formed so as to overlap the lower first p + type base region 3a. The lower first p + type base region 3a and the upper first p + type base region 3b form a continuous region to form a first p + type base region 3. The impurity concentration of the upper first p + type base region 3b is set to be about 5×10 18 / cm 3 or so.

[0040] Next, a part of the mask for ion implantation is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening, and n - type silicon carbide epitaxial layer 2, an upper n-type high-concentration region 5b having a depth of about 0.5 μm, for example, may be formed in a part of the surface region. The impurity concentration of the upper n-type high-concentration region 5b is, for example, 1×10 17 / cm 3 Set to about. The upper n-type high-concentration region 5b and the lower n-type high-concentration region 5a are formed so as to be in contact with at least a part of each other to form an n-type high-concentration region 5. However, there are cases where the n-type high-concentration region 5 is formed over the entire substrate and cases where it is not formed. The state up to this point is described in FIG. 4.

[0041] Next, n - type silicon carbide epitaxial layer 2, a p-type base layer 6 is formed on the surface by epitaxial growth to a thickness of about 1.1 μm. The impurity concentration of the p-type base layer 6 is 4×10 17 / cm 3 Set to about. After the p-type base layer 6 is formed by epitaxial growth, a p-type impurity such as aluminum may be further ion-implanted into the p-type base layer 6.

[0042] Next, a predetermined region constituting the MOS gate is formed in the first main surface layer (the surface layer of the p-type base layer 6) of the silicon carbide semiconductor substrate 18. Specifically, an ion implantation mask having a predetermined opening is formed on the surface of the p-type base layer 6, for example, with an oxide film, by photolithography. An n-type impurity such as nitrogen (N) or phosphorus (P) is ion-implanted into this opening to form an n + type source region 7 in a part of the surface of the p-type base layer 6. Next, the ion implantation mask used for forming the n + type source region 7 is removed, and an ion implantation mask having a predetermined opening is formed in the same manner, and a p-type impurity such as boron is ion-implanted into a part of the surface of the p-type base layer 6 to form a p + type contact region 8. The impurity concentration of the p + type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6.

[0043] Next, a heat treatment (activation annealing) is performed to activate the entire region formed by ion implantation. For example, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700 °C to activate the first p + -type base region 3, the second p + -type base region 4, the n + -type source region 7, the p + -type contact region 8, and the n + -type region 17. Note that, as described above, each ion implantation region may be activated collectively by a single heat treatment, or heat treatment may be performed each time ion implantation is carried out for activation. The state up to this point is described in FIG. 5.

[0044] Next, a trench formation mask having a predetermined opening is formed, for example, of an oxide film, on the surface of the p-type base layer 6 by photolithography. Next, a trench 16 that penetrates the p-type base layer 6 and reaches the n-type high-concentration region 5(2) is formed by dry etching. The bottom of the trench 16 may reach the second p + -type base region 4 formed in the n-type high-concentration region 5(2). Next, the trench formation mask is removed. Next, RCA cleaning (wet cleaning using a strong acid and a high-base solution) is performed on the front surface of the silicon carbide semiconductor substrate 18.

[0045] Next, a gate insulating film 9 is formed along the surface of the n + -type source region 7, the bottom, and the side walls of the trench 16. First, an oxide film is deposited in the trench by a chemical reaction (chemical vapor deposition method) such as thermal oxidation or high-temperature oxidation (High Temperature Oxide: HTO) at a temperature of about 1000 °C in an oxygen atmosphere.

[0046] Next, sacrificial oxidation may be performed to round the bottom of the trench and the corners of the trench opening. However, in order not to reduce the channel mobility, it is preferable not to perform sacrificial oxidation. Next, an annealing process is performed on the gate insulating film 9. When the gate insulating film 9 is formed by a deposition method such as HTO, post-annealing (NO (nitric oxide)-PDA: Post-Deposition Annealing) is generally performed with a gas containing nitrogen (N2) or the like after HTO film formation in order to improve electrical characteristics (mobility, etc.). The state up to this point is described in FIG. 6.

[0047] In the manufacturing method of a conventional silicon carbide semiconductor device, in consideration of process stability and for the purpose of making the characteristics uniform, nitridation was sufficiently advanced and the S value was saturated under conditions such as NO-PDA at a temperature of 1300 °C and NO annealing with NO 10% / N2 gas for about 30 minutes.

[0048] On the other hand, in the manufacturing method of the silicon carbide semiconductor device according to the embodiment, NO-PDA is performed under conditions where nitridation is sufficiently advanced and the S value is stable, that is, under conditions where nitridation is weaker than the conditions where the S value is saturated. By weakening the nitridation, the defect density at the interface gradually increases, the subthreshold characteristics slope, and the S value increases. As a result, the voltage at the current value that determines Vth increases, and Vth increases. At this time, by controlling the S value to be 1.1 times or more and 1.4 times or less the value at which the S value saturates with nitridation, the generation of residual carbon during the NO-PDA process is suppressed, and the mobility is also improved. If the S value is made even larger, the increase in defect density becomes remarkable and the mobility decreases.

[0049] FIG. 7 is a graph showing the IdVg characteristics with the annealing time of NO-PDA as a parameter in the silicon carbide semiconductor device according to the embodiment. In FIG. 7, the vertical axis represents the source-drain current Id, and the unit is A. The horizontal axis represents the gate voltage Vg, and the unit is V. FIG. 7 shows the IdVg characteristics when the annealing time of NO-PDA is 5 minutes, 10 minutes, 15 minutes, and 30 minutes. Here, FIG. 7 and FIGS. 8 and 9 below are examples in the case where sacrificial oxidation is not performed before forming the gate insulating film 9.

[0050] As shown in FIG. 7, as the annealing time becomes longer, the slope of the graph of the Id-Vg characteristics becomes steeper, the S value decreases, and as the annealing time becomes shorter, the voltage of the current value (the current value of the Vth determination line in FIG. 7) for determining Vth becomes higher and Vth becomes higher. This is because the nitrogen termination becomes insufficient due to the shortening of the nitridation time, resulting in an increase in the interface trap density (Dit) and the S value. Thus, it can be seen that Vth simply increases as the S value increases.

[0051] FIG. 8 is a graph showing the relationship between the annealing time of NO-PDA and the maximum mobility in the silicon carbide semiconductor device according to the embodiment. In FIG. 8, the vertical axis represents the maximum mobility μFEmax, and the unit is cm 2 / Vs. The horizontal axis represents the ratio to the reference of the annealing time of NO-PDA. The annealing time of the reference NO-PDA is 30 minutes.

[0052] As shown in FIG. 8, it can be seen that when the annealing time is lengthened, the channel mobility increases, but peaks at about 10 minutes, and then decreases as it becomes even longer. This is because both the increase in channel mobility due to the decrease in residual carbon due to the shortening of the nitridation time and the decrease in channel mobility due to the increase in Dit occur simultaneously.

[0053] As described above, from the results of FIGS. 7 and 8, by setting the annealing time of NO-PDA to be 8 minutes or more and 12 minutes or less, it is possible to achieve a higher Vth and a higher channel mobility than in the reference case.

[0054] FIG. 9 is a graph showing the annealing time dependence of the S value of NO-PDA in the silicon carbide semiconductor device according to the embodiment. In FIG. 9, the vertical axis represents the ratio of the S value to the reference, and the horizontal axis represents the ratio of the annealing time of NO-PDA to the reference. The value of the reference of the S value is the value at which the S value saturates with nitridation when forming the gate insulating film 9, which is about 0.21 V / dec., and the reference of the annealing time of NO-PDA is 30 minutes. In FIG. 9, the measurement results of the S value in the regions S1, S2, S3, and S4 shown in FIG. 7 are shown. In FIG. 9, in the region where Id is lower than S4, the influence of the leakage current is large, so the measurement of the S value is performed in the region of Id of S4 or more.

[0055] As shown in FIG. 9, in S1, S2, S3, and S4 in the subthreshold region, the lower the region is from the Vth determination line, the smaller the S value becomes. In the region S4 where the S value is the smallest, the annealing time of NO-PDA that can realize a higher Vth and a higher channel mobility than in the case of the reference is 1.1 times or more and 1.4 times or less the value at which the S value saturates with nitridation when forming the gate insulating film 9 (S value allowable range in FIG. 9).

[0056] FIG. 10 is a graph showing the Id-Vg characteristics with the NO concentration of NO-PDA as a parameter in the silicon carbide semiconductor device according to the embodiment. In FIG. 10, the vertical axis represents the current Id between the source and the drain, and the unit is A. The horizontal axis represents the gate voltage Vg, and the unit is V. FIG. 10 shows the Id-Vg characteristics when the NO concentration of NO-PDA is 3%, 5%, 10%, and 50%. The NO concentration is the ratio of NO in the N2 gas. Here, FIGS. 10 and FIGS. 11 and 12 below are examples in the case where sacrificial oxidation is performed before forming the gate insulating film 9.

[0057] As shown in FIG. 10, as the NO concentration of the NO-PDA increases, the slope of the graph of the IdVg characteristics becomes steeper, the S value decreases, and as the NO concentration of the NO-PDA decreases, the voltage of the current value that determines Vth increases, and Vth increases. This is for the same reason as in the case of shortening the nitridation time, and it can be seen that Vth simply increases as the S value increases.

[0058] FIG. 11 is a graph showing the relationship between the NO concentration of the NO-PDA and the maximum mobility in the silicon carbide semiconductor device according to the embodiment. In FIG. 11, the vertical axis represents the maximum mobility μFEmax, and the unit is cm 2 / Vs. The horizontal axis represents the NO concentration of the NO-PDA, and the unit is %.

[0059] As shown in FIG. 11, it can be seen that when the NO concentration of the NO-PDA is increased, the channel mobility increases, but peaks at about 5%, and when it is further increased, the channel mobility decreases. This is for the same reason as in the case of shortening the nitridation time. Here, when comparing FIG. 8 and FIG. 11, the peak channel mobility in FIG. 8 is higher. This is because sacrificial oxidation was performed in FIG. 11. Therefore, in order not to reduce the channel mobility, it is preferable not to perform sacrificial oxidation.

[0060] As described above, from the results of FIGS. 10 and 11, by setting the NO concentration of the NO-PDA to 3% or more and 7% or less, it is possible to achieve a higher Vth and a higher channel mobility than in the case of the reference.

[0061] FIG. 12 is a graph showing the NO concentration dependence of the S value of NO-PDA in the silicon carbide semiconductor device according to the embodiment. In FIG. 12, the vertical axis represents the ratio of the S value to the reference, and the horizontal axis represents the ratio of the NO concentration of NO-PDA to the reference. The reference value of the S value is the value at which the S value saturates with nitridation when forming the gate insulating film 9, which is about 0.21 V / dec., and the reference of the NO concentration of NO-PDA is 10%. FIG. 12 shows the measurement results of the S value in the regions S1, S2, and S3 shown in FIG. 10. In FIG. 12, in the region where Id is lower than S3, the influence of the leakage current is large, so the S value is measured in the region of Id of S3 or more.

[0062] As shown in FIG. 12, in S1, S2, and S3 in the subthreshold region, the lower the region is from the Vth determination line, the smaller the S value is. In the region S3 where the S value is the smallest, at the NO concentration of NO-PDA that can achieve a higher Vth and a higher channel mobility than in the case of the reference, it is 1.1 times or more and 1.4 times or less the value at which the S value saturates with nitridation when forming the gate insulating film 9 (the S value allowable range in FIG. 12).

[0063] Summarizing the results of FIGS. 7 to 12 above, by setting the annealing time of NO-PDA to 8 minutes or more and 12 minutes or less, or setting the NO concentration of NO-PDA to 3% or more and 7% or less, it is possible to achieve a higher Vth and a higher channel mobility than in the case of the reference. The S value in this case is 1.1 times or more and 1.4 times or less the value at which the S value saturates with nitridation when forming the gate insulating film 9.

[0064] FIG. 13 is a table showing the S value, threshold voltage, and on-resistance of the silicon carbide semiconductor device according to the embodiment and the conventional silicon carbide semiconductor device. The example in FIG. 13 is an example of an embodiment in which a silicon carbide semiconductor device is formed with the annealing time of NO-PDA being 10 minutes and the NO concentration being 10%, and the conventional example in FIG. 13 is an example in which a silicon carbide semiconductor device is formed with the annealing time of NO-PDA being 30 minutes and the NO concentration being 10%.

[0065] As shown in FIG. 13, in the embodiment, it can be confirmed that the S value has increased compared to the conventional example, and as an effect accompanying the increase in the S value, the threshold voltage Vth has increased. On the other hand, in the embodiment, the on-resistance (RonA) is at the same level as the conventional example. This is because the channel mobility is at the same level in the embodiment and the conventional example. Thus, in the embodiment, the trade-off between Vth and carrier mobility can be improved.

[0066] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 16. The polycrystalline silicon layer is patterned by photolithography and left inside the trench 16 to form the gate electrode 10.

[0067] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10 to form the interlayer insulating film 11. Next, a barrier metal 14 made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography to expose the n + -type source region 7 and the p + -type contact region 8 to form contact holes. Thereafter, heat treatment (reflow) is performed to planarize the interlayer insulating film 11.

[0068] Next, the interlayer insulating film 11 is selectively removed, and a film of nickel (Ni) or Ti is deposited on the surface of the silicon carbide semiconductor substrate 18. Next, the surface is protected and a film of Ni or Ti is deposited on the back surface side of the n + -type silicon carbide substrate 1. Next, heat treatment at about 1000 ° C. is performed to form ohmic electrodes on the surface side of the silicon carbide semiconductor substrate 18 and on the surface side of the back surface of the n + -type silicon carbide substrate 1.

[0069] Next, a conductive film serving as the source electrode 12 is provided so as to contact the ohmic electrode portion formed in the contact hole and on the interlayer insulating film 11, and the n + -type source region 7 and the p+ Bring the type - contact region 8 into contact with the source electrode 12.

[0070] Next, an + On the second main surface of the n - type silicon carbide substrate 1, form a back - surface electrode 13 made of, for example, a nickel (Ni) film. Then, perform heat treatment at a temperature of about 970 °C to + make an ohmic junction between the n - type silicon carbide substrate 1 and the back - surface electrode 13.

[0071] Next, by, for example, sputtering, deposit an electrode pad that will serve as a source - electrode pad (not shown) on the source electrode 12 on the front surface of the silicon carbide semiconductor substrate 18 and in the opening of the interlayer insulating film 11. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5 μm. The electrode pad may be formed of, for example, aluminum (Al - Si) containing silicon at a ratio of 1%. Next, selectively remove the source - electrode pad.

[0072] Next, on the surface of the back - surface electrode 13, form films of, for example, titanium (Ti), nickel (Ni), and gold (Au) in this order as a drain - electrode pad (not shown). In this way, the semiconductor device shown in FIG. 1 is completed.

[0073] As described above, according to the embodiment, the minimum value of the S value in the sub - threshold region is 0.24 V / dec. or more and 0.3 V / dec. or less. This can be achieved by setting the annealing time of NO - PDA to 8 minutes or more and 12 minutes or less, or by setting the NO concentration of NO - PDA to 3% or more and 7% or less. As a result, the carrier mobility can be made comparable to that of a conventional trench - type MOSFET, the Vth can be increased, and the trade - off between Vth and carrier mobility can be improved.

[0074] As described above, the present invention can be variously modified without departing from the spirit of the present invention. In each of the above-described embodiments, for example, the dimensions and impurity concentrations of each part are variously set according to required specifications and the like. Also, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention also holds true when the first conductivity type is p-type and the second conductivity type is n-type.

Industrial Applicability

[0075] As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices such as various industrial machines, and igniters for automobiles.

Explanation of Reference Numerals

[0076] 1 n + -type silicon carbide substrate 2 n - -type silicon carbide epitaxial layer 2a Lower n - -type silicon carbide epitaxial layer 2b Upper n - -type silicon carbide epitaxial layer 3 First p + -type base region 3a Lower first p + -type base region 3b Upper first p + -type base region 4 Second p + -type base region 5 n-type high concentration region 5a Lower n-type high concentration region 5b Upper n-type high concentration region 6 p-type base layer 7 n + -type source region 8 p + -type contact region 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Source electrode 13 Back surface electrode 14 Barrier Metal 16 Trench 17 n + -type Region 18 Silicon Carbide Semiconductor Substrate 70 Trench-Type MOSFET

Claims

1. A silicon carbide semiconductor substrate of a first conductivity type, A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate, provided on the front surface of the silicon carbide semiconductor substrate, A second semiconductor layer of a second conductivity type provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A first semiconductor region of a first conductivity type selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, A gate electrode provided inside the trench via a gate insulating film, A first electrode provided on the surfaces of the second semiconductor layer and the first semiconductor region, A second electrode provided on the back surface of the silicon carbide semiconductor substrate, Comprising, The minimum value of the S value in the subthreshold region is 0.24 V / dec. or more and 0.3 V / dec. or less, The threshold voltage is 5.9 V or more, The silicon carbide semiconductor device, wherein the second semiconductor layer has a uniform impurity concentration in a region facing the first semiconductor region in the depth direction.

2. The silicon carbide semiconductor device according to claim 1, wherein the minimum value of the S value in the subthreshold region is 1.1 times or more and 1.4 times or less of a value at which the S value saturates with nitridation when forming the gate insulating film.

3. A first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate on the front surface of the silicon carbide semiconductor substrate of the first conductivity type, A second step of forming a second semiconductor layer of a second conductivity type on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A third step of selectively forming a first semiconductor region of a first conductivity type on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A fourth step of forming a gate insulating film in contact with the second semiconductor layer, A fifth step of performing post-annealing on the gate insulating film with a gas containing nitrogen, A sixth step of forming a gate electrode on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer, A seventh step of forming a first electrode on the surfaces of the second semiconductor layer and the first semiconductor region, An eighth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate, Including, In the fifth step, the annealing time of the post-annealing is 8 minutes or more and 12 minutes or less, or the concentration of nitrogen monoxide in the post-annealing is 3% or more and 7% or less. Before the fourth step, the method includes a step of forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. In the fourth step, a gate insulating film is formed inside the trench. In the sixth step, a gate electrode is formed inside the trench via the gate insulating film. A method for manufacturing a silicon carbide semiconductor device, characterized in that no sacrificial oxidation is performed on the trench.

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