Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide an inexpensive silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device having a withstand voltage structure which is formed in a small number of processes and which can stably secure a predetermined withstand voltage.SOLUTION: An edge termination region 2 is provided with an FLR structure 30 consisting of a plurality of FLRs 31 at a floating potential concentrically surrounding an active region 1. The FLR structure 30 is divided into two or more FLR sections 30a to 30c with a predetermined FLR 31 as a boundary (change points b1, b2). The nth distance xn between the FLRs 31 adjacent to each other is wider than a first distance x1 between a p+ type extension 22a and the innermost FLR 31 (n is the total number of FLRs 31 from 2). The n-th distance xn between the FLRs 31 adjacent to each other increases in an arithmetic progression with a constant increase width for each of the FLR sections 30a to 30c as it is arranged on the outside, and the increase width increases with the outer FLR sections 30b and 30c wide.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Background Art

[0002] The breakdown voltage structure of a power semiconductor device is composed of a plurality of p-type regions selectively provided in the surface region of an n-type drift region exposed on the front surface of a semiconductor substrate in an edge termination region between an active region and an end portion of the semiconductor substrate (semiconductor chip). When the semiconductor material of the power semiconductor device is silicon carbide (SiC) whose maximum electric field strength is more than one digit larger than that of silicon (Si), as a breakdown voltage structure, a multi-zone junction termination extension (JTE) structure, a spatially modulated JTE structure, or a field limiting ring (FLR) structure is mainly arranged.

[0003] The multi-zone JTE structure is a structure in which three or more p-type regions (hereinafter referred to as JTE regions) are arranged concentrically adjacent to surround the active region so that the JTE region with a lower impurity concentration is arranged at a position farther from the inner side (the active region (the central portion of the semiconductor chip: the center of the chip) side) to the outer side (the end portion of the semiconductor substrate (the chip end) side). The electric field strength tends to decrease as it moves away from the active region to the outside. Therefore, in the multi-zone JTE structure, in accordance with the tendency of the electric field strength distribution, by lowering the impurity concentration of the JTE region as the position is farther from the active region to the outside, a predetermined breakdown voltage is stably ensured.

[0004] The spatially modulated JTE structure is an improved structure of the JTE structure, and adjacent JTE regions (when composed of only one JTE region, one JTE region and the n outside it -A space-modulated region having an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between these two regions is arranged between the (type drift region), and the impurity concentration distribution of the entire JTE structure is gently decreased toward the outside. The space-modulated region is formed by alternately arranging in a predetermined pattern two small regions having substantially the same impurity concentration as the regions adjacent to each side of the space-modulated region itself. The spatial impurity concentration distribution of the entire space-modulated region is determined by the widths and impurity concentration ratios of the two small regions.

[0005] The space-modulated JTE structure can more stably secure a predetermined breakdown voltage compared to a general JTE structure without a space-modulated region. The FLR structure is a structure in which a plurality of p-type regions (FLRs) having the same impurity concentration are arranged concentrically around the active region and separated from each other. In the FLR structure, a plurality of FLRs arranged separately from each other disperse the electric field to secure a predetermined breakdown voltage. In this way, by arranging a predetermined breakdown voltage structure in the edge termination region to relax or disperse the electric field in the edge termination region, the breakdown voltage of the edge termination region is improved, and the breakdown voltage of the entire semiconductor device is improved. The structure of a conventional silicon carbide semiconductor device will be described.

[0006] FIG. 13 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in FIG. 13 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor having an insulated gate (MOS gate) composed of a three-layer structure of metal - oxide film - semiconductor) with a trench gate structure including an FLR structure 130 in the edge termination region 102 of a semiconductor substrate (semiconductor chip) 140 made of silicon carbide. The edge termination region 102 surrounds the active region 101 through which the main current of the MOSFET flows.

[0007] The semiconductor substrate 140 is an n + -type starting substrate 111 with an n -Each silicon carbide layer 142, 143 to be an n-type drift region 112 and a p-type base region 113 is epitaxially grown in order. The portion of the p-type silicon carbide layer 143 in the edge termination region 102 is removed by etching, and a step 124 is formed on the front surface of the semiconductor substrate 140. The front surface of the semiconductor substrate 140 is recessed toward the drain electrode 125 at a second surface 140b on the outer side (the end side of the semiconductor substrate 140) rather than a first surface 140a on the chip center (center of the semiconductor substrate 140) side with the step 124 as a boundary.

[0008] Due to this step 124, a p-type silicon carbide layer 143 remains in a mesa shape at the center of the front surface (main surface on the p-type silicon carbide layer 143 side) of the semiconductor substrate 140. The first and second surfaces 140a, 140b of the front surface of the semiconductor substrate 140 are formed of the p-type silicon carbide layer 143 and an n - -type silicon carbide layer 142, respectively. On the front surface side of the semiconductor substrate 140 at the central portion 101a of the active region 101, a p-type base region 113, an n + -type source region 114, and a p ++ -type contact region 115, a trench 116, a gate insulating film 117, and a gate electrode 118 of an MOS gate are provided for each unit cell of the MOSFET.

[0009] On the surface region of the first surface 140a of the front surface of the semiconductor substrate 140 at the outer peripheral portion 101b of the active region 101, a p + -type extension portion 122a, a p-type base extension portion 113a, and a p ++ -type contact extension portion 115a are selectively provided. The p + -type extension portion 122a, the p-type base extension portion 113a, and the p ++ -type contact extension portion 115a are extensions of the outermost p + -type region 122, the p-type base region 113, and the outermost p ++ -type contact region 115 that constitute the unit cell of the central portion 101a of the active region 101, and surround the periphery of the central portion 101a of the active region 101.

[0010] p + -type extension portion 122a, the p-type base extension portion 113a, and the p++ The p-type contact extension 115a extends outward to reach the third surface (step mesa edge) 140c that connects the first surface 140a and the second surface 140b of the front surface of the semiconductor substrate 140. + The p-type extension 122a extends outward from the step 124 and is exposed on the second surface 140b of the front surface of the semiconductor substrate 140. The reference numerals 121 and 122 are p-type regions that relax the electric field applied to the gate insulating film 117 on the bottom surface of the trench 116. + The reference numerals 119, 120, 125, and 132 are an interlayer insulating film, a source electrode, a drain electrode, and an n-type channel stopper region, respectively. + respectively.

[0011] In the edge termination region 102, a plurality of p-type regions (FLR: hatched portions) 131 of the floating potential that constitute the FLR structure 130 are selectively provided inside the n-type silicon carbide layer 142 on the surface region of the second surface 140b of the front surface of the semiconductor substrate 140. The plurality of FLRs 131 are provided concentrically and spaced apart from each other around the active region 101 at a position outside the p-type extension 122a and away from the p-type extension 122a. All the FLRs 131 face the p-type extension 122a in the normal direction (the direction from the inside to the outside). All the FLRs 131 are surrounded by the n-type drift region 112. - Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. + Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. + Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. + Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. - Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131.

[0012] p + Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. 101 Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. j ,x j+1 Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. j Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. + Let the first interval between the p-type extension 122a and the innermost FLR 131 be x, and the i-th interval between the i-th FLR 131 and the (i - 1)-th FLR 131 adjacent to it on the inside be x, x,... in order from the inside to the outside (where i is from 2 to the total number of FLRs 131, and j = i + 100). The i-th interval x between adjacent FLRs 131 is the same as the first interval x between the p-type extension 122a and the innermost FLR 131. 101wider and wider in an arithmetic progression with a constant increase width (width in the normal direction) so that it is arranged more widely and on the outside (x j+1 -x j = constant). All FLR131s have the same impurity concentration and the same width w101.

[0013] As a conventional silicon carbide semiconductor device, a device having an FLR structure in which the interval between adjacent FLRs is widened in an arithmetic progression with a constant increase width so that it is arranged more widely and on the outside has been proposed (see, for example, Patent Documents 1 and 2 below). In Patent Document 1 below, when the drain-source voltage becomes a high voltage due to the p-type resurf region between the active region and the FLR structure, the electric field is concentrated not directly below the p-type resurf region but near the FLR structure. In Patent Document 2 below, the blocking voltage is stabilized by a field plate (FP: Field Plate) provided via an insulating layer on an n - type drift region between adjacent FLRs.

[0014] Also, as a conventional silicon carbide semiconductor device, an edge termination region includes an FLR structure composed of a plurality of FLRs arranged concentrically and at equal intervals surrounding the periphery of the active region, and an n-type region provided between the second surface of the front surface of the semiconductor substrate and each of the plurality of FLRs. A device has been proposed (see, for example, Patent Document 3 below). In Patent Document 3 below, by arranging the FLR at a position away from the second surface of the front surface of the semiconductor substrate due to the n-type region between the second surface of the front surface of the semiconductor substrate and each of the plurality of FLRs, the variation in the dose amount of the FLR is reduced, and the variation in the breakdown voltage of the silicon carbide semiconductor device is reduced.

Prior Art Documents

Patent Documents

[0015]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0016] However, in a general JTE structure, in order to adjust the impurity concentration distribution according to the tendency of the electric field strength distribution, it is necessary to perform ion implantation the same number of times as the number of a plurality of JTE regions (p-type regions) with different impurity concentrations arranged. This increases the number of processes and leads to an increase in cost. In a spatially modulated JTE structure, although the number of ion implantation times decreases, it is still necessary to adjust the impurity concentration distribution according to the tendency of the electric field strength distribution, which increases the number of processes and leads to an increase in cost.

[0017] In the conventional FLR structure 130 (see FIG. 13), since all the FLRs 131 have the same impurity concentration, ion implantation only needs to be performed once, and the manufacturing cost can be suppressed by reducing the number of processes. However, a large area (the length of the edge termination region 102) is required to stably ensure a predetermined breakdown voltage. Therefore, when using expensive silicon carbide as a semiconductor material, the increase in material cost becomes a major factor contributing to the cost increase.

[0018] An object of the present invention is to provide an inexpensive silicon carbide semiconductor device having a breakdown voltage structure formed with a small number of processes and capable of stably ensuring a predetermined breakdown voltage, and a method for manufacturing the silicon carbide semiconductor device, in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0019] In order to solve the above problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A semiconductor substrate made of silicon carbide is provided with an active region and a termination region surrounding the periphery of the active region. A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate from the active region to the termination region. A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region in the active region. An element structure including a pn junction between the first semiconductor region and the second semiconductor region and through which a current flows through the pn junction is provided.

[0020] A second conductivity type outer peripheral region is provided between the first main surface of the semiconductor substrate and the first semiconductor region between the element structure and the termination region. The second conductivity type outer peripheral region surrounds the periphery of the element structure. A first electrode is provided on the first main surface of the semiconductor substrate and is electrically connected to the second semiconductor region and the second conductivity type outer peripheral region. A second electrode is provided on the second main surface of the semiconductor substrate and is electrically connected to the first semiconductor region. A plurality of floating potential second conductivity type FLRs are provided between the first main surface of the semiconductor substrate and the first semiconductor region in the termination region.

[0021] The plurality of FLRs are provided at intervals from each other in a concentric shape surrounding the periphery of the active region to form an FLR structure. The FLR faces the outside of the second conductivity type outer peripheral region in a direction parallel to the first main surface of the semiconductor substrate. The FLR structure is divided into the following FLR sections with a predetermined FLR as a boundary. Three The interval between adjacent FLRs is wider than the interval between the second conductivity type outer peripheral region and the innermost FLR, and becomes wider in an arithmetic progression with a constant increase width for each FLR section as it is arranged more outward. The increase width is wider inside the FLR section arranged more outward than inside the FLR section adjacent thereto more inward. The entire first main surface of the semiconductor substrate in the terminal region is covered with an interlayer insulating film. A conductive film is not provided on the first main surface of the semiconductor substrate in the terminal region.

[0022] Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, it further includes a third semiconductor region of a first conductivity type provided between the first main surface of the semiconductor substrate and the FLR.

[0023] Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the number of the FLRs is 30 or more.

[0024] Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the impurity concentration of the FLR is 1×10 18 / cm 3 or more and 1×10 21 / cm 3 or less.

[0025] Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the width of the FLR is 2 μm or more and 5 μm or less.

[0026] Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the distance between the second conductivity type outer peripheral region and the innermost FLR is 0.1 μm or more and 1.0 μm or less.

[0027] Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the third semiconductor region is 0.4 μm or less.

[0028] Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the increased width is in the range of 0.05 μm or more and 0.12 μm or less.

[0029] Further, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, Three among the above FLR sections, the boundary between the innermost first FLR section and the second FLR section adjacent to the outside of the first FLR section is between the second and subsequent outer FLRs from the inside and the inner FLR of the FLR.

[0030] Also, in the silicon carbide semiconductor device according to this invention, in the above-described invention, Three Among the above FLR sections, the boundary between the outermost third FLR section and the second FLR section adjacent to the inside of the third FLR section is between the third and subsequent inner FLRs from the outside and the inner FLR of the FLR, and is characterized in that.

[0031] Also, in the silicon carbide semiconductor device according to this invention, in the above-described invention, the impurity concentration of the second conductivity type outer peripheral region is the same as the impurity concentration of the second semiconductor region on the first main surface side of the semiconductor substrate, and is the same as the impurity concentration of the FLR on the first semiconductor region side, and is characterized in that.

[0032] Also, in the silicon carbide semiconductor device according to this invention, in the above-described invention, the element structure includes a fourth semiconductor region of a first conductivity type, a trench, a gate electrode, a first high-concentration region of a second conductivity type, and a second high-concentration region of a second conductivity type. The fourth semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, and is electrically connected to the first electrode. The trench penetrates the fourth semiconductor region and the second semiconductor region and reaches the first semiconductor region. The gate electrode is provided inside the trench via a gate insulating film. The first high-concentration region is provided between the first semiconductor region and the second semiconductor region.

[0033] The first high-concentration region is provided selectively away from the second semiconductor region and on the second electrode side rather than the bottom surface of the trench, and faces the bottom surface of the trench in the depth direction. The first high-concentration region has a higher impurity concentration than the second semiconductor region. The second high-concentration region is provided selectively between the first semiconductor region and the second semiconductor region, away from the trench and the first high-concentration region, in contact with the second semiconductor region, and reaches the second electrode side rather than the bottom surface of the trench. The impurity concentration of the second high-concentration region is the same as the impurity concentration of the first high-concentration region. The impurity concentration of the FLR is the same as the impurity concentration of the first high-concentration region, and is characterized in that.

[0034] Also, in order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention is the method for manufacturing a silicon carbide semiconductor device described above, and has the following features. A first step of forming a first first-conductivity-type semiconductor layer that becomes the first semiconductor region is performed. A second step of selectively forming, in a surface region of the first first-conductivity-type semiconductor layer, a first portion of the second-conductivity-type outer peripheral region and the FLR is performed. A third step of forming a second first-conductivity-type semiconductor layer that becomes the first semiconductor region on the first first-conductivity-type semiconductor layer is performed. A fourth step of selectively forming a second portion of the second-conductivity-type outer peripheral region that reaches the first portion at a position in the depth direction of the second first-conductivity-type semiconductor layer that faces the first portion is performed. A fifth step of forming a second-conductivity-type semiconductor layer on the second first-conductivity-type semiconductor layer in the active region, and making a portion of the second-conductivity-type semiconductor layer that faces the second portion in the depth direction be a third portion of the second-conductivity-type outer peripheral region and the remaining portion be the second semiconductor region is performed. A sixth step of forming the first electrode electrically connected to the second semiconductor region and the second-conductivity-type outer peripheral region is performed. A seventh step of forming the second electrode electrically connected to the first semiconductor region is performed.

[0035] Also, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features in the above-described invention. The element structure includes a first-conductivity-type fourth semiconductor region, a trench, a gate electrode, a second-conductivity-type first high-concentration region, and a second-conductivity-type second high-concentration region. The fourth semiconductor region is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, and is electrically connected to the first electrode. The trench penetrates the fourth semiconductor region and the second semiconductor region and reaches the first semiconductor region. The gate electrode is provided inside the trench with a gate insulating film interposed therebetween. The first high-concentration region is provided between the first semiconductor region and the second semiconductor region. The first high-concentration region is selectively provided away from the second semiconductor region and on the second electrode side rather than the bottom surface of the trench, and faces the bottom surface of the trench in the depth direction.

[0036] The first high-concentration region has a higher impurity concentration than the second semiconductor region. The second high-concentration region is selectively provided between the first semiconductor region and the second semiconductor region, away from the trench and the first high-concentration region, in contact with the second semiconductor region, and reaching the second electrode side from the bottom surface of the trench. The impurity concentration of the second high-concentration region is the same as that of the first high-concentration region. In the second step, the first portion, the FLR, the first high-concentration region, and the fourth portion of the second high-concentration region are selectively formed on the surface region of the first first-conductivity-type semiconductor layer. In the fourth step, the second portion reaching the first portion and the fifth portion of the second high-concentration region reaching the fourth portion are selectively formed at positions in the depth direction of the second first-conductivity-type semiconductor layer facing the first portion and the fourth portion, respectively.

[0037] According to the above-described invention, by using the FLR structure for the breakdown voltage structure, the breakdown voltage structure can be formed by a single ion implantation. Therefore, the number of masks and the number of processes can be reduced compared to the case of using the JTE structure, and the manufacturing cost can be reduced. Further, according to the above-described invention, the length of the termination region can be shortened, a margin for dimensional variations of the ion implantation mask can be obtained, and breakdown voltage variations due to charges accumulated in the insulating layer on the front surface of the semiconductor substrate in the termination region during long-term operation can be suppressed.

Effect of the Invention

[0038] The present invention by has the effect of being able to provide an inexpensive silicon carbide semiconductor device having a breakdown voltage structure that can be formed with a small number of processes and can stably ensure a predetermined breakdown voltage, and a method for manufacturing a silicon carbide semiconductor device.

Brief Description of the Drawings

[0039]

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Embodiments for Carrying Out the Invention

[0040] With reference to the accompanying drawings, preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in the layers and regions preceded by n or p, it means that electrons or holes are the majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layers and regions to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0041] (Embodiment) The structure of the silicon carbide semiconductor device according to the embodiment will be described. FIG. 1 is a plan view showing the layout of the semiconductor device according to the embodiment as viewed from the front side of the semiconductor substrate. FIG. 2 is a cross-sectional view showing the cross-sectional structure taken along the cutting line A-A' in FIG. 1. FIG. 3 is a chart showing a dimensional example of the interval between adjacent FLRs in FIG. 2. The silicon carbide semiconductor device 10 according to the embodiment shown in FIGS. 1 and 2 is a vertical MOSFET having a trench gate structure (element structure) in the active region 1 of a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and an FLR structure 30 as a breakdown voltage structure in the edge termination region 2.

[0042] The active region 1 is a region where the main current (drift current) flows when the MOSFET is turned on, and a plurality of unit cells (functional units of the element) having the same structure are arranged adjacent to each other in parallel connection in the central portion 1a. The active region 1 has a substantially rectangular planar shape and is disposed substantially at the center of the semiconductor substrate 40. The active region 1 is a portion from the outer end (the end portion of the chip end of the semiconductor substrate 40) to the inner side (the central side of the chip of the semiconductor substrate 40) outside the p + type extension portion 22a. The edge termination region 2 is a region between the active region 1 and the chip end, and surrounds the active region 1 in a substantially rectangular shape. The FLR structure 30 in the edge termination region 2 will be described later.

[0043] The semiconductor substrate 40 is an n + type starting substrate 41 on the front surface, and an n -The silicon carbide layers 42 and 43 that will become the n-type drift region 12 and the p-type base region 13 are sequentially epitaxially grown. The main surface of the semiconductor substrate 40 on the p-type silicon carbide layer 43 side is defined as the front surface (the first main surface), and the main surface of the n + -type starting substrate 41 side is defined as the back surface (the second main surface). The portion of the p-type silicon carbide layer 43 in the edge termination region 2 is removed by etching, and a step 24 is formed on the front surface of the semiconductor substrate 40. Due to this step 24, the p-type silicon carbide layer 43 remains in a mesa shape in the active region 1. The front surface of the semiconductor substrate 40 is recessed on the n + -type drain region 11 side at the portion of the edge termination region 2 (the second surface) 40b compared to the portion of the active region 1 (the first surface) 40a with the step 24 as the boundary.

[0044] At the portion (below the mesa edge of the step 24, defined as the third surface) 40c that connects the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40, the active region 1 and the edge termination region 2 are element-separated. The second surface 40b of the front surface of the semiconductor substrate 40 is the exposed surface of the n - -type silicon carbide layer 42 exposed during the formation of the step 24. During the formation of the step 24, the n - -type silicon carbide layer 42 may be slightly removed together with the p-type silicon carbide layer 43. The third surface 40c of the front surface of the semiconductor substrate 40 is the side surface (exposed surface) of the p-type silicon carbide layer 43 exposed during the formation of the step 24. The exposure on the second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 means being in contact with the interlayer insulating film 19 on the second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40.

[0045] In the central portion 1a of the active region 1, on the first surface 40a side of the front surface of the semiconductor substrate 40, a trench gate structure including a p-type base region (the second semiconductor region) 13, an n + -type source region (the fourth semiconductor region) 14, a p ++ -type contact region 15, a trench 16, a gate insulating film 17, and a gate electrode 18 is provided. The n + -type starting substrate 41 is an n + -type drain region (the first semiconductor region) 11. The n - -type drift region (the first semiconductor region) 12 is an n -The portion of the p-type silicon carbide layer 42, which will be described later, of the first and second p + type regions 21, 22, n-type current diffusion regions (not shown), FLR31, and n + type channel stopper region 32, excluding these regions, is provided in contact with these regions between the n + type starting substrate 41, extending from the active region 1 to the edge termination region 2.

[0046] The p-type base region 13 is the portion of the p-type silicon carbide layer 43 excluding the n + type source region 14 and the p ++ type contact region 15. The p-type base region 13 is provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the n - type drift region 12. The n + type source region 14 and the p ++ type contact region 15 are selectively provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the p-type base region 13, respectively, in contact with the p-type base region 13 and exposed on the first surface 40a of the front surface of the semiconductor substrate 40. Being exposed on the first surface 40a of the front surface of the semiconductor substrate 40 means contacting the source electrode 20 described later through the contact hole of the interlayer insulating film 19 described later.

[0047] p ++ type contact region 15 may not be provided. In this case, instead of the p ++ type contact region 15, the p-type base region 13 is exposed on the first surface 40a of the front surface of the semiconductor substrate 40. Between the n - type drift region 12 and the p-type base region 13, at a position deeper than the bottom surface of the trench 16 on the n + type drain region 11 side, an n-type current diffusion region (not shown), which is a so-called current spreading layer (CSL: Current Spreading Layer) for reducing the spreading resistance of carriers, may be provided. Also, at a position deeper than the bottom surface of the trench 16 on the n + type drain region 11 side, the first and second p + type regions (first and second high-concentration regions) 21, 22 are provided.

[0048] 1st, 2nd p + The p-type regions 21 and 22 have a function of relaxing the electric field applied to the bottom surface of the trench 16. The 1st p + type region 21 is provided apart from the p-type base region 13 and faces the bottom surface of the trench 16 in the depth direction. The 1st p + type region 21 is electrically connected to the source electrode 20 at a portion not shown in the figure. The 2nd p + type region 22 is provided between adjacent trenches 16, the 1st p + type region 21 and the trench 16, is provided apart therefrom, and contacts the p-type base region 13. The trench 16 penetrates the n + type source region 14 and the p-type base region 13 and reaches the n - type drift region 12 (when an n-type current diffusion region is provided, the n-type current diffusion region).

[0049] The trench 16 extends in a stripe shape, for example, in a direction parallel to the front surface of the semiconductor substrate 40 and reaches the outer peripheral portion 1b of the active region 1 described later. Between adjacent trenches 16, the p-type base region 13, n + type source region 14, p ++ type contact region 15 and the 2nd p + type region 22 extend linearly in parallel with the trench 16. The p ++ type contact region 15 may be dotted in parallel with the trench 16. Inside the trench 16, a gate electrode 18 is provided via a gate insulating film 17. All the gate electrodes 18 are electrically connected via a gate runner (gate wiring layer: not shown) of the outer peripheral portion 1b of the active region 1.

[0050] The interlayer insulating film 19 is provided on the entire front surface of the semiconductor substrate 40, covers the gate electrode 18 in the active region 1, and covers the front surface of the semiconductor substrate 40 in the outer peripheral portion 1b of the active region 1 and the edge termination region 2. In the outer peripheral portion 1b of the active region 1 and the edge termination region 2, a field oxide film may be provided between the front surface of the semiconductor substrate 40 and the interlayer insulating film 19. The source electrode (first electrode) 20 is connected to the n+ type source region 14 and p ++ type contact region 15 in ohmic contact with, and electrically connected to, the p-type base region 13. The drain electrode (second electrode) 25 is provided over the entire back surface (n + type starting substrate 41) of the semiconductor substrate 40 and is electrically connected to the n + type drain region 11.

[0051] The outer peripheral portion 1b of the active region 1 surrounds the central portion 1a of the active region 1 in a substantially rectangular shape. In the outer peripheral portion 1b of the active region 1, over the entire area between the front surface first surface 40a of the semiconductor substrate 40 and the n - type drift region 12, there is provided a p-type region (second conductivity type outer peripheral region) formed by sequentially laminating an n - type drift region 12 side p + type extending portion 22a, a p-type base extending portion 13a, and a p ++ type contact extending portion 15a. The outer ends of the p + type extending portion 22a, the p-type base extending portion 13a, and the p ++ type contact extending portion 15a surround the central portion 1a of the active region 1 in a substantially rectangular shape. + type extending portion 22a, the p-type base extending portion 13a, and the p ++ type contact extending portion 15a are exposed on the third surface 40c of the front surface of the semiconductor substrate 40.

[0052] p + type extending portion 22a, the p-type base extending portion 13a, and the p ++ type contact extending portion 15a has a function of making uniform the in-plane electric field of the front surface first surface 40a of the semiconductor substrate 40 in the outer peripheral portion 1b of the active region 1. The p + type extending portion 22a, the p-type base extending portion 13a, and the p ++ type contact extending portion 15a is a region for extracting hole (positive hole) current generated in the n - type drift region 12 of the edge termination region 2 and flowing toward the active region 1 from the p ++ type contact extending portion 15a to the source electrode 20, and has a function of suppressing hole current concentration during avalanche breakdown in the edge termination region 2.

[0053] p + The p-type extension portion 22a is the extension of the second p-type region 22 of the outermost unit cell of the central portion 1a of the active region 1. + The p-type extension portion 22a is the extension of the second p-type region 22 of the outermost unit cell of the central portion 1a of the active region 1. + The p-type extension portion 22a reaches a position deeper than the second surface 40b of the front surface of the semiconductor substrate 40 on the n-type drain region 11 side. + The p-type extension portion 22a reaches a position deeper than the second surface 40b of the front surface of the semiconductor substrate 40 on the n-type drain region 11 side. + The p-type extension portion 22a extends outward from the step 24 and surrounds the boundary between the second surface 40b and the third surface 40c of the front surface of the semiconductor substrate 40 over the entire circumference. The p-type base extension portion 13a is the extension of the p-type base region 13. The p-type base extension portion 13a is provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the + p-type extension portion 22a.

[0054] p ++ The p-type contact extension portion 15a is the extension of the p-type contact region 15 of the outermost unit cell of the central portion 1a of the active region 1. ++ The p-type contact extension portion 15a is the extension of the p-type contact region 15 of the outermost unit cell of the central portion 1a of the active region 1. ++ The p-type contact extension portion 15a is provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the p-type base extension portion 13a. ++ The p-type contact extension portion 15a ( ++ when the p-type contact extension portion 15a is not provided, the p-type base extension portion 13a) makes an ohmic contact with the source electrode 20 through the contact hole of the interlayer insulating film 19. + The p-type extension portion 22a and the p-type base extension portion 13a are electrically connected to the source electrode 20 through the ++ p-type contact extension portion 15a.

[0055] In the edge termination region 2, between the second surface 40b of the front surface of the semiconductor substrate 40 and the n - type drift region 12, a plurality of p-type regions (FLR: hatched portion) 31 having a floating potential that constitutes the FLR structure 30, and n + type regions (FLR: hatched portion) 31 having a floating potential that constitutes the FLR structure 30, and n +The trench stopper regions 32 are selectively provided respectively. The FLR structure 30 has a function of relaxing the electric field on the front surface side of the semiconductor substrate 40 and maintaining the breakdown voltage. The breakdown voltage is the upper limit voltage at which the silicon carbide semiconductor device 10 does not malfunction or break down at the operating voltage. The FLR structure 30 is divided into two or more FLR sections (FLR sections 30a to 30c described later) with a predetermined FLR 31 as a boundary (the first and second change points b1 and b2 described later) as will be described later.

[0056] A plurality of FLRs 31 are + outside the p-type extension 22a and are provided concentrically and spaced apart from each other around the active region 1 at a position away from the p-type extension 22a. The innermost (the first one from the inside) FLR 31 is adjacent to the outside of the p-type extension 22a in the normal direction (the direction from the inside to the outside). + All the FLRs 31 are + formed by ion implantation in the n-type silicon carbide layer 42 and are surrounded by the n-type drift region 12 respectively. - The n-type drift region 12 is located between the p-type extension 22a and the innermost FLR 31 and between all adjacent FLRs 31. The total number of FLRs 31 is preferably about 30 or more, for example. All the FLRs 31 have the same impurity concentration and the same width (width in the normal direction) w1. - The impurity concentration of the FLR 31 is, for example, 1×10 + or more such that it does not completely deplete even when a high voltage close to the breakdown voltage of the silicon carbide semiconductor device 10 is applied to the pn junction between the FLR 31 and the n-type drift region 12, and - 1×10 or less, for example. If the impurity concentration of the FLR 31 exceeds the above upper limit value, the width w1 of the FLR 31 becomes too wide or the FLRs 31 are connected to each other due to impurity diffusion, which is not preferable. The width w1 of the FLR 31 is, for example, about 2 μm or more and 5 μm or less. In FIG. 2, the p

[0057] The impurity concentration of the FLR 31 is such that when a high voltage close to the breakdown voltage of the silicon carbide semiconductor device 10 is applied to the pn junction between the FLR 31 and the n-type drift region 12, it does not completely deplete, for example, 1×10 - / cm 18 or more, and 3 1×10 21 / cm 3 or less, for example. If the impurity concentration of the FLR 31 exceeds the above upper limit value, the width w1 of the FLR 31 becomes too wide or the FLRs 31 are connected to each other due to impurity diffusion, which is not preferable. The width w1 of the FLR 31 is, for example, about 2 μm or more and 5 μm or less. In FIG. 2, the p +Let the first interval between the type extension part 22a and the innermost (the first one from the inside) FLR31 be x1, and let the nth interval between the nth FLR31 and the (n - 1)th FLR31 adjacent to its inside be x n , x n+1 , … (where n is from 2 to the total number of FLRs 31).

[0058] p + The first interval x1 between the type extension part 22a and the innermost FLR31 may be, for example, about 0.1 μm or more and 1.0 μm or less in consideration of impurity diffusion, and preferably about 0.6 μm or more (see FIGS. 11 and 12). The nth interval x n between adjacent FLRs 31 + is wider than the first interval x1 between the type extension part 22a and the innermost FLR31, and becomes wider in an arithmetic progression with a certain increase width (width in the normal direction) for each of the FLR sections 30a to 30c as it is arranged more outward. p + Since the width of the type extension part 22a and the width w1 of the FLR31 are each widened by about 0.2 μm to 0.3 μm inward and outward from the opening width of the mask for ion implantation due to impurity diffusion, the mth interval x m (where m is from 1 to the total number of FLRs 31) is narrower than the remaining width of the mask for ion implantation (width between openings).

[0059] The increase width of the nth interval x n between adjacent FLRs 31 is constant within each FLR section divided by a predetermined FLR31 at one or more locations, and becomes wider in the FLR section arranged more outward than in the FLR section adjacent to its inside. Specifically, for example, when changing the increase width of the nth interval x n between adjacent FLRs 31 at two locations of FLR31 as boundaries (the first and second change points b1 and b2 in order from the inside to the outside), the FLR structure 30 is divided into three FLR sections (assigned symbols 30a to 30c in order from the inside to the outside). The nth interval x nThe increase width is wider within the FLR section 30b between the first and second change points b1 and b2 adjacent to the outside of the FLR section 30a than within the FLR section 30a which is inside (the innermost) of the first change point b1.

[0060] The nth interval x between adjacent FLRs 31 n The increase width is wider within the FLR section 30c outside the second change point b2 adjacent to the outside of the FLR section 30b than within the FLR section 30b between the first and second change points b1 and b2. Within the same FLR sections 30a to 30c, the nth interval x between adjacent FLRs 31 n The increase width is constant (x n+1 -x n = constant). The further outside within the same FLR sections 30a to 30c, the nth interval x between adjacent FLRs 31 n widens arithmetically with a constant increase width. The nth interval x between adjacent FLRs 31 n The increase width may be, for example, in the range of about 0.05 μm or more and 0.12 μm or less (see FIGS. 7, 8, 11).

[0061] The nth interval x between adjacent FLRs 31 n The innermost first change point b1 of the increase width of the nth interval x between adjacent FLRs 31 is set to the position of the second FLR 31 from the inside as the lower limit and to the FLRs 31 on the outside after the second from the inside. Therefore, the innermost FLR section (the first FLR section) 30a includes at least the portion of the first interval x1 between the p + type extension portion 22a and the innermost FLR 31, and the portion of the second interval x2 between the adjacent first and second FLRs 31. In the FLR section (the second FLR section: here, the FLR section 30b) outside the first change point b1, the outer nth interval x n starting from the third from the inside (the third interval x3 between the adjacent second and third FLRs 31) and later is included.

[0062] The nth interval x between adjacent FLRs 31 nThe outermost change point of the increase width (here the second change point b2) is bounded by the position of the third FLR31 from the outside (here, for example, the 28th FLR31 when the total number of FLR31 is 30), and is set for the FLR31 inside from the third one from the outside. Therefore, the outermost FLR section (the third FLR section: here FLR section 30c) includes at least the part of the two nth intervals x n (for example, the 29th and 30th intervals x 29 , x 30 ), and the FLR section (the second FLR section: here FLR section 30b) inside from the outermost change point includes the part of the inner nth intervals x 28 and after the third one from the outside (for example, the 28th interval x n ).

[0063] The FLR structure 30 is preferably divided into three or more FLR sections. The number of parts of the nth interval x n between adjacent FLR31s respectively included in each FLR section of the FLR structure 30 (the innermost FLR section 30a also includes the number including the part of the first interval x1 between the p + type extension part 22a and the innermost FLR31) is preferably the same. The reason is that the spread pattern of the depletion layer extending outward in the n + type drift region 12 from the main junction of the active region 1 (the p-type base region 13, the first and second p + type regions 21, 22 and the p - type extension part 22a and the pn junction with the n - type drift region 12) can be appropriately set (adjusted) inside, in the center, and outside of the FLR structure 30.

[0064] When the insulating layer (field oxide film and interlayer insulating film 19) covering the second surface 40b of the front surface of the semiconductor substrate 40 is positively charged due to the long-time operation of the silicon carbide semiconductor device 10, the positive charges in the insulating layer cause n -By suppressing the spread of the depletion layer in the p-type drift region 12, the electric field concentration generated inside the edge termination region 2 is dispersed in the FLR section (here, the FLR section 30a) inside the FLR structure 30. When the insulating layer covering the second surface 40b of the front surface of the semiconductor substrate 40 becomes negatively (minus) charged due to the long-term operation of the silicon carbide semiconductor device 10, the negative charges in the insulating layer cause n - The breakdown voltage reduction caused by the depletion layer in the p-type drift region 12 being likely to extend outward is suppressed in the FLR section (here, the FLR section 30c) outside the FLR structure 30.

[0065] In the normal state (charge zero) when the insulating layer covering the second surface 40b of the front surface of the semiconductor substrate 40 is not charged, in the FLR section (here, the FLR section 30b) near the center of the FLR structure 30, n - It is preferable to make the depletion layer in the p-type drift region 12 likely to extend outward and disperse the breakdown voltage borne near the center of the edge termination region 2. The above-mentioned m-th interval x m (where m is from 1 to the total number of FLRs 31) is shown in FIG. 3 as the remaining width (width between openings) of the ion implantation mask for forming the p-type extension portion 22a and the FLR 31. The "No." in FIG. 3 is the number from the inside of the FLR 31. In FIG. 3, the total number of FLRs 31 is 30, and the positions of the 10th and 20th FLRs 31 from the inside are the first and second change points b1 and b2 of the increase width of the m-th interval x + m m of.

[0066] In the innermost FLR section 30a, from the portion of the first interval x1 between the p-type extension portion 22a and the innermost FLR 31 to the portion of the 10th interval x + between the 9th and 10th adjacent FLRs 31 is included. Taking the first interval x1 as, for example, 1 μm, the n-th interval x 10 between adjacent FLRs 31 within the innermost FLR section 30a nSet the increase width to 0.05 μm. In this case, the second interval x2 between the first and second adjacent FLR31s is 1.05 μm (= 1 μm + 0.05 μm), and it increases arithmetically with an increase width of 0.05 μm as it is arranged more outward. The tenth interval x 10 between the ninth and tenth adjacent FLR31s, which are the outermost ones in the FLR section 30a, is 1.45 μm (= 1 μm + 0.05 μm × 9).

[0067] In the FLR section 30b between the first and second change points b1 and b2, the 11th interval x 11 from between the 10th and 11th adjacent FLR31s to the 20th interval x 20 between the 19th and 20th adjacent FLR31s is included. Within the FLR section 30b between the first and second change points b1 and b2, the increase width of the nth interval x n between adjacent FLR31s is widened to 0.08 μm compared to the innermost FLR section 30a. In this case, the 11th interval x 11 between the 10th and 11th adjacent FLR31s is 1.53 μm (= 1.45 μm + 0.08 μm), and it increases arithmetically with an increase width of 0.08 μm as it is arranged more outward. The 20th interval x 20 between the 19th and 20th adjacent FLR31s, which are the outermost ones in the FLR section 30b, is 2.25 μm (= 1.45 μm + 0.08 μm × 10).

[0068] In the outermost FLR section 30c, the 21st interval x 21 from between the 20th and 21st adjacent FLR31s to the 30th interval x 30 between the 29th and 30th adjacent FLR31s is included. Within the outermost FLR section 30c, the increase width of the nth interval x n between adjacent FLR31s is widened to 0.12 μm compared to the FLR section 30b between the first and second change points b1 and b2. In this case, the 21st interval x 21is 2.37 μm (= 2.25 μm + 0.12 μm), and it becomes wider in an arithmetic progression with an increase width of 0.12 μm as it is arranged more outward. The 30th interval x between the 29th and 30th FLRs 31 that are the outermost and adjacent to each other in the FLR section 30c 30 is 3.45 μm (= 2.25 μm + 0.12 μm × 10).

[0069] Even if the inside of the insulating layer covering the second surface 40b of the front surface of the semiconductor substrate 40 is charged either positively or negatively, n is such that breakdown voltage characteristics substantially the same as those in the normal state where the insulating layer is not charged can be obtained - it is only necessary to be able to set the spread of the depletion layer in the n-type drift region 12. The number of FLR sections and the nth interval x between adjacent FLRs 31 included in each FLR section of the FLR structure 30 n The number of parts can be changed as appropriate. Therefore, when the total number of FLRs 31 is 30, in the FLR section near the center of the FLR structure 30, the nth interval x between adjacent FLRs 31 n If the number of parts is relatively large, for example, 20, and a predetermined breakdown voltage of the edge termination region 2 can be ensured when the insulating layer covering the second surface 40b of the front surface of the semiconductor substrate 40 is not charged, it is sufficient.

[0070] In each of the inner and outer FLR sections of the FLR structure 30, the nth interval x between adjacent FLRs 31 n The number of parts is set to 5 each for the rest. And, as it is arranged more outward within the inner FLR section of the FLR structure 30, the nth interval x between adjacent FLRs 31 n By widening it in an arithmetic progression with a constant increase width, it is sufficient if the depletion layer can be easily extended outward inside the edge termination region 2 to disperse the electric field concentration inside the edge termination region 2 due to the positive charges in the insulating layer. As it is arranged more inward within the outer FLR section of the FLR structure 30, the nth interval x between adjacent FLRs 31 n By narrowing it in an arithmetic progression with a constant increase width, it is sufficient if the outward extension of the depletion layer outside the edge termination region 2 can be suppressed to suppress the breakdown voltage reduction due to the negative charges in the insulating layer.

[0071] All FLR31s are arranged at the same depth position and have the same thickness. All FLR31s may reach and be exposed on the second surface 40b of the front surface of the semiconductor substrate 40 (not shown), but may be arranged at a position deeper than the second surface 40b of the front surface of the semiconductor substrate 40 (FIG. 2). That is, between the second surface 40b of the front surface of the semiconductor substrate 40 and all FLR31s, an n - -type drift region (third semiconductor region) 12 may be present. Since the FLR31 is separated from the second surface 40b of the front surface of the semiconductor substrate 40, it is possible to make it less susceptible to the adverse effects of the charges accumulated in the insulating layer covering the second surface 40b of the front surface of the semiconductor substrate 40 due to the long-term operation of the silicon carbide semiconductor device 10.

[0072] Between the second surface 40b of the front surface of the semiconductor substrate 40 and the FLR31, the n - -type drift region 12 preferably has a thickness t1 of about 0.4 μm or less in consideration of the variation (about 0.2 μm) in the etching depth for forming the step 24. The FLR31 is preferably formed simultaneously with the first p + -type region 21 of the active region 1. By arranging the FLR31 and the p + -type extension portion 22a at the same depth position, the electric field concentration at the outer end of the p + -type extension portion 22a is suppressed. Further, by forming the FLR31 only simultaneously with the first p + -type region 21, the predetermined thickness (length in the depth direction) of the FLR31 can be stably ensured without being affected by the variation in the etching depth for forming the step 24.

[0073] n + -type channel stopper region 32 is provided outside the FLR structure 30 and separated from the FLR structure 30. The n + -type channel stopper region 32 is exposed on the second surface 40b of the front surface of the semiconductor substrate 40 and the chip end. The n + -type channel stopper region 32 has a floating potential. The n +The p-type channel stopper region 32 is of p - type and is surrounded by the p-type drift region 12. Between the p + type channel stopper region 32 and the outermost FLR 31 is the p - type drift region 12. + The p-type channel stopper region 32 may have, for example, the same impurity concentration as the p + type source region 14. A field plate (FP) or a channel stopper electrode is not provided on the second surface 40b of the front surface of the semiconductor substrate 40.

[0074] The operation of the silicon carbide semiconductor device 10 according to the embodiment will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 18 while a positive voltage (forward voltage) is applied to the drain electrode 25 with respect to the source electrode 20, a channel (n-type inversion layer) is formed in a portion along the trench 16 of the p-type base region 13. As a result, a current flows from the n + type drain region 11 through the n - type drift region 12 and the channel (n-type inversion layer formed along the side wall of the trench 16 inside the p-type base region 13) to the n + type source region 14, and the MOSFET (silicon carbide semiconductor device 10) turns on.

[0075] On the other hand, when a voltage lower than the gate threshold voltage is applied to the gate electrode 18 while a forward voltage is applied between the source and drain, in the active region 1, the p-type base region 13, the first and second p + type regions 21 and 22 and the p + type extension 22a and the n - type drift region 12 are reverse-biased at the pn junction (main junction of the active region 1), and the MOSFET maintains the off state. At this time, the depletion layer spreads from the pn junction into the n + type drift region 12 on the n - type drain region 11 side, and the electric field applied to the gate insulating film 17 on the bottom surface of the trench 16 located on the source electrode 20 side with respect to the pn junction is relaxed.

[0076] Furthermore, when the MOSFET is off, for the depletion layer in the n - -type drift region 12 extending outward (toward the chip end side) beyond the edge termination region 2, a predetermined breakdown voltage based on the breakdown electric field strength and depletion layer width (width in the normal direction) of silicon carbide can be ensured. In the embodiment, the nth interval x n between adjacent FLRs 31 of the FLR structure 30 increases arithmetically with a constant increase width for each of the FLR sections 30a to 30c as it is arranged more outward. Thus, even if the length w2 of the edge termination region 2 is made shorter than the length w102 of the edge termination region 102 of the conventional structure (FIG. 13), a predetermined breakdown voltage comparable to that of the conventional structure can be stably obtained.

[0077] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment will be described. FIGS. 4 to 6 are cross-sectional views showing the states during the manufacturing of the silicon carbide semiconductor device according to the embodiment. FIGS. 4 to 6 show only the outer peripheral portion 1b of the active region 1 and the edge termination region 2 (see FIG. 2) of one chip region 50a, and the central portion 1a of the active region 1 will be described with reference to FIG. 2. The chip region 50a is a region that becomes a semiconductor chip (semiconductor substrate 40) after dicing (cutting) of the semiconductor wafer 50, and a plurality of them are formed in a matrix shape surrounded by, for example, lattice-shaped dicing lines (cutting lines) 50b at the center of the semiconductor wafer 50.

[0078] First, as shown in FIG. 4, an n + -type starting substrate 41, an n + -type starting wafer 51, an n - -type drift region 12, an n - -type silicon carbide layer (first first-conductive-type semiconductor layer) 42a is epitaxially grown (first step). Next, by photolithography and ion implantation of p-type impurities, using the same ion implantation mask, in the surface region of the n - -type silicon carbide layer 42a, the first p + -type region 21 at the central portion 1a of the active region 1, the lower part (fourth part) of the second p + -type region 22 at the central portion 1a of the active region 1, and the p +Selectively form the lower part (first part) 52 of the p-type extension part 22a and all the FLRs 31 of the FLR structure 30 in the edge end region 2 respectively (second step).

[0079] Form the FLR 31 of the FLR structure 30 in the first p- + By forming the FLR 31 simultaneously with the p-type region 21, no ion implantation process is required only for forming the FLR 31, so the number of process steps can be reduced. Also, with the same ion implantation mask, other regions (the first p- + type region 21, the second p- + type region 22 at the lower part and the p- + type extension part 22a) and the FLR 31 are formed simultaneously, so the number of ion implantation masks can be reduced, and the manufacturing cost can be reduced. Also, by forming the FLR 31 of the FLR structure 30 simultaneously with the lower part 52 of the p- + type extension part 22a, the FLR 31 can be arranged at the same depth position as the p- + type extension part 22a.

[0080] Next, as shown in FIG. 5, after removing the ion implantation mask (not shown) used for forming the first p- + type region 21 and the like, an n- - type silicon carbide layer 42b is further epitaxially grown on the n- - type silicon carbide layer (the second first-conductivity-type semiconductor layer) 42a to increase the thickness (third step), thereby forming an n- - type silicon carbide layer 42 (42a, 42b) of the product (silicon carbide semiconductor device 10) thickness. Next, by photolithography and ion implantation of p-type impurities, a second p- - type region at the upper part (the fifth part) of the type region 22 is formed in the central part 1a of the active region 1. In the depth direction, the upper part and the lower part of the second p- + type region 22 are connected, and the second p- + type region 22 is formed. + type region 22 is formed.

[0081] The second p- + type region at the upper part of the type region 22, simultaneously, at the outer peripheral part 1b of the active region 1, a p- - type region is formed in the n- +Form the upper part (second part) 53 of the p-type extending portion 22a (fourth step). In the depth direction, p + The upper part 53 and the lower part 52 of the p-type extending portion 22a are connected, and p + The p-type extending portion 22a is formed. In the edge termination region 2, n - Ion implantation is not performed on the p-type silicon carbide layer 42b. Therefore, in the edge termination region 2, all FLR31s remain as n - The n-type drift region 12 - Is covered with the p-type silicon carbide layer 42b. Next, n - On the surface of the p-type silicon carbide layer 42, a p-type silicon carbide layer 43 serving as the p-type base region 13 is epitaxially grown (fifth step).

[0082] Up to this step, on the front surface of the n + Type starting wafer 51, a semiconductor wafer 50 is completed in which the n - Type drift region 12 and the p-type silicon carbide layers 42 and 43 serving as the p-type base region 13 are sequentially epitaxially grown. When forming an n-type current diffusion region (not shown), n - The n-type silicon carbide layers 42a and 42b serving as the n-type drift region 12 - Each time the n-type silicon carbide layers 42a and 42b are epitaxially grown, by photolithography and ion implantation of n-type impurities, the lower and upper parts of the n-type current diffusion region are formed so as to be connected in the depth direction over the entire active region 1 in the n - Type silicon carbide layers 42a and 42b, respectively.

[0083] Next, as shown in FIG. 6, by photolithography and etching, the portion of the edge termination region 2 of the p-type silicon carbide layer 43 is removed, and only the p-type silicon carbide layer 43 remains in the active region 1. As a result, on the front surface of the semiconductor wafer 50, the outer portion (second surface 40b) is made lower (recessed) than the inner portion (first surface 40a) toward the n + Type starting wafer 51 side, a step 24 is formed, and in the edge termination region 2, the n - Type silicon carbide layer 42b is exposed on the second surface 40b of the front surface of the semiconductor wafer 50. The n -The surface region of the n-type silicon carbide layer 42b may be slightly removed.

[0084] For example, when n - FLR31 is formed inside the n-type silicon carbide layer 42b, the surface region of the n-type silicon carbide layer 42b is slightly removed by etching to form the step 24. - As a result, the thickness of FLR31 changes. On the other hand, as described above, when FLR31 is formed only inside the n-type silicon carbide layer 42a and not inside the n-type silicon carbide layer 42b, even if the surface region of the n-type silicon carbide layer 42b is slightly removed during the formation of the step 24, FLR31 can be left with a predetermined thickness. Also, an n-type silicon carbide layer 42b that becomes the n-type drift region 12 can be left on FLR31. - For example, when n - FLR31 is formed only inside the n-type silicon carbide layer 42a and not inside the n-type silicon carbide layer 42b, even if the surface region of the n-type silicon carbide layer 42b is slightly removed during the formation of the step 24, FLR31 can be left with a predetermined thickness. Also, an n-type silicon carbide layer 42b that becomes the n-type drift region 12 can be left on FLR31. - For example, when n - FLR31 is formed only inside the n-type silicon carbide layer 42a and not inside the n-type silicon carbide layer 42b, even if the surface region of the n-type silicon carbide layer 42b is slightly removed during the formation of the step 24, FLR31 can be left with a predetermined thickness. Also, an n-type silicon carbide layer 42b that becomes the n-type drift region 12 can be left on FLR31. - FLR31 is formed only inside the n-type silicon carbide layer 42a and not inside the n-type silicon carbide layer 42b, even if the surface region of the n-type silicon carbide layer 42b is slightly removed during the formation of the step 24, FLR31 can be left with a predetermined thickness. Also, an n-type silicon carbide layer 42b that becomes the n-type drift region 12 can be left on FLR31.

[0085] Next, an etching mask (not shown) used for partially removing the p-type silicon carbide layer 43 is removed. Next, a process including photolithography, ion implantation, and removal of an ion implantation mask (not shown) is repeated under different conditions to selectively form an n-type source region 14, a p-type contact region 15, and a p-type contact extension 15a inside the p-type silicon carbide layer 43 in the surface region of the front surface (the main surface on the p-type silicon carbide layer 43 side) of the semiconductor wafer 50. The formation order of the n-type source region 14 and the p-type contact region 15 can be interchanged. + type source region 14, p ++ type contact region 15 and p ++ type contact extension 15a are selectively formed, respectively. n + type source region 14 and p ++ The formation order of the type contact region 15 can be interchanged.

[0086] n + type source region 14, at the same time, an n-type channel stopper region 32 may be selectively formed across the ends of adjacent chip regions 50a in the surface region of the second surface 40b of the front surface of the semiconductor wafer 50 (the surface region of the n-type silicon carbide layer 42). n - type silicon carbide layer 42's surface region) between the ends of adjacent chip regions 50a across the surface region of the second surface 40b of the front surface of the semiconductor wafer 50 (the surface region of the n-type silicon carbide layer 42). n + type channel stopper region 32 may be selectively formed across the ends of adjacent chip regions 50a in the surface region of the second surface 40b of the front surface of the semiconductor wafer 50 (the surface region of the n-type silicon carbide layer 42). n - type silicon carbide layer 42 (42a, 42b)'s first and second p +p-type regions 21, 22 + p-type extension portion 22a, FLR 31 and n + The portion excluding the p-type channel stopper region 32 is n - It becomes the n-type drift region 12. Of the p-type silicon carbide layer 43, n + n-type source region 14, p ++ n-type contact region 15 and p ++ The portion excluding the n-type contact extension portion 15a becomes the p-type base region 13 and the p-type base extension portion (third portion) 13a.

[0087] Next, the ion-implanted impurities are activated by heat treatment. Next, by a general method, the trench 16, the gate insulating film 17, the gate electrode 18, the interlayer insulating film 19, the source electrode 20 (sixth step), the drain electrode 25 (seventh step), and the passivation film (polyimide protective film: not shown) are formed. Next, the portion of the passivation film on the dicing line 50b is removed. Thereafter, the semiconductor wafer 50 is diced along the dicing line 50b to singulate the chip region 50a into individual semiconductor chips (semiconductor substrates 40), thereby completing the silicon carbide semiconductor device 10 of FIGS. 1 and 2.

[0088] As described above, according to the embodiment, in the edge termination region, an FLR structure composed of a plurality of floating potentials of floating potential that concentrically surround the periphery of the active region is provided. The FLR structure is divided into two or more FLR sections with a predetermined FLR as a boundary. The interval between adjacent FLRs becomes wider in an arithmetic progression with a constant increase width for each FLR section as it is arranged on the outside, and the increase width becomes wider for the outer FLR section. Thereby, the length of the edge termination region can be shortened, a margin for dimensional variations of the ion implantation mask can be taken, and the breakdown voltage variation due to the charges accumulated in the insulating layer on the front surface of the semiconductor substrate in the edge termination region during long-term operation is suppressed.

[0089] In addition, according to the embodiment, by shortening the length of the edge termination region, an increase in material cost can be suppressed. Further, according to the embodiment, by using an FLR structure for the breakdown voltage structure, the breakdown voltage structure can be formed in a single ion implantation step using a single ion implantation mask, and the number of masks and the number of steps can be reduced compared to the case where the breakdown voltage structure is a JTE structure, and the manufacturing cost can be suppressed. Further, by forming the FLR simultaneously with the first p + -type region of the active region, the number of masks and the number of steps can be further reduced. Therefore, it is possible to provide an inexpensive silicon carbide semiconductor device having a breakdown voltage structure that can be formed with a small number of steps and can stably ensure a predetermined breakdown voltage.

[0090] (Study example) The breakdown voltage characteristics of the silicon carbide semiconductor device 10 according to the above-described embodiment (hereinafter referred to as Study Examples 1 and 2; see FIG. 2) were verified. FIGS. 7 to 10 are characteristic diagrams showing the results of simulating the breakdown voltage characteristics of the conventional example. FIGS. 11 and 12 are characteristic diagrams showing the results of simulating the breakdown voltage characteristics of Study Examples 1 and 2, respectively. In Study Example 1, the FLR structure 30 is divided into FLR sections 30a to 30c under the dimensional conditions of FIG. 3 described above. In Study Example 2, the total number of FLRs 31 is different from that in Study Example 1. In Study Examples 1 and 2, the impurity concentration and the width w1 of the FLR 31 are 1×10 18 / cm 3 and 3 μm, respectively. The thickness t1 of the n - -type drift region 12 between the second surface 40b of the front surface of the semiconductor substrate 40 and the FLR 31 is 0.2 μm.

[0091] For comparison, the reliability of the breakdown voltage of the edge termination region 102 of the conventional silicon carbide semiconductor device 110 (hereinafter referred to as the conventional example; see FIG. 13) was verified. The difference between the conventional example and Study Example 1 is that the edge termination region 102 is provided with a general FLR structure 130. Therefore, in the conventional example, the FLR structure 130 is not divided into FLR sections, and the i-th interval x between adjacent FLRs 131 over the entire area of the FLR structure 130 jThe increase width is constant (where i is the total number of FLR131 from 2 to FLR131, and j = i + 100). In the conventional example, the impurity concentration of FLR131, the width w101 of FLR131, and the n between the second surface 140b of the front surface of the semiconductor substrate 140 and FLR131 - The thickness t101 of the n-type drift region 112 is the same as that in Study Example 1.

[0092] First, the breakdown voltage characteristics of the edge termination region 102 of the conventional example will be described. The i-th interval x between adjacent FLR131 in the FLR structure 130 of the conventional example j The results of simulating the breakdown voltage BVdss (vertical axis) of the edge termination region 102 by variously changing the increase width (horizontal axis) of are shown in FIGS. 7 and 8. In FIGS. 7 and 8, respectively, p + The first interval x between the p-type extension portion 122a and the innermost FLR131 101 is shown for the cases of 1.0 μm and 0.7 μm. The conventional examples in FIGS. 7 and 8 have 30 FLR131 in total. FIGS. 7 and 8 show the case where the insulating layer (field oxide film and interlayer insulating film 119) covering the second surface 140b of the front surface of the semiconductor substrate 140 is positively charged (positive charges are accumulated), the case where the insulating layer is negatively charged (negative charges are accumulated), and the normal state (charge zero) where the insulating layer is not charged (the same applies in FIGS. 9 and 10).

[0093] From the results shown in FIGS. 7 and 8, it was confirmed that in the conventional example, the breakdown voltage fluctuates due to the charges accumulated in the insulating layer (hereinafter simply referred to as the insulating layer) covering the second surface 140b of the front surface of the semiconductor substrate 140 during long-time operation at high temperature. Specifically, when the insulating layer is negatively charged in the setting where the increase width of the i-th interval x between adjacent FLR131 is narrowed (the origin side of the horizontal axis), the breakdown voltage tends to decrease compared to the normal state. When the insulating layer is positively charged in the setting where the increase width of the i-th interval x between adjacent FLR131 is widened (the side away from the origin of the horizontal axis), it was confirmed that the breakdown voltage tends to decrease compared to the normal state. Also, the i-th interval x between adjacent FLR131 j When the insulating layer is negatively charged in the setting where the increase width is narrowed (the origin side of the horizontal axis), the breakdown voltage tends to decrease compared to the normal state. The i-th interval x between adjacent FLR131 j When the insulating layer is positively charged in the setting where the increase width is widened (the side away from the origin of the horizontal axis), it was confirmed that the breakdown voltage tends to decrease compared to the normal state. Also, the i-th interval x between adjacent FLR131 jThe withstand voltage characteristics were most stable when the increase in width was set to 0.075 μm, but a withstand voltage fluctuation of 100 V or more occurred compared to normal conditions in all settings in Figures 7 and 8.

[0094] Therefore, the i-th interval x between adjacent FLR131 j The increase in p is set to 0.075 μm. + A first distance x between the mold extension 122a and the innermost FLR 131 101 9 and 10 show the results of simulating the breakdown voltage (vertical axis) of the edge termination region 102 by changing the value of the horizontal axis. In the conventional examples of FIGS. 9 and 10, the total number of FLRs 131 is 30 and 60, respectively. + A first distance x between the mold extension 122a and the innermost FLR 131 101 The remaining width of the ion implantation mask for forming the portion (first interval x 101 The lower limit of the mask dimension is the width that covers the p + A first distance x between the mold extension 122a and the innermost FLR 131 101 This is the lower limit of the remaining width of the ion implantation mask required to prevent this portion from disappearing due to impurity diffusion.

[0095] From the results shown in FIG. 9, the setting c1 (the i-th interval x between adjacent FLRs 131) in FIG. 8 is the setting that has the most stable breakdown voltage characteristics among the settings in the conventional examples in FIGS. j The increase in p is set to 0.075 μm. + A first distance x between the mold extension 122a and the innermost FLR 131 101 It was confirmed that the breakdown voltage characteristics were stable only at the single point c2, which is the same as the setting c1 where the thickness was 0.7 μm. + A first distance x between the mold extension 122a and the innermost FLR 131 101 When the setting is narrowed (towards the origin of the horizontal axis), the fluctuation in withstand voltage due to negative charge becomes large, and p + A first distance x between the mold extension 122a and the innermost FLR 131 101 It was confirmed that the variation in withstand voltage due to positive charge becomes larger when the setting is wider (farther from the origin of the horizontal axis).

[0096] From the results shown in FIG. 10, by increasing the total number of FLR131 to 60, which is twice that of the conventional example in FIG. 9, p + the first interval x between the p-type extending portion 122a and the innermost FLR131 101 in the narrowed setting, the breakdown voltage fluctuation due to negative charges could be suppressed, but p + the first interval x between the p-type extending portion 122a and the innermost FLR131 101 it was confirmed that the breakdown voltage fluctuation due to positive charges was not improved in the widened setting. Incidentally, p + the first interval x between the p-type extending portion 122a and the innermost FLR131 101 it has been confirmed by the inventor that the more the first interval x is narrowed, the more difficult the ion implantation process of FLR131 becomes. Also, the length w102 of the edge termination region 102 of the conventional example in FIG. 10 is 355 μm, and it was confirmed that it becomes more than twice as long as the length w102 (= 144 μm) of the edge termination region 102 of the conventional example in FIG. 9.

[0097] On the other hand, from the results shown in FIGS. 11 and 12, in Study Examples 1 and 2, compared with the conventional example, the breakdown voltage fluctuation due to the charges accumulated in the insulating layer (field oxide film and interlayer insulating film 19) covering the second surface 40b of the front surface of the semiconductor substrate 40 during long-term operation at high temperature was suppressed, and it was confirmed that it became less than 100 V compared with the normal state. In Study Examples 1 and 2, p + the first interval x1 (horizontal axis) between the p-type extending portion 22a and the innermost FLR31 was variously changed, and the results of simulating the breakdown voltage BVdss (vertical axis) of the edge termination region 2 are shown in FIGS. 11 and 12. FIGS. 11 and 12 show the case where the insulating layer (hereinafter simply referred to as the insulating layer) covering the second surface 40b of the front surface of the semiconductor substrate 40 is positively charged (positive charges are accumulated), negatively charged (negative charges are accumulated), and in the normal state without being charged (charge zero).

[0098] In FIGS. 11 and 12, the horizontal axis is p + the remaining width of the ion implantation mask for forming the portion of the first interval x1 between the p-type extending portion 22a and the innermost FLR31 (the width covering the portion of the first interval x1). The lower limit of the mask dimension is p +This is the lower limit of the remaining width of the ion implantation mask necessary to prevent the portion of the first interval x1 between the p-type extension portion 22a and the innermost FLR 31 from disappearing due to impurity diffusion. Specifically, in Study Examples 1 and 2 (Figs. 11 and 12), it was confirmed that by setting the first interval x1 between the p-type extension portion 22a and the innermost FLR 31 to 1 μm or less, the breakdown voltage variation due to the charge accumulated in the insulating layer can be suppressed, and stable breakdown voltage characteristics can be obtained compared to the conventional examples of Figs. 9 and 10. + By setting the first interval x1 between the p-type extension portion 22a and the innermost FLR 31 to 1 μm or less, a margin for dimensional variations of the ion implantation mask for forming FLR 31 can be obtained. Furthermore, from the results of Study Example 2 in Fig. 12, by increasing the total number of FLR 31, the breakdown voltage characteristics can be further stabilized, and it was confirmed that almost no breakdown voltage variation occurs when the first interval x1 between the p-type extension portion 22a and the innermost FLR 31 is set to 0.6 μm or more and 1.0 μm or less. In Study Example 2, 12 FLR 31 are arranged in each of the three FLR sections 30a to 30c, and the k-th interval x between adjacent FLR 31 is set to a dimension different from that of Study Example 1 (k = 2 to 36).

[0099] Therefore, + In the conventional example (see Fig. 10), even when the total number of FLR 131 is 60 and the length w102 of the edge termination region 102 is increased to 355 μm, the breakdown voltage characteristics are not stable. On the other hand, in Study Example 2, stable breakdown voltage characteristics can be obtained even when the length w2 of the edge termination region 2 is shortened to 171 μm. + As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can also be applied when the front surface of the semiconductor substrate is flat (no step is formed) from the active region to the edge termination region. Further, the present invention also holds true when the conductivity type (n-type, p-type) is reversed. k

Industrial Applicability

[0100] Moreover, in the conventional example (see Fig. 10), even when the total number of FLR 131 is 60 and the length w102 of the edge termination region 102 is increased to 355 μm, the breakdown voltage characteristics are not stable. On the other hand, in Study Example 2, stable breakdown voltage characteristics can be obtained even when the length w2 of the edge termination region 2 is shortened to 171 μm.

[0101] As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can also be applied when the front surface of the semiconductor substrate is flat (no step is formed) from the active region to the edge termination region. Further, the present invention also holds true when the conductivity type (n-type, p-type) is reversed.

Industrial Applicability

[0102] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, and the like.

Description of Reference Numerals

[0103] 1 Active region 1a Central portion of the active region 1b Outer peripheral portion of the active region 2 Edge termination region 10 Silicon carbide semiconductor device 11 n + -type drain region 12 n - -type drift region 13 p-type base region 13a p-type base extension 14 n + -type source region 15 p ++ -type contact region 15a p ++ -type contact extension 16 Trench 17 Gate insulating film 18 Gate electrode 19 Interlayer insulating film 20 Source electrode 21, 22 p + -type region 22a p + -type extension 24 Step on the front surface of the semiconductor substrate 25 Drain electrode 30 FLR structure 31 FLR 30a to 30c FLR sections 32 n + -type channel stopper region 40 Semiconductor substrate 40a First surface of the front surface of the semiconductor substrate (portion inside the step) 40b Second surface of the front surface of the semiconductor substrate (portion outside the step) The third surface (step mesa edge) of the front surface of the 40c semiconductor substrate 41 n + Type starting substrate 42, 42a, 42b n - Type silicon carbide layer 43 p-type silicon carbide layer 50 Semiconductor wafer 50a Chip region 50b Dicing line 51 n + Type starting wafer 52 p + Lower part of the p-type extension 53 p + Upper part of the p-type extension The nth interval x between adjacent FLR31s b1 and b2 n Change point of the increase width t1 n between the second surface of the front surface of the semiconductor substrate and the FLR - Thickness of the n-type drift region x1p + The first interval between the p-type extension and the innermost FLR x n The nth interval between adjacent FLRs (n is from 2 to the total number of FLRs)

Claims

1. An active region provided on a semiconductor substrate made of silicon carbide, a termination region provided on the semiconductor substrate and surrounding the active region, a first semiconductor region of a first conductivity type provided inside the semiconductor substrate extending from the active region to the termination region, a second semiconductor region of a second conductivity type provided between a first main surface of the semiconductor substrate and the first semiconductor region in the active region, an element structure including a pn junction between the first semiconductor region and the second semiconductor region, through which a current flows, a second conductivity type outer peripheral region provided between the element structure and the termination region between the first main surface of the semiconductor substrate and the first semiconductor region, surrounding the element structure, a first electrode provided on the first main surface of the semiconductor substrate, electrically connected to the second semiconductor region and the second conductivity type outer peripheral region, a second electrode provided on a second main surface of the semiconductor substrate, electrically connected to the first semiconductor region, A plurality of floating potential second conductivity type FLRs that form an FLR structure are provided concentrically and spaced apart from each other around the active region between the first main surface of the semiconductor substrate and the first semiconductor region in the termination region, facing the outside of the second conductivity type outer peripheral region in a direction parallel to the first main surface of the semiconductor substrate, comprising the FLR structure is divided into three or more FLR sections with a predetermined FLR as a boundary, the interval between adjacent FLRs is wider than the interval between the second conductivity type outer peripheral region and the innermost FLR, and the further it is arranged on the outside, the wider it becomes in an arithmetic progression with a constant increase width for each FLR section, the increase width is wider in the FLR section arranged on the outside than in the FLR section adjacent to the inside thereof, the entire first main surface of the semiconductor substrate in the termination region is covered with an interlayer insulating film, A silicon carbide semiconductor device characterized in that no conductive film is provided on the first main surface of the semiconductor substrate in the termination region.

2. The silicon carbide semiconductor device according to claim 1, further comprising a first semiconductor region of a first conductivity type provided between the first main surface of the semiconductor substrate and the FLR.

3. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that the number of the FLRs is 30 or more.

4. The impurity concentration of the FLR is 1 × 10 18 / cm 3 or more and 1 × 10 21 / cm 3 or less, and the silicon carbide semiconductor device according to any one of claims 1 to 3 is characterized in that.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the width of the FLR is 2 μm or more and 5 μm or less.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the distance between the second conductivity type outer peripheral region and the innermost FLR is 0.1 μm or more and 1.0 μm or less.

7. The silicon carbide semiconductor device according to claim 2, wherein the thickness of the third semiconductor region is 0.4 μm or less.

8. The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the increased width is in the range of 0.05 μm or more and 0.12 μm or less.

9. Among three or more of the FLR sections, the boundary between the innermost first FLR section and the second FLR section adjacent to the outside of the first FLR section is between the second and subsequent outer FLRs from the inside and the inner FLR of the FLR. The silicon carbide semiconductor device according to any one of claims 1 to 8, characterized in that.

10. Among three or more of the FLR sections, the boundary between the outermost third FLR section and the second FLR section adjacent to the inside of the third FLR section is between the third and subsequent inner FLRs from the outside and the inner FLR of the FLR. The silicon carbide semiconductor device according to any one of claims 1 to 8, characterized in that.

11. The impurity concentration of the second conductivity type outer peripheral region is the same as the impurity concentration of the second semiconductor region on the first main surface side of the semiconductor substrate, The silicon carbide semiconductor device according to any one of claims 1 to 10, characterized in that it is the same as the impurity concentration of the FLR on the first semiconductor region side.

12. The element structure is a first conductivity type fourth semiconductor region selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region and electrically connected to the first electrode; a trench penetrating the fourth semiconductor region and the second semiconductor region and reaching the first semiconductor region; a gate electrode provided in the trench via a gate insulating film; a second conductivity type first high concentration region having a higher impurity concentration than the second semiconductor region, which is selectively provided between the first semiconductor region and the second semiconductor region, away from the second semiconductor region, on the second electrode side from the bottom surface of the trench, and facing the bottom surface of the trench in the depth direction; Between the first semiconductor region and the second semiconductor region, a second high-concentration region of the second conductivity type having the same impurity concentration as the first high-concentration region is selectively provided away from the trench and the first high-concentration region, in contact with the second semiconductor region, and reaching the second electrode side from the bottom surface of the trench. comprising The silicon carbide semiconductor device according to any one of claims 1 to 11, wherein the impurity concentration of the FLR is the same as the impurity concentration of the first high-concentration region.

13. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 11, comprising: a first step of forming a first first-conductivity-type semiconductor layer that becomes the first semiconductor region; a second step of selectively forming, in a surface region of the first first-conductivity-type semiconductor layer, a first portion of the second-conductivity-type outer peripheral region and the FLR, respectively; a third step of forming, on the first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer that becomes the first semiconductor region; a fourth step of selectively forming, at a position in the depth direction of the second first-conductivity-type semiconductor layer facing the first portion, a second portion of the second-conductivity-type outer peripheral region reaching the first portion; a fifth step of forming a second-conductivity-type semiconductor layer on the second first-conductivity-type semiconductor layer in the active region, and setting a portion of the second-conductivity-type semiconductor layer facing the second portion in the depth direction as a third portion of the second-conductivity-type outer peripheral region, and the remaining portion as the second semiconductor region; a sixth step of forming the first electrode electrically connected to the second semiconductor region and the second-conductivity-type outer peripheral region; a seventh step of forming the second electrode electrically connected to the first semiconductor region; A method for manufacturing a silicon carbide semiconductor device, characterized by including the above steps.

14. The element structure is a first-conductivity-type fourth semiconductor region selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region and electrically connected to the first electrode; a trench penetrating the fourth semiconductor region and the second semiconductor region and reaching the first semiconductor region; a gate electrode provided in the trench via a gate insulating film; a first high-concentration region of the second conductivity type having a higher impurity concentration than the second semiconductor region, selectively provided between the first semiconductor region and the second semiconductor region, away from the second semiconductor region, and on the second electrode side from the bottom surface of the trench, and facing the bottom surface of the trench in the depth direction. Between the first semiconductor region and the second semiconductor region, a second high-concentration region of the second conductivity type having the same impurity concentration as the first high-concentration region is selectively provided away from the trench and the first high-concentration region, in contact with the second semiconductor region, and reaching the second electrode side from the bottom surface of the trench. In the second step, the first portion, the FLR, the first high-concentration region, and the fourth portion of the second high-concentration region are selectively formed on the surface region of the first first-conductivity-type semiconductor layer, respectively. In the fourth step, a second portion reaching the first portion and a fifth portion of the second high-concentration region reaching the fourth portion are selectively formed at positions in the depth direction of the second first-conductivity-type semiconductor layer facing the first portion and the fourth portion, respectively. The method for manufacturing a silicon carbide semiconductor device according to claim 13, characterized in that.

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